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# STM32U5 Clock Configuration for T3T1, rev E.
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## Overview
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No HSE nor LSE is used.
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We use 16 MHz HSI as PLL source.
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160 MHz PLLCLK is used as system clock SYSCLK, which is not divided further, so HCLK is also 160 MHz.
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APB1, APB2 and APB3 are also not divided, so PCLK1, PCLK2 and PCLK3 are all 160 MHz
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CLK48 is derived from HSI48, which is 48 MHz.
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## Peripherals
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### USB FS
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USB FS is clocked from CLK48, and CRS is used for clock synchronization.
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### RNG
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RNG is clocked from CLK48.
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### SDMMC
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SDMMC is clocked from CLK48.
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### I2C1
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I2C1 is clocked from PCLK1, 160 MHz
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### I2C2
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I2C2 is clocked from PCLK1, 160 MHz
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### I2C3
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I2C3 is clocked from PCLK3, 160 MHz
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### SAES
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SAES is clocked from SHSI, 48 MHz
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