mirror of
https://github.com/trezor/trezor-firmware.git
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chore(core): refactor mpu initialization
[no changelog]
This commit is contained in:
cepetr
TychoVrahe
parent
c4c571d837
commit
b504baceda
@ -18,241 +18,161 @@
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*/
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#include STM32_HAL_H
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#include <stdbool.h>
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#include "common.h"
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#include "flash.h"
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#include "model.h"
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#include "stm32u5xx_ll_cortex.h"
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#define ATTR_IDX_FLASH (0 << 1)
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#define ATTR_IDX_FLASH_NON_CACHABLE (3 << 1)
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#define ATTR_IDX_SRAM (1 << 1)
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#define ATTR_IDX_PERIPH (2 << 1)
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#define REGION_END(x) (((x) & ~0x1F) | 0x01)
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// region type
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#define MPUX_TYPE_FLASH_CODE 0
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#define MPUX_TYPE_SRAM 1
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#define MPUX_TYPE_PERIPHERAL 2
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#define MPUX_TYPE_FLASH_DATA 3
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#define SHAREABILITY_FLASH (LL_MPU_ACCESS_NOT_SHAREABLE)
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#define SHAREABILITY_SRAM \
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(LL_MPU_ACCESS_INNER_SHAREABLE | LL_MPU_ACCESS_OUTER_SHAREABLE)
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const static struct {
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uint32_t xn; // executable
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uint32_t attr; // attribute index
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uint32_t sh; // shareable
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} mpu_region_lookup[] = {
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void mpu_config_off(void) {
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// Disable MPU
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HAL_MPU_Disable();
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// 0 - FLASH_CODE
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{
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.xn = LL_MPU_INSTRUCTION_ACCESS_ENABLE,
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.attr = LL_MPU_ATTRIBUTES_NUMBER0,
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.sh = LL_MPU_ACCESS_NOT_SHAREABLE,
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},
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// 1 - SRAM
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{
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.xn = LL_MPU_INSTRUCTION_ACCESS_DISABLE,
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.attr = LL_MPU_ATTRIBUTES_NUMBER1,
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.sh = LL_MPU_ACCESS_INNER_SHAREABLE,
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},
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// 2 - PERIPHERAL
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{
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.xn = LL_MPU_INSTRUCTION_ACCESS_DISABLE,
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.attr = LL_MPU_ATTRIBUTES_NUMBER2,
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.sh = LL_MPU_ACCESS_NOT_SHAREABLE,
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},
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// 3 - FLASH_DATA
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{
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.xn = LL_MPU_INSTRUCTION_ACCESS_DISABLE,
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.attr = LL_MPU_ATTRIBUTES_NUMBER3,
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.sh = LL_MPU_ACCESS_NOT_SHAREABLE,
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},
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};
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static inline uint32_t mpu_permission_lookup(bool write, bool unpriv) {
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if (write) {
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return unpriv ? LL_MPU_REGION_ALL_RW : LL_MPU_REGION_PRIV_RW;
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} else {
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return unpriv ? LL_MPU_REGION_ALL_RO : LL_MPU_REGION_PRIV_RO;
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}
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}
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static uint32_t area_start(const flash_area_t* area) {
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return (uint32_t)flash_area_get_address(area, 0, 0);
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}
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#define MPUX_FLAG_NO 0
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#define MPUX_FLAG_YES 1
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static uint32_t area_end(const flash_area_t* area) {
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uint32_t start = area_start(area);
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uint32_t size = flash_area_get_size(area);
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return start + size;
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}
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#define SET_REGION(region, start, size, type, write, unpriv) \
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do { \
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uint32_t _type = MPUX_TYPE_##type; \
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uint32_t _write = MPUX_FLAG_##write; \
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uint32_t _unpriv = MPUX_FLAG_##unpriv; \
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MPU->RNR = LL_MPU_REGION_NUMBER##region; \
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uint32_t _start = (start) & (~0x1F); \
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uint32_t _sh = mpu_region_lookup[_type].sh; \
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uint32_t _ap = mpu_permission_lookup(_write, _unpriv); \
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uint32_t _xn = mpu_region_lookup[_type].xn; \
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MPU->RBAR = _start | _sh | _ap | _xn; \
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uint32_t _limit = (_start + (size)-1) & (~0x1F); \
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uint32_t _attr = mpu_region_lookup[_type].attr << 1; \
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uint32_t _enable = LL_MPU_REGION_ENABLE; \
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MPU->RLAR = _limit | _attr | _enable; \
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} while (0)
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void mpu_config_boardloader(void) {
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// Disable MPU
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HAL_MPU_Disable();
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#define DIS_REGION(region) \
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do { \
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MPU->RNR = LL_MPU_REGION_NUMBER##region; \
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MPU->RBAR = 0; \
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MPU->RLAR = 0; \
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} while (0)
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// flash memory
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static void mpu_set_attributes() {
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// Attr[0] - FLASH - Not-Transient, Write-Through, Read Allocation
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MPU->MAIR0 = 0xAA;
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// internal ram
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MPU->MAIR0 |= 0xAA << 8;
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// peripherals
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// Attr[1] - SRAM - Non-cacheable
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MPU->MAIR0 |= 0x44 << 8;
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// Attr[2] - Peripherals - nGnRnE
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MPU->MAIR0 |= 0x00 << 16;
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// non-cachable flash
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// Attr[3] - FLASH - Non-cacheable
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MPU->MAIR0 |= 0x44 << 24;
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}
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// Secret
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MPU->RNR = MPU_REGION_NUMBER0;
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MPU->RBAR = FLASH_BASE_S | LL_MPU_REGION_ALL_RW | SHAREABILITY_FLASH |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU->RLAR = REGION_END(BOARDLOADER_START - 1) | ATTR_IDX_FLASH_NON_CACHABLE;
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#define GFXMMU_BUFFERS_S GFXMMU_VIRTUAL_BUFFERS_BASE_S
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// Flash boardloader (read-write)
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MPU->RNR = MPU_REGION_NUMBER1;
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MPU->RBAR = BOARDLOADER_START | LL_MPU_REGION_ALL_RW | SHAREABILITY_FLASH;
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MPU->RLAR = REGION_END(BOOTLOADER_START - 1) | ATTR_IDX_FLASH;
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#define SIZE_16K (16 * 1024)
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#define SIZE_48K (48 * 1024)
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#define SIZE_64K (64 * 1024)
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#define SIZE_128K (128 * 1024)
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#define SIZE_192K (192 * 1024)
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#define SIZE_320K (320 * 1024)
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#define SIZE_768K (768 * 1024)
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#define SIZE_1728K ((832 * 2 + 64) * 1024)
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#define SIZE_3776K ((4096 - 320) * 1024)
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#define SIZE_3904K ((4096 - 192) * 1024)
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#define SIZE_4032K ((4096 - 64) * 1024)
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#define SIZE_4M (4 * 1024 * 1024)
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#define SIZE_16M (16 * 1024 * 1024)
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#define SIZE_256M (256 * 1024 * 1024)
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#define SIZE_512M (512 * 1024 * 1024)
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// Flash rest
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MPU->RNR = MPU_REGION_NUMBER2;
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MPU->RBAR = BOOTLOADER_START | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_FLASH;
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MPU->RLAR =
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REGION_END(FLASH_BASE_S + 0x400000 - 1) | ATTR_IDX_FLASH_NON_CACHABLE;
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// RAM (read-write, execute never) (SRAM1)
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MPU->RNR = MPU_REGION_NUMBER3;
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MPU->RBAR = SRAM1_BASE_S | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR = REGION_END(SRAM1_BASE_S + 0xC0000 - 1) | ATTR_IDX_SRAM;
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// RAM (read-write, execute never) (SRAM2, 3, 5, 6)
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// reserve 256 bytes for stack overflow detection
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MPU->RNR = MPU_REGION_NUMBER4;
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MPU->RBAR = (SRAM2_BASE_S + 0x100) | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR = REGION_END(SRAM1_BASE_S + 0x2F0000 - 1) | ATTR_IDX_SRAM;
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// GFXMMU_VIRTUAL_BUFFERS (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER5;
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MPU->RBAR = GFXMMU_VIRTUAL_BUFFERS_BASE_S | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR =
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REGION_END(GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x1000000 - 1) | ATTR_IDX_SRAM;
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// Peripherals (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER6;
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MPU->RBAR =
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PERIPH_BASE_NS | LL_MPU_REGION_ALL_RW | LL_MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU->RLAR = REGION_END(PERIPH_BASE_NS + 0x20000000 - 1) | ATTR_IDX_PERIPH;
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// OTP (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER7;
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MPU->RBAR = FLASH_OTP_BASE | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_FLASH;
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MPU->RLAR = REGION_END(FLASH_OTP_BASE + FLASH_OTP_SIZE - 1) |
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ATTR_IDX_FLASH_NON_CACHABLE;
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// Non-secure Flash
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MPU->RNR = MPU_REGION_NUMBER7;
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MPU->RBAR = FLASH_BASE_NS | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_FLASH;
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MPU->RLAR =
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REGION_END(FLASH_BASE_NS + 0x400000 - 1) | ATTR_IDX_FLASH_NON_CACHABLE;
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// Enable MPU
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void mpu_config_boardloader() {
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HAL_MPU_Disable();
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mpu_set_attributes();
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// clang-format off
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// REGION ADDRESS SIZE TYPE WRITE UNPRIV
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SET_REGION( 0, FLASH_BASE_S, SIZE_16K, FLASH_DATA, YES, YES ); // Secret
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SET_REGION( 1, FLASH_BASE_S + SIZE_16K, SIZE_48K, FLASH_CODE, NO, YES ); // Boardloader code
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SET_REGION( 2, FLASH_BASE_S + SIZE_64K, SIZE_4032K, FLASH_DATA, YES, YES ); // Bootloader + Storage + Firmware
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SET_REGION( 3, SRAM1_BASE_S, SIZE_768K, SRAM, YES, YES ); // SRAM1
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SET_REGION( 4, SRAM2_BASE_S + 0x100, SIZE_1728K - 0x100, SRAM, YES, YES ); // SRAM2/3/5 + stack guard
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SET_REGION( 5, GFXMMU_BUFFERS_S, SIZE_16M, SRAM, YES, YES ); // Frame buffer
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SET_REGION( 6, PERIPH_BASE_S, SIZE_256M, PERIPHERAL, YES, YES ); // Peripherals
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SET_REGION( 7, FLASH_BASE_NS, SIZE_4M, FLASH_DATA, YES, YES ); //
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// clang-format on
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HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
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}
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void mpu_config_bootloader(void) {
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// Disable MPU
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void mpu_config_bootloader() {
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HAL_MPU_Disable();
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// flash memory
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MPU->MAIR0 = 0xAA;
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// internal ram
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MPU->MAIR0 |= 0xAA << 8;
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// peripherals
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MPU->MAIR0 |= 0x00 << 16;
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// non-cachable flash
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MPU->MAIR0 |= 0x44 << 24;
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// Secret + boardloader
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MPU->RNR = MPU_REGION_NUMBER0;
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MPU->RBAR = FLASH_BASE_S | LL_MPU_REGION_ALL_RW | SHAREABILITY_FLASH;
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MPU->RLAR = REGION_END(BOOTLOADER_START - 1) | ATTR_IDX_FLASH_NON_CACHABLE;
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// Bootloader (read-write)
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MPU->RNR = MPU_REGION_NUMBER1;
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MPU->RBAR = BOOTLOADER_START | LL_MPU_REGION_ALL_RW | SHAREABILITY_FLASH;
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MPU->RLAR = REGION_END(area_start(&STORAGE_AREAS[0]) - 1) | ATTR_IDX_FLASH;
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// Flash firmware + storage (read-write, execute never), till flash end
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MPU->RNR = MPU_REGION_NUMBER2;
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MPU->RBAR = area_start(&STORAGE_AREAS[0]) | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_FLASH;
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MPU->RLAR =
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REGION_END(FLASH_BASE_S + 0x400000 - 1) | ATTR_IDX_FLASH_NON_CACHABLE;
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// RAM (read-write, execute never) (SRAM1)
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MPU->RNR = MPU_REGION_NUMBER3;
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MPU->RBAR = SRAM1_BASE_S | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR = REGION_END(SRAM1_BASE_S + 0xC0000 - 1) | ATTR_IDX_SRAM;
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// RAM (read-write, execute never) (SRAM2, 3, 5, 6)
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// reserve 256 bytes for stack overflow detection
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MPU->RNR = MPU_REGION_NUMBER4;
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MPU->RBAR = (SRAM2_BASE_S + 0x100) | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR = REGION_END(SRAM1_BASE_S + 0x2F0000 - 1) | ATTR_IDX_SRAM;
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// GFXMMU_VIRTUAL_BUFFERS (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER5;
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MPU->RBAR = GFXMMU_VIRTUAL_BUFFERS_BASE_S | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR =
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REGION_END(GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x1000000 - 1) | ATTR_IDX_SRAM;
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// Peripherals (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER6;
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MPU->RBAR =
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PERIPH_BASE_S | LL_MPU_REGION_ALL_RW | LL_MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU->RLAR = REGION_END(PERIPH_BASE_S + 0x10000000 - 1) | ATTR_IDX_PERIPH;
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// OTP (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER7;
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MPU->RBAR = FLASH_OTP_BASE | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_FLASH;
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MPU->RLAR = REGION_END(FLASH_OTP_BASE + FLASH_OTP_SIZE - 1) |
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ATTR_IDX_FLASH_NON_CACHABLE;
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// Enable MPU
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mpu_set_attributes();
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// clang-format off
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// REGION ADDRESS SIZE TYPE WRITE UNPRIV
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SET_REGION( 0, FLASH_BASE_S, SIZE_64K, FLASH_DATA, YES, YES ); // Secret + Boardloader
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SET_REGION( 1, FLASH_BASE_S + SIZE_64K, SIZE_128K, FLASH_CODE, NO, YES ); // Bootloader code
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SET_REGION( 2, FLASH_BASE_S + SIZE_192K, SIZE_3904K, FLASH_DATA, YES, YES ); // Storage + Firmware
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SET_REGION( 3, SRAM1_BASE_S, SIZE_768K, SRAM, YES, YES ); // SRAM1
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SET_REGION( 4, SRAM2_BASE_S + 0x100, SIZE_1728K - 0x100, SRAM, YES, YES ); // SRAM2/3/5 + stack guard
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SET_REGION( 5, GFXMMU_BUFFERS_S, SIZE_16M, SRAM, YES, YES ); // Frame buffer
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SET_REGION( 6, PERIPH_BASE_S, SIZE_256M, PERIPHERAL, YES, YES ); // Peripherals
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SET_REGION( 7, FLASH_OTP_BASE, FLASH_OTP_SIZE, FLASH_DATA, YES, YES ); // OTP
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// clang-format on
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HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
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}
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void mpu_config_firmware(void) {
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// Disable MPU
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void mpu_config_firmware() {
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HAL_MPU_Disable();
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// flash memory
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MPU->MAIR0 = 0xAA;
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// internal ram
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MPU->MAIR0 |= 0xAA << 8;
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// peripherals
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MPU->MAIR0 |= 0x00 << 16;
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// non-cachable flash
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MPU->MAIR0 |= 0x44 << 24;
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// bootloader + boardloader: no access, execute never: need to do everything
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// before turning on MPU
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// Storage (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER0;
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MPU->RBAR = area_start(&STORAGE_AREAS[0]) | LL_MPU_REGION_ALL_RW |
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SHAREABILITY_FLASH | LL_MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU->RLAR = REGION_END(FIRMWARE_START - 1) | ATTR_IDX_FLASH_NON_CACHABLE;
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// Flash firmware (read-write)
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MPU->RNR = MPU_REGION_NUMBER1;
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MPU->RBAR = (FIRMWARE_START) | LL_MPU_REGION_ALL_RO | SHAREABILITY_FLASH;
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MPU->RLAR = REGION_END(area_end(&FIRMWARE_AREA) - 1) | ATTR_IDX_FLASH;
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// RAM (read-write, execute never) (SRAM1)
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MPU->RNR = MPU_REGION_NUMBER2;
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MPU->RBAR = SRAM1_BASE_S | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR = REGION_END(SRAM1_BASE_S + 0xC0000 - 1) | ATTR_IDX_SRAM;
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// RAM (read-write, execute never) (SRAM2, 3, 5, 6)
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// reserve 256 bytes for stack overflow detection
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MPU->RNR = MPU_REGION_NUMBER3;
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MPU->RBAR = (SRAM2_BASE_S + 0x100) | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR = REGION_END(SRAM1_BASE_S + 0x2F0000 - 1) | ATTR_IDX_SRAM;
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// GFXMMU_VIRTUAL_BUFFERS (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER4;
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MPU->RBAR = GFXMMU_VIRTUAL_BUFFERS_BASE_S | LL_MPU_REGION_ALL_RW |
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LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_SRAM;
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MPU->RLAR =
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REGION_END(GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x1000000 - 1) | ATTR_IDX_SRAM;
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// Peripherals (read-write, execute never)
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MPU->RNR = MPU_REGION_NUMBER5;
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MPU->RBAR =
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PERIPH_BASE_S | LL_MPU_REGION_ALL_RW | LL_MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU->RLAR = REGION_END(PERIPH_BASE_S + 0x10000000 - 1) | ATTR_IDX_PERIPH;
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// OTP (read-write, execute never)
|
||||
MPU->RNR = MPU_REGION_NUMBER6;
|
||||
MPU->RBAR = FLASH_OTP_BASE | LL_MPU_REGION_ALL_RW |
|
||||
LL_MPU_INSTRUCTION_ACCESS_DISABLE | SHAREABILITY_FLASH;
|
||||
MPU->RLAR = REGION_END(FLASH_OTP_BASE + FLASH_OTP_SIZE - 1) |
|
||||
ATTR_IDX_FLASH_NON_CACHABLE;
|
||||
|
||||
// Enable MPU
|
||||
mpu_set_attributes();
|
||||
// clang-format off
|
||||
// REGION ADDRESS SIZE TYPE WRITE UNPRIV
|
||||
SET_REGION( 0, FLASH_BASE_S + SIZE_192K, SIZE_128K, FLASH_DATA, YES, YES ); // Storage
|
||||
SET_REGION( 1, FLASH_BASE_S + SIZE_320K, SIZE_3776K, FLASH_CODE, NO, YES ); // Firmware
|
||||
SET_REGION( 2, SRAM1_BASE_S, SIZE_768K, SRAM, YES, YES ); // SRAM1
|
||||
SET_REGION( 3, SRAM2_BASE_S + 0x100, SIZE_1728K - 0x100, SRAM, YES, YES ); // SRAM2/3/5 + stack guard
|
||||
SET_REGION( 4, GFXMMU_BUFFERS_S, SIZE_16M, SRAM, YES, YES ); // Frame buffer
|
||||
SET_REGION( 5, PERIPH_BASE_S, SIZE_256M, PERIPHERAL, YES, YES ); // Peripherals
|
||||
SET_REGION( 6, FLASH_OTP_BASE, FLASH_OTP_SIZE, FLASH_DATA, YES, YES ); // OTP
|
||||
DIS_REGION( 7 );
|
||||
// clang-format on
|
||||
HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
|
||||
|
||||
__asm__ volatile("dsb");
|
||||
__asm__ volatile("isb");
|
||||
}
|
||||
|
||||
void mpu_config_off(void) { HAL_MPU_Disable(); }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user