use $(CC) instead of gcc in Makefile

10 years ago · ad8e618ed2
parent 8820ae9873
commit ad8e618ed2
1 changed files with 2 additions and 2 deletions
--- a/4
+++ b/4
@ -44,10 +44,10 @@ all: tests test-openssl
 	$(CC) $(CFLAGS) -o $@ -c $<

 tests: tests.o $(OBJS)
-	gcc tests.o $(OBJS) $(TESTLIBS) -o tests
+	$(CC) tests.o $(OBJS) $(TESTLIBS) -o tests

 test-openssl: test-openssl.o $(OBJS)
-	gcc test-openssl.o $(OBJS) $(TESTSSLLIBS) -o test-openssl
+	$(CC) test-openssl.o $(OBJS) $(TESTSSLLIBS) -o test-openssl

 clean:
 	rm -f *.o tests test-openssl