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refactor(core): simplify linker scripts

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This commit is contained in:
cepetr 2025-05-19 10:37:48 +02:00 committed by cepetr
parent 5b537103bd
commit aa5ba7aba6
20 changed files with 44 additions and 138 deletions
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1
core/embed/rtl/inc/rtl/sizedefs.h
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@ -33,6 +33,7 @@
#define SIZE_320K (320 * 1024) #define SIZE_320K (320 * 1024)
#define SIZE_768K (768 * 1024) #define SIZE_768K (768 * 1024)
#define SIZE_2496K (2496 * 1024) #define SIZE_2496K (2496 * 1024)
#define SIZE_3008K (3008 * 1024)
#define SIZE_3712K ((4096 - 384) * 1024) #define SIZE_3712K ((4096 - 384) * 1024)
#define SIZE_3776K ((4096 - 320) * 1024) #define SIZE_3776K ((4096 - 320) * 1024)
#define SIZE_3904K ((4096 - 192) * 1024) #define SIZE_3904K ((4096 - 192) * 1024)

53
core/embed/sys/linker/inc/sys/linker_utils.h
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@ -20,6 +20,9 @@
#pragma once #pragma once
#include <trezor_bsp.h>
#include <rtl/sizedefs.h>
// symbols defined in the linker script // symbols defined in the linker script
extern uint8_t _stack_section_start; extern uint8_t _stack_section_start;
extern uint8_t _stack_section_end; extern uint8_t _stack_section_end;
@ -46,17 +49,47 @@ typedef struct {
memregion_block_t block[MEMREGION_MAX_BLOCKS]; memregion_block_t block[MEMREGION_MAX_BLOCKS];
} memregion_t; } memregion_t;
#define MEMREGION_ALL_ACCESSIBLE_RAM \ #define MEMBLOCK(start, size) \
({ \ { (void*)(start), (void*)((uint8_t*)(start) + (size)) }
extern uint8_t _accessible_ram_0_start; \
extern uint8_t _accessible_ram_0_end; \
extern uint8_t _accessible_ram_1_start; \ #if defined(STM32F4)
extern uint8_t _accessible_ram_1_end; \ #define MEMREGION_ALL_ACCESSIBLE_RAM \
(memregion_t){.block = { \ ({ \
{&_accessible_ram_0_start, &_accessible_ram_0_end}, \ (memregion_t){ \
{&_accessible_ram_1_start, &_accessible_ram_1_end}, \ .block = \
}}; \ { \
MEMBLOCK(CCMDATARAM_BASE, SIZE_64K), \
MEMBLOCK(SRAM_BASE, SIZE_192K), \
}, \
}; \
}) })
#elif defined(STM32U585xx)
#define MEMREGION_ALL_ACCESSIBLE_RAM \
({ \
(memregion_t){ \
.block = \
{ \
MEMBLOCK(SRAM1_BASE, SIZE_3008K), \
MEMBLOCK(SRAM4_BASE, SIZE_16K), \
}, \
}; \
})
#elif defined(STM32U5G9xx)
#define MEMREGION_ALL_ACCESSIBLE_RAM \
({ \
(memregion_t){ \
.block = \
{ \
MEMBLOCK(SRAM1_BASE, SIZE_768K), \
MEMBLOCK(SRAM4_BASE, SIZE_16K), \
}, \
}; \
})
#else
#error "Unknown STM32 family"
#endif
// Adds a new address range to the memory region. // Adds a new address range to the memory region.
// //

7
core/embed/sys/linker/stm32f4/boardloader.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32f4/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -25,11 +23,6 @@ _confidential_section_loadaddr = 0;
_confidential_section_start = 0; _confidential_section_start = 0;
_confidential_section_end = 0; _confidential_section_end = 0;
_accessible_ram_0_start = MCU_CCMRAM;
_accessible_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE;
_accessible_ram_1_start = MCU_SRAM;
_accessible_ram_1_end = MCU_SRAM + MCU_SRAM_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

7
core/embed/sys/linker/stm32f4/bootloader.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32f4/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -25,11 +23,6 @@ _confidential_section_loadaddr = 0;
_confidential_section_start = 0; _confidential_section_start = 0;
_confidential_section_end = 0; _confidential_section_end = 0;
_accessible_ram_0_start = MCU_CCMRAM;
_accessible_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE;
_accessible_ram_1_start = MCU_SRAM;
_accessible_ram_1_end = MCU_SRAM + MCU_SRAM_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

2
core/embed/sys/linker/stm32f4/firmware.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32f4/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {

7
core/embed/sys/linker/stm32f4/kernel.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32f4/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -25,11 +23,6 @@ _confidential_section_loadaddr = 0;
_confidential_section_start = 0; _confidential_section_start = 0;
_confidential_section_end = 0; _confidential_section_end = 0;
_accessible_ram_0_start = MCU_CCMRAM;
_accessible_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE;
_accessible_ram_1_start = MCU_SRAM;
_accessible_ram_1_end = MCU_SRAM + MCU_SRAM_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

6
core/embed/sys/linker/stm32f4/memory.ld
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@ -1,6 +0,0 @@
MCU_FLASH_ORIGIN = 0x08000000;
MCU_FLASH_SIZE = 2M;
MCU_CCMRAM = 0x10000000;
MCU_CCMRAM_SIZE = 64K;
MCU_SRAM = 0x20000000;
MCU_SRAM_SIZE = 192K;

7
core/embed/sys/linker/stm32f4/prodtest.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32f4/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -25,11 +23,6 @@ _confidential_section_loadaddr = 0;
_confidential_section_start = 0; _confidential_section_start = 0;
_confidential_section_end = 0; _confidential_section_end = 0;
_accessible_ram_0_start = MCU_CCMRAM;
_accessible_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE;
_accessible_ram_1_start = MCU_SRAM;
_accessible_ram_1_end = MCU_SRAM + MCU_SRAM_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

7
core/embed/sys/linker/stm32u58/boardloader.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u58/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -28,11 +26,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

7
core/embed/sys/linker/stm32u58/bootloader.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u58/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -27,11 +25,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

2
core/embed/sys/linker/stm32u58/firmware.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u58/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {

7
core/embed/sys/linker/stm32u58/kernel.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u58/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -30,11 +28,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

14
core/embed/sys/linker/stm32u58/memory.ld
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@ -1,14 +0,0 @@
MCU_FLASH_S_ORIGIN = 0x0C000000;
MCU_FLASH_ORIGIN = 0x08000000;
MCU_FLASH_SIZE = 2M;
MCU_SRAM1 = 0x30000000;
MCU_SRAM1_SIZE = 192K;
MCU_SRAM2 = 0x30030000;
MCU_SRAM2_SIZE = 64K;
MCU_SRAM3 = 0x30040000;
MCU_SRAM3_SIZE = 512K;
MCU_SRAM4 = 0x38000000;
MCU_SRAM4_SIZE = 16K;

7
core/embed/sys/linker/stm32u58/prodtest.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u58/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -27,11 +25,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

7
core/embed/sys/linker/stm32u5g/boardloader.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u5g/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -27,11 +25,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

7
core/embed/sys/linker/stm32u5g/bootloader.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u5g/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -26,11 +24,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

2
core/embed/sys/linker/stm32u5g/firmware.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u5g/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {

7
core/embed/sys/linker/stm32u5g/kernel.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u5g/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -25,11 +23,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;

18
core/embed/sys/linker/stm32u5g/memory.ld
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@ -1,18 +0,0 @@
MCU_FLASH_S_ORIGIN = 0x0C000000;
MCU_FLASH_ORIGIN = 0x08000000;
MCU_FLASH_SIZE = 4M;
MCU_SRAM1 = 0x30000000;
MCU_SRAM1_SIZE = 768K;
MCU_SRAM2 = 0x300C0000;
MCU_SRAM2_SIZE = 64K;
MCU_SRAM3 = 0x300D0000;
MCU_SRAM3_SIZE = 832K;
MCU_SRAM4 = 0x38000000;
MCU_SRAM4_SIZE = 16K;
MCU_SRAM5 = 0x301A0000;
MCU_SRAM5_SIZE = 832K;
MCU_SRAM6 = 0x30270000;
MCU_SRAM6_SIZE = 512K ;

7
core/embed/sys/linker/stm32u5g/prodtest.ld
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@ -1,5 +1,3 @@
INCLUDE "./embed/sys/linker/stm32u5g/memory.ld";
ENTRY(reset_handler) ENTRY(reset_handler)
MEMORY { MEMORY {
@ -26,11 +24,6 @@ _confidential_section_loadaddr = LOADADDR(.confidential);
_confidential_section_start = ADDR(.confidential); _confidential_section_start = ADDR(.confidential);
_confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential); _confidential_section_end = ADDR(.confidential) + SIZEOF(.confidential);
_accessible_ram_0_start = MCU_SRAM1;
_accessible_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_accessible_ram_1_start = MCU_SRAM4;
_accessible_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_bootargs_ram_start = BOOTARGS_START; _bootargs_ram_start = BOOTARGS_START;
_bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE; _bootargs_ram_end = BOOTARGS_START + BOOTARGS_SIZE;