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@ -89,8 +89,8 @@
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#include STM32_HAL_H
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#define MICROPY_HW_CLK_PLLM (8)
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#define MICROPY_HW_CLK_PLLN (336)
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#define MICROPY_HW_CLK_PLLM (4)
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#define MICROPY_HW_CLK_PLLN (168)
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#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
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#define MICROPY_HW_CLK_PLLQ (7)
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#define MICROPY_HW_CLK_LAST_FREQ (1)
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@ -170,7 +170,7 @@ const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 200
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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uint32_t SystemCoreClock = 168000000;
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/**
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* @}
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@ -197,36 +197,29 @@ const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 200
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= CONFIG_RCC_CR_1ST;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= ~ CONFIG_RCC_CR_2ND;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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RCC->CIR = 0x00000000;
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#elif defined(MCU_SERIES_L4)
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RCC->CIER = 0x00000000;
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#endif
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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// set flash wait states for an increasing HCLK frequency -- reference RM0090 section 3.5.1
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FLASH->ACR = FLASH_ACR_LATENCY_5WS;
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// configure main PLL; assumes HSE is 8 MHz; this should evaluate to 0x27402a04 -- reference RM0090 section 7.3.2
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RCC->PLLCFGR = (RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC & ~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM)
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| (7 << RCC_PLLCFGR_PLLQ_Pos) // Q = 7
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| RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
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| (0 << RCC_PLLCFGR_PLLP_Pos) // P = 2 (two bits, 00 means PLLP = 2)
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| (168 << RCC_PLLCFGR_PLLN_Pos) // N = 168
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| (4 << RCC_PLLCFGR_PLLM_Pos); // M = 4
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// enable clock security system, HSE clock, and main PLL
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RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_PLLON;
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// wait until PLL and HSE ready
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while((RCC->CR & (RCC_CR_PLLRDY | RCC_CR_HSERDY)) != (RCC_CR_PLLRDY | RCC_CR_HSERDY));
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// APB2=2, APB1=4, AHB=1, system clock = main PLL
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RCC->CFGR = RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
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// wait until PLL is system clock
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while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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// turn off the HSI as it is now unused (it will be turned on again automatically if a clock security failure occurs)
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RCC->CR &= ~RCC_CR_HSION;
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// enable full access to the fpu coprocessor
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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}
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