feat(core): add support for STM32U585

[no changelog]

core/SConscript.firmware

@@ -856,7 +856,7 @@ else:
             '$DD if=$TARGET of=${TARGET}.p1 skip=0 bs=128k count=6',
             '$CP $TARGET ' + BINARY_NAME,
         ]
-    elif 'STM32U5A9xx' in CPPDEFINES_HAL:
+    elif 'STM32U5A9xx' in CPPDEFINES_HAL or 'STM32U585xx' in CPPDEFINES_HAL:
         action_bin=[
             '$OBJCOPY -O binary -j .vendorheader -j .header -j .flash -j .data -j .sensitive $SOURCE ${TARGET}',
             '$HEADERTOOL -h $TARGET ' + ('-D' if not PRODUCTION else ''),

core/embed/boardloader/memory_stm32u58.ld

@@ -0,0 +1,109 @@
+/* Trezor v2 boardloader linker script */
+
+ENTRY(reset_handler)
+
+MEMORY {
+  FLASH  (rx)  : ORIGIN = 0x0C004000, LENGTH = 48K
+  SRAM1  (wal) : ORIGIN = 0x30000000, LENGTH =  192K - 0x100
+  BOOT_ARGS  (wal) : ORIGIN = 0x3002FF00, LENGTH =  0x100
+  SRAM2  (wal) : ORIGIN = 0x30030000, LENGTH =  64K
+  SRAM3  (wal) : ORIGIN = 0x30040000, LENGTH =  512K
+  SRAM5  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM5 is not available */
+  SRAM6  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM6 is not available */
+  SRAM4  (wal) : ORIGIN = 0x38000000, LENGTH =  16K
+}
+
+main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
+_sstack = ORIGIN(SRAM2);
+_estack = main_stack_base;
+
+/* used by the startup code to populate variables used by the C code */
+data_lma = LOADADDR(.data);
+data_vma = ADDR(.data);
+data_size = SIZEOF(.data);
+
+/* used by the startup code to populate variables used by the C code */
+sensitive_lma = LOADADDR(.sensitive);
+sensitive_vma = ADDR(.sensitive);
+sensitive_size = SIZEOF(.sensitive);
+
+/* used by the startup code to wipe memory */
+sram1_start = ORIGIN(SRAM1);
+sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
+sram2_start = ORIGIN(SRAM2);
+sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
+sram3_start = ORIGIN(SRAM3);
+sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
+sram4_start = ORIGIN(SRAM4);
+sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
+sram5_start = ORIGIN(SRAM5);
+sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
+sram6_start = ORIGIN(SRAM6);
+sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
+
+/* reserve 256 bytes for bootloader arguments */
+boot_args_start = ORIGIN(BOOT_ARGS);
+boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
+
+SECTIONS {
+  .vector_table : ALIGN(512) {
+    KEEP(*(.vector_table));
+  } >FLASH AT>FLASH
+
+  .text : ALIGN(4) {
+    *(.text*);
+    . = ALIGN(4); /* make the section size a multiple of the word size */
+  } >FLASH AT>FLASH
+
+  .rodata : ALIGN(4) {
+    *(.rodata*);
+    . = ALIGN(4); /* make the section size a multiple of the word size */
+  } >FLASH AT>FLASH
+
+  .data : ALIGN(4) {
+    *(.data*);
+    . = ALIGN(8);
+  } >SRAM1 AT>FLASH
+
+  /DISCARD/ : {
+    *(.ARM.exidx*);
+  }
+
+  .bss : ALIGN(4) {
+    *(.bss*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .buf : ALIGN(4) {
+    *(.buf*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .stack : ALIGN(8) {
+    . = 16K; /* Overflow causes UsageFault */
+  } >SRAM2
+
+  .sensitive : ALIGN(8) {
+    *(.sensitive*);
+    . = ALIGN(4);
+  } >SRAM2 AT>FLASH
+
+  .fb : ALIGN(4) {
+   __fb_start = .;
+    *(.fb1*);
+    *(.fb2*);
+   __fb_end = .;
+    . = ALIGN(4);
+  } >SRAM3
+
+  .boot_args : ALIGN(8) {
+    *(.boot_command*);
+    . = ALIGN(8);
+    *(.boot_args*);
+    . = ALIGN(8);
+  } >BOOT_ARGS
+
+
+  /* Hard-coded address for capabilities structure */
+  .capabilities 0x0C00FF00 : {KEEP(*(.capabilities_section))}
+}

core/embed/bootloader/memory_stm32u58.ld

@@ -0,0 +1,106 @@
+/* Trezor v2 bootloader linker script */
+
+ENTRY(reset_handler)
+
+MEMORY {
+  FLASH  (rx)  : ORIGIN = 0x0C010000, LENGTH = 128K
+  SRAM1  (wal) : ORIGIN = 0x30000000, LENGTH =  192K - 0x100
+  BOOT_ARGS  (wal) : ORIGIN = 0x3002FF00, LENGTH =  0x100
+  SRAM2  (wal) : ORIGIN = 0x30030000, LENGTH =  64K
+  SRAM3  (wal) : ORIGIN = 0x30040000, LENGTH =  512K
+  SRAM5  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM5 is not available */
+  SRAM6  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM6 is not available */
+  SRAM4  (wal) : ORIGIN = 0x38000000, LENGTH =  16K
+}
+
+main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
+_sstack = ORIGIN(SRAM2);
+_estack = main_stack_base;
+
+/* used by the startup code to populate variables used by the C code */
+data_lma = LOADADDR(.data);
+data_vma = ADDR(.data);
+data_size = SIZEOF(.data);
+
+/* used by the startup code to populate variables used by the C code */
+sensitive_lma = LOADADDR(.sensitive);
+sensitive_vma = ADDR(.sensitive);
+sensitive_size = SIZEOF(.sensitive);
+
+/* used by the startup code to wipe memory */
+sram1_start = ORIGIN(SRAM1);
+sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
+sram2_start = ORIGIN(SRAM2);
+sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
+sram3_start = ORIGIN(SRAM3);
+sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
+sram4_start = ORIGIN(SRAM4);
+sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
+sram5_start = ORIGIN(SRAM5);
+sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
+sram6_start = ORIGIN(SRAM6);
+sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
+
+/* reserve 256 bytes for bootloader arguments */
+boot_args_start = ORIGIN(BOOT_ARGS);
+boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
+
+_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
+
+SECTIONS {
+  .header : ALIGN(4) {
+    KEEP(*(.header));
+  } >FLASH AT>FLASH
+
+  .flash : ALIGN(512) {
+    KEEP(*(.vector_table));
+    . = ALIGN(4);
+    *(.text*);
+    . = ALIGN(4);
+    *(.rodata*);
+    . = ALIGN(512);
+  } >FLASH AT>FLASH
+
+  .data : ALIGN(4) {
+    *(.data*);
+    . = ALIGN(512);
+  } >SRAM1 AT>FLASH
+
+  /DISCARD/ : {
+    *(.ARM.exidx*);
+  }
+
+  .bss : ALIGN(4) {
+    *(.bss*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .buf : ALIGN(4) {
+    *(.buf*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .stack : ALIGN(8) {
+    . = 16K; /* Overflow causes UsageFault */
+  } >SRAM2
+
+  .sensitive : ALIGN(512) {
+    *(.sensitive*);
+    . = ALIGN(512);
+  } >SRAM2 AT>FLASH
+
+  .fb : ALIGN(4) {
+   __fb_start = .;
+    *(.fb1*);
+    *(.fb2*);
+   __fb_end = .;
+    . = ALIGN(4);
+  } >SRAM3
+
+  .boot_args : ALIGN(8) {
+    *(.boot_command*);
+    . = ALIGN(8);
+    *(.boot_args*);
+    . = ALIGN(8);
+  } >BOOT_ARGS
+}

core/embed/bootloader_ci/memory_stm32u58.ld

@@ -0,0 +1,106 @@
+/* Trezor v2 bootloader linker script */
+
+ENTRY(reset_handler)
+
+MEMORY {
+  FLASH  (rx)  : ORIGIN = 0x0C010000, LENGTH = 128K
+  SRAM1  (wal) : ORIGIN = 0x30000000, LENGTH =  192K - 0x100
+  BOOT_ARGS  (wal) : ORIGIN = 0x3002FF00, LENGTH =  0x100
+  SRAM2  (wal) : ORIGIN = 0x30030000, LENGTH =  64K
+  SRAM3  (wal) : ORIGIN = 0x30040000, LENGTH =  512K
+  SRAM5  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM5 is not available */
+  SRAM6  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM6 is not available */
+  SRAM4  (wal) : ORIGIN = 0x38000000, LENGTH =  16K
+}
+
+main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
+_sstack = ORIGIN(SRAM2);
+_estack = main_stack_base;
+
+/* used by the startup code to populate variables used by the C code */
+data_lma = LOADADDR(.data);
+data_vma = ADDR(.data);
+data_size = SIZEOF(.data);
+
+/* used by the startup code to populate variables used by the C code */
+sensitive_lma = LOADADDR(.sensitive);
+sensitive_vma = ADDR(.sensitive);
+sensitive_size = SIZEOF(.sensitive);
+
+/* used by the startup code to wipe memory */
+sram1_start = ORIGIN(SRAM1);
+sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
+sram2_start = ORIGIN(SRAM2);
+sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
+sram3_start = ORIGIN(SRAM3);
+sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
+sram4_start = ORIGIN(SRAM4);
+sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
+sram5_start = ORIGIN(SRAM5);
+sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
+sram6_start = ORIGIN(SRAM6);
+sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
+
+/* reserve 256 bytes for bootloader arguments */
+boot_args_start = ORIGIN(BOOT_ARGS);
+boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
+
+_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
+
+SECTIONS {
+  .header : ALIGN(4) {
+    KEEP(*(.header));
+  } >FLASH AT>FLASH
+
+  .flash : ALIGN(512) {
+    KEEP(*(.vector_table));
+    . = ALIGN(4);
+    *(.text*);
+    . = ALIGN(4);
+    *(.rodata*);
+    . = ALIGN(512);
+  } >FLASH AT>FLASH
+
+  .data : ALIGN(4) {
+    *(.data*);
+    . = ALIGN(512);
+  } >SRAM1 AT>FLASH
+
+  /DISCARD/ : {
+    *(.ARM.exidx*);
+  }
+
+  .bss : ALIGN(4) {
+    *(.bss*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .buf : ALIGN(4) {
+    *(.buf*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .stack : ALIGN(8) {
+    . = 16K; /* Exactly 16K allocated for stack. Overflow causes Usage fault. */
+  } >SRAM2
+
+  .sensitive : ALIGN(512) {
+    *(.sensitive*);
+    . = ALIGN(512);
+  } >SRAM2 AT>FLASH
+
+  .fb : ALIGN(4) {
+   __fb_start = .;
+    *(.fb1*);
+    *(.fb2*);
+   __fb_end = .;
+    . = ALIGN(4);
+  } >SRAM3
+
+  .boot_args : ALIGN(8) {
+    *(.boot_command*);
+    . = ALIGN(8);
+    *(.boot_args*);
+    . = ALIGN(8);
+  } >BOOT_ARGS
+}

core/embed/lib/sizedefs.h

@@ -0,0 +1,24 @@
+#ifndef SIZEDEFS_H_
+#define SIZEDEFS_H_
+
+#define SIZE_2K (2 * 1024)
+#define SIZE_16K (16 * 1024)
+#define SIZE_48K (48 * 1024)
+#define SIZE_64K (64 * 1024)
+#define SIZE_128K (128 * 1024)
+#define SIZE_192K (192 * 1024)
+#define SIZE_256K (256 * 1024)
+#define SIZE_320K (320 * 1024)
+#define SIZE_768K (768 * 1024)
+#define SIZE_2496K (2496 * 1024)
+#define SIZE_3712K ((4096 - 384) * 1024)
+#define SIZE_3776K ((4096 - 320) * 1024)
+#define SIZE_3904K ((4096 - 192) * 1024)
+#define SIZE_4032K ((4096 - 64) * 1024)
+#define SIZE_2M (2 * 1024 * 1024)
+#define SIZE_4M (4 * 1024 * 1024)
+#define SIZE_16M (16 * 1024 * 1024)
+#define SIZE_256M (256 * 1024 * 1024)
+#define SIZE_512M (512 * 1024 * 1024)
+
+#endif

core/embed/models/model_D002.h

@@ -1,6 +1,8 @@
 #ifndef MODELS_MODEL_DISC2_H_
 #define MODELS_MODEL_DISC2_H_
 
+#include "sizedefs.h"
+
 #define MODEL_NAME "T"
 #define MODEL_FULL_NAME "Trezor Model T"
 #define MODEL_INTERNAL_NAME "D002"
@@ -24,9 +26,9 @@
 #define BOOTLOADER_START 0x0C010000
 #define FIRMWARE_START 0x0C050000
 
-#define IMAGE_CHUNK_SIZE (256 * 1024)
+#define IMAGE_CHUNK_SIZE SIZE_256K
-#define BOOTLOADER_IMAGE_MAXSIZE (128 * 1024 * 1)  // 128 KB
+#define BOOTLOADER_IMAGE_MAXSIZE SIZE_128K
-#define FIRMWARE_IMAGE_MAXSIZE (128 * 1024 * 13)   // 1664 KB
+#define FIRMWARE_IMAGE_MAXSIZE SIZE_3712K
-#define NORCOW_SECTOR_SIZE (64 * 1024)
+#define NORCOW_SECTOR_SIZE SIZE_64K
 
 #endif

core/embed/models/model_D002_layout.c

@@ -24,7 +24,7 @@ const flash_area_t BOARDLOADER_AREA = {
     .num_subareas = 1,
     .subarea[0] =
         {
-            .first_sector = 1,
+            .first_sector = 2,
             .num_sectors = 6,
         },
 };
@@ -43,7 +43,7 @@ const flash_area_t FIRMWARE_AREA = {
     .subarea[0] =
         {
             .first_sector = 0x28,
-            .num_sectors = 456,
+            .num_sectors = 464,
         },
 };
 

core/embed/prodtest/memory_stm32u58.ld

@@ -0,0 +1,121 @@
+/* TREZORv2 firmware linker script */
+
+ENTRY(reset_handler)
+
+MEMORY {
+  FLASH  (rx)  : ORIGIN = 0x0C050000, LENGTH = 3648K
+  SRAM1  (wal) : ORIGIN = 0x30000000, LENGTH =  192K - 0x100
+  BOOT_ARGS  (wal) : ORIGIN = 0x3002FF00, LENGTH =  0x100
+  SRAM2  (wal) : ORIGIN = 0x30030000, LENGTH =  64K
+  SRAM3  (wal) : ORIGIN = 0x30040000, LENGTH =  512K
+  SRAM5  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM5 is not available */
+  SRAM6  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM6 is not available */
+  SRAM4  (wal) : ORIGIN = 0x38000000, LENGTH =  16K
+}
+
+main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
+_sstack = ORIGIN(SRAM2);
+_estack = main_stack_base;
+
+/* used by the startup code to populate variables used by the C code */
+data_lma = LOADADDR(.data);
+data_vma = ADDR(.data);
+data_size = SIZEOF(.data);
+
+/* used by the startup code to populate variables used by the C code */
+sensitive_lma = LOADADDR(.sensitive);
+sensitive_vma = ADDR(.sensitive);
+sensitive_size = SIZEOF(.sensitive);
+
+/* used by the startup code to wipe memory */
+sram1_start = ORIGIN(SRAM1);
+sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
+sram2_start = ORIGIN(SRAM2);
+sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
+sram3_start = ORIGIN(SRAM3);
+sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
+sram4_start = ORIGIN(SRAM4);
+sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
+sram5_start = ORIGIN(SRAM5);
+sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
+sram6_start = ORIGIN(SRAM6);
+sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
+
+/* reserve 256 bytes for bootloader arguments */
+boot_args_start = ORIGIN(BOOT_ARGS);
+boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
+_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
+_flash_start = ORIGIN(FLASH);
+_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+_heap_start = ADDR(.heap);
+_heap_end = ADDR(.heap) + SIZEOF(.heap);
+
+SECTIONS {
+  .vendorheader : ALIGN(4) {
+    KEEP(*(.vendorheader))
+  } >FLASH AT>FLASH
+
+  .header : ALIGN(4) {
+    KEEP(*(.header));
+  } >FLASH AT>FLASH
+
+  .flash : ALIGN(512) {
+    KEEP(*(.vector_table));
+    . = ALIGN(4);
+    *(.text*);
+    . = ALIGN(4);
+    *(.rodata*);
+    . = ALIGN(4);
+    KEEP(*(.bootloader));
+    *(.bootloader*);
+    . = ALIGN(512);
+  } >FLASH AT>FLASH
+
+  .data : ALIGN(4) {
+    *(.data*);
+    . = ALIGN(512);
+  } >SRAM1 AT>FLASH
+
+  /DISCARD/ : {
+    *(.ARM.exidx*);
+  }
+
+  .bss : ALIGN(4) {
+    *(.bss*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .data_ccm : ALIGN(4) {
+    *(.no_dma_buffers*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .heap : ALIGN(4) {
+    . = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
+    . = ABSOLUTE(sram1_end); /* this explicitly sets the end of the heap */
+  } >SRAM1
+
+  .stack : ALIGN(8) {
+    . = 16K; /* Overflow causes UsageFault */
+  } >SRAM2
+
+  .sensitive : ALIGN(512) {
+    *(.sensitive*);
+    . = ALIGN(512);
+  } >SRAM2 AT>FLASH
+
+  .fb : ALIGN(4) {
+   __fb_start = .;
+    *(.fb1*);
+    *(.fb2*);
+   __fb_end = .;
+    . = ALIGN(4);
+  } >SRAM3
+
+  .boot_args : ALIGN(8) {
+    *(.boot_command*);
+    . = ALIGN(8);
+    *(.boot_args*);
+    . = ALIGN(8);
+  } >BOOT_ARGS
+}

core/embed/reflash/memory_stm32u58.ld

@@ -0,0 +1,122 @@
+/* TREZORv2 firmware linker script */
+
+ENTRY(reset_handler)
+
+MEMORY {
+  FLASH  (rx)  : ORIGIN = 0x0C050000, LENGTH = 3648K
+  SRAM1  (wal) : ORIGIN = 0x30000000, LENGTH =  192K - 0x100
+  BOOT_ARGS  (wal) : ORIGIN = 0x3002FF00, LENGTH =  0x100
+  SRAM2  (wal) : ORIGIN = 0x30030000, LENGTH =  64K
+  SRAM3  (wal) : ORIGIN = 0x30040000, LENGTH =  512K
+  SRAM5  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM5 is not available */
+  SRAM6  (wal) : ORIGIN = 0x30080000, LENGTH =  0K  /* SRAM6 is not available */
+  SRAM4  (wal) : ORIGIN = 0x38000000, LENGTH =  16K
+}
+
+main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
+_sstack = ORIGIN(SRAM2);
+_estack = main_stack_base;
+
+/* used by the startup code to populate variables used by the C code */
+data_lma = LOADADDR(.data);
+data_vma = ADDR(.data);
+data_size = SIZEOF(.data);
+
+/* used by the startup code to populate variables used by the C code */
+sensitive_lma = LOADADDR(.sensitive);
+sensitive_vma = ADDR(.sensitive);
+sensitive_size = SIZEOF(.sensitive);
+
+/* used by the startup code to wipe memory */
+sram1_start = ORIGIN(SRAM1);
+sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
+sram2_start = ORIGIN(SRAM2);
+sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
+sram3_start = ORIGIN(SRAM3);
+sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
+sram4_start = ORIGIN(SRAM4);
+sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
+sram5_start = ORIGIN(SRAM5);
+sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
+sram6_start = ORIGIN(SRAM6);
+sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
+
+/* reserve 256 bytes for bootloader arguments */
+boot_args_start = ORIGIN(BOOT_ARGS);
+boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
+
+_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
+_flash_start = ORIGIN(FLASH);
+_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+_heap_start = ADDR(.heap);
+_heap_end = ADDR(.heap) + SIZEOF(.heap);
+
+SECTIONS {
+  .vendorheader : ALIGN(4) {
+    KEEP(*(.vendorheader))
+  } >FLASH AT>FLASH
+
+  .header : ALIGN(4) {
+    KEEP(*(.header));
+  } >FLASH AT>FLASH
+
+  .flash : ALIGN(512) {
+    KEEP(*(.vector_table));
+    . = ALIGN(4);
+    *(.text*);
+    . = ALIGN(4);
+    *(.rodata*);
+    . = ALIGN(4);
+    KEEP(*(.bootloader));
+    *(.bootloader*);
+    . = ALIGN(512);
+  } >FLASH AT>FLASH
+
+  .data : ALIGN(4) {
+    *(.data*);
+    . = ALIGN(512);
+  } >SRAM1 AT>FLASH
+
+  /DISCARD/ : {
+    *(.ARM.exidx*);
+  }
+
+  .bss : ALIGN(4) {
+    *(.bss*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .data_ccm : ALIGN(4) {
+    *(.no_dma_buffers*);
+    . = ALIGN(4);
+  } >SRAM1
+
+  .heap : ALIGN(4) {
+    . = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
+    . = ABSOLUTE(sram1_end); /* this explicitly sets the end of the heap */
+  } >SRAM1
+
+  .stack : ALIGN(8) {
+    . = 16K + 0x100; /* Overflow causes UsageFault */
+  } >SRAM2
+
+  .sensitive : ALIGN(512) {
+    *(.sensitive*);
+    . = ALIGN(512);
+  } >SRAM2 AT>FLASH
+
+  .fb : ALIGN(4) {
+   __fb_start = .;
+    *(.fb1*);
+    *(.fb2*);
+   __fb_end = .;
+    . = ALIGN(4);
+  } >SRAM3
+
+  .boot_args : ALIGN(8) {
+    *(.boot_command*);
+    . = ALIGN(8);
+    *(.boot_args*);
+    . = ALIGN(8);
+  } >BOOT_ARGS
+}

core/embed/trezorhal/stm32f4/displays/st7789v.c

@@ -39,8 +39,11 @@
 // differencies in the resulting binaries.
 const volatile uint8_t DISPLAY_ST7789V_INVERT_COLORS = 1;
 
-// FSMC/FMC Bank 1 - NOR/PSRAM 1
+#ifndef FMC_BANK1
-#define DISPLAY_MEMORY_BASE 0x60000000
+#define FMC_BANK1 FMC_Bank1
+#endif
+
+#define DISPLAY_MEMORY_BASE FMC_BANK1
 #define DISPLAY_MEMORY_PIN 16
 #ifdef USE_DISP_I8080_16BIT_DW
 #define DISPLAY_ADDR_SHIFT 2
@@ -260,7 +263,6 @@ void display_setup_fmc(void) {
       FMC_BURST_ACCESS_MODE_DISABLE;
   external_display_data_sram.Init.WaitSignalPolarity =
       FMC_WAIT_SIGNAL_POLARITY_LOW;
-  external_display_data_sram.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
   external_display_data_sram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
   external_display_data_sram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
   external_display_data_sram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;

core/embed/trezorhal/stm32f4/usbd_conf.c

@@ -94,7 +94,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+#ifdef STM32U5
+    GPIO_InitStruct.Alternate = GPIO_AF10_USB;
+#else
     GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+#endif
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
     /* Configure VBUS Pin */
@@ -119,6 +123,15 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
     /* Enable USB FS Clocks */
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+#ifdef STM32U5
+
+    /* Enable VDDUSB */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    HAL_PWREx_EnableVddUSB();
+    __HAL_RCC_PWR_CLK_DISABLE();
+
+#endif
+
     /* Set USBFS Interrupt priority */
     svc_setpriority(OTG_FS_IRQn, IRQ_PRI_OTG_FS);
 
@@ -763,7 +776,11 @@ void  USBD_LL_Delay(uint32_t Delay)
   * @retval None
   */
 #if defined(USE_USB_FS)
+#ifdef STM32U5
+void OTG_HS_IRQHandler(void) {
+#else
 void OTG_FS_IRQHandler(void) {
+#endif
     SEGGER_SYSVIEW_RecordEnterISR();
     IRQ_ENTER(OTG_FS_IRQn);
     if (pcd_fs_handle.Instance) {

core/embed/trezorhal/stm32u5/flash.c

@@ -26,10 +26,13 @@
 #include "flash.h"
 #include "model.h"
 
-#define FLASH_SEC_START_ADDRESS 0x0C000000
+#ifdef STM32U585xx
-#define FLASH_START_ADDRESS 0x08000000
+#define FLASH_BANK_PAGES 128
-
+#define FLASH_SECTOR_COUNT (FLASH_BANK_PAGES * 2)
-#define FLASH_SECTOR_COUNT (256 * 2)
+#else
+#define FLASH_BANK_PAGES 256
+#define FLASH_SECTOR_COUNT (FLASH_BANK_PAGES * 2)
+#endif
 
 #define FLASH_STATUS_ALL_FLAGS \
   (FLASH_NSSR_PGSERR | FLASH_NSSR_PGAERR | FLASH_NSSR_WRPERR | FLASH_NSSR_EOP)
@@ -50,8 +53,8 @@ const void *flash_get_address(uint16_t sector, uint32_t offset, uint32_t size) {
     return NULL;
   }
 
-  uint32_t base_addr = flash_sector_is_secure(sector) ? FLASH_SEC_START_ADDRESS
+  uint32_t base_addr =
-                                                      : FLASH_START_ADDRESS;
+      flash_sector_is_secure(sector) ? FLASH_BASE_S : FLASH_BASE_NS;
 
   return (const void *)(base_addr + FLASH_PAGE_SIZE * sector + offset);
 }
@@ -93,9 +96,9 @@ secbool flash_sector_erase(uint16_t sector) {
       .NbPages = 1,
   };
 
-  if (sector >= 256) {
+  if (sector >= FLASH_BANK_PAGES) {
     EraseInitStruct.Banks = FLASH_BANK_2;
-    EraseInitStruct.Page = sector - 256;
+    EraseInitStruct.Page = sector - FLASH_BANK_PAGES;
   }
 
   if (flash_sector_is_secure(sector)) {

core/embed/trezorhal/stm32u5/lowlevel.c

@@ -49,12 +49,18 @@
 #endif
 
 #if defined STM32U5A9xx | defined STM32U5G9xx
+#define WRP_DEFAULT_VALUE 0xFF00FFFF
+#define SEC_WM1R1_DEFAULT_VALUE 0xFF00FF00
+#define SEC_WM1R2_DEFAULT_VALUE 0x7F007F00
 #define SEC_AREA_1_PAGE_START 0
 #define HDP_AREA_1_PAGE_END 1
 #define SEC_AREA_1_PAGE_END 0x07
 #define SEC_AREA_2_PAGE_START 0xFF
 #define SEC_AREA_2_PAGE_END 0x00
-#elif define STM32U585xx
+#elif defined STM32U585xx
+#define WRP_DEFAULT_VALUE 0xFF80FFFF
+#define SEC_WM1R1_DEFAULT_VALUE 0xFF80FF80
+#define SEC_WM1R2_DEFAULT_VALUE 0x7F807F80
 #define SEC_AREA_1_PAGE_START 0
 #define HDP_AREA_1_PAGE_END 1
 #define SEC_AREA_1_PAGE_END 0x07
@@ -74,16 +80,20 @@
 
 #define FALSH_SECBOOTADD0R_VALUE \
   ((BOARDLOADER_START & 0xFFFFFF80) | FLASH_SECBOOTADD0R_BOOT_LOCK | 0x7C)
+
 #define FLASH_SECWM1R1_VALUE                                  \
   (SEC_AREA_1_PAGE_START << FLASH_SECWM1R1_SECWM1_PSTRT_Pos | \
-   SEC_AREA_1_PAGE_END << FLASH_SECWM1R1_SECWM1_PEND_Pos | 0xFF00FF00)
+   SEC_AREA_1_PAGE_END << FLASH_SECWM1R1_SECWM1_PEND_Pos |    \
+   SEC_WM1R1_DEFAULT_VALUE)
 #define FLASH_SECWM1R2_VALUE                             \
   (HDP_AREA_1_PAGE_END << FLASH_SECWM1R2_HDP1_PEND_Pos | \
-   FLASH_SECWM1R2_HDP1EN | 0x7F007F00)
+   FLASH_SECWM1R2_HDP1EN | SEC_WM1R2_DEFAULT_VALUE)
+
 #define FLASH_SECWM2R1_VALUE                                  \
   (SEC_AREA_2_PAGE_START << FLASH_SECWM1R1_SECWM1_PSTRT_Pos | \
-   SEC_AREA_2_PAGE_END << FLASH_SECWM1R1_SECWM1_PEND_Pos | 0xFF00FF00)
+   SEC_AREA_2_PAGE_END << FLASH_SECWM1R1_SECWM1_PEND_Pos |    \
-#define FLASH_SECWM2R2_VALUE (0x7F007F00)
+   SEC_WM1R1_DEFAULT_VALUE)
+#define FLASH_SECWM2R2_VALUE (SEC_WM1R2_DEFAULT_VALUE)
 
 #define FLASH_STATUS_ALL_FLAGS \
   (FLASH_NSSR_PGSERR | FLASH_NSSR_PGAERR | FLASH_NSSR_WRPERR | FLASH_NSSR_EOP)
@@ -119,22 +129,24 @@ secbool flash_check_option_bytes(void) {
   }
 
 #if PRODUCTION
+  // TODO error this wont work, need to add default/reset values
+#error this wont work, need to add default/reset values
   if (FLASH->WRP1AR != (WANT_WRP_PAGE_START | (WANT_WRP_PAGE_END << 16))) {
     return secfalse;
   }
 #else
-  if (FLASH->WRP1AR != 0xFF00FFFF) {
+  if (FLASH->WRP1AR != WRP_DEFAULT_VALUE) {
     return secfalse;
   }
 #endif
 
-  if (FLASH->WRP1BR != 0xFF00FFFF) {
+  if (FLASH->WRP1BR != WRP_DEFAULT_VALUE) {
     return secfalse;
   }
-  if (FLASH->WRP2AR != 0xFF00FFFF) {
+  if (FLASH->WRP2AR != WRP_DEFAULT_VALUE) {
     return secfalse;
   }
-  if (FLASH->WRP2BR != 0xFF00FFFF) {
+  if (FLASH->WRP2BR != WRP_DEFAULT_VALUE) {
     return secfalse;
   }
 

core/embed/trezorhal/stm32u5/mpu.c

@@ -20,6 +20,7 @@
 #include STM32_HAL_H
 #include <stdbool.h>
 #include "common.h"
+#include "model.h"
 #include "stm32u5xx_ll_cortex.h"
 
 // region type
@@ -108,33 +109,57 @@ static void mpu_set_attributes() {
 
 #define GFXMMU_BUFFERS_S GFXMMU_VIRTUAL_BUFFERS_BASE_S
 
-#define SIZE_16K (16 * 1024)
+#define SECRET_START FLASH_BASE_S
-#define SIZE_48K (48 * 1024)
+#define SECRET_SIZE SIZE_16K
-#define SIZE_64K (64 * 1024)
+#define BOARDLOADER_SIZE SIZE_48K
-#define SIZE_128K (128 * 1024)
+#define BOOTLOADER_SIZE BOOTLOADER_IMAGE_MAXSIZE
-#define SIZE_192K (192 * 1024)
+#define FIRMWARE_SIZE FIRMWARE_IMAGE_MAXSIZE
-#define SIZE_320K (320 * 1024)
+#define STORAGE_START \
-#define SIZE_2496K (2496 * 1024)
+  (FLASH_BASE_S + SECRET_SIZE + BOARDLOADER_SIZE + BOOTLOADER_SIZE)
-#define SIZE_3776K ((4096 - 320) * 1024)
+#define STORAGE_SIZE NORCOW_SECTOR_SIZE* STORAGE_AREAS_COUNT
-#define SIZE_3904K ((4096 - 192) * 1024)
+
-#define SIZE_4032K ((4096 - 64) * 1024)
+#if defined STM32U5A9xx
-#define SIZE_4M (4 * 1024 * 1024)
+#define SRAM_SIZE SIZE_2496K
-#define SIZE_16M (16 * 1024 * 1024)
+#elif defined STM32U5G9xx
-#define SIZE_256M (256 * 1024 * 1024)
+#define SRAM_SIZE (SIZE_2496K + SIZE_512K)
+#elif defined STM32U585xx
+#define SRAM_SIZE SIZE_768K
+#else
+#error "Unknown MCU"
+#endif
+
+#define L1_REST_SIZE (FLASH_SIZE - (BOARDLOADER_SIZE + SECRET_SIZE))
+
+#define L2_PREV_SIZE (SECRET_SIZE + BOARDLOADER_SIZE)
+#define L2_REST_SIZE \
+  (FLASH_SIZE - (BOOTLOADER_SIZE + BOARDLOADER_SIZE + SECRET_SIZE))
+
+#define ASSETS_START (FIRMWARE_START + FIRMWARE_SIZE)
+#define ASSETS_SIZE                                                   \
+  (FLASH_SIZE - (FIRMWARE_SIZE + BOOTLOADER_SIZE + BOARDLOADER_SIZE + \
+                 SECRET_SIZE + STORAGE_SIZE))
+
+#ifdef STM32U585xx
+#define GRAPHICS_START FMC_BANK1
+#define GRAPHICS_SIZE SIZE_16M
+#else
+#define GRAPHICS_START GFXMMU_BUFFERS
+#define GRAPHICS_SIZE SIZE_16M
+#endif
 
 void mpu_config_boardloader() {
   HAL_MPU_Disable();
   mpu_set_attributes();
   // clang-format off
   //   REGION    ADDRESS                   SIZE                TYPE       WRITE   UNPRIV
-  SET_REGION( 0, FLASH_BASE_S,             SIZE_16K,           FLASH_DATA,  YES,    NO ); // Secret
+  SET_REGION( 0, SECRET_START,             SECRET_SIZE,        FLASH_DATA,  YES,    NO ); // Secret
-  SET_REGION( 1, FLASH_BASE_S + SIZE_16K,  SIZE_48K,           FLASH_CODE,   NO,    NO ); // Boardloader code
+  SET_REGION( 1, BOARDLOADER_START,        BOARDLOADER_SIZE,   FLASH_CODE,   NO,    NO ); // Boardloader code
-  SET_REGION( 2, FLASH_BASE_S + SIZE_64K,  SIZE_4032K,         FLASH_DATA,  YES,    NO ); // Bootloader + Storage + Firmware
+  SET_REGION( 2, BOOTLOADER_START,         L1_REST_SIZE,       FLASH_DATA,  YES,    NO ); // Bootloader + Storage + Firmware
-  SET_REGION( 3, SRAM1_BASE_S,             SIZE_2496K,         SRAM,        YES,    NO ); // SRAM1/2/3/5
+  SET_REGION( 3, SRAM1_BASE,               SRAM_SIZE,          SRAM,        YES,    NO ); // SRAM1/2/3/5
-  SET_REGION( 4, GFXMMU_BUFFERS_S,         SIZE_16M,           SRAM,        YES,    NO ); // Frame buffer
+  SET_REGION( 4, GRAPHICS_START,           GRAPHICS_SIZE,      SRAM,        YES,    NO ); // Frame buffer or display interface
-  SET_REGION( 5, PERIPH_BASE_S,            SIZE_256M,          PERIPHERAL,  YES,    NO ); // Peripherals
+  SET_REGION( 5, PERIPH_BASE_NS,           SIZE_512M,          PERIPHERAL,  YES,    NO ); // Peripherals
   DIS_REGION( 6 );
-  DIS_REGION( 7 );
+  SET_REGION( 7, SRAM4_BASE,               SIZE_16K,           SRAM,        YES,    NO ); // SRAM4
   // clang-format on
   HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
 }
@@ -144,14 +169,14 @@ void mpu_config_bootloader() {
   mpu_set_attributes();
   // clang-format off
   //   REGION    ADDRESS                   SIZE                TYPE       WRITE   UNPRIV
-  SET_REGION( 0, FLASH_BASE_S,             SIZE_64K,           FLASH_DATA,  YES,    NO ); // Secret + Boardloader
+  SET_REGION( 0, SECRET_START,             L2_PREV_SIZE,       FLASH_DATA,  YES,    NO ); // Secret + Boardloader
-  SET_REGION( 1, FLASH_BASE_S + SIZE_64K,  SIZE_128K,          FLASH_CODE,  NO,     NO ); // Bootloader code
+  SET_REGION( 1, BOOTLOADER_START,         BOOTLOADER_SIZE,    FLASH_CODE,  NO,     NO ); // Bootloader code
-  SET_REGION( 2, FLASH_BASE_S + SIZE_192K, SIZE_3904K,         FLASH_DATA,  YES,    NO ); // Storage + Firmware
+  SET_REGION( 2, STORAGE_START,            L2_REST_SIZE,       FLASH_DATA,  YES,    NO ); // Storage + Firmware
-  SET_REGION( 3, SRAM1_BASE_S,             SIZE_2496K,         SRAM,        YES,    NO ); // SRAM1/2/3/5
+  SET_REGION( 3, SRAM1_BASE,               SRAM_SIZE,          SRAM,        YES,    NO ); // SRAM1/2/3/5
-  SET_REGION( 4, GFXMMU_BUFFERS_S,         SIZE_16M,           SRAM,        YES,    NO ); // Frame buffer
+  SET_REGION( 4, GRAPHICS_START,           GRAPHICS_SIZE,      SRAM,        YES,    NO ); // Frame buffer or display interface
-  SET_REGION( 5, PERIPH_BASE_S,            SIZE_256M,          PERIPHERAL,  YES,    NO ); // Peripherals
+  SET_REGION( 5, PERIPH_BASE_NS,           SIZE_512M,          PERIPHERAL,  YES,    NO ); // Peripherals
   SET_REGION( 6, FLASH_OTP_BASE,           FLASH_OTP_SIZE,     FLASH_DATA,  YES,    NO ); // OTP
-  DIS_REGION( 7 );
+  SET_REGION( 7, SRAM4_BASE,               SIZE_16K,           SRAM,        YES,    NO ); // SRAM4
   // clang-format on
   HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
 }
@@ -161,14 +186,14 @@ void mpu_config_firmware() {
   mpu_set_attributes();
   // clang-format off
   //   REGION    ADDRESS                   SIZE                TYPE       WRITE   UNPRIV
-  SET_REGION( 0, FLASH_BASE_S + SIZE_192K, SIZE_128K,          FLASH_DATA,  YES,   YES ); // Storage
+  SET_REGION( 0, STORAGE_START,            STORAGE_SIZE,       FLASH_DATA,  YES,   YES ); // Storage
-  SET_REGION( 1, FLASH_BASE_S + SIZE_320K, SIZE_3776K,         FLASH_CODE,   NO,   YES ); // Firmware
+  SET_REGION( 1, FIRMWARE_START,           FIRMWARE_SIZE,      FLASH_CODE,   NO,   YES ); // Firmware
-  SET_REGION( 2, SRAM1_BASE_S,             SIZE_2496K,         SRAM,        YES,   YES ); // SRAM1/2/3/5
+  SET_REGION( 2, ASSETS_START,             ASSETS_SIZE,        FLASH_DATA,  YES,   YES ); // Assets
-  SET_REGION( 3, GFXMMU_BUFFERS_S,         SIZE_16M,           SRAM,        YES,   YES ); // Frame buffer
+  SET_REGION( 3, SRAM1_BASE,               SRAM_SIZE,          SRAM,        YES,   YES ); // SRAM1/2/3/5
-  SET_REGION( 4, PERIPH_BASE_S,            SIZE_256M,          PERIPHERAL,  YES,   YES ); // Peripherals
+  SET_REGION( 4, GRAPHICS_START,           GRAPHICS_SIZE,      SRAM,        YES,   YES ); // Frame buffer or display interface
-  SET_REGION( 5, FLASH_OTP_BASE,           FLASH_OTP_SIZE,     FLASH_DATA,  YES,   YES ); // OTP
+  SET_REGION( 5, PERIPH_BASE_NS,           SIZE_512M,          PERIPHERAL,  YES,   YES ); // Peripherals
-  DIS_REGION( 6 );
+  SET_REGION( 6, FLASH_OTP_BASE,           FLASH_OTP_SIZE,     FLASH_DATA,  YES,   YES ); // OTP
-  DIS_REGION( 7 );
+  SET_REGION( 7, SRAM4_BASE,               SIZE_16K,           SRAM,        YES,   YES ); // SRAM4
   // clang-format on
   HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
 }

core/embed/trezorhal/stm32u5/platform.c

@@ -155,6 +155,7 @@ void SystemInit(void) {
    */
   HAL_PWREx_DisableUCPDDeadBattery();
 
+#ifdef USE_SMPS
   /*
    * Switch to SMPS regulator instead of LDO
    */
@@ -162,6 +163,7 @@ void SystemInit(void) {
   /* Wait until system switch on new regulator */
   while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS))
     ;
+#endif
 
   __HAL_RCC_PWR_CLK_DISABLE();
 

core/embed/trezorhal/stm32u5/stm32u5xx_hal_conf.h

@@ -29,8 +29,12 @@ extern "C" {
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 
+#ifdef STM32U585xx
+#define USE_USB_FS
+#else
 #define USE_USB_HS
 #define USE_USB_HS_INTERNAL_PHY
+#endif
 
 /* ########################## Module Selection ############################## */
 /**

core/embed/trezorhal/stm32u5/trustzone.c

@@ -48,7 +48,7 @@ static void trustzone_configure_sram(void) {
   mpcbb.AttributeConfig.MPCBB_LockConfig_array[0] = 0x00000000U;
 
   // Set all blocks secured & unprivileged
-  for (int index = 0; index < 52; index++) {
+  for (int index = 0; index < GTZC_MPCBB_NB_VCTR_REG_MAX; index++) {
     mpcbb.AttributeConfig.MPCBB_SecConfig_array[index] = 0xFFFFFFFFU;
     mpcbb.AttributeConfig.MPCBB_PrivConfig_array[index] = 0x00000000U;
   }
@@ -65,6 +65,19 @@ static void trustzone_configure_sram(void) {
 #endif
 }
 
+static void trustzone_configure_fsmc(void) {
+  __HAL_RCC_FMC_CLK_ENABLE();
+  MPCWM_ConfigTypeDef mpcwm = {0};
+
+  mpcwm.AreaId = GTZC_TZSC_MPCWM_ID1;
+  mpcwm.AreaStatus = ENABLE;
+  mpcwm.Attribute = GTZC_TZSC_MPCWM_REGION_SEC;
+  mpcwm.Length = 128 * 1024;
+  mpcwm.Offset = 0;
+  mpcwm.Lock = GTZC_TZSC_MPCWM_LOCK_OFF;
+  HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(FMC_BANK1, &mpcwm);
+}
+
 // Configure FLASH security
 static void trustzone_configure_flash(void) {
   FLASH_BBAttributesTypeDef flash_bb = {0};
@@ -97,6 +110,9 @@ void trustzone_init_boardloader(void) {
   // Configure FLASH security attributes
   trustzone_configure_flash();
 
+  // Configure FSMC security attributes
+  trustzone_configure_fsmc();
+
   // Make all peripherals secure
   HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_ALL, GTZC_TZSC_PERIPH_SEC);