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fix(core): adjust T3W1 display refresh rate

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This commit is contained in:
tychovrahe 2025-01-29 15:38:39 +01:00 committed by TychoVrahe
parent 06a722cc74
commit 64d8c18865
4 changed files with 11 additions and 9 deletions
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8
core/embed/io/display/ltdc_dsi/display_driver.c
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@ -58,7 +58,7 @@ static bool display_pll_init(void) {
#elif HSE_VALUE == 16000000 #elif HSE_VALUE == 16000000
PLL3InitPeriph.PLL3.PLL3M = 4; PLL3InitPeriph.PLL3.PLL3M = 4;
#endif #endif
PLL3InitPeriph.PLL3.PLL3N = 125; PLL3InitPeriph.PLL3.PLL3N = ((DSI_LANE_BYTE_FREQ_HZ * 8) / 4000000);
PLL3InitPeriph.PLL3.PLL3P = 8; PLL3InitPeriph.PLL3.PLL3P = 8;
PLL3InitPeriph.PLL3.PLL3Q = 8; PLL3InitPeriph.PLL3.PLL3Q = 8;
PLL3InitPeriph.PLL3.PLL3R = 24; PLL3InitPeriph.PLL3.PLL3R = 24;
@ -144,11 +144,7 @@ static bool display_dsi_init(display_driver_t *drv) {
drv->hlcd_dsi.Init.PHYFrequencyRange = DSI_DPHY_FRANGE_450MHZ_510MHZ; drv->hlcd_dsi.Init.PHYFrequencyRange = DSI_DPHY_FRANGE_450MHZ_510MHZ;
drv->hlcd_dsi.Init.PHYLowPowerOffset = 0; drv->hlcd_dsi.Init.PHYLowPowerOffset = 0;
#if HSE_VALUE == 32000000 PLLInit.PLLNDIV = ((DSI_LANE_BYTE_FREQ_HZ * 8 * 2 * 4) / (2 * HSE_VALUE));
PLLInit.PLLNDIV = 62;
#elif HSE_VALUE == 16000000
PLLInit.PLLNDIV = 125;
#endif
PLLInit.PLLIDF = 4; PLLInit.PLLIDF = 4;
PLLInit.PLLODF = 2; PLLInit.PLLODF = 2;
PLLInit.PLLVCORange = DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ; PLLInit.PLLVCORange = DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ;

2
core/embed/io/display/ltdc_dsi/panels/lx200d2406a/lx200d2406a.h
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@ -21,6 +21,8 @@
#include <trezor_types.h> #include <trezor_types.h>
#define DSI_LANE_BYTE_FREQ_HZ 62500000ULL
#define VSYNC 4 #define VSYNC 4
#define VBP 4 #define VBP 4
#define VFP 660 #define VFP 660

8
core/embed/io/display/ltdc_dsi/panels/lx250a2401a/lx250a2401a.h
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@ -21,13 +21,15 @@
#include <trezor_types.h> #include <trezor_types.h>
#define DSI_LANE_BYTE_FREQ_HZ 56000000ULL
#define VSYNC 2 #define VSYNC 2
#define VBP 26 #define VBP 26
#define VFP 16 #define VFP 16
#define VACT 520 #define VACT 520
#define HSYNC 6 // 16 #define HSYNC 6
#define HBP 2 // 32 #define HBP 2
#define HFP 6 // 26 #define HFP 56
#define HACT 480 #define HACT 480
#define LCD_WIDTH 480 #define LCD_WIDTH 480
#define LCD_HEIGHT 520 #define LCD_HEIGHT 520

2
core/embed/io/display/ltdc_dsi/panels/stm32u5a9j-dk/stm32u5a9j-dk.h
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@ -19,6 +19,8 @@
#pragma once #pragma once
#define DSI_LANE_BYTE_FREQ_HZ 62500000ULL
#define VSYNC 1 #define VSYNC 1
#define VBP 12 #define VBP 12
#define VFP 50 #define VFP 50