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hardfault handler update
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@ -80,92 +80,13 @@
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/* Cortex-M4 Processor Exceptions Handlers */
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/******************************************************************************/
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// Set the following to 1 to get some more information on the Hard Fault
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// More information about decoding the fault registers can be found here:
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// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/Cihdjcfc.html
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// The ARMv7M Architecture manual (section B.1.5.6) says that upon entry
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// to an exception, that the registers will be in the following order on the
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// stack: R0, R1, R2, R3, R12, LR, PC, XPSR
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typedef struct {
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uint32_t r0, r1, r2, r3, r12, lr, pc, xpsr;
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} ExceptionRegisters_t;
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int pyb_hard_fault_debug = 1;
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void HardFault_C_Handler(ExceptionRegisters_t *regs) {
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if (!pyb_hard_fault_debug) {
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NVIC_SystemReset();
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}
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// We need to disable the USB so it doesn't try to write data out on
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// the VCP and then block indefinitely waiting for the buffer to drain.
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// pyb_usb_flags = 0;
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display_printf("HardFault\n");
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display_printf("R0 %08x\n", (unsigned int)regs->r0);
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display_printf("R1 %08x\n", (unsigned int)regs->r1);
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display_printf("R2 %08x\n", (unsigned int)regs->r2);
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display_printf("R3 %08x\n", (unsigned int)regs->r3);
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display_printf("R12 %08x\n", (unsigned int)regs->r12);
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display_printf("SP %08x\n", (unsigned int)regs);
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display_printf("LR %08x\n", (unsigned int)regs->lr);
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display_printf("PC %08x\n", (unsigned int)regs->pc);
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display_printf("XPSR %08x\n", (unsigned int)regs->xpsr);
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uint32_t cfsr = SCB->CFSR;
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display_printf("HFSR %08x\n", (unsigned int)SCB->HFSR);
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display_printf("CFSR %08x\n", (unsigned int)cfsr);
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if (cfsr & 0x80) {
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display_printf("MMFAR %08x\n", (unsigned int)SCB->MMFAR);
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}
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if (cfsr & 0x8000) {
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display_printf("BFAR %08x\n", (unsigned int)SCB->BFAR);
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}
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if ((void*)&_ram_start <= (void*)regs && (void*)regs < (void*)&_ram_end) {
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display_printf("Stack:\n");
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uint32_t *stack_top = &_estack;
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if ((void*)regs < (void*)&_heap_end) {
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// stack not in static stack area so limit the amount we print
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stack_top = (uint32_t*)regs + 32;
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}
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for (uint32_t *sp = (uint32_t*)regs; sp < stack_top; ++sp) {
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display_printf(" %08x %08x\n", (unsigned int)sp, (unsigned int)*sp);
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}
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}
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void HardFault_Handler(void) {
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/* Go to infinite loop when Hard Fault exception occurs */
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while (1) {
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__fatal_error("HardFault", __FILE__, __LINE__, __FUNCTION__);
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}
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}
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// Naked functions have no compiler generated gunk, so are the best thing to
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// use for asm functions.
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__attribute__((naked))
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void HardFault_Handler(void) {
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// From the ARMv7M Architecture Reference Manual, section B.1.5.6
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// on entry to the Exception, the LR register contains, amongst other
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// things, the value of CONTROL.SPSEL. This can be found in bit 3.
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//
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// If CONTROL.SPSEL is 0, then the exception was stacked up using the
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// main stack pointer (aka MSP). If CONTROL.SPSEL is 1, then the exception
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// was stacked up using the process stack pointer (aka PSP).
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__asm volatile(
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" tst lr, #4 \n" // Test Bit 3 to see which stack pointer we should use.
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" ite eq \n" // Tell the assembler that the nest 2 instructions are if-then-else
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" mrseq r0, msp \n" // Make R0 point to main stack pointer
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" mrsne r0, psp \n" // Make R0 point to process stack pointer
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" b HardFault_C_Handler \n" // Off to C land
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);
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}
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/**
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* @brief This function handles NMI exception.
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* @param None
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