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feat(core): enable LSE on T3W1

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This commit is contained in:
tychovrahe 2025-02-28 14:34:30 +01:00 committed by TychoVrahe
parent d1c1503fa4
commit 4de403bbe1
4 changed files with 38 additions and 1 deletions
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36
core/embed/sys/startup/stm32u5/startup_init.c
View File

@ -121,6 +121,40 @@ void lsi_init(void) {
;
}
// This function replaces calls to universal, but flash-wasting
// function HAL_RCC_OscConfig.
//
// This is the configuration before the optimization:
// osc_init_def.OscillatorType = RCC_OSCILLATORTYPE_LSE;
// osc_init_def.LSEState = RCC_LSE_ON;
// HAL_RCC_OscConfig(&osc_init_def);
void lse_init(void) {
// Update LSE configuration in Backup Domain control register
// Requires to enable write access to Backup Domain of necessary */
if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) {
// Enable write access to Backup domain
SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
;
}
// LSE oscillator enable
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
// Wait till LSE is ready
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
;
// Make sure LSESYSEN/LSESYSRDY are reset
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
// Wait till LSESYSRDY is cleared
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
;
}
void SystemInit(void) {
// set flash wait states for an increasing HCLK frequency
@ -224,7 +258,7 @@ void SystemInit(void) {
PWR->SVMCR |= PWR_SVMCR_IO2SV;
#ifdef USE_LSE
// TODO
lse_init();
#else
lsi_init();
#endif

1
core/site_scons/models/T3W1/trezor_t3w1_revA.py
View File

@ -36,6 +36,7 @@ def configure(
("HW_REVISION", str(hw_revision)),
("HSE_VALUE", "32000000"),
("USE_HSE", "1"),
("USE_LSE", "1"),
("FIXED_HW_DEINIT", "1"),
]

1
core/site_scons/models/T3W1/trezor_t3w1_revA0.py
View File

@ -36,6 +36,7 @@ def configure(
("HW_REVISION", str(hw_revision)),
("HSE_VALUE", "32000000"),
("USE_HSE", "1"),
("USE_LSE", "1"),
("FIXED_HW_DEINIT", "1"),
]

1
core/site_scons/models/T3W1/trezor_t3w1_revB.py
View File

@ -36,6 +36,7 @@ def configure(
("HW_REVISION", str(hw_revision)),
("HSE_VALUE", "32000000"),
("USE_HSE", "1"),
("USE_LSE", "1"),
("FIXED_HW_DEINIT", "1"),
]