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Code Issues Releases Wiki Activity

fix(core): fix MPU kernel sram setting for STM32U5G

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This commit is contained in:
tychovrahe 2024-11-15 11:37:00 +01:00 committed by TychoVrahe
parent 001d3c7cbe
commit 40c5426717
23 changed files with 112 additions and 107 deletions
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2
core/embed/io/display/st-7789/display_driver.c
View File

@ -99,7 +99,7 @@ void display_deinit(display_content_mode_t mode) {
#endif
#endif
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
backlight_pwm_deinit(mode == DISPLAY_RESET_CONTENT ? BACKLIGHT_RESET
: BACKLIGHT_RETAIN);

9
core/embed/io/display/st-7789/display_fb.c
View File

@ -107,8 +107,10 @@ static uint8_t *get_fb_ptr(uint32_t index) {
void display_physical_fb_clear(void) {
for (int i = 0; i < FRAME_BUFFER_COUNT; i++) {
mpu_set_active_fb(get_fb_ptr(i), PHYSICAL_FRAME_BUFFER_SIZE);
memset(get_fb_ptr(i), 0, PHYSICAL_FRAME_BUFFER_SIZE);
}
mpu_set_active_fb(NULL, 0);
}
#ifndef BOARDLOADER
@ -198,7 +200,7 @@ bool display_get_frame_buffer(display_fb_info_t *fb) {
fb->ptr = get_fb_ptr(drv->queue.wix);
fb->stride = DISPLAY_RESX * sizeof(uint16_t);
// Enable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(fb->ptr, PHYSICAL_FRAME_BUFFER_SIZE);
mpu_set_active_fb(fb->ptr, PHYSICAL_FRAME_BUFFER_SIZE);
return true;
}
@ -208,12 +210,15 @@ static void copy_fb_to_display(uint8_t index) {
uint16_t *fb = (uint16_t *)get_fb_ptr(index);
if (fb != NULL) {
mpu_set_active_fb(fb, PHYSICAL_FRAME_BUFFER_SIZE);
display_panel_set_window(0, 0, DISPLAY_RESX - 1, DISPLAY_RESY - 1);
for (int i = 0; i < DISPLAY_RESX * DISPLAY_RESY; i++) {
// 2 bytes per pixel because we're using RGB 5-6-5 format
ISSUE_PIXEL_DATA(fb[i]);
}
}
mpu_set_active_fb(NULL, 0);
}
static void wait_for_te_signal(void) {
@ -238,7 +243,7 @@ void display_refresh(void) {
}
// Disable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
#ifndef BOARDLOADER
if (is_mode_exception()) {

2
core/embed/io/display/st7785ma/display_driver.c
View File

@ -79,7 +79,7 @@ bool display_get_frame_buffer(display_fb_info_t *fb) {
fb->ptr = get_fb_ptr(0);
fb->stride = DISPLAY_RESX * sizeof(uint16_t);
// Enable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(fb->ptr, PHYSICAL_FRAME_BUFFER_SIZE);
mpu_set_active_fb(fb->ptr, PHYSICAL_FRAME_BUFFER_SIZE);
return true;
}

6
core/embed/io/display/stm32f429i-disc1/display_driver.c
View File

@ -73,7 +73,7 @@ void display_init(display_content_mode_t mode) {
void display_deinit(display_content_mode_t mode) {
display_driver_t *drv = &g_display_driver;
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
drv->initialized = false;
}
@ -136,7 +136,7 @@ bool display_get_frame_buffer(display_fb_info_t *fb) {
fb->ptr = (void *)drv->framebuf;
fb->stride = DISPLAY_RESX * sizeof(uint16_t);
// Enable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(fb->ptr, FRAME_BUFFER_SIZE);
mpu_set_active_fb(fb->ptr, FRAME_BUFFER_SIZE);
return true;
}
}
@ -145,7 +145,7 @@ void display_refresh(void) {
// Do nothing as using just a single frame buffer
// Disable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
}
void display_fill(const gfx_bitblt_t *bb) {

9
core/embed/io/display/stm32u5a9j-dk/display_driver.c
View File

@ -70,16 +70,21 @@ void display_init(display_content_mode_t mode) {
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
// Clear framebuffers
mpu_set_active_fb(physical_frame_buffer_0, PHYSICAL_FRAME_BUFFER_SIZE);
memset(physical_frame_buffer_0, 0x00, PHYSICAL_FRAME_BUFFER_SIZE);
mpu_set_active_fb(physical_frame_buffer_1, PHYSICAL_FRAME_BUFFER_SIZE);
memset(physical_frame_buffer_1, 0x00, PHYSICAL_FRAME_BUFFER_SIZE);
mpu_set_active_fb(NULL, 0);
BSP_LCD_Init(0, LCD_ORIENTATION_PORTRAIT);
BSP_LCD_SetBrightness(0, 100);
BSP_LCD_DisplayOn(0);
} else {
// Retain display content
BSP_LCD_Reinit(0);
if (current_frame_buffer == 0) {
if (drv->current_frame_buffer == 0) {
BSP_LCD_SetFrameBuffer(0, GFXMMU_VIRTUAL_BUFFER1_BASE_S);
} else {
BSP_LCD_SetFrameBuffer(0, GFXMMU_VIRTUAL_BUFFER0_BASE_S);
@ -110,7 +115,7 @@ void display_deinit(display_content_mode_t mode) {
BSP_LCD_DeInit(0);
}
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
drv->initialized = false;
}

17
core/embed/io/display/stm32u5a9j-dk/display_fb.c
View File

@ -39,11 +39,6 @@ uint8_t physical_frame_buffer_0[PHYSICAL_FRAME_BUFFER_SIZE];
__attribute__((section(".fb2"), aligned(PHYSICAL_FRAME_BUFFER_ALIGNMENT)))
uint8_t physical_frame_buffer_1[PHYSICAL_FRAME_BUFFER_SIZE];
// The current frame buffer selector at fixed memory address
// It's shared between bootloaders and the firmware
__attribute__((section(".framebuffer_select"))) uint32_t current_frame_buffer =
0;
#ifdef USE_TRUSTZONE
void display_set_unpriv_access(bool unpriv) {
// To allow unprivileged access both GFXMMU virtual buffers area and
@ -85,7 +80,7 @@ bool display_get_frame_buffer(display_fb_info_t *fb) {
uintptr_t addr;
if (current_frame_buffer == 0) {
if (drv->current_frame_buffer == 0) {
addr = GFXMMU_VIRTUAL_BUFFER1_BASE_S;
} else {
addr = GFXMMU_VIRTUAL_BUFFER0_BASE_S;
@ -102,7 +97,7 @@ bool display_get_frame_buffer(display_fb_info_t *fb) {
fb->stride = fb_stride;
// Enable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(fb->ptr, VIRTUAL_FRAME_BUFFER_SIZE);
mpu_set_active_fb(fb->ptr, VIRTUAL_FRAME_BUFFER_SIZE);
return true;
}
@ -115,13 +110,13 @@ void display_refresh(void) {
}
// Disable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
if (current_frame_buffer == 0) {
current_frame_buffer = 1;
if (drv->current_frame_buffer == 0) {
drv->current_frame_buffer = 1;
BSP_LCD_SetFrameBuffer(0, GFXMMU_VIRTUAL_BUFFER1_BASE_S);
} else {
current_frame_buffer = 0;
drv->current_frame_buffer = 0;
BSP_LCD_SetFrameBuffer(0, GFXMMU_VIRTUAL_BUFFER0_BASE_S);
}
}

9
core/embed/io/display/stm32u5a9j-dk/display_internal.h
View File

@ -36,6 +36,8 @@ typedef struct {
int orientation_angle;
// Current backlight level ranging from 0 to 255
int backlight_level;
// The current frame buffer selector
uint32_t current_frame_buffer;
} display_driver_t;
// Display driver instance
@ -64,16 +66,11 @@ extern display_driver_t g_display_driver;
// Physical frame buffers in internal SRAM memory
//
// Both frame buffers layes in the fixed addresses that
// Both frame buffers layers in the fixed addresses that
// are shared between bootloaders and the firmware.
extern uint8_t physical_frame_buffer_0[PHYSICAL_FRAME_BUFFER_SIZE];
extern uint8_t physical_frame_buffer_1[PHYSICAL_FRAME_BUFFER_SIZE];
// The current frame buffer selector at fixed memory address
//
// The variable address is shared between bootloaders and the firmware
extern uint32_t current_frame_buffer;
// LCD orientations
#define LCD_ORIENTATION_PORTRAIT 0U
#define LCD_ORIENTATION_LANDSCAPE 1U

6
core/embed/io/display/stm32u5a9j-dk/display_ltdc_dsi.c
View File

@ -164,9 +164,6 @@ LTDC_HandleTypeDef hlcd_ltdc = {0};
DSI_HandleTypeDef hlcd_dsi = {0};
static DSI_VidCfgTypeDef DSIVidCfg = {0};
__attribute__((section(".gfxmmu_table")))
uint32_t gfxmmu_lut[2 * GFXMMU_LUT_SIZE];
/**
* @}
*/
@ -207,7 +204,6 @@ int32_t BSP_LCD_Init(uint32_t Instance, uint32_t Orientation) {
memset(&hlcd_ltdc, 0, sizeof(hlcd_ltdc));
memset(&hlcd_dsi, 0, sizeof(hlcd_dsi));
memset(&DSIVidCfg, 0, sizeof(DSIVidCfg));
memcpy(gfxmmu_lut, gfxmmu_lut_config, sizeof(gfxmmu_lut));
int32_t status = BSP_ERROR_NONE;
@ -989,7 +985,7 @@ static int32_t LCD_Init(void) {
}
/* Initialize LUT */
else if (HAL_GFXMMU_ConfigLut(&hlcd_gfxmmu, 0, LCD_WIDTH,
(uint32_t)&gfxmmu_lut) != HAL_OK) {
(uint32_t)&gfxmmu_lut_config) != HAL_OK) {
status = BSP_ERROR_PERIPH_FAILURE;
} else {
/* Disable non visible lines : from line 480 to 1023 */

9
core/embed/io/display/vg-2864/display_driver.c
View File

@ -199,6 +199,8 @@ static void display_sync_with_fb(display_driver_t *drv) {
// Send whole framebuffer to the display
mpu_set_active_fb(drv->framebuf, FRAME_BUFFER_SIZE);
if (drv->orientation_angle == 0) {
for (int y = DISPLAY_RESY / 8 - 1; y >= 0; y--) {
uint8_t buff[DISPLAY_RESX];
@ -233,6 +235,7 @@ static void display_sync_with_fb(display_driver_t *drv) {
while (HAL_SPI_STATE_READY != HAL_SPI_GetState(&drv->spi)) {
}
mpu_set_active_fb(NULL, 0);
// SPI deselect
HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_SET);
@ -321,7 +324,7 @@ void display_init(display_content_mode_t mode) {
void display_deinit(display_content_mode_t mode) {
display_driver_t *drv = &g_display_driver;
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
drv->initialized = false;
}
@ -391,7 +394,7 @@ bool display_get_frame_buffer(display_fb_info_t *fb) {
fb->ptr = &drv->framebuf[0];
fb->stride = DISPLAY_RESX;
// Enable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(fb->ptr, FRAME_BUFFER_SIZE);
mpu_set_active_fb(fb->ptr, FRAME_BUFFER_SIZE);
return true;
}
}
@ -410,7 +413,7 @@ void display_refresh(void) {
#endif
// Disable access to the frame buffer from the unprivileged code
mpu_set_unpriv_fb(NULL, 0);
mpu_set_active_fb(NULL, 0);
// Copy the frame buffer to the display
display_sync_with_fb(drv);

6
core/embed/models/D002/memory.ld
View File

@ -40,9 +40,9 @@ ASSETS_MAXSIZE = 0x10000;
ASSETS_SECTOR_START = 0x1f8;
ASSETS_SECTOR_END = 0x1ff;
KERNEL_U_RAM_SIZE = 0x200;
KERNEL_SRAM1_SIZE = 0x4000;
KERNEL_SRAM2_SIZE = 0x2400;
KERNEL_SRAM3_SIZE = 0xbb800;
KERNEL_SRAM1_SIZE = 0x0;
KERNEL_SRAM2_SIZE = 0xfe00;
KERNEL_SRAM3_SIZE = 0x0;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000;

6
core/embed/models/D002/model_D002.h
View File

@ -86,9 +86,9 @@
// RAM layout
#define KERNEL_U_RAM_SIZE 512
#define KERNEL_SRAM1_SIZE (16 * 1024)
#define KERNEL_SRAM2_SIZE (9 * 1024)
#define KERNEL_SRAM3_SIZE (750 * 1024)
#define KERNEL_SRAM1_SIZE (0 * 1024)
#define KERNEL_SRAM2_SIZE (64 * 1024 - 512)
#define KERNEL_SRAM3_SIZE (0 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x400

6
core/embed/models/T3W1/memory.ld
View File

@ -40,9 +40,9 @@ ASSETS_MAXSIZE = 0x10000;
ASSETS_SECTOR_START = 0x1f8;
ASSETS_SECTOR_END = 0x1ff;
KERNEL_U_RAM_SIZE = 0x200;
KERNEL_SRAM1_SIZE = 0x4000;
KERNEL_SRAM2_SIZE = 0x2400;
KERNEL_SRAM3_SIZE = 0xbb800;
KERNEL_SRAM1_SIZE = 0x0;
KERNEL_SRAM2_SIZE = 0xfe00;
KERNEL_SRAM3_SIZE = 0x0;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000;

6
core/embed/models/T3W1/model_T3W1.h
View File

@ -92,9 +92,9 @@
// RAM layout
#define KERNEL_U_RAM_SIZE 512
#define KERNEL_SRAM1_SIZE (16 * 1024)
#define KERNEL_SRAM2_SIZE (9 * 1024)
#define KERNEL_SRAM3_SIZE (750 * 1024)
#define KERNEL_SRAM1_SIZE (0 * 1024)
#define KERNEL_SRAM2_SIZE (64 * 1024 - 512)
#define KERNEL_SRAM3_SIZE (0 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x400

1
core/embed/sys/linker/stm32u58/boardloader.ld
View File

@ -107,7 +107,6 @@ SECTIONS {
__fb_start = .;
*(.fb1*);
*(.fb2*);
*(.framebuffer_select*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

1
core/embed/sys/linker/stm32u58/bootloader.ld
View File

@ -109,7 +109,6 @@ SECTIONS {
__fb_start = .;
*(.fb1*);
*(.fb2*);
*(.framebuffer_select*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

1
core/embed/sys/linker/stm32u58/kernel.ld
View File

@ -143,7 +143,6 @@ SECTIONS {
__fb_start = .;
*(.fb1*);
*(.fb2*);
*(.framebuffer_select*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

2
core/embed/sys/linker/stm32u5g/boardloader.ld
View File

@ -110,8 +110,6 @@ SECTIONS {
.fb2 : ALIGN(4) {
*(.fb2*);
*(.gfxmmu_table*);
*(.framebuffer_select*);
. = ALIGN(4);
} >SRAM3

2
core/embed/sys/linker/stm32u5g/bootloader.ld
View File

@ -113,8 +113,6 @@ SECTIONS {
.fb2 : ALIGN(4) {
*(.fb2*);
*(.gfxmmu_table*);
*(.framebuffer_select*);
__fb_end = .;
. = ALIGN(4);
} >SRAM3

18
core/embed/sys/linker/stm32u5g/kernel.ld
View File

@ -6,9 +6,9 @@ MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE - KERNEL_U_RAM_SIZE
SRAM3_U (wal) : ORIGIN = MCU_SRAM3 + MCU_SRAM3_SIZE - KERNEL_U_RAM_SIZE, LENGTH = KERNEL_U_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = KERNEL_SRAM2_SIZE
SRAM2_U (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE, LENGTH = KERNEL_U_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE
@ -18,8 +18,8 @@ main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descend
_sstack = ORIGIN(SRAM2);
_estack = main_stack_base;
ustack_base = ORIGIN(SRAM3_U) + 512;
_sustack = ORIGIN(SRAM3_U) + 256;
ustack_base = ORIGIN(SRAM2_U) + 512;
_sustack = ORIGIN(SRAM2_U) + 256;
_eustack = ustack_base;
/* used by the startup code to populate variables used by the C code */
@ -67,8 +67,8 @@ _coreapp_clear_ram_1_start = 0;
_coreapp_clear_ram_1_size = 0;
sram_u_start = ORIGIN(SRAM3_U);
sram_u_end = ORIGIN(SRAM3_U) + LENGTH(SRAM3_U);
sram_u_start = ORIGIN(SRAM2_U);
sram_u_end = ORIGIN(SRAM2_U) + LENGTH(SRAM2_U);
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
@ -127,7 +127,7 @@ SECTIONS {
*(.udata*);
. = ALIGN(256);
. = 256; /* Overflow causes UsageFault */
} >SRAM3_U
} >SRAM2_U
.confidential : ALIGN(512) {
*(.confidential*);
@ -146,8 +146,6 @@ SECTIONS {
.fb2 : ALIGN(4) {
*(.fb2*);
*(.gfxmmu_table*);
*(.framebuffer_select*);
. = ALIGN(4);
} >SRAM3

10
core/embed/sys/linker/stm32u5g/prodtest.ld
View File

@ -87,12 +87,12 @@ SECTIONS {
.stack : ALIGN(8) {
. = 12K; /* Overflow causes UsageFault */
} >SRAM2
} >SRAM5
.data : ALIGN(4) {
*(.data*);
. = ALIGN(512);
} >SRAM2 AT>FLASH
} >SRAM5 AT>FLASH
/DISCARD/ : {
*(.ARM.exidx*);
@ -102,7 +102,7 @@ SECTIONS {
*(.no_dma_buffers*);
*(.bss*);
. = ALIGN(4);
} >SRAM2
} >SRAM5
.confidential : ALIGN(512) {
*(.confidential*);
@ -116,15 +116,13 @@ SECTIONS {
.fb2 : ALIGN(4) {
*(.fb2*);
*(.gfxmmu_table*);
*(.framebuffer_select*);
. = ALIGN(4);
} >SRAM3
.buf : ALIGN(4) {
*(.buf*);
. = ALIGN(4);
} >SRAM2
} >SRAM5
.boot_args : ALIGN(8) {

8
core/embed/sys/mpu/inc/sys/mpu.h
View File

@ -67,15 +67,15 @@ mpu_mode_t mpu_reconfig(mpu_mode_t mode);
// Same as `mpu_reconfig()`, but with a more descriptive name.
void mpu_restore(mpu_mode_t mode);
// Sets the MPU to allow unprivileged access to the
// Sets the MPU to allow access to the
// framebuffer at the given address and size.
//
// The changes are made effective after the next MPU reconfiguration
// to the `MPU_MODE_APP` mode.
// to the `MPU_MODE_APP` or `MPU_MODE_DEFAULT` mode.
//
// Addr and size must be aligned to the 32-byte boundary.
// If addr == 0, the framebuffer is not accessible in the unprivileged mode.
void mpu_set_unpriv_fb(void* addr, size_t size);
// If addr == 0, the framebuffer is not accessible.
void mpu_set_active_fb(void* addr, size_t size);
#endif // KERNEL_MODE

2
core/embed/sys/mpu/stm32f4/mpu.c
View File

@ -206,7 +206,7 @@ mpu_mode_t mpu_get_mode(void) {
return drv->mode;
}
void mpu_set_unpriv_fb(void* addr, size_t size) {
void mpu_set_active_fb(void* addr, size_t size) {
// Not implemented on STM32F4
}

77
core/embed/sys/mpu/stm32u5/mpu.c
View File

@ -127,17 +127,6 @@ static void mpu_set_attributes(void) {
_Static_assert(NORCOW_SECTOR_SIZE == STORAGE_1_MAXSIZE, "norcow misconfigured");
_Static_assert(NORCOW_SECTOR_SIZE == STORAGE_2_MAXSIZE, "norcow misconfigured");
#if defined STM32U5A9xx
#define SRAM_SIZE (SRAM1_SIZE + SRAM2_SIZE + SRAM3_SIZE + SRAM5_SIZE)
#elif defined STM32U5G9xx
#define SRAM_SIZE \
(SRAM1_SIZE + SRAM2_SIZE + SRAM3_SIZE + SRAM5_SIZE + SRAM6_SIZE)
#elif defined STM32U585xx
#define SRAM_SIZE (SRAM1_SIZE + SRAM2_SIZE + SRAM3_SIZE)
#else
#error "Unknown MCU"
#endif
#ifdef STM32U585xx
// Two frame buffers at the end of SRAM3
#define GRAPHICS_START (SRAM3_BASE + SRAM3_SIZE - KERNEL_SRAM3_SIZE)
@ -161,9 +150,10 @@ _Static_assert(NORCOW_SECTOR_SIZE == STORAGE_2_MAXSIZE, "norcow misconfigured");
#define KERNEL_RAM_SIZE \
((KERNEL_SRAM1_SIZE + KERNEL_SRAM2_SIZE) - KERNEL_U_RAM_SIZE)
#else
#define KERNEL_RAM_START (SRAM1_BASE)
#define KERNEL_RAM_SIZE \
(SRAM1_SIZE + SRAM2_SIZE + SRAM3_SIZE - KERNEL_U_RAM_SIZE)
_Static_assert(KERNEL_SRAM1_SIZE == 0, "SRAM1 not supported in kernel");
_Static_assert(KERNEL_SRAM3_SIZE == 0, "SRAM3 not supported in kernel");
#define KERNEL_RAM_START (SRAM2_BASE - BOOTARGS_SIZE)
#define KERNEL_RAM_SIZE (BOOTARGS_SIZE + KERNEL_SRAM2_SIZE)
#endif
#ifdef SYSCALL_DISPATCH
@ -203,6 +193,20 @@ extern uint32_t _codelen;
#define COREAPP_RAM1_SIZE SRAM5_SIZE
#endif
#else
#ifdef STM32U585xx
#define MAIN_SRAM_START SRAM2_BASE
#define MAIN_SRAM_SIZE SRAM2_SIZE
#define AUX_SRAM_START SRAM1_BASE
#define AUX_SRAM_SIZE SRAM1_SIZE
#else
#define MAIN_SRAM_START SRAM2_BASE
#define MAIN_SRAM_SIZE SRAM2_SIZE
#define AUX_SRAM_START SRAM5_BASE
#define AUX_SRAM_SIZE SRAM5_SIZE
#endif
#endif
typedef struct {
@ -210,11 +214,11 @@ typedef struct {
bool initialized;
// Current mode
mpu_mode_t mode;
// Address of the framebuffer visible to unprivileged code
// Address of the active framebuffer
// (if set to 0, the framebuffer is not accessible)
uint32_t unpriv_fb_addr;
uint32_t active_fb_addr;
// Size of the framebuffer in bytes
size_t unpriv_fb_size;
size_t active_fb_size;
} mpu_driver_t;
@ -230,18 +234,18 @@ static void mpu_init_fixed_regions(void) {
#if defined(BOARDLOADER)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 0, BOARDLOADER_START, BOARDLOADER_MAXSIZE, FLASH_CODE, NO, NO );
SET_REGION( 1, SRAM1_BASE, SRAM_SIZE, SRAM, YES, NO );
SET_REGION( 1, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO );
SET_REGION( 2, BOOTLOADER_START, BOOTLOADER_MAXSIZE, FLASH_DATA, YES, NO );
SET_REGION( 3, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_DATA, YES, NO );
DIS_REGION( 4 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO );
#endif
#if defined(BOOTLOADER)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 0, BOOTLOADER_START, BOOTLOADER_MAXSIZE, FLASH_CODE, NO, NO );
SET_REGION( 1, SRAM1_BASE, SRAM_SIZE, SRAM, YES, NO );
SET_REGION( 1, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO );
SET_REGION( 2, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_DATA, YES, NO );
DIS_REGION( 3 );
DIS_REGION( 4 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO );
#endif
#if defined(KERNEL)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV
@ -258,17 +262,17 @@ static void mpu_init_fixed_regions(void) {
#if defined(FIRMWARE)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 0, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_CODE, NO, NO );
SET_REGION( 1, SRAM1_BASE, SRAM_SIZE, SRAM, YES, NO );
SET_REGION( 1, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO );
DIS_REGION( 2 );
DIS_REGION( 3 );
DIS_REGION( 4 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO );
#endif
#if defined(TREZOR_PRODTEST)
SET_REGION( 0, FIRMWARE_START, 1024, FLASH_DATA, YES, NO );
SET_REGION( 1, FIRMWARE_START + 1024, FIRMWARE_MAXSIZE - 1024, FLASH_CODE, NO, NO );
SET_REGION( 2, SRAM1_BASE, SRAM_SIZE, SRAM, YES, NO );
SET_REGION( 2, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO );
DIS_REGION( 3 );
DIS_REGION( 4 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO );
#endif
// Regions #6 and #7 are banked
@ -310,15 +314,21 @@ mpu_mode_t mpu_get_mode(void) {
return drv->mode;
}
void mpu_set_unpriv_fb(void* addr, size_t size) {
void mpu_set_active_fb(void* addr, size_t size) {
mpu_driver_t* drv = &g_mpu_driver;
if (!drv->initialized) {
return;
}
drv->unpriv_fb_addr = (uint32_t)addr;
drv->unpriv_fb_size = size;
irq_key_t lock = irq_lock();
drv->active_fb_addr = (uint32_t)addr;
drv->active_fb_size = size;
irq_unlock(lock);
mpu_reconfig(drv->mode);
}
mpu_mode_t mpu_reconfig(mpu_mode_t mode) {
@ -339,17 +349,22 @@ mpu_mode_t mpu_reconfig(mpu_mode_t mode) {
// clang-format off
switch (mode) {
case MPU_MODE_SAES:
// REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 5, PERIPH_BASE_NS, PERIPH_SIZE, PERIPHERAL, YES, YES ); // Peripherals - SAES, TAMP
break;
case MPU_MODE_APP:
if (drv->unpriv_fb_addr != 0) {
SET_REGRUN( 5, drv->unpriv_fb_addr, drv->unpriv_fb_size, SRAM, YES, YES ); // Frame buffer
if (drv->active_fb_addr != 0) {
SET_REGRUN( 5, drv->active_fb_addr, drv->active_fb_size, SRAM, YES, YES ); // Frame buffer
} else {
DIS_REGION( 5 );
}
break;
default:
SET_REGION( 5, GRAPHICS_START, GRAPHICS_SIZE, SRAM, YES, YES ); // Frame buffer or display interface
if (drv->active_fb_addr != 0) {
SET_REGRUN( 5, drv->active_fb_addr, drv->active_fb_size, SRAM, YES, NO ); // Frame buffer
} else {
DIS_REGION( 5 );
}
break;
}
// clang-format on