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fix(core): fix coreapp applet memory definition

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This commit is contained in:
cepetr 2025-03-03 16:33:10 +01:00 committed by cepetr
parent 2961f6caf9
commit 39245206f4
7 changed files with 16 additions and 16 deletions
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4
core/embed/models/D001/memory.ld
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@ -52,8 +52,6 @@ S_MAIN_RAM_START = 0x10004000;
S_MAIN_RAM_SIZE = 0xbf00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0xa000;
K_FB1_RAM_START = 0x1000c000;
K_FB1_RAM_SIZE = 0x0;
K_MAIN_RAM_START = 0x1000c000;
@ -64,5 +62,7 @@ DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x400;
AUX1_RAM_START = 0x20000400;
AUX1_RAM_SIZE = 0x2fc00;
AUX2_RAM_START = 0x10002000;
AUX2_RAM_SIZE = 0xa000;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

6
core/embed/models/D001/model_D001.h
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@ -102,9 +102,6 @@
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (40 * 1024)
#define K_FB1_RAM_START 0x1000C000
#define K_FB1_RAM_SIZE (0)
@ -121,6 +118,9 @@
#define AUX1_RAM_START (0x20000400)
#define AUX1_RAM_SIZE (191 * 1024)
#define AUX2_RAM_START 0x10002000
#define AUX2_RAM_SIZE (40 * 1024)
// misc
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200

4
core/embed/models/T2B1/memory.ld
View File

@ -56,8 +56,6 @@ S_MAIN_RAM_START = 0x10006000;
S_MAIN_RAM_SIZE = 0x9f00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0x8000;
K_FB1_RAM_START = 0x1000a000;
K_FB1_RAM_SIZE = 0x2000;
K_MAIN_RAM_START = 0x1000c000;
@ -68,5 +66,7 @@ DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x400;
AUX1_RAM_START = 0x20000400;
AUX1_RAM_SIZE = 0x2fc00;
AUX2_RAM_START = 0x10002000;
AUX2_RAM_SIZE = 0x8000;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

6
core/embed/models/T2B1/model_T2B1.h
View File

@ -108,9 +108,6 @@
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (32 * 1024)
#define K_FB1_RAM_START 0x1000A000
#define K_FB1_RAM_SIZE (8 * 1024)
@ -127,6 +124,9 @@
#define AUX1_RAM_START (0x20000400)
#define AUX1_RAM_SIZE (191 * 1024)
#define AUX2_RAM_START 0x10002000
#define AUX2_RAM_SIZE (32 * 1024)
// misc
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200

4
core/embed/models/T2T1/memory.ld
View File

@ -52,8 +52,6 @@ S_MAIN_RAM_START = 0x10004000;
S_MAIN_RAM_SIZE = 0xbf00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0xa000;
K_FB1_RAM_START = 0x1000c000;
K_FB1_RAM_SIZE = 0x0;
K_MAIN_RAM_START = 0x1000c000;
@ -64,5 +62,7 @@ DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x400;
AUX1_RAM_START = 0x20000400;
AUX1_RAM_SIZE = 0x2fc00;
AUX2_RAM_START = 0x10002000;
AUX2_RAM_SIZE = 0xa000;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

6
core/embed/models/T2T1/model_T2T1.h
View File

@ -103,9 +103,6 @@
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (40 * 1024)
#define K_FB1_RAM_START 0x1000C000
#define K_FB1_RAM_SIZE (0)
@ -122,6 +119,9 @@
#define AUX1_RAM_START (0x20000400)
#define AUX1_RAM_SIZE (191 * 1024)
#define AUX2_RAM_START 0x10002000
#define AUX2_RAM_SIZE (40 * 1024)
// misc
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200

2
core/embed/sys/linker/stm32f4/firmware.ld
View File

@ -6,7 +6,7 @@ MEMORY {
FLASH (rx) : ORIGIN = FIRMWARE_P1_START, LENGTH = FIRMWARE_P1_MAXSIZE
FLASH2 (r) : ORIGIN = FIRMWARE_P2_START, LENGTH = FIRMWARE_P2_MAXSIZE
AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
AUX2_RAM (wal) : ORIGIN = K_AUX2_RAM_START, LENGTH = K_AUX2_RAM_SIZE
AUX2_RAM (wal) : ORIGIN = AUX2_RAM_START, LENGTH = AUX2_RAM_SIZE
}
_stack_section_start = ADDR(.stack);