mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-11-12 18:49:07 +00:00
embed/firmware: add T1 display support, apply T1 fixes
This commit is contained in:
Pavol Rusnak
parent
066d4b4e9a
commit
2a06ff4986
@ -11,7 +11,9 @@ env:
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- PROTOBUF_VERSION=3.4.0
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matrix:
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- GOAL=stm32 TOOLCHAIN_SHORTVER=7-2018q2 TOOLCHAIN_LONGVER=gcc-arm-none-eabi-7-2018-q2-update
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- GOAL=stm32 TREZOR_MODEL=1 TOOLCHAIN_SHORTVER=7-2018q2 TOOLCHAIN_LONGVER=gcc-arm-none-eabi-7-2018-q2-update
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- GOAL=unix
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- GOAL=unix TREZOR_MODEL=1
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- GOAL=src
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matrix:
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@ -236,6 +236,7 @@ SOURCE_STMHAL = [
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c',
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c',
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c',
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c',
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c',
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c',
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'vendor/micropython/lib/stm32lib/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c',
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249
embed/extmod/modtrezorui/display-stm32_1.h
Normal file
249
embed/extmod/modtrezorui/display-stm32_1.h
Normal file
@ -0,0 +1,249 @@
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/*
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* This file is part of the TREZOR project, https://trezor.io/
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*
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* Copyright (c) SatoshiLabs
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include STM32_HAL_H
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#define OLED_BUFSIZE (DISPLAY_RESX * DISPLAY_RESY / 8)
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#define OLED_OFFSET(x, y) (OLED_BUFSIZE - 1 - (x) - ((y)/8) * DISPLAY_RESX)
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#define OLED_MASK(x, y) (1 << (7 - (y) % 8))
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#define OLED_SETCONTRAST 0x81
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#define OLED_DISPLAYALLON_RESUME 0xA4
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#define OLED_DISPLAYALLON 0xA5
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#define OLED_NORMALDISPLAY 0xA6
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#define OLED_INVERTDISPLAY 0xA7
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#define OLED_DISPLAYOFF 0xAE
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#define OLED_DISPLAYON 0xAF
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#define OLED_SETDISPLAYOFFSET 0xD3
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#define OLED_SETCOMPINS 0xDA
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#define OLED_SETVCOMDETECT 0xDB
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#define OLED_SETDISPLAYCLOCKDIV 0xD5
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#define OLED_SETPRECHARGE 0xD9
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#define OLED_SETMULTIPLEX 0xA8
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#define OLED_SETLOWCOLUMN 0x00
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#define OLED_SETHIGHCOLUMN 0x10
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#define OLED_SETSTARTLINE 0x40
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#define OLED_MEMORYMODE 0x20
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#define OLED_COMSCANINC 0xC0
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#define OLED_COMSCANDEC 0xC8
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#define OLED_SEGREMAP 0xA0
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#define OLED_CHARGEPUMP 0x8D
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#define OLED_DC_PORT GPIOB
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#define OLED_DC_PIN GPIO_PIN_0 // PB0 | Data/Command
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#define OLED_CS_PORT GPIOA
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#define OLED_CS_PIN GPIO_PIN_4 // PA4 | SPI Select
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#define OLED_RST_PORT GPIOB
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#define OLED_RST_PIN GPIO_PIN_1 // PB1 | Reset display
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static uint8_t OLED_BUFFER[OLED_BUFSIZE];
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static struct {
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struct {
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uint16_t x, y;
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} start;
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struct {
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uint16_t x, y;
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} end;
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struct {
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uint16_t x, y;
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} pos;
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} PIXELWINDOW;
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void PIXELDATA(uint16_t c) {
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if (PIXELWINDOW.pos.x <= PIXELWINDOW.end.x && PIXELWINDOW.pos.y <= PIXELWINDOW.end.y) {
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// set to white if highest bits of all R, G, B values are set to 1
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// bin(10000 100000 10000) = hex(0x8410)
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// otherwise set to black
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if (c & 0x8410) {
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OLED_BUFFER[OLED_OFFSET(PIXELWINDOW.pos.x, PIXELWINDOW.pos.y)] |= OLED_MASK(PIXELWINDOW.pos.x, PIXELWINDOW.pos.y);
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} else {
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OLED_BUFFER[OLED_OFFSET(PIXELWINDOW.pos.x, PIXELWINDOW.pos.y)] &= ~OLED_MASK(PIXELWINDOW.pos.x, PIXELWINDOW.pos.y);
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}
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}
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PIXELWINDOW.pos.x++;
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if (PIXELWINDOW.pos.x > PIXELWINDOW.end.x) {
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PIXELWINDOW.pos.x = PIXELWINDOW.start.x;
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PIXELWINDOW.pos.y++;
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}
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}
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static void display_set_window(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
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{
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PIXELWINDOW.start.x = x0; PIXELWINDOW.start.y = y0;
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PIXELWINDOW.end.x = x1; PIXELWINDOW.end.y = y1;
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PIXELWINDOW.pos.x = x0; PIXELWINDOW.pos.y = y0;
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}
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static void display_set_orientation(int degrees)
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{
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display_refresh();
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}
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static void display_set_backlight(int val)
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{
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}
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SPI_HandleTypeDef spi_handle;
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static inline void spi_send(const uint8_t *data, int len)
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{
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HAL_Delay(1);
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if (HAL_OK != HAL_SPI_Transmit(&spi_handle, (uint8_t *)data, len, 1000)) {
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// TODO: error
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return;
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}
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while (HAL_SPI_STATE_READY != HAL_SPI_GetState(&spi_handle)) {
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}
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}
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void display_init(void)
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{
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_SPI1_CLK_ENABLE();
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GPIO_InitTypeDef GPIO_InitStructure;
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// set GPIO for OLED display
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GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStructure.Pull = GPIO_NOPULL;
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GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStructure.Alternate = 0;
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GPIO_InitStructure.Pin = GPIO_PIN_4;
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HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_RESET);
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HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
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GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_4;
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HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0 | GPIO_PIN_4, GPIO_PIN_RESET);
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HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
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// enable SPI 1 for OLED display
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GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.Pull = GPIO_NOPULL;
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GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStructure.Alternate = GPIO_AF5_SPI1;
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GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_7;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
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spi_handle.Instance = SPI1;
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spi_handle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
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spi_handle.Init.Direction = SPI_DIRECTION_2LINES;
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spi_handle.Init.CLKPhase = SPI_PHASE_1EDGE;
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spi_handle.Init.CLKPolarity = SPI_POLARITY_LOW;
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spi_handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi_handle.Init.CRCPolynomial = 7;
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spi_handle.Init.DataSize = SPI_DATASIZE_8BIT;
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spi_handle.Init.FirstBit = SPI_FIRSTBIT_MSB;
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spi_handle.Init.NSS = SPI_NSS_HARD_OUTPUT;
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spi_handle.Init.TIMode = SPI_TIMODE_DISABLE;
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spi_handle.Init.Mode = SPI_MODE_MASTER;
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if (HAL_OK != HAL_SPI_Init(&spi_handle)) {
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// TODO: error
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return;
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}
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// initialize display
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static const uint8_t s[25] = {
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OLED_DISPLAYOFF,
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OLED_SETDISPLAYCLOCKDIV,
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0x80,
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OLED_SETMULTIPLEX,
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0x3F, // 128x64
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OLED_SETDISPLAYOFFSET,
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0x00,
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OLED_SETSTARTLINE | 0x00,
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OLED_CHARGEPUMP,
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0x14,
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OLED_MEMORYMODE,
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0x00,
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OLED_SEGREMAP | 0x01,
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OLED_COMSCANDEC,
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OLED_SETCOMPINS,
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0x12, // 128x64
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OLED_SETCONTRAST,
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0xCF,
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OLED_SETPRECHARGE,
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0xF1,
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OLED_SETVCOMDETECT,
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0x40,
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OLED_DISPLAYALLON_RESUME,
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OLED_NORMALDISPLAY,
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OLED_DISPLAYON
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};
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HAL_GPIO_WritePin(OLED_DC_PORT, OLED_DC_PIN, GPIO_PIN_RESET); // set to CMD
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_SET); // SPI deselect
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// Reset the LCD
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HAL_GPIO_WritePin(OLED_RST_PORT, OLED_RST_PIN, GPIO_PIN_SET);
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HAL_Delay(40);
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HAL_GPIO_WritePin(OLED_RST_PORT, OLED_RST_PIN, GPIO_PIN_RESET);
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HAL_Delay(400);
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HAL_GPIO_WritePin(OLED_RST_PORT, OLED_RST_PIN, GPIO_PIN_SET);
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// init
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_RESET); // SPI select
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spi_send(s, 25);
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_SET); // SPI deselect
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display_clear();
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display_refresh();
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}
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static inline uint8_t reverse_byte(uint8_t b) {
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b = (b & 0xF0) >> 4 | (b & 0x0F) << 4;
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b = (b & 0xCC) >> 2 | (b & 0x33) << 2;
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b = (b & 0xAA) >> 1 | (b & 0x55) << 1;
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return b;
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}
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static void rotate_oled_buffer(void)
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{
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for (int i = 0; i < OLED_BUFSIZE / 2; i++) {
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uint8_t b = OLED_BUFFER[i];
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OLED_BUFFER[i] = reverse_byte(OLED_BUFFER[OLED_BUFSIZE - i]);
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OLED_BUFFER[OLED_BUFSIZE - i] = reverse_byte(b);
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}
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}
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void display_refresh(void)
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{
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static const uint8_t s[3] = {OLED_SETLOWCOLUMN | 0x00, OLED_SETHIGHCOLUMN | 0x00, OLED_SETSTARTLINE | 0x00};
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_RESET); // SPI select
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spi_send(s, 3);
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_SET); // SPI deselect
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HAL_GPIO_WritePin(OLED_DC_PORT, OLED_DC_PIN, GPIO_PIN_SET); // set to DATA
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_RESET); // SPI select
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if (DISPLAY_ORIENTATION == 180) { // rotate buffer if needed
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rotate_oled_buffer();
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}
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spi_send(OLED_BUFFER, OLED_BUFSIZE);
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if (DISPLAY_ORIENTATION == 180) { // rotate buffer back to original position
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rotate_oled_buffer();
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}
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HAL_GPIO_WritePin(OLED_CS_PORT, OLED_CS_PIN, GPIO_PIN_SET); // SPI deselect
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HAL_GPIO_WritePin(OLED_DC_PORT, OLED_DC_PIN, GPIO_PIN_RESET); // set to CMD
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}
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void display_save(const char *prefix)
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{
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}
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@ -50,7 +50,11 @@ static struct {
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#ifdef TREZOR_EMULATOR
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#include "display-unix.h"
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#else
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#include "display-stm32.h"
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#if TREZOR_MODEL == T
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#include "display-stm32_t.h"
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#elif TREZOR_MODEL == 1
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#include "display-stm32_1.h"
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#endif
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#endif
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// common display functions
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@ -43,16 +43,30 @@
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int main(void)
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{
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// reinitialize HAL for Trezor One
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#if TREZOR_MODEL == 1
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HAL_Init();
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#endif
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#if TREZOR_MODEL == T
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// Enable MPU
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mpu_config();
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#endif
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// Init peripherals
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pendsv_init();
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#if TREZOR_MODEL == 1
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display_init();
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#endif
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#if TREZOR_MODEL == T
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sdcard_init();
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touch_init();
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touch_power_on();
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display_clear();
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#endif
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printf("CORE: Preparing stack\n");
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// Stack limit should be less than real stack size, so we have a chance
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@ -3,7 +3,7 @@
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x08040000, LENGTH = 768K
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FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 1024K - 64K
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SRAM (wal) : ORIGIN = 0x20000000, LENGTH = 128K
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}
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@ -16,8 +16,9 @@ data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to wipe memory */
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ccmram_start = 0;
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ccmram_end = 0;
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/* we have no CCMRAM, so erase the first word of SRAM as hack */
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ccmram_start = ORIGIN(SRAM);
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ccmram_end = ORIGIN(SRAM) + 4;
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/* used by the startup code to wipe memory */
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sram_start = ORIGIN(SRAM);
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@ -60,6 +60,10 @@
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#define FLASH_SECTOR_COUNT 24
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// note: FLASH_SR_RDERR is STM32F42xxx and STM32F43xxx specific (STM32F427) (reference RM0090 section 3.7.5)
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#ifndef FLASH_SR_RDERR
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#define FLASH_SR_RDERR 0
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#endif
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#define FLASH_STATUS_ALL_FLAGS (FLASH_SR_RDERR | FLASH_SR_PGSERR | FLASH_SR_PGPERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR | FLASH_SR_SOP | FLASH_SR_EOP)
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void flash_init(void);
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@ -57,19 +57,25 @@ void mpu_config(void)
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MPU->RBAR = FLASH_BASE | 0x100000 | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER4;
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MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO | MPU_SUBREGION_DISABLE(0x01);
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// CCMRAM (0x10000000 - 0x1000FFFF, read-write, execute never)
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MPU->RBAR = CCMDATARAM_BASE | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER5;
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MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM | LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk;
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// SRAM (0x20000000 - 0x2002FFFF, 192 KiB = 256 KiB except 2/8 at end, read-write, execute never)
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MPU->RBAR = SRAM_BASE | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER6;
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MPU->RBAR = SRAM_BASE | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER5;
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MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM | LL_MPU_REGION_SIZE_256KB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xC0);
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// Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
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// External RAM (0x60000000 - 0x7FFFFFFF, read-write, execute never)
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MPU->RBAR = PERIPH_BASE | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER7;
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MPU->RBAR = PERIPH_BASE | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER6;
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MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH | LL_MPU_REGION_SIZE_1GB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk;
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#ifdef STM32F427xx
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// CCMRAM (0x10000000 - 0x1000FFFF, read-write, execute never)
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MPU->RBAR = CCMDATARAM_BASE | MPU_RBAR_VALID_Msk | MPU_REGION_NUMBER7;
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MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM | LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk;
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#elif STM32F405xx
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// no CCMRAM
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#else
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#error Unsupported MCU
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#endif
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// Enable MPU
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HAL_MPU_Enable(0);
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}
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@ -24,7 +24,15 @@
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
|
||||
uint32_t SystemCoreClock = 168000000U;
|
||||
#ifdef STM32F427xx
|
||||
#define CORE_CLOCK_MHZ 168U
|
||||
#elif STM32F405xx
|
||||
#define CORE_CLOCK_MHZ 120U
|
||||
#else
|
||||
#error Unsupported MCU
|
||||
#endif
|
||||
|
||||
uint32_t SystemCoreClock = CORE_CLOCK_MHZ * 1000000U;
|
||||
|
||||
#pragma GCC optimize("no-stack-protector") // applies to all functions in this file
|
||||
|
||||
@ -36,11 +44,11 @@ void SystemInit(void)
|
||||
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_5WS);
|
||||
// configure main PLL; assumes HSE is 8 MHz; this should evaluate to 0x27402a04 -- reference RM0090 section 7.3.2
|
||||
RCC->PLLCFGR = (RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC & ~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM)
|
||||
| (7U << RCC_PLLCFGR_PLLQ_Pos) // Q = 7
|
||||
| RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
|
||||
| (0U << RCC_PLLCFGR_PLLP_Pos) // P = 2 (two bits, 00 means PLLP = 2)
|
||||
| (168U << RCC_PLLCFGR_PLLN_Pos) // N = 168
|
||||
| (4U << RCC_PLLCFGR_PLLM_Pos); // M = 4
|
||||
| (7U << RCC_PLLCFGR_PLLQ_Pos) // Q = 7
|
||||
| RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
|
||||
| (0U << RCC_PLLCFGR_PLLP_Pos) // P = 2 (two bits, 00 means PLLP = 2)
|
||||
| (CORE_CLOCK_MHZ << RCC_PLLCFGR_PLLN_Pos) // N = CORE_CLOCK_MHZ
|
||||
| (4U << RCC_PLLCFGR_PLLM_Pos); // M = 4
|
||||
// enable spread spectrum clock for main PLL
|
||||
RCC->SSCGR = RCC_SSCGR_SSCGEN | (44 << RCC_SSCGR_INCSTEP_Pos) | (250 << RCC_SSCGR_MODPER_Pos);
|
||||
// enable clock security system, HSE clock, and main PLL
|
||||
|
||||
Loading…
Reference in New Issue
Block a user