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setup: Enable MPU
Disable code execution from SRAM and reconfiguration of the MPU. Prevents almost all code execution attacks.
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@ -102,6 +102,11 @@ int main(void)
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}
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#endif
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#ifdef APPVER
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// enable MPU (Memory Protection Unit)
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mpu_config();
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#endif
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timer_init();
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#if DEBUG_LINK
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66
setup.c
66
setup.c
@ -17,16 +17,32 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/mpu.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scb.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/f2/rng.h>
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#include <libopencm3/stm32/rng.h>
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#include "rng.h"
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#include "layout.h"
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#include "memory.h"
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#include "util.h"
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#define MPU_RASR_SIZE_32B (0x04UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_128KB (0x10UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_256KB (0x11UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_512KB (0x12UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_LSB)
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// http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABDJJGF.html
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#define MPU_RASR_ATTR_FLASH (MPU_RASR_ATTR_C)
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#define MPU_RASR_ATTR_SRAM (MPU_RASR_ATTR_S | MPU_RASR_ATTR_C)
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#define MPU_RASR_ATTR_PERIPH (MPU_RASR_ATTR_S | MPU_RASR_ATTR_B)
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uint32_t __stack_chk_guard;
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static inline void __attribute__((noreturn)) fault_handler(const char *line1) {
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@ -46,6 +62,14 @@ void nmi_handler(void)
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}
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}
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void hard_fault_handler(void) {
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fault_handler("Hard fault");
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}
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void mem_manage_handler(void) {
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fault_handler("Memory fault");
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}
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void setup(void)
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{
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// set SCB_CCR STKALIGN bit to make sure 8-byte stack alignment on exception entry is in effect.
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@ -130,3 +154,43 @@ void setupApp(void)
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO10);
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gpio_set_af(GPIOA, GPIO_AF10, GPIO10);
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}
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// Never use in bootloader! Disables access to PPB (including MPU, NVIC, SCB)
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void mpu_config(void)
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{
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// Enable memory fault handler
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SCB_SHCSR |= SCB_SHCSR_MEMFAULTENA;
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// Disable MPU
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MPU_CTRL = 0;
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// Bootloader (read-only, execute never)
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MPU_RBAR = 0x08000000 | MPU_RBAR_VALID | (0 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_32KB | MPU_RASR_ATTR_AP_PRO_URO | MPU_RASR_ATTR_XN;
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// Metadata (read-write, execute never)
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MPU_RBAR = 0x08008000 | MPU_RBAR_VALID | (1 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_32KB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Firmware (read-only)
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MPU_RBAR = 0x08010000 | MPU_RBAR_VALID | (2 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_64KB | MPU_RASR_ATTR_AP_PRO_URO;
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MPU_RBAR = 0x08020000 | MPU_RBAR_VALID | (3 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_128KB | MPU_RASR_ATTR_AP_PRO_URO;
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MPU_RBAR = 0x08040000 | MPU_RBAR_VALID | (4 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_256KB | MPU_RASR_ATTR_AP_PRO_URO;
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// SRAM (read-write, execute never)
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MPU_RBAR = 0x20000000 | MPU_RBAR_VALID | (5 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_SRAM | MPU_RASR_SIZE_128KB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Peripherals (read-write, execute never)
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MPU_RBAR = PERIPH_BASE | MPU_RBAR_VALID | (6 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_512MB | MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Enable MPU
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MPU_CTRL = MPU_CTRL_ENABLE;
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__asm__ volatile("dsb");
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__asm__ volatile("isb");
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}
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