[no changelog]tychovrahe/coresplit/merged
tychovrahe
2 weeks ago
committed by
cepetr
parent
4df485aa03
commit
14a89de6da
@ -1,108 +0,0 @@
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/* Trezor v2 bootloader linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C010000, LENGTH = 128K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
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BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
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SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
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SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
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SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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confidential_lma = LOADADDR(.confidential);
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confidential_vma = ADDR(.confidential);
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confidential_size = SIZEOF(.confidential);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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bss_start = ADDR(.bss);
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bss_end = ADDR(.bss) + SIZEOF(.bss);
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
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SECTIONS {
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.buf : ALIGN(4) {
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*(.buf*);
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. = ALIGN(4);
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} >SRAM1
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.stack : ALIGN(8) {
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. = 16K; /* Exactly 16K allocated for stack. Overflow causes Usage fault. */
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} >SRAM2
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.confidential : ALIGN(512) {
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*(.confidential*);
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. = ALIGN(512);
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} >SRAM2 AT>FLASH
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.fb : ALIGN(4) {
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__fb_start = .;
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*(.fb1*);
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*(.fb2*);
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__fb_end = .;
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. = ALIGN(4);
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} >SRAM3
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.boot_args : ALIGN(8) {
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*(.boot_command*);
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. = ALIGN(8);
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*(.boot_args*);
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. = ALIGN(8);
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} >BOOT_ARGS
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}
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@ -1,112 +0,0 @@
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/* Trezor v2 bootloader linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C010000, LENGTH = 128K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 768K - 0x100
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BOOT_ARGS (wal) : ORIGIN = 0x300BFF00, LENGTH = 0x100
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SRAM2 (wal) : ORIGIN = 0x300C0000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x300D0000, LENGTH = 832K
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SRAM5 (wal) : ORIGIN = 0x301A0000, LENGTH = 832K
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SRAM6 (wal) : ORIGIN = 0x30270000, LENGTH = 0
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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confidential_lma = LOADADDR(.confidential);
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confidential_vma = ADDR(.confidential);
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confidential_size = SIZEOF(.confidential);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
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SECTIONS {
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(1024) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.buf : ALIGN(4) {
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*(.buf*);
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. = ALIGN(4);
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} >SRAM1
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.stack : ALIGN(8) {
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. = 16K; /* Overflow causes UsageFault */
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} >SRAM2
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.confidential : ALIGN(512) {
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*(.confidential*);
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. = ALIGN(512);
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} >SRAM2 AT>FLASH
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.fb1 : ALIGN(4) {
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__fb_start = .;
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*(.fb1*);
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*(.gfxmmu_table*);
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*(.framebuffer_select*);
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. = ALIGN(4);
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} >SRAM3
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.fb2 : ALIGN(4) {
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*(.fb2*);
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__fb_end = .;
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. = ALIGN(4);
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} >SRAM5
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.boot_args : ALIGN(8) {
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*(.boot_command*);
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. = ALIGN(8);
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*(.boot_args*);
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. = ALIGN(8);
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} >BOOT_ARGS
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}
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@ -1 +0,0 @@
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memory_T.ld
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@ -1 +0,0 @@
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memory_T.ld
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@ -1 +0,0 @@
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memory_T3T1.ld
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@ -1,74 +0,0 @@
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/* TREZORv1 firmware linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 1024K - 64K
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SRAM (wal) : ORIGIN = 0x20000000, LENGTH = 128K
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}
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main_stack_base = ORIGIN(SRAM) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to wipe memory */
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/* we have no CCMRAM, so erase the first word of SRAM as hack */
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ccmram_start = ORIGIN(SRAM);
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ccmram_end = ORIGIN(SRAM) + 4;
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/* used by the startup code to wipe memory */
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sram_start = ORIGIN(SRAM);
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sram_end = ORIGIN(SRAM) + LENGTH(SRAM);
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_ram_start = sram_start;
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_ram_end = sram_end;
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.exidx);
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_flash_start = ORIGIN(FLASH);
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_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
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_heap_start = ADDR(.heap);
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_heap_end = ADDR(.heap) + SIZEOF(.heap);
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SECTIONS {
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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/* exception handling info generated by llvm which should consist of 8 bytes of "cantunwind" */
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.exidx : ALIGN(4) {
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*(.ARM.exidx*);
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. = ALIGN(4);
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} >FLASH AT>FLASH
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.stack : ALIGN(8) {
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. = 16K; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */
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} >SRAM
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM AT>FLASH
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM
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.heap : ALIGN(4) {
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. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
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. = ABSOLUTE(sram_end - 8); /* this explicitly sets the end of the heap, T1 bootloader had 8 bytes reserved at end */
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} >SRAM
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}
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@ -1,74 +0,0 @@
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/* TREZORv1 firmware linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 1024K - 64K
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SRAM (wal) : ORIGIN = 0x20000000, LENGTH = 128K
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}
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main_stack_base = ORIGIN(SRAM) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to wipe memory */
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/* we have no CCMRAM, so erase the first word of SRAM as hack */
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ccmram_start = ORIGIN(SRAM);
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ccmram_end = ORIGIN(SRAM) + 4;
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/* used by the startup code to wipe memory */
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sram_start = ORIGIN(SRAM);
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sram_end = ORIGIN(SRAM) + LENGTH(SRAM);
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_ram_start = sram_start;
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_ram_end = sram_end;
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.exidx);
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_flash_start = ORIGIN(FLASH);
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_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
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_heap_start = ADDR(.heap);
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_heap_end = ADDR(.heap) + SIZEOF(.heap);
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SECTIONS {
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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/* exception handling info generated by llvm which should consist of 8 bytes of "cantunwind" */
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.exidx : ALIGN(4) {
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*(.ARM.exidx*);
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. = ALIGN(4);
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} >FLASH AT>FLASH
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.stack : ALIGN(8) {
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. = 16K; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */
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} >SRAM
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM AT>FLASH
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM
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.heap : ALIGN(4) {
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. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
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. = ABSOLUTE(sram_end - 8); /* this explicitly sets the end of the heap, T1 bootloader had 8 bytes reserved at end */
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} >SRAM
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}
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@ -1 +0,0 @@
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memory_T.ld
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@ -1 +0,0 @@
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memory_T.ld
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@ -1 +0,0 @@
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memory_T3T1.ld
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@ -1,54 +0,0 @@
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.syntax unified
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#include "version.h"
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.section .header, "a"
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.type g_header, %object
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.size g_header, .-g_header
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// Firmware header for both Trezor One and Trezor T.
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// Trezor One must have bootloader version >= 1.8.0 (before that version the hdrlen used to be reset vector)
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g_header:
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.byte 'T','R','Z','F' // magic
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.word g_header_end - g_header // hdrlen
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#ifdef TREZOR_MODEL_T
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.word 0 // expiry
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#else
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.word 1 // expiry
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#endif
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.word _codelen // codelen
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.byte VERSION_MAJOR // vmajor
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.byte VERSION_MINOR // vminor
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.byte VERSION_PATCH // vpatch
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.byte VERSION_BUILD // vbuild
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.byte FIX_VERSION_MAJOR // fix_vmajor
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.byte FIX_VERSION_MINOR // fix_vminor
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.byte FIX_VERSION_PATCH // fix_vpatch
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.byte FIX_VERSION_BUILD // fix_vbuild
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.word HW_MODEL // type of the designated hardware
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.byte HW_REVISION // revision of the designated hardware
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.byte VERSION_MONOTONIC // monotonic version of the binary
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. = . + 2 // reserved
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. = . + 512 // hash1 ... hash16
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#if !defined TREZOR_MODEL_1
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// trezor-core header style
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. = . + 415 // reserved
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.byte 0 // sigmask
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. = . + 64 // sig
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#else
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// model 1 compatibility header
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. = . + 64 // sig1
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. = . + 64 // sig2
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. = . + 64 // sig3
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.byte 0 // sigindex1
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.byte 0 // sigindex2
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.byte 0 // sigindex3
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. = . + 220 // reserved
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. = . + 65 // reserved
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#endif
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g_header_end:
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@ -0,0 +1,46 @@
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.syntax unified
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.text
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.global reset_handler
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.type reset_handler, STT_FUNC
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reset_handler:
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// setup environment for subsequent stage of code
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ldr r0, =ccmram_start // r0 - point to beginning of CCMRAM
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ldr r1, =ccmram_end // r1 - point to byte after the end of CCMRAM
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ldr r2, =0 // r2 - the word-sized value to be written
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bl memset_reg
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ldr r0, =boot_args_start // r0 - point to beginning of BOOT_ARGS
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ldr r1, =boot_args_end // r1 - point to byte after the end of BOOT_ARGS
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ldr r2, =0 // r2 - the word-sized value to be written
|
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bl memset_reg
|
||||
|
||||
ldr r0, =sram_start // r0 - point to beginning of SRAM
|
||||
ldr r1, =sram_end // r1 - point to byte after the end of SRAM
|
||||
ldr r2, =0 // r2 - the word-sized value to be written
|
||||
bl memset_reg
|
||||
|
||||
// copy data in from flash
|
||||
ldr r0, =data_vma // dst addr
|
||||
ldr r1, =data_lma // src addr
|
||||
ldr r2, =data_size // size in bytes
|
||||
bl memcpy
|
||||
|
||||
// setup the stack protector (see build script "-fstack-protector-all") with an unpredictable value
|
||||
bl rng_get
|
||||
ldr r1, = __stack_chk_guard
|
||||
str r0, [r1]
|
||||
|
||||
// re-enable exceptions
|
||||
// according to "ARM Cortex-M Programming Guide to Memory Barrier Instructions" Application Note 321, section 4.7:
|
||||
// "If it is not necessary to ensure that a pended interrupt is recognized immediately before
|
||||
// subsequent operations, it is not necessary to insert a memory barrier instruction."
|
||||
cpsie f
|
||||
|
||||
// enter the application code
|
||||
bl main
|
||||
|
||||
b shutdown_privileged
|
||||
|
||||
.end
|
||||
@ -0,0 +1,25 @@
|
||||
FLASH_START = 0x8000000;
|
||||
BOARDLOADER_START = 0x8000000;
|
||||
BOOTLOADER_START = 0x8020000;
|
||||
FIRMWARE_START = 0x8040000;
|
||||
FIRMWARE_P2_START = 0x8120000;
|
||||
STORAGE_1_OFFSET = 0x10000;
|
||||
STORAGE_2_OFFSET = 0x110000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOARDLOADER_IMAGE_MAXSIZE = 0xc000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x20000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0x1a0000;
|
||||
FIRMWARE_P1_IMAGE_MAXSIZE = 0xc0000;
|
||||
FIRMWARE_P2_IMAGE_MAXSIZE = 0xe0000;
|
||||
BOARDLOADER_SECTOR_START = 0x0;
|
||||
BOARDLOADER_SECTOR_END = 0x3;
|
||||
BOOTLOADER_SECTOR_START = 0x5;
|
||||
BOOTLOADER_SECTOR_END = 0x5;
|
||||
FIRMWARE_SECTOR_START = 0x6;
|
||||
FIRMWARE_SECTOR_END = 0xb;
|
||||
FIRMWARE_P2_SECTOR_START = 0x11;
|
||||
FIRMWARE_P2_SECTOR_END = 0x17;
|
||||
STORAGE_1_SECTOR_START = 0x4;
|
||||
STORAGE_1_SECTOR_END = 0x4;
|
||||
STORAGE_2_SECTOR_START = 0x10;
|
||||
STORAGE_2_SECTOR_END = 0x10;
|
||||
@ -0,0 +1,30 @@
|
||||
FLASH_START = 0xc000000;
|
||||
BOARDLOADER_START = 0xc004000;
|
||||
BOOTLOADER_START = 0xc010000;
|
||||
KERNEL_START = 0xc050000;
|
||||
FIRMWARE_START = 0xc050000;
|
||||
STORAGE_1_OFFSET = 0x30000;
|
||||
STORAGE_2_OFFSET = 0x50000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOARDLOADER_IMAGE_MAXSIZE = 0xc000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x20000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0x3a0000;
|
||||
KERNEL_IMAGE_MAXSIZE = 0x80000;
|
||||
BOARDLOADER_SECTOR_START = 0x2;
|
||||
BOARDLOADER_SECTOR_END = 0x7;
|
||||
BOOTLOADER_SECTOR_START = 0x8;
|
||||
BOOTLOADER_SECTOR_END = 0x17;
|
||||
FIRMWARE_SECTOR_START = 0x28;
|
||||
FIRMWARE_SECTOR_END = 0x1f7;
|
||||
STORAGE_1_SECTOR_START = 0x18;
|
||||
STORAGE_1_SECTOR_END = 0x1f;
|
||||
STORAGE_2_SECTOR_START = 0x20;
|
||||
STORAGE_2_SECTOR_END = 0x27;
|
||||
KERNEL_U_FLASH_SIZE = 0x200;
|
||||
KERNEL_U_RAM_SIZE = 0x200;
|
||||
KERNEL_SRAM1_SIZE = 0x4000;
|
||||
KERNEL_SRAM2_SIZE = 0x2400;
|
||||
KERNEL_SRAM3_SIZE = 0xbb800;
|
||||
BOOTARGS_SIZE = 0x100;
|
||||
BOARD_CAPABILITIES_ADDR = 0xc00ff00;
|
||||
CODE_ALIGNMENT = 0x400;
|
||||
@ -0,0 +1,14 @@
|
||||
FLASH_START = 0x8000000;
|
||||
BOOTLOADER_START = 0x8000000;
|
||||
FIRMWARE_START = 0x8010000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x8000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0xf0000;
|
||||
BOOTLOADER_SECTOR_START = 0x0;
|
||||
BOOTLOADER_SECTOR_END = 0x2;
|
||||
FIRMWARE_SECTOR_START = 0x4;
|
||||
FIRMWARE_SECTOR_END = 0xb;
|
||||
STORAGE_1_SECTOR_START = 0x2;
|
||||
STORAGE_1_SECTOR_END = 0x2;
|
||||
STORAGE_2_SECTOR_START = 0x3;
|
||||
STORAGE_2_SECTOR_END = 0x3;
|
||||
@ -0,0 +1,30 @@
|
||||
FLASH_START = 0x8000000;
|
||||
BOARDLOADER_START = 0x8000000;
|
||||
BOOTLOADER_START = 0x8020000;
|
||||
FIRMWARE_START = 0x8040000;
|
||||
FIRMWARE_P2_START = 0x8120000;
|
||||
KERNEL_START = 0x8040000;
|
||||
STORAGE_1_OFFSET = 0x10000;
|
||||
STORAGE_2_OFFSET = 0x110000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOARDLOADER_IMAGE_MAXSIZE = 0xc000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x20000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0x1a0000;
|
||||
FIRMWARE_P1_IMAGE_MAXSIZE = 0xc0000;
|
||||
FIRMWARE_P2_IMAGE_MAXSIZE = 0xe0000;
|
||||
KERNEL_IMAGE_MAXSIZE = 0x80000;
|
||||
BOARDLOADER_SECTOR_START = 0x0;
|
||||
BOARDLOADER_SECTOR_END = 0x3;
|
||||
BOOTLOADER_SECTOR_START = 0x5;
|
||||
BOOTLOADER_SECTOR_END = 0x5;
|
||||
FIRMWARE_SECTOR_START = 0x6;
|
||||
FIRMWARE_SECTOR_END = 0xb;
|
||||
FIRMWARE_P2_SECTOR_START = 0x11;
|
||||
FIRMWARE_P2_SECTOR_END = 0x17;
|
||||
STORAGE_1_SECTOR_START = 0x4;
|
||||
STORAGE_1_SECTOR_END = 0x4;
|
||||
STORAGE_2_SECTOR_START = 0x10;
|
||||
STORAGE_2_SECTOR_END = 0x10;
|
||||
BOOTARGS_SIZE = 0x100;
|
||||
BOARD_CAPABILITIES_ADDR = 0x800bf00;
|
||||
CODE_ALIGNMENT = 0x200;
|
||||
@ -0,0 +1,32 @@
|
||||
FLASH_START = 0x8000000;
|
||||
BOARDLOADER_START = 0x8000000;
|
||||
BOOTLOADER_START = 0x8020000;
|
||||
FIRMWARE_START = 0x8040000;
|
||||
FIRMWARE_P2_START = 0x8120000;
|
||||
KERNEL_START = 0x8040000;
|
||||
STORAGE_1_OFFSET = 0x10000;
|
||||
STORAGE_2_OFFSET = 0x110000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOARDLOADER_IMAGE_MAXSIZE = 0xc000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x20000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0x1a0000;
|
||||
FIRMWARE_P1_IMAGE_MAXSIZE = 0xc0000;
|
||||
FIRMWARE_P2_IMAGE_MAXSIZE = 0xe0000;
|
||||
KERNEL_IMAGE_MAXSIZE = 0x80000;
|
||||
BOARDLOADER_SECTOR_START = 0x0;
|
||||
BOARDLOADER_SECTOR_END = 0x3;
|
||||
BOOTLOADER_SECTOR_START = 0x5;
|
||||
BOOTLOADER_SECTOR_END = 0x5;
|
||||
FIRMWARE_SECTOR_START = 0x6;
|
||||
FIRMWARE_SECTOR_END = 0xb;
|
||||
FIRMWARE_P2_SECTOR_START = 0x11;
|
||||
FIRMWARE_P2_SECTOR_END = 0x17;
|
||||
STORAGE_1_SECTOR_START = 0x4;
|
||||
STORAGE_1_SECTOR_END = 0x4;
|
||||
STORAGE_2_SECTOR_START = 0x10;
|
||||
STORAGE_2_SECTOR_END = 0x10;
|
||||
KERNEL_CCMRAM_SIZE = 0x4000;
|
||||
KERNEL_SRAM_SIZE = 0x0;
|
||||
BOOTARGS_SIZE = 0x100;
|
||||
BOARD_CAPABILITIES_ADDR = 0x800bf00;
|
||||
CODE_ALIGNMENT = 0x200;
|
||||
@ -0,0 +1,30 @@
|
||||
FLASH_START = 0xc000000;
|
||||
BOARDLOADER_START = 0xc004000;
|
||||
BOOTLOADER_START = 0xc010000;
|
||||
KERNEL_START = 0xc050000;
|
||||
FIRMWARE_START = 0xc050000;
|
||||
STORAGE_1_OFFSET = 0x30000;
|
||||
STORAGE_2_OFFSET = 0x50000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOARDLOADER_IMAGE_MAXSIZE = 0xc000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x20000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0x1a0000;
|
||||
KERNEL_IMAGE_MAXSIZE = 0x80000;
|
||||
BOARDLOADER_SECTOR_START = 0x2;
|
||||
BOARDLOADER_SECTOR_END = 0x7;
|
||||
BOOTLOADER_SECTOR_START = 0x8;
|
||||
BOOTLOADER_SECTOR_END = 0x17;
|
||||
FIRMWARE_SECTOR_START = 0x28;
|
||||
FIRMWARE_SECTOR_END = 0xf7;
|
||||
STORAGE_1_SECTOR_START = 0x18;
|
||||
STORAGE_1_SECTOR_END = 0x1f;
|
||||
STORAGE_2_SECTOR_START = 0x20;
|
||||
STORAGE_2_SECTOR_END = 0x27;
|
||||
KERNEL_U_FLASH_SIZE = 0x200;
|
||||
KERNEL_U_RAM_SIZE = 0x200;
|
||||
KERNEL_SRAM1_SIZE = 0x4000;
|
||||
KERNEL_SRAM2_SIZE = 0x2000;
|
||||
KERNEL_SRAM3_SIZE = 0x38400;
|
||||
BOOTARGS_SIZE = 0x100;
|
||||
BOARD_CAPABILITIES_ADDR = 0xc00ff00;
|
||||
CODE_ALIGNMENT = 0x200;
|
||||
@ -0,0 +1,30 @@
|
||||
FLASH_START = 0xc000000;
|
||||
BOARDLOADER_START = 0xc004000;
|
||||
BOOTLOADER_START = 0xc010000;
|
||||
KERNEL_START = 0xc050000;
|
||||
FIRMWARE_START = 0xc050000;
|
||||
STORAGE_1_OFFSET = 0x30000;
|
||||
STORAGE_2_OFFSET = 0x50000;
|
||||
NORCOW_SECTOR_SIZE = 0x10000;
|
||||
BOARDLOADER_IMAGE_MAXSIZE = 0xc000;
|
||||
BOOTLOADER_IMAGE_MAXSIZE = 0x20000;
|
||||
FIRMWARE_IMAGE_MAXSIZE = 0x1a0000;
|
||||
KERNEL_IMAGE_MAXSIZE = 0x80000;
|
||||
BOARDLOADER_SECTOR_START = 0x2;
|
||||
BOARDLOADER_SECTOR_END = 0x7;
|
||||
BOOTLOADER_SECTOR_START = 0x8;
|
||||
BOOTLOADER_SECTOR_END = 0x17;
|
||||
FIRMWARE_SECTOR_START = 0x28;
|
||||
FIRMWARE_SECTOR_END = 0xf7;
|
||||
STORAGE_1_SECTOR_START = 0x18;
|
||||
STORAGE_1_SECTOR_END = 0x1f;
|
||||
STORAGE_2_SECTOR_START = 0x20;
|
||||
STORAGE_2_SECTOR_END = 0x27;
|
||||
KERNEL_U_FLASH_SIZE = 0x200;
|
||||
KERNEL_U_RAM_SIZE = 0x200;
|
||||
KERNEL_SRAM1_SIZE = 0x4000;
|
||||
KERNEL_SRAM2_SIZE = 0x2000;
|
||||
KERNEL_SRAM3_SIZE = 0x38400;
|
||||
BOOTARGS_SIZE = 0x100;
|
||||
BOARD_CAPABILITIES_ADDR = 0xc00ff00;
|
||||
CODE_ALIGNMENT = 0x200;
|
||||
@ -1,127 +0,0 @@
|
||||
/* TREZORv2 firmware linker script */
|
||||
|
||||
ENTRY(reset_handler)
|
||||
|
||||
MEMORY {
|
||||
FLASH (rx) : ORIGIN = 0x0C050000, LENGTH = 3648K
|
||||
SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 768K - 0x100
|
||||
BOOT_ARGS (wal) : ORIGIN = 0x300BFF00, LENGTH = 0x100
|
||||
SRAM2 (wal) : ORIGIN = 0x300C0000, LENGTH = 64K
|
||||
SRAM3 (wal) : ORIGIN = 0x300D0000, LENGTH = 832K
|
||||
SRAM5 (wal) : ORIGIN = 0x301A0000, LENGTH = 832K
|
||||
SRAM6 (wal) : ORIGIN = 0x30270000, LENGTH = 0
|
||||
SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
|
||||
_sstack = ORIGIN(SRAM2);
|
||||
_estack = main_stack_base;
|
||||
|
||||
/* used by the startup code to populate variables used by the C code */
|
||||
data_lma = LOADADDR(.data);
|
||||
data_vma = ADDR(.data);
|
||||
data_size = SIZEOF(.data);
|
||||
|
||||
/* used by the startup code to populate variables used by the C code */
|
||||
confidential_lma = LOADADDR(.confidential);
|
||||
confidential_vma = ADDR(.confidential);
|
||||
confidential_size = SIZEOF(.confidential);
|
||||
|
||||
/* used by the startup code to wipe memory */
|
||||
sram1_start = ORIGIN(SRAM1);
|
||||
sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
|
||||
sram2_start = ORIGIN(SRAM2);
|
||||
sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
|
||||
sram3_start = ORIGIN(SRAM3);
|
||||
sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
|
||||
sram4_start = ORIGIN(SRAM4);
|
||||
sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
|
||||
sram5_start = ORIGIN(SRAM5);
|
||||
sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
|
||||
sram6_start = ORIGIN(SRAM6);
|
||||
sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
|
||||
|
||||
/* reserve 256 bytes for bootloader arguments */
|
||||
boot_args_start = ORIGIN(BOOT_ARGS);
|
||||
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
|
||||
_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
|
||||
_flash_start = ORIGIN(FLASH);
|
||||
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
|
||||
_heap_start = ADDR(.heap);
|
||||
_heap_end = ADDR(.heap) + SIZEOF(.heap);
|
||||
|
||||
SECTIONS {
|
||||
.vendorheader : ALIGN(4) {
|
||||
KEEP(*(.vendorheader))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.header : ALIGN(4) {
|
||||
KEEP(*(.header));
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.flash : ALIGN(1024) {
|
||||
KEEP(*(.vector_table));
|
||||
. = ALIGN(4);
|
||||
*(.text*);
|
||||
. = ALIGN(4);
|
||||
*(.rodata*);
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.bootloader));
|
||||
*(.bootloader*);
|
||||
. = ALIGN(512);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data : ALIGN(4) {
|
||||
*(.data*);
|
||||
. = ALIGN(512);
|
||||
} >SRAM1 AT>FLASH
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.ARM.exidx*);
|
||||
}
|
||||
|
||||
.bss : ALIGN(4) {
|
||||
*(.bss*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM1
|
||||
|
||||
.data_ccm : ALIGN(4) {
|
||||
*(.no_dma_buffers*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM1
|
||||
|
||||
.heap : ALIGN(4) {
|
||||
. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
|
||||
. = ABSOLUTE(sram1_end); /* this explicitly sets the end of the heap */
|
||||
} >SRAM1
|
||||
|
||||
.stack : ALIGN(8) {
|
||||
. = 16K; /* Overflow causes UsageFault */
|
||||
} >SRAM2
|
||||
|
||||
.confidential : ALIGN(512) {
|
||||
*(.confidential*);
|
||||
. = ALIGN(512);
|
||||
} >SRAM2 AT>FLASH
|
||||
|
||||
.fb1 : ALIGN(4) {
|
||||
__fb_start = .;
|
||||
*(.fb1*);
|
||||
*(.gfxmmu_table*);
|
||||
*(.framebuffer_select*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM3
|
||||
|
||||
.fb2 : ALIGN(4) {
|
||||
*(.fb2*);
|
||||
__fb_end = .;
|
||||
. = ALIGN(4);
|
||||
} >SRAM5
|
||||
|
||||
.boot_args : ALIGN(8) {
|
||||
*(.boot_command*);
|
||||
. = ALIGN(8);
|
||||
*(.boot_args*);
|
||||
. = ALIGN(8);
|
||||
} >BOOT_ARGS
|
||||
}
|
||||
@ -0,0 +1,6 @@
|
||||
MCU_FLASH_ORIGIN = 0x08000000;
|
||||
MCU_FLASH_SIZE = 2M;
|
||||
MCU_CCMRAM = 0x10000000;
|
||||
MCU_CCMRAM_SIZE = 64K;
|
||||
MCU_SRAM = 0x20000000;
|
||||
MCU_SRAM_SIZE = 192K;
|
||||
@ -0,0 +1,143 @@
|
||||
INCLUDE "./embed/trezorhal/stm32u5/linker/u58/memory.ld";
|
||||
|
||||
ENTRY(reset_handler)
|
||||
|
||||
MEMORY {
|
||||
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_IMAGE_MAXSIZE
|
||||
SRAM1 (wal) : ORIGIN = MCU_SRAM2 - KERNEL_SRAM1_SIZE, LENGTH = KERNEL_SRAM1_SIZE - BOOTARGS_SIZE
|
||||
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE
|
||||
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE
|
||||
SRAM2_U (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE, LENGTH = KERNEL_U_RAM_SIZE
|
||||
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = KERNEL_SRAM3_SIZE
|
||||
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */
|
||||
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */
|
||||
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE
|
||||
}
|
||||
|
||||
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
|
||||
_sstack = ORIGIN(SRAM2);
|
||||
_estack = main_stack_base;
|
||||
|
||||
ustack_base = ORIGIN(SRAM2_U) + 512;
|
||||
_sustack = ORIGIN(SRAM2_U) + 256;
|
||||
_eustack = ustack_base;
|
||||
|
||||
/* used by the startup code to populate variables used by the C code */
|
||||
data_lma = LOADADDR(.data);
|
||||
data_vma = ADDR(.data);
|
||||
data_size = SIZEOF(.data);
|
||||
bss_start = ADDR(.bss);
|
||||
bss_end = ADDR(.bss) + SIZEOF(.bss);
|
||||
|
||||
/* used by the startup code to populate variables used by the C code */
|
||||
confidential_lma = LOADADDR(.confidential);
|
||||
confidential_vma = ADDR(.confidential);
|
||||
confidential_size = SIZEOF(.confidential);
|
||||
|
||||
/* used by the startup code to wipe memory */
|
||||
sram1_start = ORIGIN(SRAM1);
|
||||
sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
|
||||
sram2_start = ORIGIN(SRAM2);
|
||||
sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
|
||||
sram2_u_start = ORIGIN(SRAM2_U);
|
||||
sram2_u_end = ORIGIN(SRAM2_U) + LENGTH(SRAM2_U);
|
||||
sram3_start = ORIGIN(SRAM3);
|
||||
sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
|
||||
sram4_start = ORIGIN(SRAM4);
|
||||
sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
|
||||
sram5_start = ORIGIN(SRAM5);
|
||||
sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
|
||||
sram6_start = ORIGIN(SRAM6);
|
||||
sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
|
||||
|
||||
/* reserve 256 bytes for bootloader arguments */
|
||||
boot_args_start = ORIGIN(BOOT_ARGS);
|
||||
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
|
||||
|
||||
_codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.uflash) + SIZEOF(.data) + SIZEOF(.confidential);
|
||||
_flash_start = ORIGIN(FLASH);
|
||||
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
|
||||
|
||||
_uflash_start = ADDR(.uflash);
|
||||
_uflash_end = ADDR(.uflash) + SIZEOF(.uflash);
|
||||
|
||||
SECTIONS {
|
||||
.vendorheader : ALIGN(4) {
|
||||
KEEP(*(.vendorheader))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.header : ALIGN(4) {
|
||||
. = 1K;
|
||||
. = ALIGN(CODE_ALIGNMENT);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.flash : ALIGN(CODE_ALIGNMENT) {
|
||||
KEEP(*(.vector_table));
|
||||
. = ALIGN(4);
|
||||
*(.text*);
|
||||
. = ALIGN(4);
|
||||
*(.rodata*);
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.bootloader));
|
||||
*(.bootloader*);
|
||||
. = ALIGN(512);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data : ALIGN(4) {
|
||||
*(.data*);
|
||||
. = ALIGN(512);
|
||||
} >SRAM1 AT>FLASH
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.ARM.exidx*);
|
||||
}
|
||||
|
||||
.bss : ALIGN(4) {
|
||||
*(.no_dma_buffers*);
|
||||
*(.bss*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM1
|
||||
|
||||
.stack : ALIGN(8) {
|
||||
. = 6K; /* Overflow causes UsageFault */
|
||||
} >SRAM2
|
||||
|
||||
/* unprivileged data and stack for SAES */
|
||||
.udata : ALIGN(512) {
|
||||
*(.udata*);
|
||||
. = ALIGN(256);
|
||||
. = 256; /* Overflow causes UsageFault */
|
||||
} >SRAM2_U
|
||||
|
||||
.confidential : ALIGN(512) {
|
||||
*(.confidential*);
|
||||
. = ALIGN(CODE_ALIGNMENT);
|
||||
} >SRAM2 AT>FLASH
|
||||
|
||||
.uflash : ALIGN(512) {
|
||||
*(.uflash*);
|
||||
. = ALIGN(512);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fb : ALIGN(4) {
|
||||
__fb_start = .;
|
||||
*(.fb1*);
|
||||
*(.fb2*);
|
||||
*(.framebuffer_select*);
|
||||
__fb_end = .;
|
||||
. = ALIGN(4);
|
||||
} >SRAM3
|
||||
|
||||
.buf : ALIGN(4) {
|
||||
*(.buf*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM3
|
||||
|
||||
|
||||
.boot_args : ALIGN(8) {
|
||||
*(.boot_command*);
|
||||
. = ALIGN(8);
|
||||
*(.boot_args*);
|
||||
. = ALIGN(8);
|
||||
} >BOOT_ARGS
|
||||
}
|
||||
@ -0,0 +1,18 @@
|
||||
|
||||
|
||||
MCU_FLASH_S_ORIGIN = 0x0C000000;
|
||||
MCU_FLASH_ORIGIN = 0x08000000;
|
||||
MCU_FLASH_SIZE = 2M;
|
||||
|
||||
MCU_SRAM1 = 0x30000000;
|
||||
MCU_SRAM1_SIZE = 192K;
|
||||
MCU_SRAM2 = 0x30030000;
|
||||
MCU_SRAM2_SIZE = 64K;
|
||||
MCU_SRAM3 = 0x30040000;
|
||||
MCU_SRAM3_SIZE = 512K;
|
||||
MCU_SRAM4 = 0x38000000;
|
||||
MCU_SRAM4_SIZE = 16K;
|
||||
MCU_SRAM5 = 0x30080000;
|
||||
MCU_SRAM5_SIZE = 0K; /* SRAM5 is not available */
|
||||
MCU_SRAM6 = 0x30080000;
|
||||
MCU_SRAM6_SIZE = 0K ; /* SRAM6 is not available */
|
||||
@ -0,0 +1,18 @@
|
||||
|
||||
|
||||
MCU_FLASH_S_ORIGIN = 0x0C000000;
|
||||
MCU_FLASH_ORIGIN = 0x08000000;
|
||||
MCU_FLASH_SIZE = 2M;
|
||||
|
||||
MCU_SRAM1 = 0x30000000;
|
||||
MCU_SRAM1_SIZE = 768K;
|
||||
MCU_SRAM2 = 0x300C0000;
|
||||
MCU_SRAM2_SIZE = 64K;
|
||||
MCU_SRAM3 = 0x300D0000;
|
||||
MCU_SRAM3_SIZE = 832K;
|
||||
MCU_SRAM4 = 0x38000000;
|
||||
MCU_SRAM4_SIZE = 16K;
|
||||
MCU_SRAM5 = 0x301A0000;
|
||||
MCU_SRAM5_SIZE = 832K;
|
||||
MCU_SRAM6 = 0x30270000;
|
||||
MCU_SRAM6_SIZE = 0K ;
|
||||
@ -0,0 +1,29 @@
|
||||
#!/usr/bin/env python3
|
||||
from __future__ import annotations
|
||||
|
||||
import click
|
||||
|
||||
from .common import get_linkerscript_for_model, MODELS_DIR
|
||||
from .layout_parser import find_all_values
|
||||
|
||||
@click.command()
|
||||
@click.option("--check", is_flag=True)
|
||||
def main(check: bool) -> None:
|
||||
|
||||
models = list(MODELS_DIR.iterdir())
|
||||
models = [model for model in models if model.is_dir()]
|
||||
|
||||
for model in models:
|
||||
values = find_all_values(model.name)
|
||||
content = ""
|
||||
for name, value in values.items():
|
||||
content += f"{name} = {hex(value)};\n"
|
||||
if not check:
|
||||
get_linkerscript_for_model(model.name).write_text(content)
|
||||
else:
|
||||
#todo
|
||||
pass
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in new issue