mirror of
https://github.com/trezor/trezor-firmware.git
synced 2025-02-16 17:42:02 +00:00
reorganization (wip)
This commit is contained in:
Pavol Rusnak
parent
110dca7711
commit
10b687c318
@ -12,12 +12,6 @@ install:
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script:
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script:
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- make build_cross
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- make build_cross
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- make build_bootloader
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- make clean_stmhal
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- make build_stmhal
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- make clean_stmhal
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- make build_stmhal_frozen
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- make build_stmhal_frozen
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- make build_unix_frozen TREZORUI_NOUI=1
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- make build_unix_frozen TREZORUI_NOUI=1
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88
Makefile
88
Makefile
@ -2,9 +2,12 @@
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JOBS=4
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JOBS=4
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MAKE=make -j $(JOBS)
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MAKE=make -j $(JOBS)
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BOARD=TREZORV2
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STMHAL_BUILD_DIR=vendor/micropython/stmhal/build-$(BOARD)
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TREZORHAL_BUILD_DIR=micropython/trezorhal/build
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TREZORHAL_PORT_OPTS=FROZEN_MPY_DIR=../../../src
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UNIX_PORT_OPTS=MICROPY_FORCE_32BIT=1 MICROPY_PY_BTREE=0 MICROPY_PY_TERMIOS=0 MICROPY_PY_FFI=0 MICROPY_PY_USSL=0 MICROPY_SSL_AXTLS=0
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CROSS_PORT_OPTS=MICROPY_FORCE_32BIT=1
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help: ## show this help
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help: ## show this help
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@awk 'BEGIN {FS = ":.*?## "} /^[a-zA-Z0-9_-]+:.*?## / {printf "\033[36mmake %-20s\033[0m %s\n", $$1, $$2}' $(MAKEFILE_LIST)
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@awk 'BEGIN {FS = ":.*?## "} /^[a-zA-Z0-9_-]+:.*?## / {printf "\033[36mmake %-20s\033[0m %s\n", $$1, $$2}' $(MAKEFILE_LIST)
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@ -15,34 +18,22 @@ vendor: ## update git submodules
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res: ## update resources
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res: ## update resources
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./tools/res_collect
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./tools/res_collect
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build: build_stmhal build_unix build_cross ## build stmhal, unix and mpy-cross micropython ports
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build: build_trezorhal build_unix build_cross ## build trezorhal, unix and mpy-cross micropython ports
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build_stmhal: vendor build_cross ## build stmhal port
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build_trezorhal: vendor res build_cross ## build trezorhal port with frozen modules
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$(MAKE) -C vendor/micropython/stmhal BOARD=$(BOARD)
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$(MAKE) -C vendor/micropython/trezorhal $(TREZORHAL_PORT_OPTS)
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build_stmhal_debug: vendor build_cross ## build stmhal port with debug symbols
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build_trezorhal_debug: vendor res build_cross ## build trezorhal port with frozen modules and debug symbols
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$(MAKE) -C vendor/micropython/stmhal BOARD=$(BOARD) DEBUG=1
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$(MAKE) -C vendor/micropython/trezorhal $(TREZORHAL_PORT_OPTS) DEBUG=1
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build_stmhal_frozen: vendor res build_cross ## build stmhal port with frozen modules (from /src)
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$(MAKE) -C vendor/micropython/stmhal BOARD=$(BOARD) FROZEN_MPY_DIR=../../../src
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build_trezorhal_frozen: vendor res build_cross ## build trezorhal port with frozen modules (from /src)
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$(MAKE) -C vendor/micropython/trezorhal FROZEN_MPY_DIR=../../../src
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build_bootloader: vendor ## build bootloader
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$(MAKE) -C vendor/micropython/stmhal -f Makefile.bootloader BOARD=$(BOARD) BUILD=build-$(BOARD)_bootloader
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build_unix: vendor ## build unix port
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build_unix: vendor ## build unix port
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$(MAKE) -C vendor/micropython/unix MICROPY_FORCE_32BIT=1
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$(MAKE) -C vendor/micropython/unix $(UNIX_PORT_OPTS)
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build_unix_debug: vendor ## build unix port with debug symbols
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build_unix_debug: vendor ## build unix port with debug symbols
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$(MAKE) -C vendor/micropython/unix MICROPY_FORCE_32BIT=1 DEBUG=1
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$(MAKE) -C vendor/micropython/unix $(UNIX_PORT_OPTS) DEBUG=1
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build_unix_frozen: vendor res build_cross ## build unix port with frozen modules (from /src)
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$(MAKE) -C vendor/micropython/unix MICROPY_FORCE_32BIT=1 FROZEN_MPY_DIR=../../../src
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build_cross: vendor ## build mpy-cross port
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build_cross: vendor ## build mpy-cross port
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$(MAKE) -C vendor/micropython/mpy-cross MICROPY_FORCE_32BIT=1
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$(MAKE) -C vendor/micropython/mpy-cross $(CROSS_PORT_OPTS)
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run: ## run unix port
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run: ## run unix port
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cd src ; ../vendor/micropython/unix/micropython
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cd src ; ../vendor/micropython/unix/micropython
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@ -50,50 +41,26 @@ run: ## run unix port
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emu: ## run emulator
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emu: ## run emulator
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./emu.sh
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./emu.sh
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clean: clean_stmhal clean_trezorhal clean_bootloader clean_unix clean_cross ## clean all builds
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clean: clean_trezorhal clean_unix clean_cross ## clean all builds
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clean_stmhal: ## clean stmhal build
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$(MAKE) -C vendor/micropython/stmhal clean BOARD=$(BOARD)
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clean_trezorhal: ## clean trezorhal build
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clean_trezorhal: ## clean trezorhal build
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$(MAKE) -C vendor/micropython/trezorhal clean
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$(MAKE) -C vendor/micropython/trezorhal clean $(TREZORHAL_PORT_OPTS)
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clean_bootloader: ## clean stmhal build
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$(MAKE) -C vendor/micropython/stmhal -f Makefile.bootloader clean BOARD=$(BOARD) BUILD=build-$(BOARD)_bootloader
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clean_unix: ## clean unix build
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clean_unix: ## clean unix build
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$(MAKE) -C vendor/micropython/unix clean
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$(MAKE) -C vendor/micropython/unix clean $(UNIX_PORT_OPTS)
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clean_cross: ## clean mpy-cross build
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clean_cross: ## clean mpy-cross build
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$(MAKE) -C vendor/micropython/mpy-cross clean
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$(MAKE) -C vendor/micropython/mpy-cross clean $(CROSS_PORT_OPTS)
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test: ## run unit tests
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cd tests ; ./run_tests.sh
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testpy: ## run selected unit tests from python-trezor
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cd tests ; ./run_tests_python_trezor.sh
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flash: ## flash firmware using st-flash
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flash: ## flash firmware using st-flash
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st-flash write $(STMHAL_BUILD_DIR)/firmware.bin 0x8000000
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st-flash write $(TREZORHAL_BUILD_DIR)/firmware.bin 0x8000000
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flash_bl: vendor ## flash bootloader using st-flash
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flash_openocd: $(TREZORHAL_BUILD_DIR)/firmware.hex ## flash firmware using openocd
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st-flash write $(STMHAL_BUILD_DIR)_bootloader/firmware.bin 0x8000000
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openocd_flash: $(STMHAL_BUILD_DIR)/firmware.hex ## flash firmware using openocd
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openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg \
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openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg \
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-c "init" \
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-c "init" \
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-c "reset init" \
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-c "reset init" \
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-c "stm32f4x mass_erase 0" \
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-c "stm32f4x mass_erase 0" \
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-c "flash write_image $(STMHAL_BUILD_DIR)/firmware.hex" \
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-c "flash write_image $(TREZORHAL_BUILD_DIR)/firmware.hex" \
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-c "reset" \
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-c "shutdown"
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openocd_flash_bl: $(STMHAL_BUILD_DIR)_bootloader/firmware.hex ## flash bootloader using openocd
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openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg \
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-c "init" \
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-c "reset init" \
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-c "stm32f4x mass_erase 0" \
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-c "flash write_image $(STMHAL_BUILD_DIR)_bootloader/firmware.hex" \
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-c "reset" \
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-c "reset" \
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-c "shutdown"
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-c "shutdown"
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@ -101,15 +68,10 @@ openocd: ## start openocd which connects to the device
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openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg
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openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg
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gdb: ## start remote gdb session which connects to the openocd
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gdb: ## start remote gdb session which connects to the openocd
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arm-none-eabi-gdb $(STMHAL_BUILD_DIR)/firmware.elf -ex 'target remote localhost:3333'
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arm-none-eabi-gdb $(TREZORHAL_BUILD_DIR)/firmware.elf -ex 'target remote localhost:3333'
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gdb_bl: ## start remote gdb session which connects to the openocd
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test: ## run unit tests
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arm-none-eabi-gdb $(STMHAL_BUILD_DIR)_bootloader/firmware.elf -ex 'target remote localhost:3333'
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cd tests ; ./run_tests.sh
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load: ## load contents of src into mass storage of trezor
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testpy: ## run selected unit tests from python-trezor
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rm -rf /run/media/${USER}/PYBFLASH/*
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cd tests ; ./run_tests_python_trezor.sh
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cp -a src/apps /run/media/${USER}/PYBFLASH/
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cp -a src/lib /run/media/${USER}/PYBFLASH/
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cp -a src/trezor /run/media/${USER}/PYBFLASH/
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cp -a src/*.py /run/media/${USER}/PYBFLASH/
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sync
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78
_patches/py/py.mk.diff
Normal file
78
_patches/py/py.mk.diff
Normal file
@ -0,0 +1,78 @@
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--- a/py/py.mk
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+++ b/py/py.mk
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@@ -101,6 +101,75 @@ CFLAGS_MOD += -DMICROPY_PY_BTREE=1
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$(BUILD)/$(BTREE_DIR)/%.o: CFLAGS += -Wno-old-style-definition -Wno-sign-compare -Wno-unused-parameter
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endif
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+ifeq ($(MICROPY_PY_TREZORCONFIG),1)
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+SRC_MOD += extmod/modtrezorconfig/modtrezorconfig.c
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+SRC_MOD += extmod/modtrezorconfig/norcow.c
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+endif
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+
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+ifeq ($(MICROPY_PY_TREZORCRYPTO),1)
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+CFLAGS_MOD += -I../extmod/modtrezorcrypto/trezor-crypto
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+CFLAGS_MOD += -I../extmod/modtrezorcrypto/trezor-crypto/curve25519-donna
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+CFLAGS_MOD += -I../extmod/modtrezorcrypto/trezor-crypto/ed25519-donna
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+CFLAGS_MOD += -DED25519_CUSTOMRANDOM=1
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+CFLAGS_MOD += -DED25519_CUSTOMHASH=1
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+CFLAGS_MOD += -DED25519_NO_INLINE_ASM
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+CFLAGS_MOD += -DED25519_FORCE_32BIT=1
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+CFLAGS_MOD += -DAES_128
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+CFLAGS_MOD += -DAES_192
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+CFLAGS_MOD += -DUSE_KECCAK=1
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+CFLAGS_MOD += -Wno-sequence-point
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+SRC_MOD += \
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+ extmod/modtrezorcrypto/modtrezorcrypto.c \
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+ extmod/modtrezorcrypto/rand.c \
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+ extmod/modtrezorcrypto/ssss.c \
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+ extmod/modtrezorcrypto/trezor-crypto/address.c \
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+ extmod/modtrezorcrypto/trezor-crypto/aescrypt.c \
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+ extmod/modtrezorcrypto/trezor-crypto/aeskey.c \
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+ extmod/modtrezorcrypto/trezor-crypto/aes_modes.c \
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+ extmod/modtrezorcrypto/trezor-crypto/aestab.c \
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+ extmod/modtrezorcrypto/trezor-crypto/base58.c \
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+ extmod/modtrezorcrypto/trezor-crypto/bignum.c \
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+ extmod/modtrezorcrypto/trezor-crypto/bip32.c \
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+ extmod/modtrezorcrypto/trezor-crypto/bip39.c \
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+ extmod/modtrezorcrypto/trezor-crypto/blake2s.c \
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+ extmod/modtrezorcrypto/trezor-crypto/curve25519-donna/curve25519.c \
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+ extmod/modtrezorcrypto/trezor-crypto/curves.c \
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+ extmod/modtrezorcrypto/trezor-crypto/ecdsa.c \
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+ extmod/modtrezorcrypto/trezor-crypto/ed25519-donna/ed25519.c \
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+ extmod/modtrezorcrypto/trezor-crypto/hmac.c \
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+ extmod/modtrezorcrypto/trezor-crypto/nist256p1.c \
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+ extmod/modtrezorcrypto/trezor-crypto/pbkdf2.c \
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+ extmod/modtrezorcrypto/trezor-crypto/ripemd160.c \
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+ extmod/modtrezorcrypto/trezor-crypto/secp256k1.c \
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+ extmod/modtrezorcrypto/trezor-crypto/sha2.c \
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+ extmod/modtrezorcrypto/trezor-crypto/sha3.c
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+endif
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+
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+ifeq ($(MICROPY_PY_TREZORDEBUG),1)
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+SRC_MOD += extmod/modtrezordebug/modtrezordebug.c
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+endif
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+
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+ifeq ($(MICROPY_PY_TREZORMSG),1)
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+SRC_MOD += extmod/modtrezormsg/modtrezormsg.c
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+endif
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+
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+ifeq ($(MICROPY_PY_TREZORUI),1)
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+CFLAGS_MOD += -DQR_MAX_VERSION=0
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+SRC_MOD += \
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+ extmod/modtrezorui/display.c \
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+ extmod/modtrezorui/inflate.c \
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+ extmod/modtrezorui/font_bitmap.c \
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+ extmod/modtrezorui/font_roboto_bold_20.c \
|
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+ extmod/modtrezorui/font_roboto_regular_20.c \
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+ extmod/modtrezorui/font_robotomono_regular_20.c \
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+ extmod/modtrezorui/modtrezorui.c \
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+ extmod/modtrezorui/trezor-qrenc/qr_encode.c
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|
+endif
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|
+
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+ifeq ($(MICROPY_PY_TREZORUTILS),1)
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+SRC_MOD += extmod/modtrezorutils/modtrezorutils.c
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|
+endif
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|
+
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# py object files
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|
PY_O_BASENAME = \
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|
mpstate.o \
|
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43
_patches/stmhal/mpconfigport.h.diff
Normal file
43
_patches/stmhal/mpconfigport.h.diff
Normal file
@ -0,0 +1,43 @@
|
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|
--- a/stmhal/mpconfigport.h
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|
+++ b/stmhal/mpconfigport.h
|
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|
@@ -130,6 +130,14 @@
|
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|
#define MICROPY_PY_MACHINE_SPI_MIN_DELAY (0)
|
||||||
|
#define MICROPY_PY_MACHINE_SPI_MAX_BAUDRATE (HAL_RCC_GetSysClockFreq() / 48)
|
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|
#define MICROPY_PY_FRAMEBUF (1)
|
||||||
|
+
|
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|
+#define MICROPY_PY_TREZORCONFIG (1)
|
||||||
|
+#define MICROPY_PY_TREZORCRYPTO (1)
|
||||||
|
+#define MICROPY_PY_TREZORDEBUG (1)
|
||||||
|
+#define MICROPY_PY_TREZORMSG (1)
|
||||||
|
+#define MICROPY_PY_TREZORUI (1)
|
||||||
|
+#define MICROPY_PY_TREZORUTILS (1)
|
||||||
|
+
|
||||||
|
#ifndef MICROPY_PY_USOCKET
|
||||||
|
#define MICROPY_PY_USOCKET (1)
|
||||||
|
#endif
|
||||||
|
@@ -172,6 +180,12 @@ extern const struct _mp_obj_module_t mp_module_uos;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_utime;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_usocket;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_network;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorConfig;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorCrypto;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorDebug;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorMsg;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorUi;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorUtils;
|
||||||
|
|
||||||
|
#if MICROPY_PY_USOCKET
|
||||||
|
#define SOCKET_BUILTIN_MODULE { MP_OBJ_NEW_QSTR(MP_QSTR_usocket), (mp_obj_t)&mp_module_usocket },
|
||||||
|
@@ -213,6 +227,12 @@ extern const struct _mp_obj_module_t mp_module_network;
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_struct), (mp_obj_t)&mp_module_ustruct }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_machine), (mp_obj_t)&machine_module }, \
|
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{ MP_OBJ_NEW_QSTR(MP_QSTR_errno), (mp_obj_t)&mp_module_uerrno }, \
|
||||||
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+ { MP_OBJ_NEW_QSTR(MP_QSTR_TrezorConfig), (mp_obj_t)&mp_module_TrezorConfig }, \
|
||||||
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+ { MP_OBJ_NEW_QSTR(MP_QSTR_TrezorCrypto), (mp_obj_t)&mp_module_TrezorCrypto }, \
|
||||||
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+ { MP_OBJ_NEW_QSTR(MP_QSTR_TrezorDebug), (mp_obj_t)&mp_module_TrezorDebug }, \
|
||||||
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+ { MP_OBJ_NEW_QSTR(MP_QSTR_TrezorMsg), (mp_obj_t)&mp_module_TrezorMsg }, \
|
||||||
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+ { MP_OBJ_NEW_QSTR(MP_QSTR_TrezorUi), (mp_obj_t)&mp_module_TrezorUi }, \
|
||||||
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+ { MP_OBJ_NEW_QSTR(MP_QSTR_TrezorUtils), (mp_obj_t)&mp_module_TrezorUtils }, \
|
||||||
|
|
||||||
|
// extra constants
|
||||||
|
#define MICROPY_PORT_CONSTANTS \
|
||||||
18
_patches/stmhal/mpconfigport.mk.diff
Normal file
18
_patches/stmhal/mpconfigport.mk.diff
Normal file
@ -0,0 +1,18 @@
|
|||||||
|
--- a/stmhal/mpconfigport.mk
|
||||||
|
+++ b/stmhal/mpconfigport.mk
|
||||||
|
@@ -5,3 +5,15 @@ MICROPY_PY_WIZNET5K ?= 0
|
||||||
|
|
||||||
|
# cc3k module for wifi support
|
||||||
|
MICROPY_PY_CC3K ?= 0
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORCONFIG = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORCRYPTO = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORDEBUG = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORMSG = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORUI = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORUTILS = 1
|
||||||
16
_patches/unix/Makefile.diff
Normal file
16
_patches/unix/Makefile.diff
Normal file
@ -0,0 +1,16 @@
|
|||||||
|
--- a/unix/Makefile
|
||||||
|
+++ b/unix/Makefile
|
||||||
|
@@ -103,6 +103,13 @@ ifeq ($(MICROPY_PY_THREAD),1)
|
||||||
|
CFLAGS_MOD += -DMICROPY_PY_THREAD=1 -DMICROPY_PY_THREAD_GIL=0
|
||||||
|
LDFLAGS_MOD += -lpthread
|
||||||
|
endif
|
||||||
|
+ifeq ($(MICROPY_PY_TREZORUI),1)
|
||||||
|
+ifeq ($(TREZORUI_NOUI),1)
|
||||||
|
+CFLAGS_MOD += -DTREZORUI_NOUI=1
|
||||||
|
+else
|
||||||
|
+LDFLAGS_MOD += -lSDL2 -lSDL2_image
|
||||||
|
+endif
|
||||||
|
+endif
|
||||||
|
|
||||||
|
ifeq ($(MICROPY_PY_FFI),1)
|
||||||
|
|
||||||
80
_patches/unix/mpconfigport.h.diff
Normal file
80
_patches/unix/mpconfigport.h.diff
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
--- a/unix/mpconfigport.h
|
||||||
|
+++ b/unix/mpconfigport.h
|
||||||
|
@@ -131,6 +131,12 @@
|
||||||
|
#define MICROPY_PY_MACHINE_PULSE (1)
|
||||||
|
#define MICROPY_MACHINE_MEM_GET_READ_ADDR mod_machine_mem_get_addr
|
||||||
|
#define MICROPY_MACHINE_MEM_GET_WRITE_ADDR mod_machine_mem_get_addr
|
||||||
|
+#define MICROPY_PY_TREZORCONFIG (1)
|
||||||
|
+#define MICROPY_PY_TREZORCRYPTO (1)
|
||||||
|
+#define MICROPY_PY_TREZORDEBUG (1)
|
||||||
|
+#define MICROPY_PY_TREZORMSG (1)
|
||||||
|
+#define MICROPY_PY_TREZORUI (1)
|
||||||
|
+#define MICROPY_PY_TREZORUTILS (1)
|
||||||
|
|
||||||
|
#define MICROPY_FATFS_ENABLE_LFN (1)
|
||||||
|
#define MICROPY_FATFS_RPATH (2)
|
||||||
|
@@ -167,6 +173,12 @@ extern const struct _mp_obj_module_t mp_module_termios;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_socket;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_ffi;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_jni;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorConfig;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorCrypto;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorDebug;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorMsg;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorUi;
|
||||||
|
+extern const struct _mp_obj_module_t mp_module_TrezorUtils;
|
||||||
|
|
||||||
|
#if MICROPY_PY_UOS_VFS
|
||||||
|
#define MICROPY_PY_UOS_VFS_DEF { MP_ROM_QSTR(MP_QSTR_uos_vfs), MP_ROM_PTR(&mp_module_uos_vfs) },
|
||||||
|
@@ -203,6 +215,38 @@ extern const struct _mp_obj_module_t mp_module_jni;
|
||||||
|
#else
|
||||||
|
#define MICROPY_PY_USELECT_DEF
|
||||||
|
#endif
|
||||||
|
+#if MICROPY_PY_TREZORCONFIG
|
||||||
|
+#define MICROPY_PY_TREZORCONFIG_DEF { MP_ROM_QSTR(MP_QSTR_TrezorConfig), MP_ROM_PTR(&mp_module_TrezorConfig) },
|
||||||
|
+#else
|
||||||
|
+#define MICROPY_PY_TREZORCONFIG_DEF
|
||||||
|
+#endif
|
||||||
|
+#if MICROPY_PY_TREZORCRYPTO
|
||||||
|
+#define MICROPY_PY_TREZORCRYPTO_DEF { MP_ROM_QSTR(MP_QSTR_TrezorCrypto), MP_ROM_PTR(&mp_module_TrezorCrypto) },
|
||||||
|
+#else
|
||||||
|
+#define MICROPY_PY_TREZORCRYPTO_DEF
|
||||||
|
+#endif
|
||||||
|
+#if MICROPY_PY_TREZORDEBUG
|
||||||
|
+#define MICROPY_PY_TREZORDEBUG_DEF { MP_ROM_QSTR(MP_QSTR_TrezorDebug), MP_ROM_PTR(&mp_module_TrezorDebug) },
|
||||||
|
+#else
|
||||||
|
+#define MICROPY_PY_TREZORDEBUGI_DEF
|
||||||
|
+#endif
|
||||||
|
+#if MICROPY_PY_TREZORMSG
|
||||||
|
+#define MICROPY_PY_TREZORMSG_DEF { MP_ROM_QSTR(MP_QSTR_TrezorMsg), MP_ROM_PTR(&mp_module_TrezorMsg) },
|
||||||
|
+#else
|
||||||
|
+#define MICROPY_PY_TREZORMSG_DEF
|
||||||
|
+#endif
|
||||||
|
+#if MICROPY_PY_TREZORUI
|
||||||
|
+#define MICROPY_PY_TREZORUI_DEF { MP_ROM_QSTR(MP_QSTR_TrezorUi), MP_ROM_PTR(&mp_module_TrezorUi) },
|
||||||
|
+#else
|
||||||
|
+#define MICROPY_PY_TREZORUI_DEF
|
||||||
|
+#endif
|
||||||
|
+#if MICROPY_PY_TREZORUTILS
|
||||||
|
+#define MICROPY_PY_TREZORUTILS_DEF { MP_ROM_QSTR(MP_QSTR_TrezorUtils), MP_ROM_PTR(&mp_module_TrezorUtils) },
|
||||||
|
+#else
|
||||||
|
+#define MICROPY_PY_TREZORUTILS_DEF
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+
|
||||||
|
|
||||||
|
#define MICROPY_PORT_BUILTIN_MODULES \
|
||||||
|
MICROPY_PY_FFI_DEF \
|
||||||
|
@@ -214,6 +258,12 @@ extern const struct _mp_obj_module_t mp_module_jni;
|
||||||
|
MICROPY_PY_UOS_VFS_DEF \
|
||||||
|
MICROPY_PY_USELECT_DEF \
|
||||||
|
MICROPY_PY_TERMIOS_DEF \
|
||||||
|
+ MICROPY_PY_TREZORCONFIG_DEF \
|
||||||
|
+ MICROPY_PY_TREZORCRYPTO_DEF \
|
||||||
|
+ MICROPY_PY_TREZORDEBUG_DEF \
|
||||||
|
+ MICROPY_PY_TREZORMSG_DEF \
|
||||||
|
+ MICROPY_PY_TREZORUI_DEF \
|
||||||
|
+ MICROPY_PY_TREZORUTILS_DEF \
|
||||||
|
|
||||||
|
// type definitions for the specific machine
|
||||||
|
|
||||||
22
_patches/unix/mpconfigport.mk.diff
Normal file
22
_patches/unix/mpconfigport.mk.diff
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
--- a/unix/mpconfigport.mk
|
||||||
|
+++ b/unix/mpconfigport.mk
|
||||||
|
@@ -34,6 +34,19 @@ MICROPY_SSL_MBEDTLS = 0
|
||||||
|
# jni module requires JVM/JNI
|
||||||
|
MICROPY_PY_JNI = 0
|
||||||
|
|
||||||
|
+MICROPY_PY_TREZORCONFIG = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORCRYPTO = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORDEBUG = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORMSG = 1
|
||||||
|
+
|
||||||
|
+# TrezorUi module requires SDL2+SDL2_image unless TREZORUI_NOUI=1 is used
|
||||||
|
+MICROPY_PY_TREZORUI = 1
|
||||||
|
+
|
||||||
|
+MICROPY_PY_TREZORUTILS = 1
|
||||||
|
+
|
||||||
|
# Avoid using system libraries, use copies bundled with MicroPython
|
||||||
|
# as submodules (currently affects only libffi).
|
||||||
|
MICROPY_STANDALONE = 0
|
||||||
@ -1,317 +0,0 @@
|
|||||||
# Select the board to build for: if not given on the command line,
|
|
||||||
# then default to PYBV10.
|
|
||||||
BOARD ?= PYBV10
|
|
||||||
ifeq ($(wildcard boards/$(BOARD)/.),)
|
|
||||||
$(error Invalid BOARD specified)
|
|
||||||
endif
|
|
||||||
|
|
||||||
# If the build directory is not given, make it reflect the board name.
|
|
||||||
BUILD ?= build-$(BOARD)
|
|
||||||
|
|
||||||
include ../py/mkenv.mk
|
|
||||||
-include mpconfigport.mk
|
|
||||||
include boards/$(BOARD)/mpconfigboard.mk
|
|
||||||
|
|
||||||
# qstr definitions (must come before including py.mk)
|
|
||||||
QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h $(BUILD)/modstm_qstr.h
|
|
||||||
|
|
||||||
# include py core make definitions
|
|
||||||
include ../py/py.mk
|
|
||||||
|
|
||||||
LD_DIR=boards
|
|
||||||
CMSIS_DIR=cmsis
|
|
||||||
HAL_DIR=hal/$(MCU_SERIES)
|
|
||||||
USBDEV_DIR=usbdev
|
|
||||||
#USBHOST_DIR=usbhost
|
|
||||||
FATFS_DIR=lib/fatfs
|
|
||||||
DFU=../tools/dfu.py
|
|
||||||
# may need to prefix dfu-util with sudo
|
|
||||||
USE_PYDFU ?= 1
|
|
||||||
PYDFU ?= ../tools/pydfu.py
|
|
||||||
DFU_UTIL ?= dfu-util
|
|
||||||
DEVICE=0483:df11
|
|
||||||
STFLASH ?= st-flash
|
|
||||||
OPENOCD ?= openocd
|
|
||||||
OPENOCD_CONFIG ?= boards/openocd_stm32f4.cfg
|
|
||||||
|
|
||||||
CROSS_COMPILE = arm-none-eabi-
|
|
||||||
|
|
||||||
INC += -I.
|
|
||||||
INC += -I..
|
|
||||||
INC += -I$(BUILD)
|
|
||||||
INC += -I../lib/cmsis/inc
|
|
||||||
INC += -I$(CMSIS_DIR)/
|
|
||||||
INC += -I$(HAL_DIR)/inc
|
|
||||||
INC += -I$(USBDEV_DIR)/core/inc -I$(USBDEV_DIR)/class/inc
|
|
||||||
#INC += -I$(USBHOST_DIR)
|
|
||||||
|
|
||||||
CFLAGS_CORTEX_M = -mthumb -mabi=aapcs-linux -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion
|
|
||||||
CFLAGS_MCU_f4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -DMCU_SERIES_F4
|
|
||||||
CFLAGS_MCU_f7 = $(CFLAGS_CORTEX_M) -mtune=cortex-m7 -mcpu=cortex-m7 -DMCU_SERIES_F7
|
|
||||||
CFLAGS_MCU_l4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -DMCU_SERIES_L4
|
|
||||||
|
|
||||||
CFLAGS = $(INC) -Wall -Wpointer-arith -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_MOD)
|
|
||||||
CFLAGS += -D$(CMSIS_MCU)
|
|
||||||
CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES))
|
|
||||||
CFLAGS += $(COPT)
|
|
||||||
CFLAGS += -Iboards/$(BOARD)
|
|
||||||
CFLAGS += -DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>'
|
|
||||||
|
|
||||||
LDFLAGS = -nostdlib -L $(LD_DIR) -T $(LD_FILE) -Map=$(@:.elf=.map) --cref
|
|
||||||
LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
|
|
||||||
|
|
||||||
# Remove uncalled code from the final image.
|
|
||||||
CFLAGS += -fdata-sections -ffunction-sections
|
|
||||||
LDFLAGS += --gc-sections
|
|
||||||
|
|
||||||
# Debugging/Optimization
|
|
||||||
ifeq ($(DEBUG), 1)
|
|
||||||
CFLAGS += -g -DPENDSV_DEBUG
|
|
||||||
COPT = -O0
|
|
||||||
else
|
|
||||||
COPT += -Os -DNDEBUG
|
|
||||||
endif
|
|
||||||
|
|
||||||
SRC_LIB = $(addprefix lib/,\
|
|
||||||
libc/string0.c \
|
|
||||||
)
|
|
||||||
|
|
||||||
SRC_C = \
|
|
||||||
bootloader/basic.c \
|
|
||||||
bootloader/bootloader.c \
|
|
||||||
bootloader/crypto.c \
|
|
||||||
bootloader/sdcard.c \
|
|
||||||
system_stm32.c \
|
|
||||||
$(wildcard boards/$(BOARD)/*.c)
|
|
||||||
|
|
||||||
SRC_O = \
|
|
||||||
startup_stm32.o \
|
|
||||||
|
|
||||||
SRC_HAL = $(addprefix $(HAL_DIR)/src/stm32$(MCU_SERIES)xx_,\
|
|
||||||
hal.c \
|
|
||||||
hal_adc.c \
|
|
||||||
hal_adc_ex.c \
|
|
||||||
hal_can.c \
|
|
||||||
hal_cortex.c \
|
|
||||||
hal_dac.c \
|
|
||||||
hal_dac_ex.c \
|
|
||||||
hal_dma.c \
|
|
||||||
hal_flash.c \
|
|
||||||
hal_flash_ex.c \
|
|
||||||
hal_gpio.c \
|
|
||||||
hal_i2c.c \
|
|
||||||
hal_pcd.c \
|
|
||||||
hal_pcd_ex.c \
|
|
||||||
hal_pwr.c \
|
|
||||||
hal_pwr_ex.c \
|
|
||||||
hal_rcc.c \
|
|
||||||
hal_rcc_ex.c \
|
|
||||||
hal_rng.c \
|
|
||||||
hal_rtc.c \
|
|
||||||
hal_rtc_ex.c \
|
|
||||||
hal_sd.c \
|
|
||||||
hal_spi.c \
|
|
||||||
hal_sram.c \
|
|
||||||
hal_tim.c \
|
|
||||||
hal_tim_ex.c \
|
|
||||||
hal_uart.c \
|
|
||||||
ll_fsmc.c \
|
|
||||||
ll_sdmmc.c \
|
|
||||||
ll_usb.c \
|
|
||||||
)
|
|
||||||
|
|
||||||
SRC_USBDEV = $(addprefix $(USBDEV_DIR)/,\
|
|
||||||
core/src/usbd_core.c \
|
|
||||||
core/src/usbd_ctlreq.c \
|
|
||||||
core/src/usbd_ioreq.c \
|
|
||||||
class/src/usbd_cdc_msc_hid.c \
|
|
||||||
class/src/usbd_msc_bot.c \
|
|
||||||
class/src/usbd_msc_scsi.c \
|
|
||||||
class/src/usbd_msc_data.c \
|
|
||||||
)
|
|
||||||
|
|
||||||
ifeq ($(MICROPY_PY_WIZNET5K),1)
|
|
||||||
WIZNET5K_DIR=drivers/wiznet5k
|
|
||||||
INC += -I$(TOP)/$(WIZNET5K_DIR)
|
|
||||||
CFLAGS_MOD += -DMICROPY_PY_WIZNET5K=1
|
|
||||||
SRC_MOD += modnwwiznet5k.c
|
|
||||||
SRC_MOD += $(addprefix $(WIZNET5K_DIR)/,\
|
|
||||||
ethernet/w5200/w5200.c \
|
|
||||||
ethernet/wizchip_conf.c \
|
|
||||||
ethernet/socket.c \
|
|
||||||
internet/dns/dns.c \
|
|
||||||
)
|
|
||||||
endif
|
|
||||||
|
|
||||||
# for CC3000 module
|
|
||||||
ifeq ($(MICROPY_PY_CC3K),1)
|
|
||||||
CC3000_DIR=drivers/cc3000
|
|
||||||
INC += -I$(TOP)/$(CC3000_DIR)/inc
|
|
||||||
CFLAGS_MOD += -DMICROPY_PY_CC3K=1
|
|
||||||
SRC_MOD += modnwcc3k.c
|
|
||||||
SRC_MOD += $(addprefix $(CC3000_DIR)/src/,\
|
|
||||||
cc3000_common.c \
|
|
||||||
evnt_handler.c \
|
|
||||||
hci.c \
|
|
||||||
netapp.c \
|
|
||||||
nvmem.c \
|
|
||||||
security.c \
|
|
||||||
socket.c \
|
|
||||||
wlan.c \
|
|
||||||
ccspi.c \
|
|
||||||
inet_ntop.c \
|
|
||||||
inet_pton.c \
|
|
||||||
patch.c \
|
|
||||||
patch_prog.c \
|
|
||||||
)
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifeq ($(MICROPY_PY_TREZORUI),1)
|
|
||||||
INC += -I../extmod/modtrezorui
|
|
||||||
SRC_MOD += $(addprefix extmod/modtrezorui/,\
|
|
||||||
display.c \
|
|
||||||
inflate.c \
|
|
||||||
font_robotomono_regular_20.c \
|
|
||||||
)
|
|
||||||
endif
|
|
||||||
|
|
||||||
OBJ =
|
|
||||||
OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
|
|
||||||
OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
|
|
||||||
OBJ += $(addprefix $(BUILD)/, $(SRC_O))
|
|
||||||
OBJ += $(addprefix $(BUILD)/, $(SRC_HAL:.c=.o))
|
|
||||||
OBJ += $(addprefix $(BUILD)/, $(SRC_USBDEV:.c=.o))
|
|
||||||
OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
|
|
||||||
OBJ += $(BUILD)/pins_$(BOARD).o
|
|
||||||
|
|
||||||
# We put several files into the first 16K section with the ISRs.
|
|
||||||
# If we compile these using -O0 then it won't fit. So if you really want these
|
|
||||||
# to be compiled with -O0, then edit boards/common.ld (in the .isr_vector section)
|
|
||||||
# and comment out the following lines.
|
|
||||||
$(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os
|
|
||||||
$(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os
|
|
||||||
$(PY_BUILD)/formatfloat.o: COPT += -Os
|
|
||||||
$(PY_BUILD)/parsenum.o: COPT += -Os
|
|
||||||
$(PY_BUILD)/mpprint.o: COPT += -Os
|
|
||||||
|
|
||||||
all: $(BUILD)/firmware.dfu $(BUILD)/firmware.hex
|
|
||||||
|
|
||||||
ifneq ($(FROZEN_DIR),)
|
|
||||||
# To use frozen source modules, put your .py files in a subdirectory (eg scripts/)
|
|
||||||
# and then invoke make with FROZEN_DIR=scripts (be sure to build from scratch).
|
|
||||||
CFLAGS += -DMICROPY_MODULE_FROZEN_STR
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifneq ($(FROZEN_MPY_DIR),)
|
|
||||||
# To use frozen bytecode, put your .py files in a subdirectory (eg frozen/) and
|
|
||||||
# then invoke make with FROZEN_MPY_DIR=frozen (be sure to build from scratch).
|
|
||||||
CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool
|
|
||||||
CFLAGS += -DMICROPY_MODULE_FROZEN_MPY
|
|
||||||
endif
|
|
||||||
|
|
||||||
.PHONY: deploy
|
|
||||||
|
|
||||||
deploy: $(BUILD)/firmware.dfu
|
|
||||||
$(ECHO) "Writing $< to the board"
|
|
||||||
ifeq ($(USE_PYDFU),1)
|
|
||||||
$(Q)$(PYTHON) $(PYDFU) -u $<
|
|
||||||
else
|
|
||||||
$(Q)$(DFU_UTIL) -a 0 -d $(DEVICE) -D $<
|
|
||||||
endif
|
|
||||||
|
|
||||||
FLASH_ADDR ?= 0x08000000
|
|
||||||
TEXT_ADDR ?= 0x08020000
|
|
||||||
|
|
||||||
deploy-stlink: $(BUILD)/firmware.dfu
|
|
||||||
$(ECHO) "Writing $(BUILD)/firmware0.bin to the board via ST-LINK"
|
|
||||||
$(Q)$(STFLASH) write $(BUILD)/firmware0.bin $(FLASH_ADDR)
|
|
||||||
$(ECHO) "Writing $(BUILD)/firmware1.bin to the board via ST-LINK"
|
|
||||||
$(Q)$(STFLASH) --reset write $(BUILD)/firmware1.bin $(TEXT_ADDR)
|
|
||||||
|
|
||||||
deploy-openocd: $(BUILD)/firmware.dfu
|
|
||||||
$(ECHO) "Writing $(BUILD)/firmware{0,1}.bin to the board via ST-LINK using OpenOCD"
|
|
||||||
$(Q)$(OPENOCD) -f $(OPENOCD_CONFIG) -c "stm_flash $(BUILD)/firmware0.bin $(FLASH_ADDR) $(BUILD)/firmware1.bin $(TEXT_ADDR)"
|
|
||||||
|
|
||||||
$(BUILD)/firmware.dfu: $(BUILD)/firmware.elf
|
|
||||||
$(ECHO) "Create $@"
|
|
||||||
$(Q)$(OBJCOPY) -O binary -j .isr_vector $^ $(BUILD)/firmware0.bin
|
|
||||||
$(Q)$(OBJCOPY) -O binary -j .text -j .data $^ $(BUILD)/firmware1.bin
|
|
||||||
$(Q)$(PYTHON) $(DFU) -b $(FLASH_ADDR):$(BUILD)/firmware0.bin -b $(TEXT_ADDR):$(BUILD)/firmware1.bin $@
|
|
||||||
|
|
||||||
$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
|
|
||||||
$(ECHO) "Create $@"
|
|
||||||
$(Q)$(OBJCOPY) -O ihex $< $@
|
|
||||||
|
|
||||||
$(BUILD)/firmware.elf: $(OBJ)
|
|
||||||
$(ECHO) "LINK $@"
|
|
||||||
$(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
|
|
||||||
$(Q)$(SIZE) $@
|
|
||||||
|
|
||||||
MAKE_PINS = boards/make-pins.py
|
|
||||||
BOARD_PINS = boards/$(BOARD)/pins.csv
|
|
||||||
PREFIX_FILE = boards/stm32f4xx_prefix.c
|
|
||||||
GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c
|
|
||||||
GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
|
|
||||||
GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
|
|
||||||
GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h
|
|
||||||
GEN_PINS_AF_PY = $(BUILD)/pins_af.py
|
|
||||||
|
|
||||||
INSERT_USB_IDS = ../tools/insert-usb-ids.py
|
|
||||||
FILE2H = ../tools/file2h.py
|
|
||||||
|
|
||||||
USB_IDS_FILE = usb.h
|
|
||||||
CDCINF_TEMPLATE = pybcdc.inf_template
|
|
||||||
GEN_CDCINF_FILE = $(HEADER_BUILD)/pybcdc.inf
|
|
||||||
GEN_CDCINF_HEADER = $(HEADER_BUILD)/pybcdc_inf.h
|
|
||||||
|
|
||||||
# List of sources for qstr extraction
|
|
||||||
SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB)
|
|
||||||
# Append any auto-generated sources that are needed by sources listed in
|
|
||||||
# SRC_QSTR
|
|
||||||
SRC_QSTR_AUTO_DEPS += $(GEN_CDCINF_HEADER)
|
|
||||||
|
|
||||||
# Making OBJ use an order-only depenedency on the generated pins.h file
|
|
||||||
# has the side effect of making the pins.h file before we actually compile
|
|
||||||
# any of the objects. The normal dependency generation will deal with the
|
|
||||||
# case when pins.h is modified. But when it doesn't exist, we don't know
|
|
||||||
# which source files might need it.
|
|
||||||
$(OBJ): | $(HEADER_BUILD)/pins.h
|
|
||||||
|
|
||||||
# With conditional pins, we may need to regenerate qstrdefs.h when config
|
|
||||||
# options change.
|
|
||||||
$(HEADER_BUILD)/qstrdefs.generated.h: boards/$(BOARD)/mpconfigboard.h
|
|
||||||
|
|
||||||
# main.c can't be even preprocessed without $(GEN_CDCINF_HEADER)
|
|
||||||
main.c: $(GEN_CDCINF_HEADER)
|
|
||||||
|
|
||||||
# Use a pattern rule here so that make will only call make-pins.py once to make
|
|
||||||
# both pins_$(BOARD).c and pins.h
|
|
||||||
$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(BUILD)/%_qstr.h: boards/$(BOARD)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD)
|
|
||||||
$(ECHO) "Create $@"
|
|
||||||
$(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) --af-const $(GEN_PINS_AF_CONST) --af-py $(GEN_PINS_AF_PY) > $(GEN_PINS_SRC)
|
|
||||||
|
|
||||||
$(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c
|
|
||||||
$(call compile_c)
|
|
||||||
|
|
||||||
GEN_STMCONST_HDR = $(HEADER_BUILD)/modstm_const.h
|
|
||||||
GEN_STMCONST_QSTR = $(BUILD)/modstm_qstr.h
|
|
||||||
GEN_STMCONST_MPZ = $(HEADER_BUILD)/modstm_mpz.h
|
|
||||||
CMSIS_MCU_LOWER = $(shell echo $(CMSIS_MCU) | tr '[:upper:]' '[:lower:]')
|
|
||||||
CMSIS_MCU_HDR = cmsis/$(CMSIS_MCU_LOWER).h
|
|
||||||
|
|
||||||
$(BUILD)/modstm.o: $(GEN_STMCONST_HDR)
|
|
||||||
# Use a pattern rule here so that make will only call make-stmconst.py once to
|
|
||||||
# make both modstm_const.h and modstm_qstr.h
|
|
||||||
$(HEADER_BUILD)/%_const.h $(BUILD)/%_qstr.h: $(CMSIS_MCU_HDR) make-stmconst.py | $(HEADER_BUILD)
|
|
||||||
$(ECHO) "Create stmconst $@"
|
|
||||||
$(Q)$(PYTHON) make-stmconst.py --qstr $(GEN_STMCONST_QSTR) --mpz $(GEN_STMCONST_MPZ) $(CMSIS_MCU_HDR) > $(GEN_STMCONST_HDR)
|
|
||||||
|
|
||||||
$(GEN_CDCINF_HEADER): $(GEN_CDCINF_FILE) $(FILE2H) | $(HEADER_BUILD)
|
|
||||||
$(ECHO) "Create $@"
|
|
||||||
$(Q)$(PYTHON) $(FILE2H) $< > $@
|
|
||||||
|
|
||||||
$(GEN_CDCINF_FILE): $(CDCINF_TEMPLATE) $(INSERT_USB_IDS) $(USB_IDS_FILE) | $(HEADER_BUILD)
|
|
||||||
$(ECHO) "Create $@"
|
|
||||||
$(Q)$(PYTHON) $(INSERT_USB_IDS) $(USB_IDS_FILE) $< > $@
|
|
||||||
|
|
||||||
include ../py/mkrules.mk
|
|
||||||
@ -1,4 +0,0 @@
|
|||||||
MCU_SERIES = f4
|
|
||||||
CMSIS_MCU = STM32F405xx
|
|
||||||
AF_FILE = boards/stm32f405_af.csv
|
|
||||||
LD_FILE = boards/TREZORV2/trezorv2.ld
|
|
||||||
@ -1,32 +0,0 @@
|
|||||||
LED,PC6
|
|
||||||
|
|
||||||
X9,PB6
|
|
||||||
X10,PB7
|
|
||||||
|
|
||||||
SD_D0,PC8
|
|
||||||
SD_D1,PC9
|
|
||||||
SD_D2,PC10
|
|
||||||
SD_D3,PC11
|
|
||||||
SD_CMD,PD2
|
|
||||||
SD_CK,PC12
|
|
||||||
SD,PC13
|
|
||||||
SD_SW,PC13
|
|
||||||
|
|
||||||
USB_DM,PA11
|
|
||||||
USB_DP,PA12
|
|
||||||
|
|
||||||
LCD_RST,PC14
|
|
||||||
LCD_CS,PD7
|
|
||||||
LCD_RS,PD11
|
|
||||||
LCD_RD,PD4
|
|
||||||
LCD_WR,PD5
|
|
||||||
LCD_PWM,PB13
|
|
||||||
|
|
||||||
LCD_D0,PD14
|
|
||||||
LCD_D1,PD15
|
|
||||||
LCD_D2,PD0
|
|
||||||
LCD_D3,PD1
|
|
||||||
LCD_D4,PE7
|
|
||||||
LCD_D5,PE8
|
|
||||||
LCD_D6,PE9
|
|
||||||
LCD_D7,PE10
|
|
||||||
|
175
micropython/trezorhal/Makefile
Normal file
175
micropython/trezorhal/Makefile
Normal file
@ -0,0 +1,175 @@
|
|||||||
|
# include default settings
|
||||||
|
include ../py/mkenv.mk
|
||||||
|
|
||||||
|
# qstr definitions target, used in py.mk
|
||||||
|
QSTR_DEFS = qstrdefsport.h
|
||||||
|
|
||||||
|
# directory containing scripts to be frozen as bytecode
|
||||||
|
FROZEN_MPY_DIR ?= modules
|
||||||
|
|
||||||
|
# enable external modules, used in py.mk
|
||||||
|
MICROPY_PY_TREZORCONFIG = 1
|
||||||
|
MICROPY_PY_TREZORCRYPTO = 1
|
||||||
|
MICROPY_PY_TREZORDEBUG = 1
|
||||||
|
MICROPY_PY_TREZORMSG = 1
|
||||||
|
MICROPY_PY_TREZORUI = 1
|
||||||
|
MICROPY_PY_TREZORUTILS = 1
|
||||||
|
|
||||||
|
# include py core make definitions
|
||||||
|
include ../py/py.mk
|
||||||
|
|
||||||
|
CROSS_COMPILE = arm-none-eabi-
|
||||||
|
|
||||||
|
INC += -I.
|
||||||
|
INC += -I..
|
||||||
|
INC += -I../stmhal
|
||||||
|
INC += -I../stmhal/cmsis
|
||||||
|
INC += -I../stmhal/hal/f4/inc
|
||||||
|
INC += -I../stmhal/usbdev/core/inc
|
||||||
|
INC += -I../stmhal/usbdev/class/inc
|
||||||
|
INC += -I../lib/cmsis/inc
|
||||||
|
INC += -I../lib/mp-readline
|
||||||
|
INC += -I$(BUILD)
|
||||||
|
|
||||||
|
ifeq ($(DEBUG), 1)
|
||||||
|
COPT = -O0 -ggdb
|
||||||
|
else
|
||||||
|
COPT = -Os -DNDEBUG
|
||||||
|
endif
|
||||||
|
|
||||||
|
CFLAGS += $(INC) $(COPT) $(CFLAGS_MOD) $(CFLAGS_EXTRA)
|
||||||
|
CFLAGS += -std=gnu99 -nostdlib -Wall -Werror -Wdouble-promotion -Wpointer-arith
|
||||||
|
CFLAGS += -mthumb -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant
|
||||||
|
|
||||||
|
CFLAGS += -DSTM32F405xx -DMCU_SERIES_F4
|
||||||
|
CFLAGS += -DSTM32_HAL_H='<stm32f4xx_hal.h>'
|
||||||
|
|
||||||
|
LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
|
||||||
|
|
||||||
|
LDFLAGS = -nostdlib -T trezorv2.ld -Map=$@.map --cref
|
||||||
|
|
||||||
|
# remove uncalled code from the final image
|
||||||
|
CFLAGS += -fdata-sections -ffunction-sections
|
||||||
|
LDFLAGS += --gc-sections
|
||||||
|
|
||||||
|
SRC_LIB = $(addprefix lib/,\
|
||||||
|
libc/string0.c \
|
||||||
|
libm/math.c \
|
||||||
|
libm/thumb_vfp_sqrtf.c \
|
||||||
|
libm/asinfacosf.c \
|
||||||
|
libm/atanf.c \
|
||||||
|
libm/atan2f.c \
|
||||||
|
libm/fmodf.c \
|
||||||
|
libm/roundf.c \
|
||||||
|
libm/log1pf.c \
|
||||||
|
libm/acoshf.c \
|
||||||
|
libm/asinhf.c \
|
||||||
|
libm/atanhf.c \
|
||||||
|
libm/kf_rem_pio2.c \
|
||||||
|
libm/kf_sin.c \
|
||||||
|
libm/kf_cos.c \
|
||||||
|
libm/kf_tan.c \
|
||||||
|
libm/ef_rem_pio2.c \
|
||||||
|
libm/erf_lgamma.c \
|
||||||
|
libm/sf_sin.c \
|
||||||
|
libm/sf_cos.c \
|
||||||
|
libm/sf_tan.c \
|
||||||
|
libm/sf_frexp.c \
|
||||||
|
libm/sf_modf.c \
|
||||||
|
libm/sf_ldexp.c \
|
||||||
|
libm/sf_erf.c \
|
||||||
|
libm/wf_lgamma.c \
|
||||||
|
libm/wf_tgamma.c \
|
||||||
|
libc/string0.c \
|
||||||
|
mp-readline/readline.c \
|
||||||
|
utils/stdout_helpers.c \
|
||||||
|
utils/pyexec.c \
|
||||||
|
)
|
||||||
|
|
||||||
|
SRC_HAL = $(addprefix stmhal/hal/f4/src/stm32f4xx_,\
|
||||||
|
hal.c \
|
||||||
|
hal_adc.c \
|
||||||
|
hal_adc_ex.c \
|
||||||
|
hal_can.c \
|
||||||
|
hal_cortex.c \
|
||||||
|
hal_dac.c \
|
||||||
|
hal_dac_ex.c \
|
||||||
|
hal_dma.c \
|
||||||
|
hal_flash.c \
|
||||||
|
hal_flash_ex.c \
|
||||||
|
hal_gpio.c \
|
||||||
|
hal_i2c.c \
|
||||||
|
hal_pcd.c \
|
||||||
|
hal_pcd_ex.c \
|
||||||
|
hal_pwr.c \
|
||||||
|
hal_pwr_ex.c \
|
||||||
|
hal_rcc.c \
|
||||||
|
hal_rcc_ex.c \
|
||||||
|
hal_rng.c \
|
||||||
|
hal_rtc.c \
|
||||||
|
hal_rtc_ex.c \
|
||||||
|
hal_sd.c \
|
||||||
|
hal_spi.c \
|
||||||
|
hal_sram.c \
|
||||||
|
hal_tim.c \
|
||||||
|
hal_tim_ex.c \
|
||||||
|
hal_uart.c \
|
||||||
|
ll_fsmc.c \
|
||||||
|
ll_sdmmc.c \
|
||||||
|
ll_usb.c \
|
||||||
|
)
|
||||||
|
|
||||||
|
SRC_USBDEV = $(addprefix stmhal/usbdev/,\
|
||||||
|
core/src/usbd_core.c \
|
||||||
|
core/src/usbd_ctlreq.c \
|
||||||
|
core/src/usbd_ioreq.c \
|
||||||
|
class/src/usbd_cdc_msc_hid.c \
|
||||||
|
class/src/usbd_msc_bot.c \
|
||||||
|
class/src/usbd_msc_scsi.c \
|
||||||
|
class/src/usbd_msc_data.c \
|
||||||
|
)
|
||||||
|
|
||||||
|
SRC_C = \
|
||||||
|
main.c \
|
||||||
|
stm32_it.c \
|
||||||
|
modutime.c \
|
||||||
|
lib/utils/stdout_helpers.c \
|
||||||
|
lib/utils/pyexec.c \
|
||||||
|
lib/libc/string0.c \
|
||||||
|
lib/mp-readline/readline.c \
|
||||||
|
stmhal/pendsv.c \
|
||||||
|
stmhal/systick.c \
|
||||||
|
stmhal/gccollect.c \
|
||||||
|
stmhal/system_stm32.c \
|
||||||
|
stmhal/usbd_conf.c \
|
||||||
|
stmhal/usbd_desc.c \
|
||||||
|
stmhal/usbd_cdc_interface.c \
|
||||||
|
stmhal/usbd_hid_interface.c \
|
||||||
|
$(BUILD)/frozen_mpy.c
|
||||||
|
|
||||||
|
SRC_QSTR += modutime.c
|
||||||
|
|
||||||
|
SRC_O = \
|
||||||
|
stmhal/startup_stm32.o \
|
||||||
|
stmhal/gchelper.o \
|
||||||
|
|
||||||
|
OBJ = \
|
||||||
|
$(PY_O) \
|
||||||
|
$(addprefix $(BUILD)/, $(SRC_O)) \
|
||||||
|
$(addprefix $(BUILD)/, $(SRC_C:.c=.o)) \
|
||||||
|
$(addprefix $(BUILD)/, $(SRC_LIB:.c=.o)) \
|
||||||
|
$(addprefix $(BUILD)/, $(SRC_HAL:.c=.o)) \
|
||||||
|
$(addprefix $(BUILD)/, $(SRC_USBDEV:.c=.o)) \
|
||||||
|
$(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
|
||||||
|
|
||||||
|
all: $(BUILD)/firmware.bin
|
||||||
|
|
||||||
|
$(BUILD)/firmware.elf: $(OBJ)
|
||||||
|
$(ECHO) "LINK $@"
|
||||||
|
$(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
|
||||||
|
$(Q)$(SIZE) $@
|
||||||
|
|
||||||
|
$(BUILD)/firmware.bin: $(BUILD)/firmware.elf
|
||||||
|
$(Q)$(OBJCOPY) -O binary -j .flash -j .data $^ $(BUILD)/firmware.bin
|
||||||
|
|
||||||
|
include ../py/mkrules.mk
|
||||||
248
micropython/trezorhal/main.c
Normal file
248
micropython/trezorhal/main.c
Normal file
@ -0,0 +1,248 @@
|
|||||||
|
#include <stdint.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "usbd_core.h"
|
||||||
|
#include "usbd_desc.h"
|
||||||
|
#include "usbd_cdc_msc_hid.h"
|
||||||
|
#include "usbd_cdc_interface.h"
|
||||||
|
#include "usbd_hid_interface.h"
|
||||||
|
|
||||||
|
#include "py/nlr.h"
|
||||||
|
#include "py/compile.h"
|
||||||
|
#include "py/runtime.h"
|
||||||
|
#include "py/stackctrl.h"
|
||||||
|
#include "py/repl.h"
|
||||||
|
#include "py/gc.h"
|
||||||
|
#include "lib/utils/pyexec.h"
|
||||||
|
|
||||||
|
#include "pendsv.h"
|
||||||
|
|
||||||
|
void SystemClock_Config(void);
|
||||||
|
|
||||||
|
extern uint32_t _etext;
|
||||||
|
extern uint32_t _sidata;
|
||||||
|
extern uint32_t _ram_start;
|
||||||
|
extern uint32_t _sdata;
|
||||||
|
extern uint32_t _edata;
|
||||||
|
extern uint32_t _sbss;
|
||||||
|
extern uint32_t _ebss;
|
||||||
|
extern uint32_t _heap_start;
|
||||||
|
extern uint32_t _heap_end;
|
||||||
|
extern uint32_t _estack;
|
||||||
|
extern uint32_t _ram_end;
|
||||||
|
|
||||||
|
void flash_init(void);
|
||||||
|
void usb_init(void);
|
||||||
|
|
||||||
|
int main(void) {
|
||||||
|
|
||||||
|
// STM32F4xx HAL library initialization:
|
||||||
|
// - configure the Flash prefetch, instruction and data caches
|
||||||
|
// - configure the Systick to generate an interrupt each 1 msec
|
||||||
|
// - set NVIC Group Priority to 4
|
||||||
|
// - global MSP (MCU Support Package) initialization
|
||||||
|
HAL_Init();
|
||||||
|
|
||||||
|
// Set the system clock to be HSE
|
||||||
|
SystemClock_Config();
|
||||||
|
|
||||||
|
// Enable GPIO clocks
|
||||||
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||||
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||||
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||||
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||||
|
|
||||||
|
// Enable the CCM RAM
|
||||||
|
__HAL_RCC_CCMDATARAMEN_CLK_ENABLE();
|
||||||
|
|
||||||
|
// machine_init
|
||||||
|
if (PWR->CSR & PWR_CSR_SBF) {
|
||||||
|
PWR->CR |= PWR_CR_CSBF;
|
||||||
|
}
|
||||||
|
RCC->CSR |= RCC_CSR_RMVF;
|
||||||
|
|
||||||
|
pendsv_init();
|
||||||
|
flash_init();
|
||||||
|
usb_init();
|
||||||
|
|
||||||
|
// TODO: sdcard
|
||||||
|
|
||||||
|
for (;;) {
|
||||||
|
// Stack limit should be less than real stack size, so we have a chance
|
||||||
|
// to recover from limit hit.
|
||||||
|
mp_stack_set_top(&_estack);
|
||||||
|
mp_stack_set_limit((char*)&_estack - (char*)&_heap_end - 1024);
|
||||||
|
|
||||||
|
// GC init
|
||||||
|
gc_init(&_heap_start, &_heap_end);
|
||||||
|
|
||||||
|
// Interpreter init
|
||||||
|
mp_init();
|
||||||
|
mp_obj_list_init(mp_sys_argv, 0);
|
||||||
|
mp_obj_list_init(mp_sys_path, 0);
|
||||||
|
mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script)
|
||||||
|
|
||||||
|
// Run the main script
|
||||||
|
pyexec_frozen_module("main.py");
|
||||||
|
|
||||||
|
// Clean up
|
||||||
|
mp_deinit();
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Errors
|
||||||
|
|
||||||
|
void NORETURN nlr_jump_fail(void *val) {
|
||||||
|
for (;;) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
void NORETURN __fatal_error(const char *msg) {
|
||||||
|
for (;;) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef NDEBUG
|
||||||
|
void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) {
|
||||||
|
printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line);
|
||||||
|
__fatal_error("Assertion failed");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Flash
|
||||||
|
|
||||||
|
void flash_init(void) {
|
||||||
|
// Enable the flash IRQ, which is used to also call our storage IRQ handler
|
||||||
|
// It needs to go at a higher priority than all those components that rely on
|
||||||
|
// the flash storage (eg higher than USB MSC).
|
||||||
|
HAL_NVIC_SetPriority(FLASH_IRQn, 2, 0);
|
||||||
|
HAL_NVIC_EnableIRQ(FLASH_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
// USB
|
||||||
|
|
||||||
|
USBD_HandleTypeDef hUSBDDevice;
|
||||||
|
|
||||||
|
void usb_init(void) {
|
||||||
|
const uint16_t vid = 0x1209;
|
||||||
|
const uint16_t pid = 0x53C1;
|
||||||
|
|
||||||
|
USBD_HID_ModeInfoTypeDef hid_info = {
|
||||||
|
.subclass = 0,
|
||||||
|
.protocol = 0,
|
||||||
|
.max_packet_len = 64,
|
||||||
|
.polling_interval = 1,
|
||||||
|
.report_desc = (const uint8_t*)"\x06\x00\xff\x09\x01\xa1\x01\x09\x20\x15\x00\x26\xff\x00\x75\x08\x95\x40\x81\x02\x09\x21\x15\x00\x26\xff\x00\x75\x08\x95\x40\x91\x02\xc0",
|
||||||
|
.report_desc_len = 34,
|
||||||
|
};
|
||||||
|
|
||||||
|
USBD_SetVIDPIDRelease(vid, pid, 0x0200, 0);
|
||||||
|
if (USBD_SelectMode(USBD_MODE_CDC_HID, &hid_info) != 0) {
|
||||||
|
for (;;) {
|
||||||
|
__fatal_error("USB init failed");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
USBD_Init(&hUSBDDevice, (USBD_DescriptorsTypeDef*)&USBD_Descriptors, 0); // 0 == full speed
|
||||||
|
USBD_RegisterClass(&hUSBDDevice, &USBD_CDC_MSC_HID);
|
||||||
|
USBD_CDC_RegisterInterface(&hUSBDDevice, (USBD_CDC_ItfTypeDef*)&USBD_CDC_fops);
|
||||||
|
USBD_HID_RegisterInterface(&hUSBDDevice, (USBD_HID_ItfTypeDef*)&USBD_HID_fops);
|
||||||
|
USBD_Start(&hUSBDDevice);
|
||||||
|
}
|
||||||
|
|
||||||
|
// I2C
|
||||||
|
|
||||||
|
I2C_HandleTypeDef *I2CHandle1;
|
||||||
|
|
||||||
|
void i2c_init(I2C_HandleTypeDef *i2c) {
|
||||||
|
|
||||||
|
// Enable I2C clock
|
||||||
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
||||||
|
|
||||||
|
// Init SCL and SDA GPIO lines (PB6 & PB7)
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure = {
|
||||||
|
.Pin = GPIO_PIN_6 | GPIO_PIN_7,
|
||||||
|
.Mode = GPIO_MODE_AF_OD,
|
||||||
|
.Pull = GPIO_NOPULL,
|
||||||
|
.Speed = GPIO_SPEED_FREQ_VERY_HIGH,
|
||||||
|
.Alternate = GPIO_AF4_I2C1,
|
||||||
|
};
|
||||||
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
// Init I2C handle
|
||||||
|
if (HAL_I2C_Init(i2c) != HAL_OK) {
|
||||||
|
for (;;) {
|
||||||
|
__fatal_error("i2c_init failed");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Enable IRQs
|
||||||
|
I2CHandle1 = i2c;
|
||||||
|
HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
|
||||||
|
HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
// RNG
|
||||||
|
|
||||||
|
STATIC RNG_HandleTypeDef rng_handle = {
|
||||||
|
.State = HAL_RNG_STATE_RESET,
|
||||||
|
.Instance = RNG,
|
||||||
|
};
|
||||||
|
|
||||||
|
void rng_init(RNG_HandleTypeDef *rng) {
|
||||||
|
|
||||||
|
// Enable RNG clock
|
||||||
|
__HAL_RCC_RNG_CLK_ENABLE();
|
||||||
|
|
||||||
|
// Init RNG handle
|
||||||
|
HAL_RNG_Init(rng);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t rng_get(void) {
|
||||||
|
if (rng_handle.State == HAL_RNG_STATE_RESET) {
|
||||||
|
rng_init(&rng_handle);
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_RNG_GetRandomNumber(&rng_handle);
|
||||||
|
}
|
||||||
|
|
||||||
|
// I/O
|
||||||
|
|
||||||
|
mp_lexer_t *mp_lexer_new_from_file(const char *filename) {
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
mp_import_stat_t mp_import_stat(const char *path) {
|
||||||
|
return MP_IMPORT_STAT_NO_EXIST;
|
||||||
|
}
|
||||||
|
|
||||||
|
mp_obj_t mp_builtin_open(uint n_args, const mp_obj_t *args, mp_map_t *kwargs) {
|
||||||
|
return mp_const_none;
|
||||||
|
}
|
||||||
|
MP_DEFINE_CONST_FUN_OBJ_KW(mp_builtin_open_obj, 1, mp_builtin_open);
|
||||||
|
|
||||||
|
int mp_hal_stdin_rx_chr(void) {
|
||||||
|
for (;;) {
|
||||||
|
byte c;
|
||||||
|
if (USBD_CDC_Rx(&c, 1, 0) != 0) {
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void mp_hal_stdout_tx_strn(const char *str, size_t len) {
|
||||||
|
USBD_CDC_TxAlways((const uint8_t*)str, len);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Time
|
||||||
|
|
||||||
|
bool mp_hal_ticks_cpu_enabled;
|
||||||
|
|
||||||
|
void mp_hal_ticks_cpu_enable(void) {
|
||||||
|
if (!mp_hal_ticks_cpu_enabled) {
|
||||||
|
// CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||||
|
// DWT->CYCCNT = 0;
|
||||||
|
// DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
||||||
|
mp_hal_ticks_cpu_enabled = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
54
micropython/trezorhal/modutime.c
Normal file
54
micropython/trezorhal/modutime.c
Normal file
@ -0,0 +1,54 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the Micro Python project, http://micropython.org/
|
||||||
|
*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2013, 2014 Damien P. George
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include STM32_HAL_H
|
||||||
|
|
||||||
|
#include "py/nlr.h"
|
||||||
|
#include "py/smallint.h"
|
||||||
|
#include "py/obj.h"
|
||||||
|
#include "extmod/utime_mphal.h"
|
||||||
|
|
||||||
|
STATIC const mp_rom_map_elem_t time_module_globals_table[] = {
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_utime) },
|
||||||
|
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&mp_utime_sleep_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_sleep_ms), MP_ROM_PTR(&mp_utime_sleep_ms_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_sleep_us), MP_ROM_PTR(&mp_utime_sleep_us_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_ticks_ms), MP_ROM_PTR(&mp_utime_ticks_ms_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_ticks_us), MP_ROM_PTR(&mp_utime_ticks_us_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_ticks_cpu), MP_ROM_PTR(&mp_utime_ticks_cpu_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_ticks_add), MP_ROM_PTR(&mp_utime_ticks_add_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_ticks_diff), MP_ROM_PTR(&mp_utime_ticks_diff_obj) },
|
||||||
|
};
|
||||||
|
|
||||||
|
STATIC MP_DEFINE_CONST_DICT(time_module_globals, time_module_globals_table);
|
||||||
|
|
||||||
|
const mp_obj_module_t mp_module_utime = {
|
||||||
|
.base = { &mp_type_module },
|
||||||
|
.globals = (mp_obj_dict_t*)&time_module_globals,
|
||||||
|
};
|
||||||
@ -23,10 +23,15 @@
|
|||||||
#define MICROPY_HW_CLK_LAST_FREQ (1)
|
#define MICROPY_HW_CLK_LAST_FREQ (1)
|
||||||
|
|
||||||
// I2C busses
|
// I2C busses
|
||||||
#define MICROPY_HW_I2C1_NAME "X"
|
#define MICROPY_HW_I2C1_NAME "I2C"
|
||||||
#define MICROPY_HW_I2C1_SCL (pin_B6)
|
#define MICROPY_HW_I2C1_SCL (pin_B6)
|
||||||
#define MICROPY_HW_I2C1_SDA (pin_B7)
|
#define MICROPY_HW_I2C1_SDA (pin_B7)
|
||||||
|
|
||||||
|
// UART config
|
||||||
|
#define MICROPY_HW_UART1_NAME "UART"
|
||||||
|
#define MICROPY_HW_UART1_TX (pin_A2)
|
||||||
|
#define MICROPY_HW_UART1_RX (pin_A3)
|
||||||
|
|
||||||
// The board has 2 LEDs
|
// The board has 2 LEDs
|
||||||
#define MICROPY_HW_LED1 (pin_C6)
|
#define MICROPY_HW_LED1 (pin_C6)
|
||||||
#define MICROPY_HW_LED2 (pin_B13)
|
#define MICROPY_HW_LED2 (pin_B13)
|
||||||
@ -39,3 +44,6 @@
|
|||||||
#define MICROPY_HW_SDCARD_DETECT_PIN (pin_C13)
|
#define MICROPY_HW_SDCARD_DETECT_PIN (pin_C13)
|
||||||
#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_PULLUP)
|
#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_PULLUP)
|
||||||
#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_RESET)
|
#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_RESET)
|
||||||
|
|
||||||
|
// USB config
|
||||||
|
#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
|
||||||
170
micropython/trezorhal/mpconfigport.h
Normal file
170
micropython/trezorhal/mpconfigport.h
Normal file
@ -0,0 +1,170 @@
|
|||||||
|
#include <limits.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <alloca.h>
|
||||||
|
|
||||||
|
// Memory allocation policies
|
||||||
|
#define MICROPY_ALLOC_PATH_MAX (128)
|
||||||
|
|
||||||
|
// Emitters
|
||||||
|
#define MICROPY_PERSISTENT_CODE_LOAD (0)
|
||||||
|
#define MICROPY_EMIT_THUMB (0)
|
||||||
|
#define MICROPY_EMIT_INLINE_THUMB (0)
|
||||||
|
|
||||||
|
// Compiler configuration
|
||||||
|
#define MICROPY_ENABLE_COMPILER (1)
|
||||||
|
#define MICROPY_COMP_MODULE_CONST (1)
|
||||||
|
#define MICROPY_COMP_DOUBLE_TUPLE_ASSIGN (1)
|
||||||
|
#define MICROPY_COMP_TRIPLE_TUPLE_ASSIGN (1)
|
||||||
|
|
||||||
|
// Optimisations
|
||||||
|
#define MICROPY_OPT_COMPUTED_GOTO (1)
|
||||||
|
#define MICROPY_OPT_MPZ_BITWISE (1)
|
||||||
|
|
||||||
|
// Python internal features
|
||||||
|
#define MICROPY_READER_VFS (0)
|
||||||
|
#define MICROPY_ENABLE_GC (1)
|
||||||
|
#define MICROPY_ENABLE_FINALISER (1)
|
||||||
|
#define MICROPY_STACK_CHECK (1)
|
||||||
|
#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1)
|
||||||
|
#define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0)
|
||||||
|
#define MICROPY_KBD_EXCEPTION (1)
|
||||||
|
#define MICROPY_HELPER_REPL (1)
|
||||||
|
#define MICROPY_REPL_EMACS_KEYS (1)
|
||||||
|
#define MICROPY_REPL_AUTO_INDENT (1)
|
||||||
|
#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ)
|
||||||
|
#define MICROPY_ENABLE_SOURCE_LINE (1)
|
||||||
|
#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT)
|
||||||
|
#define MICROPY_STREAMS_NON_BLOCK (1)
|
||||||
|
#define MICROPY_MODULE_WEAK_LINKS (1)
|
||||||
|
#define MICROPY_MODULE_FROZEN_MPY (1)
|
||||||
|
#define MICROPY_CAN_OVERRIDE_BUILTINS (1)
|
||||||
|
#define MICROPY_USE_INTERNAL_ERRNO (1)
|
||||||
|
#define MICROPY_VFS (0)
|
||||||
|
#define MICROPY_VFS_FAT (0)
|
||||||
|
#define MICROPY_QSTR_EXTRA_POOL mp_qstr_frozen_const_pool
|
||||||
|
|
||||||
|
// Control over Python builtins
|
||||||
|
#define MICROPY_PY_FUNCTION_ATTRS (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_STR_UNICODE (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_STR_CENTER (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_STR_PARTITION (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_STR_SPLITLINES (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_MEMORYVIEW (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_FROZENSET (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_SLICE_ATTRS (1)
|
||||||
|
#define MICROPY_PY_ALL_SPECIAL_METHODS (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_COMPILE (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_EXECFILE (1)
|
||||||
|
#define MICROPY_PY_BUILTINS_POW3 (0)
|
||||||
|
#define MICROPY_PY_BUILTINS_HELP (0)
|
||||||
|
#define MICROPY_PY_BUILTINS_HELP_MODULES (0)
|
||||||
|
#define MICROPY_PY_MICROPYTHON_MEM_INFO (1)
|
||||||
|
#define MICROPY_PY_ARRAY_SLICE_ASSIGN (1)
|
||||||
|
#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1)
|
||||||
|
#define MICROPY_PY_MATH_SPECIAL_FUNCTIONS (1)
|
||||||
|
#define MICROPY_PY_CMATH (1)
|
||||||
|
#define MICROPY_PY_IO (0)
|
||||||
|
#define MICROPY_PY_IO_FILEIO (0)
|
||||||
|
#define MICROPY_PY_SYS_MAXSIZE (0)
|
||||||
|
#define MICROPY_PY_SYS_EXIT (0)
|
||||||
|
#define MICROPY_PY_SYS_STDFILES (0)
|
||||||
|
#define MICROPY_PY_SYS_STDIO_BUFFER (0)
|
||||||
|
#define MICROPY_PY_UERRNO (1)
|
||||||
|
#define MICROPY_PY_THREAD (0)
|
||||||
|
#define MICROPY_PY_THREAD_GIL (0)
|
||||||
|
|
||||||
|
// Extended modules
|
||||||
|
#define MICROPY_PY_UBINASCII (1)
|
||||||
|
#define MICROPY_PY_UCTYPES (1)
|
||||||
|
#define MICROPY_PY_UZLIB (1)
|
||||||
|
#define MICROPY_PY_UTIME_MP_HAL (1)
|
||||||
|
#define MICROPY_PY_UTIMEQ (1)
|
||||||
|
#define MICROPY_PY_TREZORCONFIG (1)
|
||||||
|
#define MICROPY_PY_TREZORCRYPTO (1)
|
||||||
|
#define MICROPY_PY_TREZORDEBUG (1)
|
||||||
|
#define MICROPY_PY_TREZORMSG (1)
|
||||||
|
#define MICROPY_PY_TREZORUI (1)
|
||||||
|
#define MICROPY_PY_TREZORUTILS (1)
|
||||||
|
|
||||||
|
// Type definitions for the specific machine
|
||||||
|
|
||||||
|
#include STM32_HAL_H
|
||||||
|
|
||||||
|
static inline void enable_irq(uint32_t state) {
|
||||||
|
__set_PRIMASK(state);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline uint32_t disable_irq(void) {
|
||||||
|
uint32_t st = __get_PRIMASK();
|
||||||
|
__disable_irq();
|
||||||
|
return st;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define BYTES_PER_WORD (4)
|
||||||
|
#define MP_HAL_UNIQUE_ID_ADDRESS (0x1fff7a10)
|
||||||
|
#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1))
|
||||||
|
#define MP_PLAT_PRINT_STRN(str, len) mp_hal_stdout_tx_strn_cooked(str, len)
|
||||||
|
|
||||||
|
// This port is intended to be 32-bit, but unfortunately, int32_t for
|
||||||
|
// different targets may be defined in different ways - either as int
|
||||||
|
// or as long. This requires different printf formatting specifiers
|
||||||
|
// to print such value. So, we avoid int32_t and use int directly.
|
||||||
|
#define UINT_FMT "%u"
|
||||||
|
#define INT_FMT "%d"
|
||||||
|
typedef int mp_int_t; // must be pointer size
|
||||||
|
typedef unsigned mp_uint_t; // must be pointer size
|
||||||
|
typedef long mp_off_t;
|
||||||
|
|
||||||
|
#define MP_SSIZE_MAX INT_MAX
|
||||||
|
#define MICROPY_MIN_USE_CORTEX_CPU (1)
|
||||||
|
#define MICROPY_MIN_USE_STM32_MCU (1)
|
||||||
|
#define MICROPY_HW_BOARD_NAME "TREZORv2"
|
||||||
|
#define MICROPY_HW_MCU_NAME "STM32F405VG"
|
||||||
|
#define MICROPY_PY_SYS_PLATFORM "trezor"
|
||||||
|
|
||||||
|
#define MP_STATE_PORT MP_STATE_VM
|
||||||
|
#define MICROPY_PORT_ROOT_POINTERS const char *readline_hist[8];
|
||||||
|
|
||||||
|
extern const struct _mp_obj_module_t mp_module_utime;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_TrezorConfig;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_TrezorCrypto;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_TrezorDebug;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_TrezorMsg;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_TrezorUi;
|
||||||
|
extern const struct _mp_obj_module_t mp_module_TrezorUtils;
|
||||||
|
|
||||||
|
// Extra built in modules to add to the list of known ones
|
||||||
|
#define MICROPY_PORT_BUILTIN_MODULES \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_utime), (mp_obj_t)&mp_module_utime }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_TrezorConfig), (mp_obj_t)&mp_module_TrezorConfig }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_TrezorCrypto), (mp_obj_t)&mp_module_TrezorCrypto }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_TrezorDebug), (mp_obj_t)&mp_module_TrezorDebug }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_TrezorMsg), (mp_obj_t)&mp_module_TrezorMsg }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_TrezorUi), (mp_obj_t)&mp_module_TrezorUi }, \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_TrezorUtils), (mp_obj_t)&mp_module_TrezorUtils },
|
||||||
|
|
||||||
|
// Extra built in names to add to the global namespace
|
||||||
|
#define MICROPY_PORT_BUILTINS \
|
||||||
|
{ MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj },
|
||||||
|
|
||||||
|
// Timing functions
|
||||||
|
|
||||||
|
#include "stmhal/systick.h"
|
||||||
|
|
||||||
|
#define mp_hal_delay_ms HAL_Delay
|
||||||
|
#define mp_hal_delay_us(us) sys_tick_udelay(us)
|
||||||
|
#define mp_hal_delay_us_fast(us) sys_tick_udelay(us)
|
||||||
|
#define mp_hal_ticks_ms HAL_GetTick
|
||||||
|
#define mp_hal_ticks_us() sys_tick_get_microseconds()
|
||||||
|
|
||||||
|
extern bool mp_hal_ticks_cpu_enabled;
|
||||||
|
|
||||||
|
void mp_hal_ticks_cpu_enable(void);
|
||||||
|
|
||||||
|
static inline mp_uint_t mp_hal_ticks_cpu(void) {
|
||||||
|
if (!mp_hal_ticks_cpu_enabled) {
|
||||||
|
mp_hal_ticks_cpu_enable();
|
||||||
|
}
|
||||||
|
return DWT->CYCCNT;
|
||||||
|
}
|
||||||
1
micropython/trezorhal/mphalport.h
Normal file
1
micropython/trezorhal/mphalport.h
Normal file
@ -0,0 +1 @@
|
|||||||
|
static inline void mp_hal_set_interrupt_char(char c) {}
|
||||||
1
micropython/trezorhal/qstrdefsport.h
Normal file
1
micropython/trezorhal/qstrdefsport.h
Normal file
@ -0,0 +1 @@
|
|||||||
|
// qstrs specific to this port
|
||||||
754
micropython/trezorhal/stm32_it.c
Normal file
754
micropython/trezorhal/stm32_it.c
Normal file
@ -0,0 +1,754 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the Micro Python project, http://micropython.org/
|
||||||
|
*
|
||||||
|
* Original template from ST Cube library. See below for header.
|
||||||
|
*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2013, 2014 Damien P. George
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file Templates/Src/stm32f4xx_it.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 26-February-2014
|
||||||
|
* @brief Main Interrupt Service Routines.
|
||||||
|
* This file provides template for all exceptions handler and
|
||||||
|
* peripherals interrupt service routine.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
#include STM32_HAL_H
|
||||||
|
|
||||||
|
#include "py/mphal.h"
|
||||||
|
#include "pendsv.h"
|
||||||
|
#include "gccollect.h"
|
||||||
|
|
||||||
|
#define IRQ_ENTER(irq)
|
||||||
|
#define IRQ_EXIT(irq)
|
||||||
|
|
||||||
|
extern void __fatal_error(const char*);
|
||||||
|
extern PCD_HandleTypeDef pcd_fs_handle;
|
||||||
|
extern PCD_HandleTypeDef pcd_hs_handle;
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Cortex-M4 Processor Exceptions Handlers */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
// Set the following to 1 to get some more information on the Hard Fault
|
||||||
|
// More information about decoding the fault registers can be found here:
|
||||||
|
// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/Cihdjcfc.html
|
||||||
|
|
||||||
|
STATIC char *fmt_hex(uint32_t val, char *buf) {
|
||||||
|
const char *hexDig = "0123456789abcdef";
|
||||||
|
|
||||||
|
buf[0] = hexDig[(val >> 28) & 0x0f];
|
||||||
|
buf[1] = hexDig[(val >> 24) & 0x0f];
|
||||||
|
buf[2] = hexDig[(val >> 20) & 0x0f];
|
||||||
|
buf[3] = hexDig[(val >> 16) & 0x0f];
|
||||||
|
buf[4] = hexDig[(val >> 12) & 0x0f];
|
||||||
|
buf[5] = hexDig[(val >> 8) & 0x0f];
|
||||||
|
buf[6] = hexDig[(val >> 4) & 0x0f];
|
||||||
|
buf[7] = hexDig[(val >> 0) & 0x0f];
|
||||||
|
buf[8] = '\0';
|
||||||
|
|
||||||
|
return buf;
|
||||||
|
}
|
||||||
|
|
||||||
|
STATIC void print_reg(const char *label, uint32_t val) {
|
||||||
|
char hexStr[9];
|
||||||
|
|
||||||
|
mp_hal_stdout_tx_str(label);
|
||||||
|
mp_hal_stdout_tx_str(fmt_hex(val, hexStr));
|
||||||
|
mp_hal_stdout_tx_str("\r\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
STATIC void print_hex_hex(const char *label, uint32_t val1, uint32_t val2) {
|
||||||
|
char hex_str[9];
|
||||||
|
mp_hal_stdout_tx_str(label);
|
||||||
|
mp_hal_stdout_tx_str(fmt_hex(val1, hex_str));
|
||||||
|
mp_hal_stdout_tx_str(" ");
|
||||||
|
mp_hal_stdout_tx_str(fmt_hex(val2, hex_str));
|
||||||
|
mp_hal_stdout_tx_str("\r\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
// The ARMv7M Architecture manual (section B.1.5.6) says that upon entry
|
||||||
|
// to an exception, that the registers will be in the following order on the
|
||||||
|
// stack: R0, R1, R2, R3, R12, LR, PC, XPSR
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint32_t r0, r1, r2, r3, r12, lr, pc, xpsr;
|
||||||
|
} ExceptionRegisters_t;
|
||||||
|
|
||||||
|
int pyb_hard_fault_debug = 1;
|
||||||
|
|
||||||
|
void HardFault_C_Handler(ExceptionRegisters_t *regs) {
|
||||||
|
if (!pyb_hard_fault_debug) {
|
||||||
|
NVIC_SystemReset();
|
||||||
|
}
|
||||||
|
|
||||||
|
// We need to disable the USB so it doesn't try to write data out on
|
||||||
|
// the VCP and then block indefinitely waiting for the buffer to drain.
|
||||||
|
// pyb_usb_flags = 0;
|
||||||
|
|
||||||
|
mp_hal_stdout_tx_str("HardFault\r\n");
|
||||||
|
|
||||||
|
print_reg("R0 ", regs->r0);
|
||||||
|
print_reg("R1 ", regs->r1);
|
||||||
|
print_reg("R2 ", regs->r2);
|
||||||
|
print_reg("R3 ", regs->r3);
|
||||||
|
print_reg("R12 ", regs->r12);
|
||||||
|
print_reg("SP ", (uint32_t)regs);
|
||||||
|
print_reg("LR ", regs->lr);
|
||||||
|
print_reg("PC ", regs->pc);
|
||||||
|
print_reg("XPSR ", regs->xpsr);
|
||||||
|
|
||||||
|
uint32_t cfsr = SCB->CFSR;
|
||||||
|
|
||||||
|
print_reg("HFSR ", SCB->HFSR);
|
||||||
|
print_reg("CFSR ", cfsr);
|
||||||
|
if (cfsr & 0x80) {
|
||||||
|
print_reg("MMFAR ", SCB->MMFAR);
|
||||||
|
}
|
||||||
|
if (cfsr & 0x8000) {
|
||||||
|
print_reg("BFAR ", SCB->BFAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((void*)&_ram_start <= (void*)regs && (void*)regs < (void*)&_ram_end) {
|
||||||
|
mp_hal_stdout_tx_str("Stack:\r\n");
|
||||||
|
uint32_t *stack_top = &_estack;
|
||||||
|
if ((void*)regs < (void*)&_heap_end) {
|
||||||
|
// stack not in static stack area so limit the amount we print
|
||||||
|
stack_top = (uint32_t*)regs + 32;
|
||||||
|
}
|
||||||
|
for (uint32_t *sp = (uint32_t*)regs; sp < stack_top; ++sp) {
|
||||||
|
print_hex_hex(" ", (uint32_t)sp, *sp);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Go to infinite loop when Hard Fault exception occurs */
|
||||||
|
while (1) {
|
||||||
|
__fatal_error("HardFault");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Naked functions have no compiler generated gunk, so are the best thing to
|
||||||
|
// use for asm functions.
|
||||||
|
__attribute__((naked))
|
||||||
|
void HardFault_Handler(void) {
|
||||||
|
|
||||||
|
// From the ARMv7M Architecture Reference Manual, section B.1.5.6
|
||||||
|
// on entry to the Exception, the LR register contains, amongst other
|
||||||
|
// things, the value of CONTROL.SPSEL. This can be found in bit 3.
|
||||||
|
//
|
||||||
|
// If CONTROL.SPSEL is 0, then the exception was stacked up using the
|
||||||
|
// main stack pointer (aka MSP). If CONTROL.SPSEL is 1, then the exception
|
||||||
|
// was stacked up using the process stack pointer (aka PSP).
|
||||||
|
|
||||||
|
__asm volatile(
|
||||||
|
" tst lr, #4 \n" // Test Bit 3 to see which stack pointer we should use.
|
||||||
|
" ite eq \n" // Tell the assembler that the nest 2 instructions are if-then-else
|
||||||
|
" mrseq r0, msp \n" // Make R0 point to main stack pointer
|
||||||
|
" mrsne r0, psp \n" // Make R0 point to process stack pointer
|
||||||
|
" b HardFault_C_Handler \n" // Off to C land
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles NMI exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void NMI_Handler(void) {
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Memory Manage exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void MemManage_Handler(void) {
|
||||||
|
/* Go to infinite loop when Memory Manage exception occurs */
|
||||||
|
while (1) {
|
||||||
|
__fatal_error("MemManage");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Bus Fault exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BusFault_Handler(void) {
|
||||||
|
/* Go to infinite loop when Bus Fault exception occurs */
|
||||||
|
while (1) {
|
||||||
|
__fatal_error("BusFault");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Usage Fault exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void UsageFault_Handler(void) {
|
||||||
|
/* Go to infinite loop when Usage Fault exception occurs */
|
||||||
|
while (1) {
|
||||||
|
__fatal_error("UsageFault");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles SVCall exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SVC_Handler(void) {
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Debug Monitor exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DebugMon_Handler(void) {
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles PendSVC exception.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PendSV_Handler(void) {
|
||||||
|
pendsv_isr_handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles SysTick Handler.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SysTick_Handler(void) {
|
||||||
|
// Instead of calling HAL_IncTick we do the increment here of the counter.
|
||||||
|
// This is purely for efficiency, since SysTick is called 1000 times per
|
||||||
|
// second at the highest interrupt priority.
|
||||||
|
// Note: we don't need uwTick to be declared volatile here because this is
|
||||||
|
// the only place where it can be modified, and the code is more efficient
|
||||||
|
// without the volatile specifier.
|
||||||
|
extern uint32_t uwTick;
|
||||||
|
uwTick += 1;
|
||||||
|
|
||||||
|
// Read the systick control regster. This has the side effect of clearing
|
||||||
|
// the COUNTFLAG bit, which makes the logic in sys_tick_get_microseconds
|
||||||
|
// work properly.
|
||||||
|
SysTick->CTRL;
|
||||||
|
|
||||||
|
// Right now we have the storage and DMA controllers to process during
|
||||||
|
// this interrupt and we use custom dispatch handlers. If this needs to
|
||||||
|
// be generalised in the future then a dispatch table can be used as
|
||||||
|
// follows: ((void(*)(void))(systick_dispatch[uwTick & 0xf]))();
|
||||||
|
|
||||||
|
// if (STORAGE_IDLE_TICK(uwTick)) {
|
||||||
|
// NVIC->STIR = FLASH_IRQn;
|
||||||
|
// }
|
||||||
|
|
||||||
|
// if (DMA_IDLE_ENABLED() && DMA_IDLE_TICK(uwTick)) {
|
||||||
|
// dma_idle_handler(uwTick);
|
||||||
|
// }
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* STM32F4xx Peripherals Interrupt Handlers */
|
||||||
|
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
|
||||||
|
/* available peripheral interrupt handler's name please refer to the startup */
|
||||||
|
/* file (startup_stm32f4xx.s). */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles USB-On-The-Go FS global interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#if defined(USE_USB_FS)
|
||||||
|
void OTG_FS_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(OTG_FS_IRQn);
|
||||||
|
HAL_PCD_IRQHandler(&pcd_fs_handle);
|
||||||
|
IRQ_EXIT(OTG_FS_IRQn);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if defined(USE_USB_HS)
|
||||||
|
void OTG_HS_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(OTG_HS_IRQn);
|
||||||
|
HAL_PCD_IRQHandler(&pcd_hs_handle);
|
||||||
|
IRQ_EXIT(OTG_HS_IRQn);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(USE_USB_FS) || defined(USE_USB_HS)
|
||||||
|
/**
|
||||||
|
* @brief This function handles USB OTG Common FS/HS Wakeup functions.
|
||||||
|
* @param *pcd_handle for FS or HS
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
STATIC void OTG_CMD_WKUP_Handler(PCD_HandleTypeDef *pcd_handle) {
|
||||||
|
|
||||||
|
if (pcd_handle->Init.low_power_enable) {
|
||||||
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||||
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
||||||
|
|
||||||
|
/* Configures system clock after wake-up from STOP: enable HSE, PLL and select
|
||||||
|
PLL as system clock source (HSE and PLL are disabled in STOP mode) */
|
||||||
|
|
||||||
|
__HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
|
||||||
|
|
||||||
|
/* Wait till HSE is ready */
|
||||||
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
||||||
|
{}
|
||||||
|
|
||||||
|
/* Enable the main PLL. */
|
||||||
|
__HAL_RCC_PLL_ENABLE();
|
||||||
|
|
||||||
|
/* Wait till PLL is ready */
|
||||||
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
||||||
|
{}
|
||||||
|
|
||||||
|
/* Select PLL as SYSCLK */
|
||||||
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
|
||||||
|
|
||||||
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
||||||
|
{}
|
||||||
|
|
||||||
|
/* ungate PHY clock */
|
||||||
|
__HAL_PCD_UNGATE_PHYCLOCK(pcd_handle);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(USE_USB_FS)
|
||||||
|
/**
|
||||||
|
* @brief This function handles USB OTG FS Wakeup IRQ Handler.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void OTG_FS_WKUP_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(OTG_FS_WKUP_IRQn);
|
||||||
|
|
||||||
|
OTG_CMD_WKUP_Handler(&pcd_fs_handle);
|
||||||
|
|
||||||
|
/* Clear EXTI pending Bit*/
|
||||||
|
__HAL_USB_FS_EXTI_CLEAR_FLAG();
|
||||||
|
|
||||||
|
IRQ_EXIT(OTG_FS_WKUP_IRQn);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(USE_USB_HS)
|
||||||
|
/**
|
||||||
|
* @brief This function handles USB OTG HS Wakeup IRQ Handler.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void OTG_HS_WKUP_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(OTG_HS_WKUP_IRQn);
|
||||||
|
|
||||||
|
OTG_CMD_WKUP_Handler(&pcd_hs_handle);
|
||||||
|
|
||||||
|
/* Clear EXTI pending Bit*/
|
||||||
|
__HAL_USB_HS_EXTI_CLEAR_FLAG();
|
||||||
|
|
||||||
|
IRQ_EXIT(OTG_HS_WKUP_IRQn);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles PPP interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
/*void PPP_IRQHandler(void)
|
||||||
|
{
|
||||||
|
}*/
|
||||||
|
|
||||||
|
// Handle a flash (erase/program) interrupt.
|
||||||
|
void FLASH_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(FLASH_IRQn);
|
||||||
|
// This calls the real flash IRQ handler, if needed
|
||||||
|
/*
|
||||||
|
uint32_t flash_cr = FLASH->CR;
|
||||||
|
if ((flash_cr & FLASH_IT_EOP) || (flash_cr & FLASH_IT_ERR)) {
|
||||||
|
HAL_FLASH_IRQHandler();
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
// This call the storage IRQ handler, to check if the flash cache needs flushing
|
||||||
|
// storage_irq_handler();
|
||||||
|
IRQ_EXIT(FLASH_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief These functions handle the EXTI interrupt requests.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
// void EXTI0_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI0_IRQn);
|
||||||
|
// Handle_EXTI_Irq(0);
|
||||||
|
// IRQ_EXIT(EXTI0_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void EXTI1_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI1_IRQn);
|
||||||
|
// Handle_EXTI_Irq(1);
|
||||||
|
// IRQ_EXIT(EXTI1_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void EXTI2_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI2_IRQn);
|
||||||
|
// Handle_EXTI_Irq(2);
|
||||||
|
// IRQ_EXIT(EXTI2_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void EXTI3_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI3_IRQn);
|
||||||
|
// Handle_EXTI_Irq(3);
|
||||||
|
// IRQ_EXIT(EXTI3_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void EXTI4_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI4_IRQn);
|
||||||
|
// Handle_EXTI_Irq(4);
|
||||||
|
// IRQ_EXIT(EXTI4_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void EXTI9_5_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI9_5_IRQn);
|
||||||
|
// Handle_EXTI_Irq(5);
|
||||||
|
// Handle_EXTI_Irq(6);
|
||||||
|
// Handle_EXTI_Irq(7);
|
||||||
|
// Handle_EXTI_Irq(8);
|
||||||
|
// Handle_EXTI_Irq(9);
|
||||||
|
// IRQ_EXIT(EXTI9_5_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void EXTI15_10_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(EXTI15_10_IRQn);
|
||||||
|
// Handle_EXTI_Irq(10);
|
||||||
|
// Handle_EXTI_Irq(11);
|
||||||
|
// Handle_EXTI_Irq(12);
|
||||||
|
// Handle_EXTI_Irq(13);
|
||||||
|
// Handle_EXTI_Irq(14);
|
||||||
|
// Handle_EXTI_Irq(15);
|
||||||
|
// IRQ_EXIT(EXTI15_10_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void PVD_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(PVD_IRQn);
|
||||||
|
// Handle_EXTI_Irq(EXTI_PVD_OUTPUT);
|
||||||
|
// IRQ_EXIT(PVD_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(MCU_SERIES_L4)
|
||||||
|
// void PVD_PVM_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(PVD_PVM_IRQn);
|
||||||
|
// Handle_EXTI_Irq(EXTI_PVD_OUTPUT);
|
||||||
|
// IRQ_EXIT(PVD_PVM_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// void RTC_Alarm_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(RTC_Alarm_IRQn);
|
||||||
|
// Handle_EXTI_Irq(EXTI_RTC_ALARM);
|
||||||
|
// IRQ_EXIT(RTC_Alarm_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(ETH) // The 407 has ETH, the 405 doesn't
|
||||||
|
// void ETH_WKUP_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(ETH_WKUP_IRQn);
|
||||||
|
// Handle_EXTI_Irq(EXTI_ETH_WAKEUP);
|
||||||
|
// IRQ_EXIT(ETH_WKUP_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// void TAMP_STAMP_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TAMP_STAMP_IRQn);
|
||||||
|
// Handle_EXTI_Irq(EXTI_RTC_TIMESTAMP);
|
||||||
|
// IRQ_EXIT(TAMP_STAMP_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void RTC_WKUP_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(RTC_WKUP_IRQn);
|
||||||
|
// RTC->ISR &= ~(1 << 10); // clear wakeup interrupt flag
|
||||||
|
// Handle_EXTI_Irq(EXTI_RTC_WAKEUP); // clear EXTI flag and execute optional callback
|
||||||
|
// IRQ_EXIT(RTC_WKUP_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM1_BRK_TIM9_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_BRK_TIM9_IRQn);
|
||||||
|
// timer_irq_handler(9);
|
||||||
|
// IRQ_EXIT(TIM1_BRK_TIM9_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(MCU_SERIES_L4)
|
||||||
|
// void TIM1_BRK_TIM15_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_BRK_TIM15_IRQn);
|
||||||
|
// timer_irq_handler(15);
|
||||||
|
// IRQ_EXIT(TIM1_BRK_TIM15_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// void TIM1_UP_TIM10_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_UP_TIM10_IRQn);
|
||||||
|
// timer_irq_handler(1);
|
||||||
|
// timer_irq_handler(10);
|
||||||
|
// IRQ_EXIT(TIM1_UP_TIM10_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(MCU_SERIES_L4)
|
||||||
|
// void TIM1_UP_TIM16_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_UP_TIM16_IRQn);
|
||||||
|
// timer_irq_handler(1);
|
||||||
|
// timer_irq_handler(16);
|
||||||
|
// IRQ_EXIT(TIM1_UP_TIM16_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// void TIM1_TRG_COM_TIM11_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_TRG_COM_TIM11_IRQn);
|
||||||
|
// timer_irq_handler(11);
|
||||||
|
// IRQ_EXIT(TIM1_TRG_COM_TIM11_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(MCU_SERIES_L4)
|
||||||
|
// void TIM1_TRG_COM_TIM17_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_TRG_COM_TIM17_IRQn);
|
||||||
|
// timer_irq_handler(17);
|
||||||
|
// IRQ_EXIT(TIM1_TRG_COM_TIM17_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// void TIM1_CC_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM1_CC_IRQn);
|
||||||
|
// timer_irq_handler(1);
|
||||||
|
// IRQ_EXIT(TIM1_CC_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM2_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM2_IRQn);
|
||||||
|
// timer_irq_handler(2);
|
||||||
|
// IRQ_EXIT(TIM2_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM3_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM3_IRQn);
|
||||||
|
// timer_irq_handler(3);
|
||||||
|
// IRQ_EXIT(TIM3_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM4_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM4_IRQn);
|
||||||
|
// timer_irq_handler(4);
|
||||||
|
// IRQ_EXIT(TIM4_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM5_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM5_IRQn);
|
||||||
|
// timer_irq_handler(5);
|
||||||
|
// HAL_TIM_IRQHandler(&TIM5_Handle);
|
||||||
|
// IRQ_EXIT(TIM5_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(TIM6) // STM32F401 doesn't have TIM6
|
||||||
|
// void TIM6_DAC_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM6_DAC_IRQn);
|
||||||
|
// timer_irq_handler(6);
|
||||||
|
// IRQ_EXIT(TIM6_DAC_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// #if defined(TIM7) // STM32F401 doesn't have TIM7
|
||||||
|
// void TIM7_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM7_IRQn);
|
||||||
|
// timer_irq_handler(7);
|
||||||
|
// IRQ_EXIT(TIM7_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// #if defined(TIM8) // STM32F401 doesn't have TIM8
|
||||||
|
// void TIM8_BRK_TIM12_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM8_BRK_TIM12_IRQn);
|
||||||
|
// timer_irq_handler(12);
|
||||||
|
// IRQ_EXIT(TIM8_BRK_TIM12_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM8_UP_TIM13_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM8_UP_TIM13_IRQn);
|
||||||
|
// timer_irq_handler(8);
|
||||||
|
// timer_irq_handler(13);
|
||||||
|
// IRQ_EXIT(TIM8_UP_TIM13_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(MCU_SERIES_L4)
|
||||||
|
// void TIM8_UP_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM8_UP_IRQn);
|
||||||
|
// timer_irq_handler(8);
|
||||||
|
// IRQ_EXIT(TIM8_UP_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// void TIM8_CC_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM8_CC_IRQn);
|
||||||
|
// timer_irq_handler(8);
|
||||||
|
// IRQ_EXIT(TIM8_CC_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void TIM8_TRG_COM_TIM14_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(TIM8_TRG_COM_TIM14_IRQn);
|
||||||
|
// timer_irq_handler(14);
|
||||||
|
// IRQ_EXIT(TIM8_TRG_COM_TIM14_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// // UART/USART IRQ handlers
|
||||||
|
// void USART1_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(USART1_IRQn);
|
||||||
|
// uart_irq_handler(1);
|
||||||
|
// IRQ_EXIT(USART1_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void USART2_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(USART2_IRQn);
|
||||||
|
// uart_irq_handler(2);
|
||||||
|
// IRQ_EXIT(USART2_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void USART3_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(USART3_IRQn);
|
||||||
|
// uart_irq_handler(3);
|
||||||
|
// IRQ_EXIT(USART3_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void UART4_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(UART4_IRQn);
|
||||||
|
// uart_irq_handler(4);
|
||||||
|
// IRQ_EXIT(UART4_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void UART5_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(UART5_IRQn);
|
||||||
|
// uart_irq_handler(5);
|
||||||
|
// IRQ_EXIT(UART5_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void USART6_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(USART6_IRQn);
|
||||||
|
// uart_irq_handler(6);
|
||||||
|
// IRQ_EXIT(USART6_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// #if defined(MICROPY_HW_UART7_TX)
|
||||||
|
// void UART7_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(UART7_IRQn);
|
||||||
|
// uart_irq_handler(7);
|
||||||
|
// IRQ_EXIT(UART7_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// #if defined(MICROPY_HW_UART8_TX)
|
||||||
|
// void UART8_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(UART8_IRQn);
|
||||||
|
// uart_irq_handler(8);
|
||||||
|
// IRQ_EXIT(UART8_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
// #if MICROPY_HW_ENABLE_CAN
|
||||||
|
// void CAN1_RX0_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(CAN1_RX0_IRQn);
|
||||||
|
// can_rx_irq_handler(PYB_CAN_1, CAN_FIFO0);
|
||||||
|
// IRQ_EXIT(CAN1_RX0_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void CAN1_RX1_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(CAN1_RX1_IRQn);
|
||||||
|
// can_rx_irq_handler(PYB_CAN_1, CAN_FIFO1);
|
||||||
|
// IRQ_EXIT(CAN1_RX1_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void CAN2_RX0_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(CAN2_RX0_IRQn);
|
||||||
|
// can_rx_irq_handler(PYB_CAN_2, CAN_FIFO0);
|
||||||
|
// IRQ_EXIT(CAN2_RX0_IRQn);
|
||||||
|
// }
|
||||||
|
|
||||||
|
// void CAN2_RX1_IRQHandler(void) {
|
||||||
|
// IRQ_ENTER(CAN2_RX1_IRQn);
|
||||||
|
// can_rx_irq_handler(PYB_CAN_2, CAN_FIFO1);
|
||||||
|
// IRQ_EXIT(CAN2_RX1_IRQn);
|
||||||
|
// }
|
||||||
|
// #endif // MICROPY_HW_ENABLE_CAN
|
||||||
|
|
||||||
|
#if defined(MICROPY_HW_I2C1_SCL)
|
||||||
|
|
||||||
|
extern I2C_HandleTypeDef *i2c_handle;
|
||||||
|
|
||||||
|
void I2C1_EV_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(I2C1_EV_IRQn);
|
||||||
|
HAL_I2C_EV_IRQHandler(i2c_handle);
|
||||||
|
IRQ_EXIT(I2C1_EV_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
void I2C1_ER_IRQHandler(void) {
|
||||||
|
IRQ_ENTER(I2C1_ER_IRQn);
|
||||||
|
HAL_I2C_ER_IRQHandler(i2c_handle);
|
||||||
|
IRQ_EXIT(I2C1_ER_IRQn);
|
||||||
|
}
|
||||||
|
#endif // defined(MICROPY_HW_I2C1_SCL)
|
||||||
@ -1,411 +1,411 @@
|
|||||||
/**
|
/**
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f4xx_hal_conf.h
|
* @file stm32f4xx_hal_conf.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @version V1.1.0
|
* @version V1.1.0
|
||||||
* @date 19-June-2014
|
* @date 19-June-2014
|
||||||
* @brief HAL configuration file.
|
* @brief HAL configuration file.
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
* are permitted provided that the following conditions are met:
|
* are permitted provided that the following conditions are met:
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
* this list of conditions and the following disclaimer.
|
* this list of conditions and the following disclaimer.
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
* and/or other materials provided with the distribution.
|
* and/or other materials provided with the distribution.
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
* may be used to endorse or promote products derived from this software
|
* may be used to endorse or promote products derived from this software
|
||||||
* without specific prior written permission.
|
* without specific prior written permission.
|
||||||
*
|
*
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F4xx_HAL_CONF_H
|
#ifndef __STM32F4xx_HAL_CONF_H
|
||||||
#define __STM32F4xx_HAL_CONF_H
|
#define __STM32F4xx_HAL_CONF_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
#define USE_USB_FS
|
#define USE_USB_FS
|
||||||
|
|
||||||
/* ########################## Module Selection ############################## */
|
/* ########################## Module Selection ############################## */
|
||||||
/**
|
/**
|
||||||
* @brief This is the list of modules to be used in the HAL driver
|
* @brief This is the list of modules to be used in the HAL driver
|
||||||
*/
|
*/
|
||||||
#define HAL_MODULE_ENABLED
|
#define HAL_MODULE_ENABLED
|
||||||
#define HAL_ADC_MODULE_ENABLED
|
#define HAL_ADC_MODULE_ENABLED
|
||||||
#define HAL_CAN_MODULE_ENABLED
|
#define HAL_CAN_MODULE_ENABLED
|
||||||
/* #define HAL_CRC_MODULE_ENABLED */
|
/* #define HAL_CRC_MODULE_ENABLED */
|
||||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||||
#define HAL_DAC_MODULE_ENABLED
|
#define HAL_DAC_MODULE_ENABLED
|
||||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||||
#define HAL_DMA_MODULE_ENABLED
|
#define HAL_DMA_MODULE_ENABLED
|
||||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||||
/* #define HAL_ETH_MODULE_ENABLED */
|
/* #define HAL_ETH_MODULE_ENABLED */
|
||||||
#define HAL_FLASH_MODULE_ENABLED
|
#define HAL_FLASH_MODULE_ENABLED
|
||||||
/* #define HAL_NAND_MODULE_ENABLED */
|
/* #define HAL_NAND_MODULE_ENABLED */
|
||||||
/* #define HAL_NOR_MODULE_ENABLED */
|
/* #define HAL_NOR_MODULE_ENABLED */
|
||||||
/* #define HAL_PCCARD_MODULE_ENABLED */
|
/* #define HAL_PCCARD_MODULE_ENABLED */
|
||||||
#define HAL_SRAM_MODULE_ENABLED
|
#define HAL_SRAM_MODULE_ENABLED
|
||||||
/* #define HAL_SDRAM_MODULE_ENABLED */
|
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||||
/* #define HAL_HASH_MODULE_ENABLED */
|
/* #define HAL_HASH_MODULE_ENABLED */
|
||||||
#define HAL_GPIO_MODULE_ENABLED
|
#define HAL_GPIO_MODULE_ENABLED
|
||||||
#define HAL_I2C_MODULE_ENABLED
|
#define HAL_I2C_MODULE_ENABLED
|
||||||
#define HAL_I2S_MODULE_ENABLED
|
#define HAL_I2S_MODULE_ENABLED
|
||||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||||
#define HAL_PWR_MODULE_ENABLED
|
#define HAL_PWR_MODULE_ENABLED
|
||||||
#define HAL_RCC_MODULE_ENABLED
|
#define HAL_RCC_MODULE_ENABLED
|
||||||
#define HAL_RNG_MODULE_ENABLED
|
#define HAL_RNG_MODULE_ENABLED
|
||||||
#define HAL_RTC_MODULE_ENABLED
|
#define HAL_RTC_MODULE_ENABLED
|
||||||
/* #define HAL_SAI_MODULE_ENABLED */
|
/* #define HAL_SAI_MODULE_ENABLED */
|
||||||
#define HAL_SD_MODULE_ENABLED
|
#define HAL_SD_MODULE_ENABLED
|
||||||
#define HAL_SPI_MODULE_ENABLED
|
#define HAL_SPI_MODULE_ENABLED
|
||||||
#define HAL_TIM_MODULE_ENABLED
|
#define HAL_TIM_MODULE_ENABLED
|
||||||
#define HAL_UART_MODULE_ENABLED
|
#define HAL_UART_MODULE_ENABLED
|
||||||
/* #define HAL_USART_MODULE_ENABLED */
|
/* #define HAL_USART_MODULE_ENABLED */
|
||||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||||
#define HAL_CORTEX_MODULE_ENABLED
|
#define HAL_CORTEX_MODULE_ENABLED
|
||||||
#define HAL_PCD_MODULE_ENABLED
|
#define HAL_PCD_MODULE_ENABLED
|
||||||
/* #define HAL_HCD_MODULE_ENABLED */
|
/* #define HAL_HCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
|
||||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||||
/**
|
/**
|
||||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||||
* This value is used by the RCC HAL module to compute the system frequency
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
* (when HSE is used as system clock source, directly or through the PLL).
|
* (when HSE is used as system clock source, directly or through the PLL).
|
||||||
*/
|
*/
|
||||||
#if !defined (HSE_VALUE)
|
#if !defined (HSE_VALUE)
|
||||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||||
#endif /* HSE_VALUE */
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
|
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
|
||||||
#endif /* HSE_STARTUP_TIMEOUT */
|
#endif /* HSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Internal High Speed oscillator (HSI) value.
|
* @brief Internal High Speed oscillator (HSI) value.
|
||||||
* This value is used by the RCC HAL module to compute the system frequency
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
* (when HSI is used as system clock source, directly or through the PLL).
|
* (when HSI is used as system clock source, directly or through the PLL).
|
||||||
*/
|
*/
|
||||||
#if !defined (HSI_VALUE)
|
#if !defined (HSI_VALUE)
|
||||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||||
#endif /* HSI_VALUE */
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Internal Low Speed oscillator (LSI) value.
|
* @brief Internal Low Speed oscillator (LSI) value.
|
||||||
*/
|
*/
|
||||||
#if !defined (LSI_VALUE)
|
#if !defined (LSI_VALUE)
|
||||||
#define LSI_VALUE ((uint32_t)40000)
|
#define LSI_VALUE ((uint32_t)40000)
|
||||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||||
The real value may vary depending on the variations
|
The real value may vary depending on the variations
|
||||||
in voltage and temperature. */
|
in voltage and temperature. */
|
||||||
/**
|
/**
|
||||||
* @brief External Low Speed oscillator (LSE) value.
|
* @brief External Low Speed oscillator (LSE) value.
|
||||||
*/
|
*/
|
||||||
#if !defined (LSE_VALUE)
|
#if !defined (LSE_VALUE)
|
||||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
||||||
#endif /* LSE_VALUE */
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
|
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
|
||||||
#endif /* LSE_STARTUP_TIMEOUT */
|
#endif /* LSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief External clock source for I2S peripheral
|
* @brief External clock source for I2S peripheral
|
||||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||||
*/
|
*/
|
||||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
|
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
|
||||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||||
|
|
||||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||||
|
|
||||||
/* ########################### System Configuration ######################### */
|
/* ########################### System Configuration ######################### */
|
||||||
/**
|
/**
|
||||||
* @brief This is the HAL system configuration section
|
* @brief This is the HAL system configuration section
|
||||||
*/
|
*/
|
||||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||||
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
|
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
|
||||||
#define USE_RTOS 0
|
#define USE_RTOS 0
|
||||||
#define PREFETCH_ENABLE 1
|
#define PREFETCH_ENABLE 1
|
||||||
#define INSTRUCTION_CACHE_ENABLE 1
|
#define INSTRUCTION_CACHE_ENABLE 1
|
||||||
#define DATA_CACHE_ENABLE 1
|
#define DATA_CACHE_ENABLE 1
|
||||||
|
|
||||||
/* ########################## Assert Selection ############################## */
|
/* ########################## Assert Selection ############################## */
|
||||||
/**
|
/**
|
||||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||||
* HAL drivers code
|
* HAL drivers code
|
||||||
*/
|
*/
|
||||||
/* #define USE_FULL_ASSERT 1 */
|
/* #define USE_FULL_ASSERT 1 */
|
||||||
|
|
||||||
/* ################## Ethernet peripheral configuration ##################### */
|
/* ################## Ethernet peripheral configuration ##################### */
|
||||||
|
|
||||||
/* Section 1 : Ethernet peripheral configuration */
|
/* Section 1 : Ethernet peripheral configuration */
|
||||||
|
|
||||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||||
#define MAC_ADDR0 2
|
#define MAC_ADDR0 2
|
||||||
#define MAC_ADDR1 0
|
#define MAC_ADDR1 0
|
||||||
#define MAC_ADDR2 0
|
#define MAC_ADDR2 0
|
||||||
#define MAC_ADDR3 0
|
#define MAC_ADDR3 0
|
||||||
#define MAC_ADDR4 0
|
#define MAC_ADDR4 0
|
||||||
#define MAC_ADDR5 0
|
#define MAC_ADDR5 0
|
||||||
|
|
||||||
/* Definition of the Ethernet driver buffers size and count */
|
/* Definition of the Ethernet driver buffers size and count */
|
||||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||||
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||||
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||||
|
|
||||||
/* Section 2: PHY configuration section */
|
/* Section 2: PHY configuration section */
|
||||||
|
|
||||||
/* DP83848 PHY Address*/
|
/* DP83848 PHY Address*/
|
||||||
#define DP83848_PHY_ADDRESS 0x01
|
#define DP83848_PHY_ADDRESS 0x01
|
||||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
|
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
|
||||||
/* PHY Configuration delay */
|
/* PHY Configuration delay */
|
||||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
||||||
|
|
||||||
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
||||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
||||||
|
|
||||||
/* Section 3: Common PHY Registers */
|
/* Section 3: Common PHY Registers */
|
||||||
|
|
||||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
||||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
||||||
|
|
||||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||||
|
|
||||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||||
|
|
||||||
/* Section 4: Extended PHY Registers */
|
/* Section 4: Extended PHY Registers */
|
||||||
|
|
||||||
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
|
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
|
||||||
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
|
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
|
||||||
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
|
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
|
||||||
|
|
||||||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||||
|
|
||||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||||
|
|
||||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
/**
|
/**
|
||||||
* @brief Include module's header file
|
* @brief Include module's header file
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef HAL_RCC_MODULE_ENABLED
|
#ifdef HAL_RCC_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_rcc.h"
|
#include "stm32f4xx_hal_rcc.h"
|
||||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_gpio.h"
|
#include "stm32f4xx_hal_gpio.h"
|
||||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_DMA_MODULE_ENABLED
|
#ifdef HAL_DMA_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_dma.h"
|
#include "stm32f4xx_hal_dma.h"
|
||||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_cortex.h"
|
#include "stm32f4xx_hal_cortex.h"
|
||||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_ADC_MODULE_ENABLED
|
#ifdef HAL_ADC_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_adc.h"
|
#include "stm32f4xx_hal_adc.h"
|
||||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_CAN_MODULE_ENABLED
|
#ifdef HAL_CAN_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_can.h"
|
#include "stm32f4xx_hal_can.h"
|
||||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_CRC_MODULE_ENABLED
|
#ifdef HAL_CRC_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_crc.h"
|
#include "stm32f4xx_hal_crc.h"
|
||||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_cryp.h"
|
#include "stm32f4xx_hal_cryp.h"
|
||||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_dma2d.h"
|
#include "stm32f4xx_hal_dma2d.h"
|
||||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_DAC_MODULE_ENABLED
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_dac.h"
|
#include "stm32f4xx_hal_dac.h"
|
||||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_dcmi.h"
|
#include "stm32f4xx_hal_dcmi.h"
|
||||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_ETH_MODULE_ENABLED
|
#ifdef HAL_ETH_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_eth.h"
|
#include "stm32f4xx_hal_eth.h"
|
||||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_flash.h"
|
#include "stm32f4xx_hal_flash.h"
|
||||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_sram.h"
|
#include "stm32f4xx_hal_sram.h"
|
||||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_NOR_MODULE_ENABLED
|
#ifdef HAL_NOR_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_nor.h"
|
#include "stm32f4xx_hal_nor.h"
|
||||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_NAND_MODULE_ENABLED
|
#ifdef HAL_NAND_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_nand.h"
|
#include "stm32f4xx_hal_nand.h"
|
||||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_pccard.h"
|
#include "stm32f4xx_hal_pccard.h"
|
||||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_sdram.h"
|
#include "stm32f4xx_hal_sdram.h"
|
||||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_HASH_MODULE_ENABLED
|
#ifdef HAL_HASH_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_hash.h"
|
#include "stm32f4xx_hal_hash.h"
|
||||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_I2C_MODULE_ENABLED
|
#ifdef HAL_I2C_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_i2c.h"
|
#include "stm32f4xx_hal_i2c.h"
|
||||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_I2S_MODULE_ENABLED
|
#ifdef HAL_I2S_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_i2s.h"
|
#include "stm32f4xx_hal_i2s.h"
|
||||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_iwdg.h"
|
#include "stm32f4xx_hal_iwdg.h"
|
||||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_ltdc.h"
|
#include "stm32f4xx_hal_ltdc.h"
|
||||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_PWR_MODULE_ENABLED
|
#ifdef HAL_PWR_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_pwr.h"
|
#include "stm32f4xx_hal_pwr.h"
|
||||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_RNG_MODULE_ENABLED
|
#ifdef HAL_RNG_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_rng.h"
|
#include "stm32f4xx_hal_rng.h"
|
||||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_RTC_MODULE_ENABLED
|
#ifdef HAL_RTC_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_rtc.h"
|
#include "stm32f4xx_hal_rtc.h"
|
||||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_SAI_MODULE_ENABLED
|
#ifdef HAL_SAI_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_sai.h"
|
#include "stm32f4xx_hal_sai.h"
|
||||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_SD_MODULE_ENABLED
|
#ifdef HAL_SD_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_sd.h"
|
#include "stm32f4xx_hal_sd.h"
|
||||||
#endif /* HAL_SD_MODULE_ENABLED */
|
#endif /* HAL_SD_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_SPI_MODULE_ENABLED
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_spi.h"
|
#include "stm32f4xx_hal_spi.h"
|
||||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_TIM_MODULE_ENABLED
|
#ifdef HAL_TIM_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_tim.h"
|
#include "stm32f4xx_hal_tim.h"
|
||||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_UART_MODULE_ENABLED
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_uart.h"
|
#include "stm32f4xx_hal_uart.h"
|
||||||
#endif /* HAL_UART_MODULE_ENABLED */
|
#endif /* HAL_UART_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_USART_MODULE_ENABLED
|
#ifdef HAL_USART_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_usart.h"
|
#include "stm32f4xx_hal_usart.h"
|
||||||
#endif /* HAL_USART_MODULE_ENABLED */
|
#endif /* HAL_USART_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_irda.h"
|
#include "stm32f4xx_hal_irda.h"
|
||||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_smartcard.h"
|
#include "stm32f4xx_hal_smartcard.h"
|
||||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_wwdg.h"
|
#include "stm32f4xx_hal_wwdg.h"
|
||||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_PCD_MODULE_ENABLED
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_pcd.h"
|
#include "stm32f4xx_hal_pcd.h"
|
||||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_HCD_MODULE_ENABLED
|
#ifdef HAL_HCD_MODULE_ENABLED
|
||||||
#include "stm32f4xx_hal_hcd.h"
|
#include "stm32f4xx_hal_hcd.h"
|
||||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
#ifdef USE_FULL_ASSERT
|
#ifdef USE_FULL_ASSERT
|
||||||
/**
|
/**
|
||||||
* @brief The assert_param macro is used for function's parameters check.
|
* @brief The assert_param macro is used for function's parameters check.
|
||||||
* @param expr: If expr is false, it calls assert_failed function
|
* @param expr: If expr is false, it calls assert_failed function
|
||||||
* which reports the name of the source file and the source
|
* which reports the name of the source file and the source
|
||||||
* line number of the call that failed.
|
* line number of the call that failed.
|
||||||
* If expr is true, it returns no value.
|
* If expr is true, it returns no value.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||||
/* Exported functions ------------------------------------------------------- */
|
/* Exported functions ------------------------------------------------------- */
|
||||||
void assert_failed(uint8_t* file, uint32_t line);
|
void assert_failed(uint8_t* file, uint32_t line);
|
||||||
#else
|
#else
|
||||||
#define assert_param(expr) ((void)0)
|
#define assert_param(expr) ((void)0)
|
||||||
#endif /* USE_FULL_ASSERT */
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __STM32F4xx_HAL_CONF_H */
|
#endif /* __STM32F4xx_HAL_CONF_H */
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
693
micropython/trezorhal/stm32f4xx_hal_sram.c
Normal file
693
micropython/trezorhal/stm32f4xx_hal_sram.c
Normal file
@ -0,0 +1,693 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f4xx_hal_sram.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.5.2
|
||||||
|
* @date 22-September-2016
|
||||||
|
* @brief SRAM HAL module driver.
|
||||||
|
* This file provides a generic firmware to drive SRAM memories
|
||||||
|
* mounted as external device.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This driver is a generic layered driver which contains a set of APIs used to
|
||||||
|
control SRAM memories. It uses the FMC layer functions to interface
|
||||||
|
with SRAM devices.
|
||||||
|
The following sequence should be followed to configure the FMC/FSMC to interface
|
||||||
|
with SRAM/PSRAM memories:
|
||||||
|
|
||||||
|
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
|
||||||
|
SRAM_HandleTypeDef hsram; and:
|
||||||
|
|
||||||
|
(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
|
||||||
|
values of the structure member.
|
||||||
|
|
||||||
|
(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
|
||||||
|
base register instance for NOR or SRAM device
|
||||||
|
|
||||||
|
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
|
||||||
|
base register instance for NOR or SRAM extended mode
|
||||||
|
|
||||||
|
(#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
|
||||||
|
mode timings; for example:
|
||||||
|
FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
|
||||||
|
and fill its fields with the allowed values of the structure member.
|
||||||
|
|
||||||
|
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
|
||||||
|
performs the following sequence:
|
||||||
|
|
||||||
|
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
|
||||||
|
(##) Control register configuration using the FMC NORSRAM interface function
|
||||||
|
FMC_NORSRAM_Init()
|
||||||
|
(##) Timing register configuration using the FMC NORSRAM interface function
|
||||||
|
FMC_NORSRAM_Timing_Init()
|
||||||
|
(##) Extended mode Timing register configuration using the FMC NORSRAM interface function
|
||||||
|
FMC_NORSRAM_Extended_Timing_Init()
|
||||||
|
(##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
|
||||||
|
|
||||||
|
(#) At this stage you can perform read/write accesses from/to the memory connected
|
||||||
|
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
|
||||||
|
following APIs:
|
||||||
|
(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
|
||||||
|
(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
|
||||||
|
|
||||||
|
(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
|
||||||
|
HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
|
||||||
|
|
||||||
|
(#) You can continuously monitor the SRAM device HAL state by calling the function
|
||||||
|
HAL_SRAM_GetState()
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f4xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM SRAM
|
||||||
|
* @brief SRAM driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||||
|
|
||||||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
|
||||||
|
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
|
||||||
|
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
|
||||||
|
defined(STM32F412Vx) || defined(STM32F412Rx)
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM Initialization and de_initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to initialize/de-initialize
|
||||||
|
the SRAM memory
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Performs the SRAM device initialization sequence
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param Timing: Pointer to SRAM control timing structure
|
||||||
|
* @param ExtTiming: Pointer to SRAM extended mode timing structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||||
|
{
|
||||||
|
/* Check the SRAM handle parameter */
|
||||||
|
if(hsram == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Allocate lock resource and initialize it */
|
||||||
|
hsram->Lock = HAL_UNLOCKED;
|
||||||
|
/* Initialize the low level hardware (MSP) */
|
||||||
|
HAL_SRAM_MspInit(hsram);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize SRAM control Interface */
|
||||||
|
FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
|
||||||
|
|
||||||
|
/* Initialize SRAM timing Interface */
|
||||||
|
FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
/* Initialize SRAM extended mode timing Interface */
|
||||||
|
FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
|
||||||
|
|
||||||
|
/* Enable the NORSRAM device */
|
||||||
|
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Performs the SRAM device De-initialization sequence.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* De-Initialize the low level hardware (MSP) */
|
||||||
|
HAL_SRAM_MspDeInit(hsram);
|
||||||
|
|
||||||
|
/* Configure the SRAM registers with their reset values */
|
||||||
|
FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
hsram->State = HAL_SRAM_STATE_RESET;
|
||||||
|
|
||||||
|
/* Release Lock */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM MSP Init.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hsram);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_MspInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM MSP DeInit.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hsram);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_MspDeInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA transfer complete callback.
|
||||||
|
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdma);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA transfer complete error callback.
|
||||||
|
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdma);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
|
||||||
|
* @brief Input Output and memory control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM Input and Output functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to use and control the SRAM memory
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads 8-bit buffer from SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Read data from memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*pDstBuffer = *(__IO uint8_t *)pSramAddress;
|
||||||
|
pDstBuffer++;
|
||||||
|
pSramAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes 8-bit buffer to SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
|
||||||
|
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Write data to memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*(__IO uint8_t *)pSramAddress = *pSrcBuffer;
|
||||||
|
pSrcBuffer++;
|
||||||
|
pSramAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads 16-bit buffer from SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Read data from memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*pDstBuffer = *(__IO uint16_t *)pSramAddress;
|
||||||
|
pDstBuffer++;
|
||||||
|
pSramAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes 16-bit buffer to SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
|
||||||
|
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Write data to memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*(__IO uint16_t *)pSramAddress = *pSrcBuffer;
|
||||||
|
pSrcBuffer++;
|
||||||
|
pSramAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads 32-bit buffer from SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Read data from memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*pDstBuffer = *(__IO uint32_t *)pAddress;
|
||||||
|
pDstBuffer++;
|
||||||
|
pAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes 32-bit buffer to SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Write data to memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*(__IO uint32_t *)pAddress = *pSrcBuffer;
|
||||||
|
pSrcBuffer++;
|
||||||
|
pAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads a Words data from the SRAM memory using DMA transfer.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Configure DMA user callbacks */
|
||||||
|
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||||
|
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||||
|
|
||||||
|
/* Enable the DMA Stream */
|
||||||
|
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Configure DMA user callbacks */
|
||||||
|
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||||
|
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||||
|
|
||||||
|
/* Enable the DMA Stream */
|
||||||
|
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
||||||
|
* @brief management functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM Control functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to control dynamically
|
||||||
|
the SRAM interface.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables dynamically SRAM write operation.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Enable write operation */
|
||||||
|
FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables dynamically SRAM write operation.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Disable write operation */
|
||||||
|
FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group4 State functions
|
||||||
|
* @brief Peripheral State functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM State functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection permits to get in run-time the status of the SRAM controller
|
||||||
|
and the data flow.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the SRAM controller state
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL state
|
||||||
|
*/
|
||||||
|
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
return hsram->State;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
||||||
|
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
|
||||||
|
STM32F412Vx || STM32F412Rx || STM32F412Cx */
|
||||||
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
207
micropython/trezorhal/stm32f4xx_hal_sram.h
Normal file
207
micropython/trezorhal/stm32f4xx_hal_sram.h
Normal file
@ -0,0 +1,207 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f4xx_hal_sram.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.5.2
|
||||||
|
* @date 22-September-2016
|
||||||
|
* @brief Header file of SRAM HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F4xx_HAL_SRAM_H
|
||||||
|
#define __STM32F4xx_HAL_SRAM_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
|
||||||
|
#include "stm32f4xx_ll_fsmc.h"
|
||||||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx*/
|
||||||
|
|
||||||
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
||||||
|
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||||
|
#include "stm32f4xx_ll_fmc.h"
|
||||||
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32F4xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
|
||||||
|
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
|
||||||
|
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
|
||||||
|
defined(STM32F412Vx) || defined(STM32F412Rx)
|
||||||
|
|
||||||
|
/** @addtogroup SRAM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported typedef ----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief HAL SRAM State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
|
||||||
|
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
|
||||||
|
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
|
||||||
|
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
|
||||||
|
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
|
||||||
|
|
||||||
|
}HAL_SRAM_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||||
|
|
||||||
|
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< SRAM locking object */
|
||||||
|
|
||||||
|
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||||
|
|
||||||
|
}SRAM_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @brief Reset SRAM handle state
|
||||||
|
* @param __HANDLE__: SRAM handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||||
|
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||||
|
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||||
|
|
||||||
|
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||||
|
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* SRAM Control functions ******************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group4
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* SRAM State functions *********************************************************/
|
||||||
|
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
||||||
|
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
|
||||||
|
STM32F412Vx || STM32F412Rx */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F4xx_HAL_SRAM_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
1026
micropython/trezorhal/stm32f4xx_ll_fsmc.c
Normal file
1026
micropython/trezorhal/stm32f4xx_ll_fsmc.c
Normal file
File diff suppressed because it is too large
Load Diff
1049
micropython/trezorhal/stm32f4xx_ll_fsmc.h
Normal file
1049
micropython/trezorhal/stm32f4xx_ll_fsmc.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -7,8 +7,6 @@
|
|||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x100000 /* entire flash, 1 MiB */
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x100000 /* entire flash, 1 MiB */
|
||||||
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */
|
|
||||||
FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x0E0000 /* sectors 5,6,7,8,9,10,11 7*128KiB = 896 KiB */
|
|
||||||
CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0x010000 /* 64 KiB */
|
CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0x010000 /* 64 KiB */
|
||||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000 /* 128 KiB */
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000 /* 128 KiB */
|
||||||
}
|
}
|
||||||
@ -28,42 +26,16 @@ ENTRY(Reset_Handler)
|
|||||||
SECTIONS
|
SECTIONS
|
||||||
{
|
{
|
||||||
/* The startup code goes first into FLASH */
|
/* The startup code goes first into FLASH */
|
||||||
.isr_vector :
|
.flash :
|
||||||
{
|
{
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
|
||||||
/* This first flash block is 16K annd the isr vectors only take up
|
|
||||||
about 400 bytes. So we pull in a couple of object files to pad it
|
|
||||||
out. */
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
/* NOTE: If you update the list of files contained in .isr_vector,
|
|
||||||
then be sure to also update smhal/Makefile where it forcibly
|
|
||||||
builds each of these files with -Os */
|
|
||||||
|
|
||||||
*/ff.o(.text*)
|
|
||||||
*/vfs_fat_*.o(.text*)
|
|
||||||
*/py/formatfloat.o(.text*)
|
|
||||||
*/py/parsenum.o(.text*)
|
|
||||||
*/py/mpprint.o(.text*)
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >FLASH_ISR
|
|
||||||
|
|
||||||
/* The program code and other data goes into FLASH */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
*(.text*) /* .text* sections (code) */
|
*(.text*) /* .text* sections (code) */
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
/* *(.glue_7) */ /* glue arm to thumb code */
|
|
||||||
/* *(.glue_7t) */ /* glue thumb to arm code */
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_etext = .; /* define a global symbol at end of code */
|
_etext = .; /* define a global symbol at end of code */
|
||||||
} >FLASH_TEXT
|
} >FLASH
|
||||||
|
|
||||||
/* used by the startup to initialize data */
|
/* used by the startup to initialize data */
|
||||||
_sidata = LOADADDR(.data);
|
_sidata = LOADADDR(.data);
|
||||||
@ -80,7 +52,7 @@ SECTIONS
|
|||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
|
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
|
||||||
} >RAM AT> FLASH_TEXT
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
/* Uninitialized data section */
|
/* Uninitialized data section */
|
||||||
.bss :
|
.bss :
|
||||||
2
vendor/micropython
vendored
2
vendor/micropython
vendored
@ -1 +1 @@
|
|||||||
Subproject commit a47b3052f851cc70d5d7f181064ea43ea1ccc91f
|
Subproject commit 815700a492ae1253910b79b6f6c32bfce4d5a848
|
||||||
Loading…
Reference in New Issue
Block a user