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fixup! feat(core): add BLE to t3w1 board
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@ -129,20 +129,20 @@
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#define SBU_2_PORT GPIOC
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#define SBU_2_CLK_ENA __HAL_RCC_GPIOC_CLK_ENABLE
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#define NRF_RESET_PIN GPIO_PIN_0
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#define NRF_RESET_PORT GPIOG
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#define NRF_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
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#define NRF_GPIO0_PIN GPIO_PIN_7
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#define NRF_GPIO0_PORT GPIOE
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#define NRF_GPIO0_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_GPIO1_PIN GPIO_PIN_13
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#define NRF_GPIO1_PORT GPIOE
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#define NRF_GPIO1_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_GPIO2_PIN GPIO_PIN_15
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#define NRF_GPIO2_PORT GPIOE
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#define NRF_GPIO2_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_GPIO3_PIN GPIO_PIN_11
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#define NRF_GPIO3_PORT GPIOE
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#define NRF_GPIO3_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_IN_GPIO0_PIN GPIO_PIN_7
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#define NRF_IN_GPIO0_PORT GPIOE
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#define NRF_IN_GPIO0_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_IN_FW_RUNNING_PIN GPIO_PIN_13
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#define NRF_IN_FW_RUNNING_PORT GPIOE
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#define NRF_IN_FW_RUNNING_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_OUT_RESET_PIN GPIO_PIN_0
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#define NRF_OUT_RESET_PORT GPIOG
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#define NRF_OUT_RESET_CLK_ENA __HAL_RCC_GPIOG_CLK_ENABLE
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#define NRF_OUT_STAY_IN_BLD_PIN GPIO_PIN_15
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#define NRF_OUT_STAY_IN_BLD_PORT GPIOE
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#define NRF_OUT_STAY_IN_BLD_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#define NRF_OUT_FW_RUNNING_PIN GPIO_PIN_11
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#define NRF_OUT_FW_RUNNING_PORT GPIOE
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#define NRF_OUT_FW_RUNNING_CLK_ENA __HAL_RCC_GPIOE_CLK_ENABLE
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#endif // TREZOR_T3W1_REVA_H_
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