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refactor(core): streamline RAM layout

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This commit is contained in:
tychovrahe 2024-11-27 15:44:05 +01:00 committed by TychoVrahe
parent 0d3407b075
commit 0bc729a3da
35 changed files with 588 additions and 458 deletions
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2
core/SConscript.prodtest
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@ -136,7 +136,7 @@ env.Replace(
'-fstack-protector-all ' '-fstack-protector-all '
+ env.get('ENV')["CPU_CCFLAGS"] + CCFLAGS_MOD, + env.get('ENV')["CPU_CCFLAGS"] + CCFLAGS_MOD,
CCFLAGS_QSTR='-DNO_QSTR -DN_X64 -DN_X86 -DN_THUMB', CCFLAGS_QSTR='-DNO_QSTR -DN_X64 -DN_X86 -DN_THUMB',
LINKFLAGS=f'-T build/prodtest/memory.ld -Wl,--gc-sections -Wl,-Map=build/prodtest/prodtest.map -Wl,--warn-common', LINKFLAGS=f'-T build/prodtest/memory.ld -Wl,--gc-sections -Wl,--print-memory-usage -Wl,-Map=build/prodtest/prodtest.map -Wl,--warn-common',
CPPPATH=[ CPPPATH=[
'embed/projects/prodtest', 'embed/projects/prodtest',
'embed/rtl/inc', 'embed/rtl/inc',

23
core/embed/models/D001/memory.ld
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@ -44,10 +44,25 @@ FIRMWARE_P2_START = 0x8120000;
FIRMWARE_P2_MAXSIZE = 0xe0000; FIRMWARE_P2_MAXSIZE = 0xe0000;
FIRMWARE_P2_SECTOR_START = 0x11; FIRMWARE_P2_SECTOR_START = 0x11;
FIRMWARE_P2_SECTOR_END = 0x17; FIRMWARE_P2_SECTOR_END = 0x17;
KERNEL_STACK_SIZE = 0x2000; S_MAIN_STACK_START = 0x10000000;
KERNEL_CCMRAM_SIZE = 0x4000; S_MAIN_STACK_SIZE = 0x4000;
KERNEL_FRAMEBUFFER_SIZE = 0x0; S_FB1_RAM_START = 0x10004000;
KERNEL_SRAM_SIZE = 0x400; S_FB1_RAM_SIZE = 0x0;
S_MAIN_RAM_START = 0x10004000;
S_MAIN_RAM_SIZE = 0xbf00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0xa000;
K_FB1_RAM_START = 0x1000c000;
K_FB1_RAM_SIZE = 0x0;
K_MAIN_RAM_START = 0x1000c000;
K_MAIN_RAM_SIZE = 0x3f00;
BOOTARGS_START = 0x1000ff00;
BOOTARGS_SIZE = 0x100; BOOTARGS_SIZE = 0x100;
DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x400;
AUX1_RAM_START = 0x20000400;
AUX1_RAM_SIZE = 0x2fc00;
CODE_ALIGNMENT = 0x200; CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200; COREAPP_ALIGNMENT = 0x200;

37
core/embed/models/D001/model_D001.h
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@ -89,13 +89,40 @@
#define FIRMWARE_P2_SECTOR_START 17 #define FIRMWARE_P2_SECTOR_START 17
#define FIRMWARE_P2_SECTOR_END 23 #define FIRMWARE_P2_SECTOR_END 23
// RAM layout // Ram layout - shared boardloader, bootloader, prodtest
#define KERNEL_STACK_SIZE (8 * 1024) #define S_MAIN_STACK_START 0x10000000
#define KERNEL_CCMRAM_SIZE (16 * 1024) #define S_MAIN_STACK_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define S_FB1_RAM_START 0x10004000
#define S_FB1_RAM_SIZE (0)
#define S_MAIN_RAM_START 0x10004000
#define S_MAIN_RAM_SIZE (48 * 1024 - 0x100)
// RAM layout - kernel
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (40 * 1024)
#define K_FB1_RAM_START 0x1000C000
#define K_FB1_RAM_SIZE (0)
#define K_MAIN_RAM_START 0x1000C000
#define K_MAIN_RAM_SIZE (16 * 1024 - 0x100)
// RAM layout - common
#define BOOTARGS_START 0x1000FF00
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_SIZE 0x100
#define DMABUF_RAM_START 0x20000000
#define DMABUF_RAM_SIZE (1 * 1024)
#define AUX1_RAM_START (0x20000400)
#define AUX1_RAM_SIZE (191 * 1024)
// misc
#define CODE_ALIGNMENT 0x200 #define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200 #define COREAPP_ALIGNMENT 0x200

15
core/embed/models/D002/memory.ld
View File

@ -39,8 +39,17 @@ ASSETS_START = 0xc3f0000;
ASSETS_MAXSIZE = 0x10000; ASSETS_MAXSIZE = 0x10000;
ASSETS_SECTOR_START = 0x1f8; ASSETS_SECTOR_START = 0x1f8;
ASSETS_SECTOR_END = 0x1ff; ASSETS_SECTOR_END = 0x1ff;
KERNEL_U_RAM_SIZE = 0x200; FB1_RAM_START = 0x30000000;
KERNEL_SRAM2_SIZE = 0xfe00; FB1_RAM_SIZE = 0xbfe00;
BOOTARGS_SIZE = 0x100; BOOTARGS_START = 0x300bfe00;
BOOTARGS_SIZE = 0x200;
MAIN_RAM_START = 0x300c0000;
MAIN_RAM_SIZE = 0xfe00;
SAES_RAM_START = 0x300cfe00;
SAES_RAM_SIZE = 0x200;
FB2_RAM_START = 0x300d0000;
FB2_RAM_SIZE = 0xc0000;
AUX1_RAM_START = 0x30190000;
AUX1_RAM_SIZE = 0xe0000;
CODE_ALIGNMENT = 0x400; CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000; COREAPP_ALIGNMENT = 0x2000;

21
core/embed/models/D002/model_D002.h
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@ -85,10 +85,25 @@
#define ASSETS_SECTOR_END 0x1FF #define ASSETS_SECTOR_END 0x1FF
// RAM layout // RAM layout
#define KERNEL_U_RAM_SIZE 512 #define FB1_RAM_START 0x30000000
#define KERNEL_SRAM2_SIZE (64 * 1024 - 512) #define FB1_RAM_SIZE (768 * 1024 - 512)
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_START 0x300BFE00
#define BOOTARGS_SIZE 0x200
#define MAIN_RAM_START 0x300C0000
#define MAIN_RAM_SIZE (64 * 1024 - 512)
#define SAES_RAM_START 0x300CFE00
#define SAES_RAM_SIZE 512
#define FB2_RAM_START 0x300D0000
#define FB2_RAM_SIZE (768 * 1024)
#define AUX1_RAM_START 0x30190000
#define AUX1_RAM_SIZE (896 * 1024)
// misc
#define CODE_ALIGNMENT 0x400 #define CODE_ALIGNMENT 0x400
#define COREAPP_ALIGNMENT 0x2000 #define COREAPP_ALIGNMENT 0x2000

23
core/embed/models/T2B1/memory.ld
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@ -48,10 +48,25 @@ FIRMWARE_P2_START = 0x8120000;
FIRMWARE_P2_MAXSIZE = 0xe0000; FIRMWARE_P2_MAXSIZE = 0xe0000;
FIRMWARE_P2_SECTOR_START = 0x11; FIRMWARE_P2_SECTOR_START = 0x11;
FIRMWARE_P2_SECTOR_END = 0x17; FIRMWARE_P2_SECTOR_END = 0x17;
KERNEL_STACK_SIZE = 0x2000; S_MAIN_STACK_START = 0x10000000;
KERNEL_CCMRAM_SIZE = 0x4000; S_MAIN_STACK_SIZE = 0x4000;
KERNEL_FRAMEBUFFER_SIZE = 0x2000; S_FB1_RAM_START = 0x10004000;
KERNEL_SRAM_SIZE = 0x400; S_FB1_RAM_SIZE = 0x2000;
S_MAIN_RAM_START = 0x10006000;
S_MAIN_RAM_SIZE = 0x9f00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0x8000;
K_FB1_RAM_START = 0x1000a000;
K_FB1_RAM_SIZE = 0x2000;
K_MAIN_RAM_START = 0x1000c000;
K_MAIN_RAM_SIZE = 0x3f00;
BOOTARGS_START = 0x1000ff00;
BOOTARGS_SIZE = 0x100; BOOTARGS_SIZE = 0x100;
DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x400;
AUX1_RAM_START = 0x20000400;
AUX1_RAM_SIZE = 0x2fc00;
CODE_ALIGNMENT = 0x200; CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200; COREAPP_ALIGNMENT = 0x200;

37
core/embed/models/T2B1/model_T2B1.h
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@ -94,13 +94,40 @@
#define FIRMWARE_P2_SECTOR_START 17 #define FIRMWARE_P2_SECTOR_START 17
#define FIRMWARE_P2_SECTOR_END 23 #define FIRMWARE_P2_SECTOR_END 23
// RAM layout // Ram layout - shared boardloader, bootloader, prodtest
#define KERNEL_STACK_SIZE (8 * 1024) #define S_MAIN_STACK_START 0x10000000
#define KERNEL_CCMRAM_SIZE (16 * 1024) #define S_MAIN_STACK_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (8 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define S_FB1_RAM_START 0x10004000
#define S_FB1_RAM_SIZE (8 * 1024)
#define S_MAIN_RAM_START 0x10006000
#define S_MAIN_RAM_SIZE (40 * 1024 - 0x100)
// RAM layout - kernel
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (32 * 1024)
#define K_FB1_RAM_START 0x1000A000
#define K_FB1_RAM_SIZE (8 * 1024)
#define K_MAIN_RAM_START 0x1000C000
#define K_MAIN_RAM_SIZE (16 * 1024 - 0x100)
// RAM layout - common
#define BOOTARGS_START 0x1000FF00
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_SIZE 0x100
#define DMABUF_RAM_START 0x20000000
#define DMABUF_RAM_SIZE (1 * 1024)
#define AUX1_RAM_START (0x20000400)
#define AUX1_RAM_SIZE (191 * 1024)
// misc
#define CODE_ALIGNMENT 0x200 #define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200 #define COREAPP_ALIGNMENT 0x200

23
core/embed/models/T2T1/memory.ld
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@ -44,10 +44,25 @@ FIRMWARE_P2_START = 0x8120000;
FIRMWARE_P2_MAXSIZE = 0xe0000; FIRMWARE_P2_MAXSIZE = 0xe0000;
FIRMWARE_P2_SECTOR_START = 0x11; FIRMWARE_P2_SECTOR_START = 0x11;
FIRMWARE_P2_SECTOR_END = 0x17; FIRMWARE_P2_SECTOR_END = 0x17;
KERNEL_STACK_SIZE = 0x2000; S_MAIN_STACK_START = 0x10000000;
KERNEL_CCMRAM_SIZE = 0x4000; S_MAIN_STACK_SIZE = 0x4000;
KERNEL_FRAMEBUFFER_SIZE = 0x0; S_FB1_RAM_START = 0x10004000;
KERNEL_SRAM_SIZE = 0x400; S_FB1_RAM_SIZE = 0x0;
S_MAIN_RAM_START = 0x10004000;
S_MAIN_RAM_SIZE = 0xbf00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0xa000;
K_FB1_RAM_START = 0x1000c000;
K_FB1_RAM_SIZE = 0x0;
K_MAIN_RAM_START = 0x1000c000;
K_MAIN_RAM_SIZE = 0x3f00;
BOOTARGS_START = 0x1000ff00;
BOOTARGS_SIZE = 0x100; BOOTARGS_SIZE = 0x100;
DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x400;
AUX1_RAM_START = 0x20000400;
AUX1_RAM_SIZE = 0x2fc00;
CODE_ALIGNMENT = 0x200; CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200; COREAPP_ALIGNMENT = 0x200;

37
core/embed/models/T2T1/model_T2T1.h
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@ -89,13 +89,40 @@
#define FIRMWARE_P2_SECTOR_START 17 #define FIRMWARE_P2_SECTOR_START 17
#define FIRMWARE_P2_SECTOR_END 23 #define FIRMWARE_P2_SECTOR_END 23
// RAM layout // Ram layout - shared boardloader, bootloader, prodtest
#define KERNEL_STACK_SIZE (8 * 1024) #define S_MAIN_STACK_START 0x10000000
#define KERNEL_CCMRAM_SIZE (16 * 1024) #define S_MAIN_STACK_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define S_FB1_RAM_START 0x10004000
#define S_FB1_RAM_SIZE (0)
#define S_MAIN_RAM_START 0x10004000
#define S_MAIN_RAM_SIZE (48 * 1024 - 0x100)
// RAM layout - kernel
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (40 * 1024)
#define K_FB1_RAM_START 0x1000C000
#define K_FB1_RAM_SIZE (0)
#define K_MAIN_RAM_START 0x1000C000
#define K_MAIN_RAM_SIZE (16 * 1024 - 0x100)
// RAM layout - common
#define BOOTARGS_START 0x1000FF00
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_SIZE 0x100
#define DMABUF_RAM_START 0x20000000
#define DMABUF_RAM_SIZE (1 * 1024)
#define AUX1_RAM_START (0x20000400)
#define AUX1_RAM_SIZE (191 * 1024)
// misc
#define CODE_ALIGNMENT 0x200 #define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200 #define COREAPP_ALIGNMENT 0x200

16
core/embed/models/T3B1/memory.ld
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@ -38,9 +38,19 @@ ASSETS_START = 0xc1f0000;
ASSETS_MAXSIZE = 0x10000; ASSETS_MAXSIZE = 0x10000;
ASSETS_SECTOR_START = 0xf8; ASSETS_SECTOR_START = 0xf8;
ASSETS_SECTOR_END = 0xff; ASSETS_SECTOR_END = 0xff;
KERNEL_U_RAM_SIZE = 0x200; AUX1_RAM_START = 0x30000000;
KERNEL_SRAM2_SIZE = 0x6000; AUX1_RAM_SIZE = 0x2fe00;
FRAMEBUFFER_SRAM_SIZE = 0x38400; BOOTARGS_START = 0x3002ff00;
BOOTARGS_SIZE = 0x100; BOOTARGS_SIZE = 0x100;
MAIN_RAM_START = 0x30030000;
MAIN_RAM_SIZE = 0x5e00;
SAES_RAM_START = 0x30035e00;
SAES_RAM_SIZE = 0x200;
AUX2_RAM_START = 0x30036000;
AUX2_RAM_SIZE = 0x88000;
FB1_RAM_START = 0x300be000;
FB1_RAM_SIZE = 0x2000;
FB2_RAM_START = 0x300c0000;
FB2_RAM_SIZE = 0x0;
CODE_ALIGNMENT = 0x200; CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x2000; COREAPP_ALIGNMENT = 0x2000;

25
core/embed/models/T3B1/model_T3B1.h
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@ -83,11 +83,30 @@
#define ASSETS_SECTOR_END 0xFF #define ASSETS_SECTOR_END 0xFF
// RAM layout // RAM layout
#define KERNEL_U_RAM_SIZE 512 #define AUX1_RAM_START 0x30000000
#define KERNEL_SRAM2_SIZE (24 * 1024) #define AUX1_RAM_SIZE (192 * 1024 - 512)
#define FRAMEBUFFER_SRAM_SIZE 0x38400
// 256 bytes skipped - trustzone alignment vs fixed bootargs position
#define BOOTARGS_START 0x3002FF00
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_SIZE 0x100
#define MAIN_RAM_START 0x30030000
#define MAIN_RAM_SIZE (24 * 1024 - 512)
#define SAES_RAM_START 0x30035E00
#define SAES_RAM_SIZE 512
#define AUX2_RAM_START 0x30036000
#define AUX2_RAM_SIZE (544 * 1024)
#define FB1_RAM_START 0x300BE000
#define FB1_RAM_SIZE (0x2000)
#define FB2_RAM_START 0x300C0000
#define FB2_RAM_SIZE (0)
// misc
#define CODE_ALIGNMENT 0x200 #define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x2000 #define COREAPP_ALIGNMENT 0x2000

16
core/embed/models/T3T1/memory.ld
View File

@ -38,9 +38,19 @@ ASSETS_START = 0xc1f0000;
ASSETS_MAXSIZE = 0x10000; ASSETS_MAXSIZE = 0x10000;
ASSETS_SECTOR_START = 0xf8; ASSETS_SECTOR_START = 0xf8;
ASSETS_SECTOR_END = 0xff; ASSETS_SECTOR_END = 0xff;
KERNEL_U_RAM_SIZE = 0x200; AUX1_RAM_START = 0x30000000;
KERNEL_SRAM2_SIZE = 0x6000; AUX1_RAM_SIZE = 0x2fe00;
FRAMEBUFFER_SRAM_SIZE = 0x38400; BOOTARGS_START = 0x3002ff00;
BOOTARGS_SIZE = 0x100; BOOTARGS_SIZE = 0x100;
MAIN_RAM_START = 0x30030000;
MAIN_RAM_SIZE = 0x5e00;
SAES_RAM_START = 0x30035e00;
SAES_RAM_SIZE = 0x200;
AUX2_RAM_START = 0x30036000;
AUX2_RAM_SIZE = 0x51c00;
FB1_RAM_START = 0x30087c00;
FB1_RAM_SIZE = 0x1c200;
FB2_RAM_START = 0x300a3e00;
FB2_RAM_SIZE = 0x1c200;
CODE_ALIGNMENT = 0x200; CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x2000; COREAPP_ALIGNMENT = 0x2000;

25
core/embed/models/T3T1/model_T3T1.h
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@ -83,11 +83,30 @@
#define ASSETS_SECTOR_END 0xFF #define ASSETS_SECTOR_END 0xFF
// RAM layout // RAM layout
#define KERNEL_U_RAM_SIZE 512 #define AUX1_RAM_START 0x30000000
#define KERNEL_SRAM2_SIZE (24 * 1024) #define AUX1_RAM_SIZE (192 * 1024 - 512)
#define FRAMEBUFFER_SRAM_SIZE 0x38400
// 256 bytes skipped - trustzone alignment vs fixed bootargs position
#define BOOTARGS_START 0x3002FF00
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_SIZE 0x100
#define MAIN_RAM_START 0x30030000
#define MAIN_RAM_SIZE (24 * 1024 - 512)
#define SAES_RAM_START 0x30035E00
#define SAES_RAM_SIZE 512
#define AUX2_RAM_START 0x30036000
#define AUX2_RAM_SIZE (327 * 1024)
#define FB1_RAM_START 0x30087C00
#define FB1_RAM_SIZE (115200)
#define FB2_RAM_START 0x300A3E00
#define FB2_RAM_SIZE (115200)
// misc
#define CODE_ALIGNMENT 0x200 #define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x2000 #define COREAPP_ALIGNMENT 0x2000

15
core/embed/models/T3W1/memory.ld
View File

@ -39,8 +39,17 @@ ASSETS_START = 0xc3f0000;
ASSETS_MAXSIZE = 0x10000; ASSETS_MAXSIZE = 0x10000;
ASSETS_SECTOR_START = 0x1f8; ASSETS_SECTOR_START = 0x1f8;
ASSETS_SECTOR_END = 0x1ff; ASSETS_SECTOR_END = 0x1ff;
KERNEL_U_RAM_SIZE = 0x200; FB1_RAM_START = 0x30000000;
KERNEL_SRAM2_SIZE = 0xfe00; FB1_RAM_SIZE = 0xbfe00;
BOOTARGS_SIZE = 0x100; BOOTARGS_START = 0x300bfe00;
BOOTARGS_SIZE = 0x200;
MAIN_RAM_START = 0x300c0000;
MAIN_RAM_SIZE = 0xfe00;
SAES_RAM_START = 0x300cfe00;
SAES_RAM_SIZE = 0x200;
FB2_RAM_START = 0x300d0000;
FB2_RAM_SIZE = 0xc0000;
AUX1_RAM_START = 0x30190000;
AUX1_RAM_SIZE = 0xe0000;
CODE_ALIGNMENT = 0x400; CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000; COREAPP_ALIGNMENT = 0x2000;

21
core/embed/models/T3W1/model_T3W1.h
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@ -91,10 +91,25 @@
#define ASSETS_SECTOR_END 0x1FF #define ASSETS_SECTOR_END 0x1FF
// RAM layout // RAM layout
#define KERNEL_U_RAM_SIZE 512 #define FB1_RAM_START 0x30000000
#define KERNEL_SRAM2_SIZE (64 * 1024 - 512) #define FB1_RAM_SIZE (768 * 1024 - 512)
#define BOOTARGS_SIZE 0x100 #define BOOTARGS_START 0x300BFE00
#define BOOTARGS_SIZE 0x200
#define MAIN_RAM_START 0x300C0000
#define MAIN_RAM_SIZE (64 * 1024 - 512)
#define SAES_RAM_START 0x300CFE00
#define SAES_RAM_SIZE 512
#define FB2_RAM_START 0x300D0000
#define FB2_RAM_SIZE (768 * 1024)
#define AUX1_RAM_START 0x30190000
#define AUX1_RAM_SIZE (896 * 1024)
// misc
#define CODE_ALIGNMENT 0x400 #define CODE_ALIGNMENT 0x400
#define COREAPP_ALIGNMENT 0x2000 #define COREAPP_ALIGNMENT 0x2000

15
core/embed/projects/kernel/main.c
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@ -212,10 +212,7 @@ void drivers_init() {
// defined in linker script // defined in linker script
extern uint32_t _codelen; extern uint32_t _codelen;
extern uint32_t _coreapp_clear_ram_0_start;
extern uint32_t _coreapp_clear_ram_0_size;
extern uint32_t _coreapp_clear_ram_1_start;
extern uint32_t _coreapp_clear_ram_1_size;
#define KERNEL_SIZE (uint32_t) & _codelen #define KERNEL_SIZE (uint32_t) & _codelen
// Initializes coreapp applet // Initializes coreapp applet
@ -231,10 +228,12 @@ static void coreapp_init(applet_t *applet) {
applet_header_t *coreapp_header = (applet_header_t *)CODE1_START; applet_header_t *coreapp_header = (applet_header_t *)CODE1_START;
applet_layout_t coreapp_layout = { applet_layout_t coreapp_layout = {
.data1.start = (uint32_t)&_coreapp_clear_ram_0_start, .data1.start = (uint32_t)AUX1_RAM_START,
.data1.size = (uint32_t)&_coreapp_clear_ram_0_size, .data1.size = (uint32_t)AUX1_RAM_SIZE,
.data2.start = (uint32_t)&_coreapp_clear_ram_1_start, #ifdef AUX2_RAM_START
.data2.size = (uint32_t)&_coreapp_clear_ram_1_size, .data2.start = (uint32_t)AUX2_RAM_START,
.data2.size = (uint32_t)AUX2_RAM_SIZE,
#endif
.code1.start = CODE1_START, .code1.start = CODE1_START,
.code1.size = CODE1_END - CODE1_START, .code1.size = CODE1_END - CODE1_START,
#ifdef FIRMWARE_P2_START #ifdef FIRMWARE_P2_START

12
core/embed/sec/secure_aes/stm32u5/secure_aes.c
View File

@ -145,8 +145,6 @@ saes_invoke(void) {
return 0; return 0;
} }
extern uint8_t sram_u_start;
extern uint8_t sram_u_end;
extern uint8_t _uflash_start; extern uint8_t _uflash_start;
extern uint8_t _uflash_end; extern uint8_t _uflash_end;
@ -166,10 +164,10 @@ secbool unpriv_encrypt(const uint8_t* input, size_t size, uint8_t* output,
__set_BASEPRI(IRQ_PRI_HIGHEST + 1); __set_BASEPRI(IRQ_PRI_HIGHEST + 1);
#ifdef USE_TRUSTZONE #ifdef USE_TRUSTZONE
uint32_t unpriv_ram_start = (uint32_t)&sram_u_start; uint32_t unpriv_ram_start = SAES_RAM_START;
uint32_t unpriv_ram_size = &sram_u_end - &sram_u_start; uint32_t unpriv_ram_size = SAES_RAM_SIZE;
// `saes_invoke()` function is too small to justigy placing it in a region // `saes_invoke()` function is too small to justify placing it in a region
// that is aligned to TZ_FLASH_ALIGNMENT (8KB), as doing so would result // that is aligned to TZ_FLASH_ALIGNMENT (8KB), as doing so would result
// in significant wasted space. Therefore, we need to align the flash // in significant wasted space. Therefore, we need to align the flash
// addresses to the nearest lower and the nearest higher multiple of // addresses to the nearest lower and the nearest higher multiple of
@ -187,7 +185,7 @@ secbool unpriv_encrypt(const uint8_t* input, size_t size, uint8_t* output,
mpu_mode_t mpu_mode = mpu_reconfig(MPU_MODE_SAES); mpu_mode_t mpu_mode = mpu_reconfig(MPU_MODE_SAES);
memset(&sram_u_start, 0, &sram_u_end - &sram_u_start); memset((void*)SAES_RAM_START, 0, SAES_RAM_SIZE);
memcpy(saes_input, input, size); memcpy(saes_input, input, size);
SAES->CR |= AES_CR_KEYSEL_0; SAES->CR |= AES_CR_KEYSEL_0;
@ -205,7 +203,7 @@ secbool unpriv_encrypt(const uint8_t* input, size_t size, uint8_t* output,
__HAL_RCC_SAES_CLK_ENABLE(); __HAL_RCC_SAES_CLK_ENABLE();
memcpy(output, saes_output, size); memcpy(output, saes_output, size);
memset(&sram_u_start, 0, &sram_u_end - &sram_u_start); memset((void*)SAES_RAM_START, 0, SAES_RAM_SIZE);
mpu_reconfig(mpu_mode); mpu_reconfig(mpu_mode);

28
core/embed/sys/linker/stm32f4/boardloader.ld
View File

@ -5,12 +5,14 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = BOARDLOADER_START, LENGTH = BOARDLOADER_MAXSIZE - BOARDCAPS_MAXSIZE FLASH (rx) : ORIGIN = BOARDLOADER_START, LENGTH = BOARDLOADER_MAXSIZE - BOARDCAPS_MAXSIZE
BOARDCAPS (rx) : ORIGIN = BOARDCAPS_START, LENGTH = BOARDCAPS_MAXSIZE BOARDCAPS (rx) : ORIGIN = BOARDCAPS_START, LENGTH = BOARDCAPS_MAXSIZE
CCMRAM (wal) : ORIGIN = MCU_CCMRAM, LENGTH = MCU_CCMRAM_SIZE MAIN_STACK (wal) : ORIGIN = S_MAIN_STACK_START, LENGTH = S_MAIN_STACK_SIZE
SRAM (wal) : ORIGIN = MCU_SRAM, LENGTH = MCU_SRAM_SIZE MAIN_RAM (wal) : ORIGIN = S_MAIN_RAM_START, LENGTH = S_MAIN_RAM_SIZE
FB1 (wal) : ORIGIN = S_FB1_RAM_START, LENGTH = S_FB1_RAM_SIZE
AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
} }
main_stack_base = ORIGIN(CCMRAM) + LENGTH(CCMRAM); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(CCMRAM); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -53,27 +55,33 @@ SECTIONS {
. = ALIGN(4); /* make the section size a multiple of the word size */ . = ALIGN(4); /* make the section size a multiple of the word size */
} >FLASH AT>FLASH } >FLASH AT>FLASH
.stack : ALIGN(8) {
. = 16K; /* this acts as a build time assertion that at least this much memory is available for stack use */
} >MAIN_STACK
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(4); /* make the section size a multiple of the word size */ . = ALIGN(4); /* make the section size a multiple of the word size */
} >CCMRAM AT>FLASH } >MAIN_RAM AT>FLASH
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); /* make the section size a multiple of the word size */ . = ALIGN(4); /* make the section size a multiple of the word size */
} >CCMRAM } >MAIN_RAM
.fb : ALIGN(4) {
*(.fb1*);
. = ALIGN(4);
} >FB1
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM } >AUX1_RAM
.capabilities : ALIGN(4) { .capabilities : ALIGN(4) {
KEEP(*(.capabilities_section*)); KEEP(*(.capabilities_section*));
. = ALIGN(4); . = ALIGN(4);
} >BOARDCAPS } >BOARDCAPS
.stack : ALIGN(8) {
. = 4K; /* this acts as a build time assertion that at least this much memory is available for stack use */
} >CCMRAM
} }

25
core/embed/sys/linker/stm32f4/bootloader.ld
View File

@ -4,13 +4,15 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = BOOTLOADER_START, LENGTH = BOOTLOADER_MAXSIZE FLASH (rx) : ORIGIN = BOOTLOADER_START, LENGTH = BOOTLOADER_MAXSIZE
CCMRAM (wal) : ORIGIN = MCU_CCMRAM, LENGTH = MCU_CCMRAM_SIZE - BOOTARGS_SIZE MAIN_STACK (wal) : ORIGIN = S_MAIN_STACK_START, LENGTH = S_MAIN_STACK_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_CCMRAM + MCU_CCMRAM_SIZE - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = S_MAIN_RAM_START, LENGTH = S_MAIN_RAM_SIZE
SRAM (wal) : ORIGIN = MCU_SRAM, LENGTH = MCU_SRAM_SIZE FB1 (wal) : ORIGIN = S_FB1_RAM_START, LENGTH = S_FB1_RAM_SIZE
BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
} }
main_stack_base = ORIGIN(CCMRAM) + SIZEOF(.stack) ; /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(CCMRAM); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -60,12 +62,12 @@ SECTIONS {
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */ . = 16K; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */
} >CCMRAM } >MAIN_STACK
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >CCMRAM AT>FLASH } >MAIN_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -74,14 +76,19 @@ SECTIONS {
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >CCMRAM } >MAIN_RAM
.fb : ALIGN(4) {
*(.fb1*);
. = ALIGN(4);
} >FB1
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
*(.no_dma_buffers*); *(.no_dma_buffers*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM } >AUX1_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_args*); *(.boot_args*);

24
core/embed/sys/linker/stm32f4/firmware.ld
View File

@ -5,12 +5,12 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = FIRMWARE_P1_START, LENGTH = FIRMWARE_P1_MAXSIZE FLASH (rx) : ORIGIN = FIRMWARE_P1_START, LENGTH = FIRMWARE_P1_MAXSIZE
FLASH2 (r) : ORIGIN = FIRMWARE_P2_START, LENGTH = FIRMWARE_P2_MAXSIZE FLASH2 (r) : ORIGIN = FIRMWARE_P2_START, LENGTH = FIRMWARE_P2_MAXSIZE
CCMRAM (wal) : ORIGIN = MCU_CCMRAM + KERNEL_STACK_SIZE, LENGTH = MCU_CCMRAM_SIZE - KERNEL_CCMRAM_SIZE - KERNEL_FRAMEBUFFER_SIZE - KERNEL_STACK_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM (wal) : ORIGIN = MCU_SRAM + KERNEL_SRAM_SIZE, LENGTH = MCU_SRAM_SIZE - KERNEL_SRAM_SIZE AUX2_RAM (wal) : ORIGIN = K_AUX2_RAM_START, LENGTH = K_AUX2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
_stack_size = SIZEOF(.stack); _stack_size = SIZEOF(.stack);
@ -23,8 +23,6 @@ bss_start = ADDR(.bss);
bss_end = ADDR(.bss) + SIZEOF(.bss); bss_end = ADDR(.bss) + SIZEOF(.bss);
_codelen = LENGTH(FLASH) - SIZEOF(.vendorheader) - SIZEOF(.header) + SIZEOF(.flash2); _codelen = LENGTH(FLASH) - SIZEOF(.vendorheader) - SIZEOF(.header) + SIZEOF(.flash2);
_flash_start = ORIGIN(FLASH);
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
_heap_start = ADDR(.heap); _heap_start = ADDR(.heap);
_heap_end = ADDR(.heap) + SIZEOF(.heap); _heap_end = ADDR(.heap) + SIZEOF(.heap);
@ -64,32 +62,32 @@ SECTIONS {
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */ . = 16K; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */
} >SRAM } >AUX1_RAM
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM AT>FLASH } >AUX1_RAM AT>FLASH
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM } >AUX1_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM } >AUX1_RAM
.heap : ALIGN(4) { .heap : ALIGN(4) {
. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */ . = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
. = ABSOLUTE(ORIGIN(SRAM) + LENGTH(SRAM)); /* this explicitly sets the end of the heap */ . = ABSOLUTE(ORIGIN(AUX1_RAM) + LENGTH(AUX1_RAM)); /* this explicitly sets the end of the heap */
} >SRAM } >AUX1_RAM
.data_ccm : ALIGN(4) { .data_ccm : ALIGN(4) {
*(.no_dma_buffers*); *(.no_dma_buffers*);
. = ALIGN(4); . = ALIGN(4);
} >CCMRAM } >AUX2_RAM
/DISCARD/ : { /DISCARD/ : {

37
core/embed/sys/linker/stm32f4/kernel.ld
View File

@ -4,15 +4,15 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE
CCMRAM_STACK (wal) : ORIGIN = MCU_CCMRAM, LENGTH = KERNEL_STACK_SIZE MAIN_STACK (wal): ORIGIN = K_MAIN_STACK_START, LENGTH = K_MAIN_STACK_SIZE
CCMRAM_FB (wal) : ORIGIN = MCU_CCMRAM + MCU_CCMRAM_SIZE - KERNEL_CCMRAM_SIZE - KERNEL_FRAMEBUFFER_SIZE, LENGTH = KERNEL_FRAMEBUFFER_SIZE FB1 (wal) : ORIGIN = K_FB1_RAM_START, LENGTH = K_FB1_RAM_SIZE
CCMRAM (wal) : ORIGIN = MCU_CCMRAM + MCU_CCMRAM_SIZE - KERNEL_CCMRAM_SIZE, LENGTH = KERNEL_CCMRAM_SIZE - BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = K_MAIN_RAM_START, LENGTH = K_MAIN_RAM_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_CCMRAM + MCU_CCMRAM_SIZE - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM (wal) : ORIGIN = MCU_SRAM, LENGTH = KERNEL_SRAM_SIZE DMABUF (wal) : ORIGIN = DMABUF_RAM_START, LENGTH = DMABUF_RAM_SIZE
} }
main_stack_base = ORIGIN(CCMRAM_STACK) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(CCMRAM_STACK); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -22,10 +22,6 @@ data_size = SIZEOF(.data);
bss_start = ADDR(.bss); bss_start = ADDR(.bss);
bss_end = ADDR(.bss) + SIZEOF(.bss); bss_end = ADDR(.bss) + SIZEOF(.bss);
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
/* used by the startup code to wipe memory */ /* used by the startup code to wipe memory */
_startup_clear_ram_0_start = MCU_CCMRAM; _startup_clear_ram_0_start = MCU_CCMRAM;
_startup_clear_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE; _startup_clear_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE;
@ -44,16 +40,7 @@ _shutdown_clear_ram_0_end = MCU_CCMRAM + MCU_CCMRAM_SIZE;
_shutdown_clear_ram_1_start = MCU_SRAM; _shutdown_clear_ram_1_start = MCU_SRAM;
_shutdown_clear_ram_1_end = MCU_SRAM + MCU_SRAM_SIZE; _shutdown_clear_ram_1_end = MCU_SRAM + MCU_SRAM_SIZE;
/* used by applet cleaning code */
_coreapp_clear_ram_0_start = MCU_CCMRAM + KERNEL_STACK_SIZE;
_coreapp_clear_ram_0_size = MCU_CCMRAM_SIZE - KERNEL_CCMRAM_SIZE - KERNEL_FRAMEBUFFER_SIZE - KERNEL_STACK_SIZE;
_coreapp_clear_ram_1_start = MCU_SRAM + KERNEL_SRAM_SIZE;
_coreapp_clear_ram_1_size = MCU_SRAM_SIZE - KERNEL_SRAM_SIZE;
_codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.data) ; _codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.data) ;
_flash_start = ORIGIN(FLASH);
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
SECTIONS { SECTIONS {
.vendorheader : ALIGN(4) { .vendorheader : ALIGN(4) {
@ -79,27 +66,27 @@ SECTIONS {
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 8K; /* Exactly 6k allocated for stack. Overflow causes MemManage fault (when using MPU). */ . = 8K; /* Exactly 6k allocated for stack. Overflow causes MemManage fault (when using MPU). */
} >CCMRAM_STACK } >MAIN_STACK
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >CCMRAM AT>FLASH } >MAIN_RAM AT>FLASH
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >CCMRAM } >MAIN_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM } >DMABUF
.fb : ALIGN(4) { .fb : ALIGN(4) {
*(.fb1*); *(.fb1*);
. = ALIGN(4); . = ALIGN(4);
} >CCMRAM_FB } >FB1
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_args*); *(.boot_args*);

27
core/embed/sys/linker/stm32f4/prodtest.ld
View File

@ -4,13 +4,15 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = FIRMWARE_P1_START, LENGTH = FIRMWARE_P1_MAXSIZE FLASH (rx) : ORIGIN = FIRMWARE_P1_START, LENGTH = FIRMWARE_P1_MAXSIZE
CCMRAM (wal) : ORIGIN = MCU_CCMRAM, LENGTH = MCU_CCMRAM_SIZE - BOOTARGS_SIZE MAIN_STACK (wal) : ORIGIN = S_MAIN_STACK_START, LENGTH = S_MAIN_STACK_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_CCMRAM + MCU_CCMRAM_SIZE - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = S_MAIN_RAM_START, LENGTH = S_MAIN_RAM_SIZE
SRAM (wal) : ORIGIN = MCU_SRAM, LENGTH = MCU_SRAM_SIZE FB1 (wal) : ORIGIN = S_FB1_RAM_START, LENGTH = S_FB1_RAM_SIZE
BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM) + LENGTH(SRAM); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -68,19 +70,24 @@ SECTIONS {
*(.ARM.exidx*); *(.ARM.exidx*);
} }
.stack : ALIGN(8) {
. = 16K; /* this acts as a build time assertion that at least this much memory is available for stack use */
} >MAIN_STACK
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM AT>FLASH } >AUX1_RAM AT>FLASH
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM } >AUX1_RAM
.stack : ALIGN(8) { .fb : ALIGN(4) {
. = 4K; /* this acts as a build time assertion that at least this much memory is available for stack use */ *(.fb1*);
} >SRAM . = ALIGN(4);
} >FB1
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_args*); *(.boot_args*);

49
core/embed/sys/linker/stm32u58/boardloader.ld
View File

@ -5,17 +5,17 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = BOARDLOADER_START, LENGTH = BOARDLOADER_MAXSIZE FLASH (rx) : ORIGIN = BOARDLOADER_START, LENGTH = BOARDLOADER_MAXSIZE
BOARDCAPS (rx) : ORIGIN = BOARDCAPS_START, LENGTH = BOARDCAPS_MAXSIZE BOARDCAPS (rx) : ORIGIN = BOARDCAPS_START, LENGTH = BOARDCAPS_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -34,7 +34,7 @@ confidential_size = SIZEOF(.confidential);
_startup_clear_ram_0_start = MCU_SRAM1; _startup_clear_ram_0_start = MCU_SRAM1;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE; _startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_startup_clear_ram_1_start = MCU_SRAM2; _startup_clear_ram_1_start = MCU_SRAM2;
_startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _startup_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_startup_clear_ram_2_start = MCU_SRAM4; _startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
@ -42,13 +42,13 @@ _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1; _handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE; _handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_handoff_clear_ram_1_start = MCU_SRAM2; _handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _handoff_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4; _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = MCU_SRAM1; _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _shutdown_clear_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_shutdown_clear_ram_1_start = MCU_SRAM4; _shutdown_clear_ram_1_start = MCU_SRAM4;
_shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_shutdown_clear_ram_2_start = 0; _shutdown_clear_ram_2_start = 0;
@ -56,9 +56,6 @@ _shutdown_clear_ram_2_end = 0;
_shutdown_clear_ram_3_start = 0; _shutdown_clear_ram_3_start = 0;
_shutdown_clear_ram_3_end = 0; _shutdown_clear_ram_3_end = 0;
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
SECTIONS { SECTIONS {
.vector_table : ALIGN(CODE_ALIGNMENT) { .vector_table : ALIGN(CODE_ALIGNMENT) {
@ -78,7 +75,7 @@ SECTIONS {
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(8); . = ALIGN(8);
} >SRAM1 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -87,29 +84,31 @@ SECTIONS {
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >AUX1_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >AUX1_RAM
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */ . = 16K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.confidential : ALIGN(8) { .confidential : ALIGN(8) {
*(.confidential*); *(.confidential*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.fb : ALIGN(4) { .fb1 : ALIGN(4) {
__fb_start = .;
*(.fb1*); *(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB1_RAM
.fb2 : ALIGN(4) {
*(.fb2*);
. = ALIGN(4);
} >FB2_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

50
core/embed/sys/linker/stm32u58/bootloader.ld
View File

@ -4,17 +4,17 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = BOOTLOADER_START, LENGTH = BOOTLOADER_MAXSIZE FLASH (rx) : ORIGIN = BOOTLOADER_START, LENGTH = BOOTLOADER_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -33,7 +33,7 @@ confidential_size = SIZEOF(.confidential);
_startup_clear_ram_0_start = MCU_SRAM1; _startup_clear_ram_0_start = MCU_SRAM1;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE; _startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_startup_clear_ram_1_start = MCU_SRAM2; _startup_clear_ram_1_start = MCU_SRAM2;
_startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _startup_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_startup_clear_ram_2_start = MCU_SRAM4; _startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
@ -41,13 +41,13 @@ _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1; _handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE; _handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_handoff_clear_ram_1_start = MCU_SRAM2; _handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _handoff_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4; _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = MCU_SRAM1; _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _shutdown_clear_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_shutdown_clear_ram_1_start = MCU_SRAM4; _shutdown_clear_ram_1_start = MCU_SRAM4;
_shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_shutdown_clear_ram_2_start = 0; _shutdown_clear_ram_2_start = 0;
@ -55,10 +55,6 @@ _shutdown_clear_ram_2_end = 0;
_shutdown_clear_ram_3_start = 0; _shutdown_clear_ram_3_start = 0;
_shutdown_clear_ram_3_end = 0; _shutdown_clear_ram_3_end = 0;
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential); _codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
SECTIONS { SECTIONS {
@ -78,7 +74,7 @@ SECTIONS {
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM1 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -87,31 +83,33 @@ SECTIONS {
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >AUX1_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
*(.no_dma_buffers*); *(.no_dma_buffers*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >AUX1_RAM
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */ . = 16K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.fb : ALIGN(4) { .fb1 : ALIGN(4) {
__fb_start = .;
*(.fb1*); *(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB1_RAM
.fb2 : ALIGN(4) {
*(.fb2*);
. = ALIGN(4);
} >FB2_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

26
core/embed/sys/linker/stm32u58/firmware.ld
View File

@ -4,16 +4,12 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = FIRMWARE_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = FIRMWARE_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - 512 AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE + KERNEL_U_RAM_SIZE, LENGTH = MCU_SRAM2_SIZE - KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE AUX2_RAM (wal) : ORIGIN = AUX2_RAM_START, LENGTH = AUX2_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE - FRAMEBUFFER_SRAM_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = 0K /* not allocated to coreapp */
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
_stack_size = SIZEOF(.stack); _stack_size = SIZEOF(.stack);
@ -59,7 +55,7 @@ SECTIONS {
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM1 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -69,24 +65,24 @@ SECTIONS {
*(.no_dma_buffers*); *(.no_dma_buffers*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >AUX1_RAM
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 32K; /* Overflow causes UsageFault */ . = 32K; /* Overflow causes UsageFault */
} >SRAM2 } >AUX2_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >AUX2_RAM AT>FLASH
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >AUX2_RAM
.heap : ALIGN(4) { .heap : ALIGN(4) {
. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */ . = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
. = ABSOLUTE(ORIGIN(SRAM3) + LENGTH(SRAM3)); /* this explicitly sets the end of the heap */ . = ABSOLUTE(ORIGIN(AUX2_RAM) + LENGTH(AUX2_RAM)); /* this explicitly sets the end of the heap */
} >SRAM3 } >AUX2_RAM
} }

62
core/embed/sys/linker/stm32u58/kernel.ld
View File

@ -4,22 +4,20 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM2, LENGTH = 0K
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = KERNEL_SRAM2_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM2_U (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE, LENGTH = KERNEL_U_RAM_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3 + MCU_SRAM3_SIZE - FRAMEBUFFER_SRAM_SIZE, LENGTH = FRAMEBUFFER_SRAM_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */ FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
ustack_base = ORIGIN(SRAM2_U) + 512; ustack_base = ADDR(.udata) + 512;
_sustack = ORIGIN(SRAM2_U) + 256; _sustack = ADDR(.udata) + 256;
_eustack = ustack_base; _eustack = ustack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -38,7 +36,7 @@ confidential_size = SIZEOF(.confidential);
_startup_clear_ram_0_start = MCU_SRAM1; _startup_clear_ram_0_start = MCU_SRAM1;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE; _startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_startup_clear_ram_1_start = MCU_SRAM2; _startup_clear_ram_1_start = MCU_SRAM2;
_startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _startup_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_startup_clear_ram_2_start = MCU_SRAM4; _startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
@ -46,13 +44,13 @@ _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1; _handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - 512; _handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - 512;
_handoff_clear_ram_1_start = MCU_SRAM2; _handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _handoff_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4; _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = MCU_SRAM1; _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _shutdown_clear_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_shutdown_clear_ram_1_start = MCU_SRAM4; _shutdown_clear_ram_1_start = MCU_SRAM4;
_shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_shutdown_clear_ram_2_start = 0; _shutdown_clear_ram_2_start = 0;
@ -60,19 +58,6 @@ _shutdown_clear_ram_2_end = 0;
_shutdown_clear_ram_3_start = 0; _shutdown_clear_ram_3_start = 0;
_shutdown_clear_ram_3_end = 0; _shutdown_clear_ram_3_end = 0;
/* used by applet cleaning code */
_coreapp_clear_ram_0_start = MCU_SRAM1;
_coreapp_clear_ram_0_size = MCU_SRAM1_SIZE - 512;
_coreapp_clear_ram_1_start = MCU_SRAM2 + KERNEL_SRAM2_SIZE + KERNEL_U_RAM_SIZE;
_coreapp_clear_ram_1_size = MCU_SRAM2_SIZE - KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE + MCU_SRAM3_SIZE - FRAMEBUFFER_SRAM_SIZE;
sram_u_start = ORIGIN(SRAM2_U);
sram_u_end = ORIGIN(SRAM2_U) + LENGTH(SRAM2_U);
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
_codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.uflash) + SIZEOF(.data) + SIZEOF(.confidential); _codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.uflash) + SIZEOF(.data) + SIZEOF(.confidential);
_flash_start = ORIGIN(FLASH); _flash_start = ORIGIN(FLASH);
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH); _flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
@ -104,12 +89,12 @@ SECTIONS {
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 6K; /* Overflow causes UsageFault */ . = 6K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -120,33 +105,34 @@ SECTIONS {
*(.buf*); *(.buf*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM2 } >MAIN_RAM
/* unprivileged data and stack for SAES */ /* unprivileged data and stack for SAES */
.udata : ALIGN(512) { .udata : ALIGN(512) {
*(.udata*); *(.udata*);
. = ALIGN(256); . = ALIGN(256);
. = 256; /* Overflow causes UsageFault */ . = 256; /* Overflow causes UsageFault */
} >SRAM2_U } >SAES_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(CODE_ALIGNMENT); . = ALIGN(CODE_ALIGNMENT);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.uflash : ALIGN(512) { .uflash : ALIGN(512) {
*(.uflash*); *(.uflash*);
. = ALIGN(COREAPP_ALIGNMENT); . = ALIGN(COREAPP_ALIGNMENT);
} >FLASH AT>FLASH } >FLASH AT>FLASH
.fb : ALIGN(4) { .fb1 : ALIGN(4) {
__fb_start = .;
*(.fb1*); *(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB1_RAM
.fb2 : ALIGN(4) {
*(.fb2*);
. = ALIGN(4);
} >FB2_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

4
core/embed/sys/linker/stm32u58/memory.ld
View File

@ -12,7 +12,3 @@ MCU_SRAM3 = 0x30040000;
MCU_SRAM3_SIZE = 512K; MCU_SRAM3_SIZE = 512K;
MCU_SRAM4 = 0x38000000; MCU_SRAM4 = 0x38000000;
MCU_SRAM4_SIZE = 16K; MCU_SRAM4_SIZE = 16K;
MCU_SRAM5 = 0x30080000;
MCU_SRAM5_SIZE = 0K; /* SRAM5 is not available */
MCU_SRAM6 = 0x30080000;
MCU_SRAM6_SIZE = 0K ; /* SRAM6 is not available */

60
core/embed/sys/linker/stm32u58/prodtest.ld
View File

@ -4,17 +4,17 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = FIRMWARE_START, LENGTH = FIRMWARE_MAXSIZE FLASH (rx) : ORIGIN = FIRMWARE_START, LENGTH = FIRMWARE_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE /* SRAM5 is not available */ SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE /* SRAM6 is not available */ FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -24,7 +24,6 @@ data_size = SIZEOF(.data);
bss_start = ADDR(.bss); bss_start = ADDR(.bss);
bss_end = ADDR(.bss) + SIZEOF(.bss); bss_end = ADDR(.bss) + SIZEOF(.bss);
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
confidential_lma = LOADADDR(.confidential); confidential_lma = LOADADDR(.confidential);
confidential_vma = ADDR(.confidential); confidential_vma = ADDR(.confidential);
@ -34,7 +33,7 @@ confidential_size = SIZEOF(.confidential);
_startup_clear_ram_0_start = MCU_SRAM1; _startup_clear_ram_0_start = MCU_SRAM1;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE; _startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_startup_clear_ram_1_start = MCU_SRAM2; _startup_clear_ram_1_start = MCU_SRAM2;
_startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _startup_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_startup_clear_ram_2_start = MCU_SRAM4; _startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
@ -42,13 +41,13 @@ _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1; _handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE; _handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_handoff_clear_ram_1_start = MCU_SRAM2; _handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _handoff_clear_ram_1_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4; _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = MCU_SRAM1; _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = MCU_SRAM6 + MCU_SRAM6_SIZE; _shutdown_clear_ram_0_end = MCU_SRAM3 + MCU_SRAM3_SIZE;
_shutdown_clear_ram_1_start = MCU_SRAM4; _shutdown_clear_ram_1_start = MCU_SRAM4;
_shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _shutdown_clear_ram_1_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
_shutdown_clear_ram_2_start = 0; _shutdown_clear_ram_2_start = 0;
@ -56,10 +55,6 @@ _shutdown_clear_ram_2_end = 0;
_shutdown_clear_ram_3_start = 0; _shutdown_clear_ram_3_start = 0;
_shutdown_clear_ram_3_end = 0; _shutdown_clear_ram_3_end = 0;
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential); _codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
_flash_start = ORIGIN(FLASH); _flash_start = ORIGIN(FLASH);
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH); _flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
@ -79,43 +74,48 @@ SECTIONS {
*(.text*); *(.text*);
. = ALIGN(4); . = ALIGN(4);
*(.rodata*); *(.rodata*);
. = ALIGN(4);
KEEP(*(.bootloader));
*(.bootloader*);
. = ALIGN(512); . = ALIGN(512);
} >FLASH AT>FLASH } >FLASH AT>FLASH
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM1 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
} }
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.no_dma_buffers*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >AUX1_RAM
.buf : ALIGN(4) {
*(.buf*);
. = ALIGN(4);
*(.no_dma_buffers*);
. = ALIGN(4);
} >AUX1_RAM
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */ . = 16K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.fb : ALIGN(4) { .fb1 : ALIGN(4) {
__fb_start = .;
*(.fb1*); *(.fb1*);
*(.fb2*);
__fb_end = .;
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB1_RAM
.fb2 : ALIGN(4) {
*(.fb2*);
. = ALIGN(4);
} >FB2_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

44
core/embed/sys/linker/stm32u5g/boardloader.ld
View File

@ -5,17 +5,17 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = BOARDLOADER_START, LENGTH = BOARDLOADER_MAXSIZE FLASH (rx) : ORIGIN = BOARDLOADER_START, LENGTH = BOARDLOADER_MAXSIZE
BOARDCAPS (rx) : ORIGIN = BOARDCAPS_START, LENGTH = BOARDCAPS_MAXSIZE BOARDCAPS (rx) : ORIGIN = BOARDCAPS_START, LENGTH = BOARDCAPS_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -47,18 +47,14 @@ _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = ORIGIN(SRAM1); _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = ADDR(.fb1); _shutdown_clear_ram_0_end = ADDR(.fb1);
_shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1); _shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1);
_shutdown_clear_ram_1_end = ADDR(.fb2); _shutdown_clear_ram_1_end = ADDR(.fb2);
_shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2); _shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2);
_shutdown_clear_ram_2_end = ORIGIN(SRAM6)+ LENGTH(SRAM6); _shutdown_clear_ram_2_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_shutdown_clear_ram_3_start = ORIGIN(SRAM4); _shutdown_clear_ram_3_start = MCU_SRAM4;
_shutdown_clear_ram_3_end = ORIGIN(SRAM4) + LENGTH(SRAM4); _shutdown_clear_ram_3_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
SECTIONS { SECTIONS {
.vector_table : ALIGN(CODE_ALIGNMENT) { .vector_table : ALIGN(CODE_ALIGNMENT) {
@ -78,7 +74,7 @@ SECTIONS {
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(8); . = ALIGN(8);
} >SRAM5 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -87,31 +83,31 @@ SECTIONS {
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */ . = 16K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.confidential : ALIGN(8) { .confidential : ALIGN(8) {
*(.confidential*); *(.confidential*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.fb1 : ALIGN(4) { .fb1 : ALIGN(4) {
*(.fb1*); *(.fb1*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >FB1_RAM
.fb2 : ALIGN(4) { .fb2 : ALIGN(4) {
*(.fb2*); *(.fb2*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB2_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

46
core/embed/sys/linker/stm32u5g/bootloader.ld
View File

@ -4,17 +4,17 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = BOOTLOADER_START, LENGTH = BOOTLOADER_MAXSIZE FLASH (rx) : ORIGIN = BOOTLOADER_START, LENGTH = BOOTLOADER_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -46,18 +46,14 @@ _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = ORIGIN(SRAM1); _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = ADDR(.fb1); _shutdown_clear_ram_0_end = ADDR(.fb1);
_shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1); _shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1);
_shutdown_clear_ram_1_end = ADDR(.fb2); _shutdown_clear_ram_1_end = ADDR(.fb2);
_shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2); _shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2);
_shutdown_clear_ram_2_end = ORIGIN(SRAM6)+ LENGTH(SRAM6); _shutdown_clear_ram_2_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_shutdown_clear_ram_3_start = ORIGIN(SRAM4); _shutdown_clear_ram_3_start = MCU_SRAM4;
_shutdown_clear_ram_3_end = ORIGIN(SRAM4) + LENGTH(SRAM4); _shutdown_clear_ram_3_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential); _codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
@ -78,7 +74,7 @@ SECTIONS {
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM5 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -87,35 +83,33 @@ SECTIONS {
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
*(.no_dma_buffers*); *(.no_dma_buffers*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 16K; /* Overflow causes UsageFault */ . = 16K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.fb1 : ALIGN(4) { .fb1 : ALIGN(4) {
__fb_start = .;
*(.fb1*); *(.fb1*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >FB1_RAM
.fb2 : ALIGN(4) { .fb2 : ALIGN(4) {
*(.fb2*); *(.fb2*);
__fb_end = .;
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB2_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

25
core/embed/sys/linker/stm32u5g/firmware.ld
View File

@ -4,16 +4,11 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = FIRMWARE_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = FIRMWARE_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = 0K /* not allocated to coreapp */ AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = 0K /* not allocated to coreapp */
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = 0K /* not allocated to coreapp */
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* not allocated to coreapp */
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = 0K /* not allocated to coreapp */
} }
main_stack_base = ORIGIN(SRAM5) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM5); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
_stack_size = SIZEOF(.stack); _stack_size = SIZEOF(.stack);
@ -57,12 +52,12 @@ SECTIONS {
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 32K; /* Overflow causes UsageFault */ . = 32K; /* Overflow causes UsageFault */
} >SRAM5 } >AUX1_RAM
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM5 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -72,21 +67,21 @@ SECTIONS {
*(.no_dma_buffers*); *(.no_dma_buffers*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM5 AT>FLASH } >AUX1_RAM AT>FLASH
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.heap : ALIGN(4) { .heap : ALIGN(4) {
. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */ . = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
. = ABSOLUTE(ORIGIN(SRAM5) + LENGTH(SRAM5)); /* this explicitly sets the end of the heap */ . = ABSOLUTE(ORIGIN(AUX1_RAM) + LENGTH(AUX1_RAM)); /* this explicitly sets the end of the heap */
} >SRAM5 } >AUX1_RAM
} }

60
core/embed/sys/linker/stm32u5g/kernel.ld
View File

@ -4,22 +4,20 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = KERNEL_SRAM2_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM2_U (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE, LENGTH = KERNEL_U_RAM_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
ustack_base = ORIGIN(SRAM2_U) + 512; ustack_base = ADDR(.udata) + 512;
_sustack = ORIGIN(SRAM2_U) + 256; _sustack = ADDR(.udata) + 256;
_eustack = ustack_base; _eustack = ustack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -51,28 +49,14 @@ _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = ORIGIN(SRAM1); _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = ADDR(.fb1); _shutdown_clear_ram_0_end = ADDR(.fb1);
_shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1); _shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1);
_shutdown_clear_ram_1_end = ADDR(.fb2); _shutdown_clear_ram_1_end = ADDR(.fb2);
_shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2); _shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2);
_shutdown_clear_ram_2_end = ORIGIN(SRAM6)+ LENGTH(SRAM6); _shutdown_clear_ram_2_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_shutdown_clear_ram_3_start = ORIGIN(SRAM4); _shutdown_clear_ram_3_start = MCU_SRAM4;
_shutdown_clear_ram_3_end = ORIGIN(SRAM4) + LENGTH(SRAM4); _shutdown_clear_ram_3_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by appleet cleaning code */
_coreapp_clear_ram_0_start = MCU_SRAM5;
_coreapp_clear_ram_0_size = MCU_SRAM5_SIZE;
_coreapp_clear_ram_1_start = 0;
_coreapp_clear_ram_1_size = 0;
sram_u_start = ORIGIN(SRAM2_U);
sram_u_end = ORIGIN(SRAM2_U) + LENGTH(SRAM2_U);
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
_codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.uflash) + SIZEOF(.data) + SIZEOF(.confidential); _codelen = SIZEOF(.vendorheader) + SIZEOF(.header) + SIZEOF(.flash) + SIZEOF(.uflash) + SIZEOF(.data) + SIZEOF(.confidential);
_flash_start = ORIGIN(FLASH); _flash_start = ORIGIN(FLASH);
@ -105,12 +89,12 @@ SECTIONS {
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 12K; /* Overflow causes UsageFault */ . = 12K; /* Overflow causes UsageFault */
} >SRAM2 } >MAIN_RAM
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -120,19 +104,19 @@ SECTIONS {
*(.no_dma_buffers*); *(.no_dma_buffers*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM2 } >MAIN_RAM
/* unprivileged data and stack for SAES */ /* unprivileged data and stack for SAES */
.udata : ALIGN(512) { .udata : ALIGN(512) {
*(.udata*); *(.udata*);
. = ALIGN(256); . = ALIGN(256);
. = 256; /* Overflow causes UsageFault */ . = 256; /* Overflow causes UsageFault */
} >SRAM2_U } >SAES_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.uflash : ALIGN(512) { .uflash : ALIGN(512) {
*(.uflash*); *(.uflash*);
@ -142,17 +126,17 @@ SECTIONS {
.fb1 : ALIGN(4) { .fb1 : ALIGN(4) {
*(.fb1*); *(.fb1*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >FB1_RAM
.fb2 : ALIGN(4) { .fb2 : ALIGN(4) {
*(.fb2*); *(.fb2*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB2_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM2 } >MAIN_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {

46
core/embed/sys/linker/stm32u5g/prodtest.ld
View File

@ -4,17 +4,17 @@ ENTRY(reset_handler)
MEMORY { MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = KERNEL_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - BOOTARGS_SIZE
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE MAIN_RAM (wal) : ORIGIN = MAIN_RAM_START, LENGTH = MAIN_RAM_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = MCU_SRAM2_SIZE AUX1_RAM (wal) : ORIGIN = AUX1_RAM_START, LENGTH = AUX1_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE BOOT_ARGS (wal) : ORIGIN = BOOTARGS_START, LENGTH = BOOTARGS_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = MCU_SRAM5_SIZE SAES_RAM (wal) : ORIGIN = SAES_RAM_START, LENGTH = SAES_RAM_SIZE
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = MCU_SRAM6_SIZE FB1_RAM (wal) : ORIGIN = FB1_RAM_START, LENGTH = FB1_RAM_SIZE
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE FB2_RAM (wal) : ORIGIN = FB2_RAM_START, LENGTH = FB2_RAM_SIZE
} }
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */ main_stack_base = ADDR(.stack) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
_sstack = ORIGIN(SRAM2); _sstack = ADDR(.stack);
_estack = main_stack_base; _estack = main_stack_base;
/* used by the startup code to populate variables used by the C code */ /* used by the startup code to populate variables used by the C code */
@ -46,19 +46,16 @@ _handoff_clear_ram_2_start = MCU_SRAM4;
_handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE; _handoff_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the shutdown code to wipe memory */ /* used by the shutdown code to wipe memory */
_shutdown_clear_ram_0_start = ORIGIN(SRAM1); _shutdown_clear_ram_0_start = MCU_SRAM1;
_shutdown_clear_ram_0_end = ADDR(.fb1); _shutdown_clear_ram_0_end = ADDR(.fb1);
_shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1); _shutdown_clear_ram_1_start = ADDR(.fb1) + SIZEOF(.fb1);
_shutdown_clear_ram_1_end = ADDR(.fb2); _shutdown_clear_ram_1_end = ADDR(.fb2);
_shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2); _shutdown_clear_ram_2_start = ADDR(.fb2) + SIZEOF(.fb2);
_shutdown_clear_ram_2_end = ORIGIN(SRAM6)+ LENGTH(SRAM6); _shutdown_clear_ram_2_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_shutdown_clear_ram_3_start = ORIGIN(SRAM4); _shutdown_clear_ram_3_start = MCU_SRAM4;
_shutdown_clear_ram_3_end = ORIGIN(SRAM4) + LENGTH(SRAM4); _shutdown_clear_ram_3_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* reserve 256 bytes for bootloader arguments */
boot_args_start = ORIGIN(BOOT_ARGS);
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential); _codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.confidential);
_flash_start = ORIGIN(FLASH); _flash_start = ORIGIN(FLASH);
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH); _flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
@ -79,20 +76,17 @@ SECTIONS {
*(.text*); *(.text*);
. = ALIGN(4); . = ALIGN(4);
*(.rodata*); *(.rodata*);
. = ALIGN(4);
KEEP(*(.bootloader));
*(.bootloader*);
. = ALIGN(512); . = ALIGN(512);
} >FLASH AT>FLASH } >FLASH AT>FLASH
.stack : ALIGN(8) { .stack : ALIGN(8) {
. = 12K; /* Overflow causes UsageFault */ . = 12K; /* Overflow causes UsageFault */
} >SRAM5 } >MAIN_RAM
.data : ALIGN(4) { .data : ALIGN(4) {
*(.data*); *(.data*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM5 AT>FLASH } >AUX1_RAM AT>FLASH
/DISCARD/ : { /DISCARD/ : {
*(.ARM.exidx*); *(.ARM.exidx*);
@ -102,27 +96,27 @@ SECTIONS {
*(.no_dma_buffers*); *(.no_dma_buffers*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.confidential : ALIGN(512) { .confidential : ALIGN(512) {
*(.confidential*); *(.confidential*);
. = ALIGN(512); . = ALIGN(512);
} >SRAM2 AT>FLASH } >MAIN_RAM AT>FLASH
.fb1 : ALIGN(4) { .fb1 : ALIGN(4) {
*(.fb1*); *(.fb1*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >FB1_RAM
.fb2 : ALIGN(4) { .fb2 : ALIGN(4) {
*(.fb2*); *(.fb2*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >FB2_RAM
.buf : ALIGN(4) { .buf : ALIGN(4) {
*(.buf*); *(.buf*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM5 } >AUX1_RAM
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {

8
core/embed/sys/mpu/stm32f4/mpu.c
View File

@ -67,14 +67,6 @@ mpu_driver_t g_mpu_driver = {
.mode = MPU_MODE_DISABLED, .mode = MPU_MODE_DISABLED,
}; };
#define SRAM_SIZE (192 * 1024)
#define KERNEL_STACK_START (CCMDATARAM_BASE)
#define KERNEL_CCMRAM_START (CCMDATARAM_END + 1 - KERNEL_CCMRAM_SIZE)
#define KERNEL_SRAM_START (SRAM1_BASE + SRAM_SIZE - KERNEL_SRAM_SIZE)
#define KERNEL_CCMRAM_FB_START (KERNEL_CCMRAM_START - KERNEL_FRAMEBUFFER_SIZE)
_Static_assert(NORCOW_SECTOR_SIZE == STORAGE_1_MAXSIZE, "norcow misconfigured"); _Static_assert(NORCOW_SECTOR_SIZE == STORAGE_1_MAXSIZE, "norcow misconfigured");
_Static_assert(NORCOW_SECTOR_SIZE == STORAGE_2_MAXSIZE, "norcow misconfigured"); _Static_assert(NORCOW_SECTOR_SIZE == STORAGE_2_MAXSIZE, "norcow misconfigured");
_Static_assert(NORCOW_SECTOR_SIZE == SIZE_64K, "norcow misconfigured"); _Static_assert(NORCOW_SECTOR_SIZE == SIZE_64K, "norcow misconfigured");

62
core/embed/sys/mpu/stm32u5/mpu.c
View File

@ -137,16 +137,10 @@ _Static_assert(NORCOW_SECTOR_SIZE == STORAGE_2_MAXSIZE, "norcow misconfigured");
#define OTP_AND_ID_SIZE 0x800 #define OTP_AND_ID_SIZE 0x800
// clang-format on
extern uint8_t boot_args_start;
#define BOOTARGS_START ((uint32_t) & boot_args_start)
#ifdef KERNEL #ifdef KERNEL
extern uint8_t _uflash_start; extern uint8_t _uflash_start;
extern uint8_t _uflash_end; extern uint8_t _uflash_end;
#define KERNEL_RAM_U_START (KERNEL_RAM_START + KERNEL_RAM_SIZE)
#define KERNEL_RAM_U_SIZE KERNEL_U_RAM_SIZE
#define KERNEL_FLASH_U_START (uint32_t) & _uflash_start #define KERNEL_FLASH_U_START (uint32_t) & _uflash_start
#define KERNEL_FLASH_U_SIZE ((uint32_t) & _uflash_end - KERNEL_FLASH_U_START) #define KERNEL_FLASH_U_SIZE ((uint32_t) & _uflash_end - KERNEL_FLASH_U_START)
@ -161,36 +155,6 @@ extern uint32_t _codelen;
#define COREAPP_FLASH_SIZE \ #define COREAPP_FLASH_SIZE \
(FIRMWARE_MAXSIZE - (COREAPP_FLASH_START - KERNEL_FLASH_START)) (FIRMWARE_MAXSIZE - (COREAPP_FLASH_START - KERNEL_FLASH_START))
#define KERNEL_RAM_START (SRAM2_BASE)
#define KERNEL_RAM_SIZE (KERNEL_SRAM2_SIZE)
#ifdef STM32U585xx
#define COREAPP_RAM1_START SRAM1_BASE
#define COREAPP_RAM1_SIZE (SRAM1_SIZE - 512)
#define COREAPP_RAM2_START (SRAM2_BASE + KERNEL_SRAM2_SIZE + KERNEL_U_RAM_SIZE)
#define COREAPP_RAM2_SIZE \
(SRAM2_SIZE - KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE + SRAM3_SIZE - \
FRAMEBUFFER_SRAM_SIZE)
#else
#define COREAPP_RAM1_START SRAM5_BASE
#define COREAPP_RAM1_SIZE SRAM5_SIZE
#endif
#else
#ifdef STM32U585xx
#define MAIN_SRAM_START SRAM2_BASE
#define MAIN_SRAM_SIZE SRAM2_SIZE
#define AUX_SRAM_START SRAM1_BASE
#define AUX_SRAM_SIZE (SRAM1_SIZE - BOOTARGS_SIZE)
#else
#define MAIN_SRAM_START SRAM2_BASE
#define MAIN_SRAM_SIZE SRAM2_SIZE
#define AUX_SRAM_START SRAM5_BASE
#define AUX_SRAM_SIZE SRAM5_SIZE
#endif
#endif #endif
typedef struct { typedef struct {
@ -218,27 +182,27 @@ static void mpu_init_fixed_regions(void) {
#if defined(BOARDLOADER) #if defined(BOARDLOADER)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV // REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 0, BOARDLOADER_START, BOARDLOADER_MAXSIZE, FLASH_CODE, NO, NO ); SET_REGION( 0, BOARDLOADER_START, BOARDLOADER_MAXSIZE, FLASH_CODE, NO, NO );
SET_REGION( 1, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 1, MAIN_RAM_START, MAIN_RAM_SIZE, SRAM, YES, NO );
SET_REGION( 2, BOOTLOADER_START, BOOTLOADER_MAXSIZE, FLASH_DATA, YES, NO ); SET_REGION( 2, BOOTLOADER_START, BOOTLOADER_MAXSIZE, FLASH_DATA, YES, NO );
SET_REGION( 3, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_DATA, YES, NO ); SET_REGION( 3, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_DATA, YES, NO );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 4, AUX1_RAM_START, AUX1_RAM_SIZE, SRAM, YES, NO );
#endif #endif
#if defined(BOOTLOADER) #if defined(BOOTLOADER)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV // REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 0, BOOTLOADER_START, BOOTLOADER_MAXSIZE, FLASH_CODE, NO, NO ); SET_REGION( 0, BOOTLOADER_START, BOOTLOADER_MAXSIZE, FLASH_CODE, NO, NO );
SET_REGION( 1, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 1, MAIN_RAM_START, MAIN_RAM_SIZE, SRAM, YES, NO );
SET_REGION( 2, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_DATA, YES, NO ); SET_REGION( 2, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_DATA, YES, NO );
DIS_REGION( 3 ); DIS_REGION( 3 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 4, AUX1_RAM_START, AUX1_RAM_SIZE , SRAM, YES, NO );
#endif #endif
#if defined(KERNEL) #if defined(KERNEL)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV // REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGRUN( 0, KERNEL_FLASH_START, KERNEL_FLASH_SIZE, FLASH_CODE, NO, NO ); // Kernel Code SET_REGRUN( 0, KERNEL_FLASH_START, KERNEL_FLASH_SIZE, FLASH_CODE, NO, NO ); // Kernel Code
SET_REGION( 1, KERNEL_RAM_START, KERNEL_RAM_SIZE, SRAM, YES, NO ); // Kernel RAM SET_REGION( 1, MAIN_RAM_START, MAIN_RAM_SIZE, SRAM, YES, NO ); // Kernel RAM
SET_REGRUN( 2, COREAPP_FLASH_START, COREAPP_FLASH_SIZE, FLASH_CODE, NO, YES ); // CoreApp Code SET_REGRUN( 2, COREAPP_FLASH_START, COREAPP_FLASH_SIZE, FLASH_CODE, NO, YES ); // CoreApp Code
SET_REGION( 3, COREAPP_RAM1_START, COREAPP_RAM1_SIZE, SRAM, YES, YES ); // CoraApp RAM SET_REGION( 3, AUX1_RAM_START, AUX1_RAM_SIZE, SRAM, YES, YES ); // CoraApp RAM
#ifdef STM32U585xx #ifdef STM32U585xx
SET_REGION( 4, COREAPP_RAM2_START, COREAPP_RAM2_SIZE, SRAM, YES, YES ); // CoraAPP RAM2 SET_REGION( 4, AUX2_RAM_START, AUX2_RAM_SIZE, SRAM, YES, YES ); // CoraAPP RAM2
#else #else
DIS_REGION( 4 ); DIS_REGION( 4 );
#endif #endif
@ -246,17 +210,17 @@ static void mpu_init_fixed_regions(void) {
#if defined(FIRMWARE) #if defined(FIRMWARE)
// REGION ADDRESS SIZE TYPE WRITE UNPRIV // REGION ADDRESS SIZE TYPE WRITE UNPRIV
SET_REGION( 0, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_CODE, NO, NO ); SET_REGION( 0, FIRMWARE_START, FIRMWARE_MAXSIZE, FLASH_CODE, NO, NO );
SET_REGION( 1, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 1, MAIN_RAM_START, MAIN_RAM_SIZE, SRAM, YES, NO );
DIS_REGION( 2 ); DIS_REGION( 2 );
DIS_REGION( 3 ); DIS_REGION( 3 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 4, AUX1_RAM_START, AUX1_RAM_SIZE, SRAM, YES, NO );
#endif #endif
#if defined(TREZOR_PRODTEST) #if defined(TREZOR_PRODTEST)
SET_REGION( 0, FIRMWARE_START, 1024, FLASH_DATA, YES, NO ); SET_REGION( 0, FIRMWARE_START, 1024, FLASH_DATA, YES, NO );
SET_REGION( 1, FIRMWARE_START + 1024, FIRMWARE_MAXSIZE - 1024, FLASH_CODE, NO, NO ); SET_REGION( 1, FIRMWARE_START + 1024, FIRMWARE_MAXSIZE - 1024, FLASH_CODE, NO, NO );
SET_REGION( 2, MAIN_SRAM_START, MAIN_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 2, MAIN_RAM_START, MAIN_RAM_SIZE, SRAM, YES, NO );
DIS_REGION( 3 ); DIS_REGION( 3 );
SET_REGION( 4, AUX_SRAM_START, AUX_SRAM_SIZE, SRAM, YES, NO ); SET_REGION( 4, AUX1_RAM_START, AUX1_RAM_SIZE, SRAM, YES, NO );
#endif #endif
// Regions #6 and #7 are banked // Regions #6 and #7 are banked
@ -386,7 +350,7 @@ mpu_mode_t mpu_reconfig(mpu_mode_t mode) {
SET_REGION( 6, ASSETS_START, ASSETS_MAXSIZE, FLASH_DATA, NO, YES ); SET_REGION( 6, ASSETS_START, ASSETS_MAXSIZE, FLASH_DATA, NO, YES );
break; break;
case MPU_MODE_BOOTARGS: case MPU_MODE_BOOTARGS:
SET_REGRUN( 6, BOOTARGS_START, BOOTARGS_SIZE, SRAM, YES, NO ); SET_REGION( 6, BOOTARGS_START, BOOTARGS_SIZE, SRAM, YES, NO );
break; break;
default: default:
DIS_REGION( 6 ); DIS_REGION( 6 );
@ -401,7 +365,7 @@ mpu_mode_t mpu_reconfig(mpu_mode_t mode) {
// REGION ADDRESS SIZE TYPE WRITE UNPRIV // REGION ADDRESS SIZE TYPE WRITE UNPRIV
#ifdef KERNEL #ifdef KERNEL
case MPU_MODE_SAES: case MPU_MODE_SAES:
SET_REGION( 7, KERNEL_RAM_U_START, KERNEL_RAM_U_SIZE, SRAM, YES, YES ); // Unprivileged kernel SRAM SET_REGION( 7, SAES_RAM_START, SAES_RAM_SIZE, SRAM, YES, YES ); // Unprivileged kernel SRAM
break; break;
#endif #endif
case MPU_MODE_APP: case MPU_MODE_APP: