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694 lines
23 KiB
C
694 lines
23 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_hal_sram.c
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* @author MCD Application Team
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* @version V1.5.2
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* @date 22-September-2016
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* @brief SRAM HAL module driver.
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* This file provides a generic firmware to drive SRAM memories
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* mounted as external device.
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control SRAM memories. It uses the FMC layer functions to interface
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with SRAM devices.
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The following sequence should be followed to configure the FMC/FSMC to interface
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with SRAM/PSRAM memories:
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(#) Declare a SRAM_HandleTypeDef handle structure, for example:
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SRAM_HandleTypeDef hsram; and:
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(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
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values of the structure member.
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(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
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base register instance for NOR or SRAM device
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(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
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base register instance for NOR or SRAM extended mode
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(#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
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mode timings; for example:
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FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
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and fill its fields with the allowed values of the structure member.
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(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
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performs the following sequence:
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(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
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(##) Control register configuration using the FMC NORSRAM interface function
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FMC_NORSRAM_Init()
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(##) Timing register configuration using the FMC NORSRAM interface function
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FMC_NORSRAM_Timing_Init()
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(##) Extended mode Timing register configuration using the FMC NORSRAM interface function
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FMC_NORSRAM_Extended_Timing_Init()
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(##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
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(#) At this stage you can perform read/write accesses from/to the memory connected
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to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
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following APIs:
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(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
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(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
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(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
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HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
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(#) You can continuously monitor the SRAM device HAL state by calling the function
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HAL_SRAM_GetState()
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup SRAM SRAM
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* @brief SRAM driver modules
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* @{
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*/
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#ifdef HAL_SRAM_MODULE_ENABLED
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
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defined(STM32F412Vx) || defined(STM32F412Rx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
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* @{
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*/
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/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### SRAM Initialization and de_initialization functions #####
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==============================================================================
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[..] This section provides functions allowing to initialize/de-initialize
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the SRAM memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Performs the SRAM device initialization sequence
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param Timing: Pointer to SRAM control timing structure
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* @param ExtTiming: Pointer to SRAM extended mode timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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{
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/* Check the SRAM handle parameter */
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if(hsram == NULL)
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{
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return HAL_ERROR;
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}
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if(hsram->State == HAL_SRAM_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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hsram->Lock = HAL_UNLOCKED;
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/* Initialize the low level hardware (MSP) */
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HAL_SRAM_MspInit(hsram);
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}
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/* Initialize SRAM control Interface */
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FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
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/* Initialize SRAM timing Interface */
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FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
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/* Initialize SRAM extended mode timing Interface */
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FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
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/* Enable the NORSRAM device */
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__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
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return HAL_OK;
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}
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/**
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* @brief Performs the SRAM device De-initialization sequence.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
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{
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/* De-Initialize the low level hardware (MSP) */
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HAL_SRAM_MspDeInit(hsram);
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/* Configure the SRAM registers with their reset values */
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FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
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hsram->State = HAL_SRAM_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hsram);
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return HAL_OK;
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}
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/**
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* @brief SRAM MSP Init.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hsram);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief SRAM MSP DeInit.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hsram);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief DMA transfer complete callback.
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* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hdma);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
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*/
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}
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/**
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* @brief DMA transfer complete error callback.
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* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hdma);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### SRAM Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the SRAM memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Reads 8-bit buffer from SRAM memory.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress: Pointer to read start address
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* @param pDstBuffer: Pointer to destination buffer
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* @param BufferSize: Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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{
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__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Read data from memory */
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for(; BufferSize != 0U; BufferSize--)
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{
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*pDstBuffer = *(__IO uint8_t *)pSramAddress;
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pDstBuffer++;
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pSramAddress++;
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}
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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return HAL_OK;
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}
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/**
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* @brief Writes 8-bit buffer to SRAM memory.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress: Pointer to write start address
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* @param pSrcBuffer: Pointer to source buffer to write
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* @param BufferSize: Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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{
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__IO uint8_t * pSramAddress = (uint8_t *)pAddress;
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/* Check the SRAM controller state */
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if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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{
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return HAL_ERROR;
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}
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Write data to memory */
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for(; BufferSize != 0U; BufferSize--)
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{
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*(__IO uint8_t *)pSramAddress = *pSrcBuffer;
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pSrcBuffer++;
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pSramAddress++;
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}
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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return HAL_OK;
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}
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/**
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* @brief Reads 16-bit buffer from SRAM memory.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress: Pointer to read start address
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* @param pDstBuffer: Pointer to destination buffer
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* @param BufferSize: Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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{
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__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Read data from memory */
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for(; BufferSize != 0U; BufferSize--)
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{
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*pDstBuffer = *(__IO uint16_t *)pSramAddress;
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pDstBuffer++;
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pSramAddress++;
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}
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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return HAL_OK;
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}
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/**
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* @brief Writes 16-bit buffer to SRAM memory.
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* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress: Pointer to write start address
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* @param pSrcBuffer: Pointer to source buffer to write
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* @param BufferSize: Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
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{
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__IO uint16_t * pSramAddress = (uint16_t *)pAddress;
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/* Check the SRAM controller state */
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if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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{
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return HAL_ERROR;
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}
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Write data to memory */
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for(; BufferSize != 0U; BufferSize--)
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{
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*(__IO uint16_t *)pSramAddress = *pSrcBuffer;
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pSrcBuffer++;
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pSramAddress++;
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}
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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return HAL_OK;
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|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Reads 32-bit buffer from SRAM memory.
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @param pAddress: Pointer to read start address
|
||
|
* @param pDstBuffer: Pointer to destination buffer
|
||
|
* @param BufferSize: Size of the buffer to read from memory
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||
|
{
|
||
|
/* Process Locked */
|
||
|
__HAL_LOCK(hsram);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||
|
|
||
|
/* Read data from memory */
|
||
|
for(; BufferSize != 0U; BufferSize--)
|
||
|
{
|
||
|
*pDstBuffer = *(__IO uint32_t *)pAddress;
|
||
|
pDstBuffer++;
|
||
|
pAddress++;
|
||
|
}
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||
|
|
||
|
/* Process unlocked */
|
||
|
__HAL_UNLOCK(hsram);
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Writes 32-bit buffer to SRAM memory.
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @param pAddress: Pointer to write start address
|
||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||
|
* @param BufferSize: Size of the buffer to write to memory
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||
|
{
|
||
|
/* Check the SRAM controller state */
|
||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||
|
{
|
||
|
return HAL_ERROR;
|
||
|
}
|
||
|
|
||
|
/* Process Locked */
|
||
|
__HAL_LOCK(hsram);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||
|
|
||
|
/* Write data to memory */
|
||
|
for(; BufferSize != 0U; BufferSize--)
|
||
|
{
|
||
|
*(__IO uint32_t *)pAddress = *pSrcBuffer;
|
||
|
pSrcBuffer++;
|
||
|
pAddress++;
|
||
|
}
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||
|
|
||
|
/* Process unlocked */
|
||
|
__HAL_UNLOCK(hsram);
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Reads a Words data from the SRAM memory using DMA transfer.
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @param pAddress: Pointer to read start address
|
||
|
* @param pDstBuffer: Pointer to destination buffer
|
||
|
* @param BufferSize: Size of the buffer to read from memory
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||
|
{
|
||
|
/* Process Locked */
|
||
|
__HAL_LOCK(hsram);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||
|
|
||
|
/* Configure DMA user callbacks */
|
||
|
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||
|
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||
|
|
||
|
/* Enable the DMA Stream */
|
||
|
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||
|
|
||
|
/* Process unlocked */
|
||
|
__HAL_UNLOCK(hsram);
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @param pAddress: Pointer to write start address
|
||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||
|
* @param BufferSize: Size of the buffer to write to memory
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||
|
{
|
||
|
/* Check the SRAM controller state */
|
||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||
|
{
|
||
|
return HAL_ERROR;
|
||
|
}
|
||
|
|
||
|
/* Process Locked */
|
||
|
__HAL_LOCK(hsram);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||
|
|
||
|
/* Configure DMA user callbacks */
|
||
|
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||
|
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||
|
|
||
|
/* Enable the DMA Stream */
|
||
|
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||
|
|
||
|
/* Process unlocked */
|
||
|
__HAL_UNLOCK(hsram);
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
||
|
* @brief management functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### SRAM Control functions #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This subsection provides a set of functions allowing to control dynamically
|
||
|
the SRAM interface.
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Enables dynamically SRAM write operation.
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
||
|
{
|
||
|
/* Process Locked */
|
||
|
__HAL_LOCK(hsram);
|
||
|
|
||
|
/* Enable write operation */
|
||
|
FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||
|
|
||
|
/* Process unlocked */
|
||
|
__HAL_UNLOCK(hsram);
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Disables dynamically SRAM write operation.
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
||
|
{
|
||
|
/* Process Locked */
|
||
|
__HAL_LOCK(hsram);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||
|
|
||
|
/* Disable write operation */
|
||
|
FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
||
|
|
||
|
/* Update the SRAM controller state */
|
||
|
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
||
|
|
||
|
/* Process unlocked */
|
||
|
__HAL_UNLOCK(hsram);
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/** @defgroup SRAM_Exported_Functions_Group4 State functions
|
||
|
* @brief Peripheral State functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### SRAM State functions #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This subsection permits to get in run-time the status of the SRAM controller
|
||
|
and the data flow.
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Returns the SRAM controller state
|
||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||
|
* the configuration information for SRAM module.
|
||
|
* @retval HAL state
|
||
|
*/
|
||
|
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
||
|
{
|
||
|
return hsram->State;
|
||
|
}
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
||
|
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
|
||
|
STM32F412Vx || STM32F412Rx || STM32F412Cx */
|
||
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|