mirror of
https://github.com/trezor/trezor-firmware.git
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1027 lines
38 KiB
C
1027 lines
38 KiB
C
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/**
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******************************************************************************
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* @file stm32f4xx_ll_fsmc.c
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* @author MCD Application Team
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* @version V1.5.2
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* @date 22-September-2016
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* @brief FSMC Low Layer HAL module driver.
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*
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* This file provides firmware functions to manage the following
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* functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
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* + Initialization/de-initialization functions
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* + Peripheral Control functions
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* + Peripheral State functions
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*
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@verbatim
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==============================================================================
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##### FSMC peripheral features #####
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==============================================================================
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[..] The Flexible static memory controller (FSMC) includes two memory controllers:
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(+) The NOR/PSRAM memory controller
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(+) The NAND/PC Card memory controller
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[..] The FSMC functional block makes the interface with synchronous and asynchronous static
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memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
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(+) to translate AHB transactions into the appropriate external device protocol.
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(+) to meet the access time requirements of the external memory devices.
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[..] All external memories share the addresses, data and control signals with the controller.
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Each external device is accessed by means of a unique Chip Select. The FSMC performs
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only one access at a time to an external device.
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The main features of the FSMC controller are the following:
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(+) Interface with static-memory mapped devices including:
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(++) Static random access memory (SRAM).
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(++) Read-only memory (ROM).
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(++) NOR Flash memory/OneNAND Flash memory.
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(++) PSRAM (4 memory banks).
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(++) 16-bit PC Card compatible devices.
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(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
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data.
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(+) Independent Chip Select control for each memory bank.
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(+) Independent configuration for each memory bank.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup FSMC_LL FSMC Low Layer
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* @brief FSMC driver modules
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* @{
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*/
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#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup FSMC_LL_Private_Functions
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* @{
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*/
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/** @addtogroup FSMC_LL_NORSRAM
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* @brief NORSRAM Controller functions
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*
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@verbatim
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==============================================================================
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##### How to use NORSRAM device driver #####
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==============================================================================
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[..]
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This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
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to run the NORSRAM external devices.
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(+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
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(+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
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(+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
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(+) FSMC NORSRAM bank extended timing configuration using the function
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FSMC_NORSRAM_Extended_Timing_Init()
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(+) FSMC NORSRAM bank enable/disable write operation using the functions
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FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
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@endverbatim
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* @{
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*/
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/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### Initialization and de_initialization functions #####
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==============================================================================
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[..]
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This section provides functions allowing to:
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(+) Initialize and configure the FSMC NORSRAM interface
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(+) De-initialize the FSMC NORSRAM interface
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(+) Configure the FSMC clock and associated GPIOs
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@endverbatim
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* @{
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*/
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/**
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* @brief Initialize the FSMC_NORSRAM device according to the specified
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* control parameters in the FSMC_NORSRAM_InitTypeDef
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* @param Device: Pointer to NORSRAM device instance
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* @param Init: Pointer to NORSRAM Initialization structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
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{
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uint32_t tmpr = 0U;
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/* Check the parameters */
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assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
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assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
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assert_param(IS_FSMC_MUX(Init->DataAddressMux));
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assert_param(IS_FSMC_MEMORY(Init->MemoryType));
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assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
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assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
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assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
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assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
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assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
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assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
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assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
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assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
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assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
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#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
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assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
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assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
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#endif /* STM32F412Zx || TM32F412Vx */
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/* Get the BTCR register value */
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tmpr = Device->BTCR[Init->NSBank];
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
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WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
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tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
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FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
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FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
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FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
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FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW));
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/* Set NORSRAM device control parameters */
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tmpr |= (uint32_t)(Init->DataAddressMux |\
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Init->MemoryType |\
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Init->MemoryDataWidth |\
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Init->BurstAccessMode |\
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Init->WaitSignalPolarity |\
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Init->WrapMode |\
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Init->WaitSignalActive |\
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Init->WriteOperation |\
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Init->WaitSignal |\
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Init->ExtendedMode |\
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Init->AsynchronousWait |\
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Init->PageSize |\
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Init->WriteBurst
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);
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#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
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/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
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WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */
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tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
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FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
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FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \
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FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \
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FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \
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FSMC_BCR1_WFDIS));
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/* Set NORSRAM device control parameters */
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tmpr |= (uint32_t)(Init->DataAddressMux |\
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Init->MemoryType |\
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Init->MemoryDataWidth |\
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Init->BurstAccessMode |\
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Init->WaitSignalPolarity |\
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Init->WaitSignalActive |\
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Init->WriteOperation |\
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Init->WaitSignal |\
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Init->ExtendedMode |\
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Init->AsynchronousWait |\
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Init->WriteBurst |\
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Init->ContinuousClock |\
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Init->PageSize |\
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Init->WriteFifo);
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
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{
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tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
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}
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Device->BTCR[Init->NSBank] = tmpr;
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#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
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/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
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if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
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{
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Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
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}
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if(Init->NSBank != FSMC_NORSRAM_BANK1)
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{
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Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
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}
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#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
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return HAL_OK;
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}
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/**
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* @brief DeInitialize the FSMC_NORSRAM peripheral
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* @param Device: Pointer to NORSRAM device instance
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* @param ExDevice: Pointer to NORSRAM extended mode device instance
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* @param Bank: NORSRAM bank number
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* @retval HAL status
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*/
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HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
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{
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/* Check the parameters */
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assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
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assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
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assert_param(IS_FSMC_NORSRAM_BANK(Bank));
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/* Disable the FSMC_NORSRAM device */
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__FSMC_NORSRAM_DISABLE(Device, Bank);
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/* De-initialize the FSMC_NORSRAM device */
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/* FSMC_NORSRAM_BANK1 */
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if(Bank == FSMC_NORSRAM_BANK1)
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{
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Device->BTCR[Bank] = 0x000030DBU;
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}
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/* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
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else
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{
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Device->BTCR[Bank] = 0x000030D2U;
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}
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Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
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ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
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return HAL_OK;
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}
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/**
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* @brief Initialize the FSMC_NORSRAM Timing according to the specified
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* parameters in the FSMC_NORSRAM_TimingTypeDef
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* @param Device: Pointer to NORSRAM device instance
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* @param Timing: Pointer to NORSRAM Timing structure
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* @param Bank: NORSRAM bank number
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* @retval HAL status
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*/
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HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
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{
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uint32_t tmpr = 0U;
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/* Check the parameters */
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assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
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assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
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assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
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assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
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assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
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assert_param(IS_FSMC_NORSRAM_BANK(Bank));
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/* Get the BTCR register value */
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tmpr = Device->BTCR[Bank + 1U];
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/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
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FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
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FSMC_BTR1_ACCMOD));
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/* Set FSMC_NORSRAM device timing parameters */
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tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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((Timing->AddressHoldTime) << 4U) |\
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((Timing->DataSetupTime) << 8U) |\
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((Timing->BusTurnAroundDuration) << 16U) |\
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(((Timing->CLKDivision)-1U) << 20U) |\
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(((Timing->DataLatency)-2U) << 24U) |\
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(Timing->AccessMode));
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Device->BTCR[Bank + 1] = tmpr;
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#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
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/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
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if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
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{
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tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0FU) << 20U));
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tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
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Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
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}
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#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
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return HAL_OK;
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}
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/**
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* @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
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||
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* parameters in the FSMC_NORSRAM_TimingTypeDef
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* @param Device: Pointer to NORSRAM device instance
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||
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* @param Timing: Pointer to NORSRAM Timing structure
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* @param Bank: NORSRAM bank number
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* @retval HAL status
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*/
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HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
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||
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{
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uint32_t tmpr = 0U;
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||
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/* Check the parameters */
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||
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assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
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||
|
|
||
|
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
|
||
|
if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
|
||
|
{
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
|
||
|
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
|
||
|
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
|
||
|
assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
|
||
|
assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
|
||
|
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
|
||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||
|
|
||
|
/* Get the BWTR register value */
|
||
|
tmpr = Device->BWTR[Bank];
|
||
|
|
||
|
/* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
|
||
|
FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
|
||
|
|
||
|
tmpr |= (uint32_t)(Timing->AddressSetupTime |\
|
||
|
((Timing->AddressHoldTime) << 4U) |\
|
||
|
((Timing->DataSetupTime) << 8U) |\
|
||
|
((Timing->BusTurnAroundDuration) << 16U) |\
|
||
|
(Timing->AccessMode));
|
||
|
|
||
|
Device->BWTR[Bank] = tmpr;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
Device->BWTR[Bank] = 0x0FFFFFFFU;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
|
||
|
* @brief management functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### FSMC_NORSRAM Control functions #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This subsection provides a set of functions allowing to control dynamically
|
||
|
the FSMC NORSRAM interface.
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Enables dynamically FSMC_NORSRAM write operation.
|
||
|
* @param Device: Pointer to NORSRAM device instance
|
||
|
* @param Bank: NORSRAM bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
|
||
|
{
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||
|
|
||
|
/* Enable write operation */
|
||
|
Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Disables dynamically FSMC_NORSRAM write operation.
|
||
|
* @param Device: Pointer to NORSRAM device instance
|
||
|
* @param Bank: NORSRAM bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
|
||
|
{
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||
|
|
||
|
/* Disable write operation */
|
||
|
Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
|
||
|
/** @addtogroup FSMC_LL_NAND
|
||
|
* @brief NAND Controller functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### How to use NAND device driver #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This driver contains a set of APIs to interface with the FSMC NAND banks in order
|
||
|
to run the NAND external devices.
|
||
|
|
||
|
(+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
|
||
|
(+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
|
||
|
(+) FSMC NAND bank common space timing configuration using the function
|
||
|
FSMC_NAND_CommonSpace_Timing_Init()
|
||
|
(+) FSMC NAND bank attribute space timing configuration using the function
|
||
|
FSMC_NAND_AttributeSpace_Timing_Init()
|
||
|
(+) FSMC NAND bank enable/disable ECC correction feature using the functions
|
||
|
FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
|
||
|
(+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
|
||
|
* @brief Initialization and Configuration functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### Initialization and de_initialization functions #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This section provides functions allowing to:
|
||
|
(+) Initialize and configure the FSMC NAND interface
|
||
|
(+) De-initialize the FSMC NAND interface
|
||
|
(+) Configure the FSMC clock and associated GPIOs
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_NAND device according to the specified
|
||
|
* control parameters in the FSMC_NAND_HandleTypeDef
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param Init: Pointer to NAND Initialization structure
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
|
||
|
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
||
|
assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
|
||
|
assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
|
||
|
assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
|
||
|
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
||
|
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
||
|
|
||
|
if(Init->NandBank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* Get the NAND bank 2 register value */
|
||
|
tmpr = Device->PCR2;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* Get the NAND bank 3 register value */
|
||
|
tmpr = Device->PCR3;
|
||
|
}
|
||
|
|
||
|
/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
|
||
|
FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
|
||
|
FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
|
||
|
|
||
|
/* Set NAND device control parameters */
|
||
|
tmpr |= (uint32_t)(Init->Waitfeature |\
|
||
|
FSMC_PCR_MEMORY_TYPE_NAND |\
|
||
|
Init->MemoryDataWidth |\
|
||
|
Init->EccComputation |\
|
||
|
Init->ECCPageSize |\
|
||
|
((Init->TCLRSetupTime) << 9U) |\
|
||
|
((Init->TARSetupTime) << 13U));
|
||
|
|
||
|
if(Init->NandBank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* NAND bank 2 registers configuration */
|
||
|
Device->PCR2 = tmpr;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* NAND bank 3 registers configuration */
|
||
|
Device->PCR3 = tmpr;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_NAND Common space Timing according to the specified
|
||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param Timing: Pointer to NAND timing structure
|
||
|
* @param Bank: NAND bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||
|
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* Get the NAND bank 2 register value */
|
||
|
tmpr = Device->PMEM2;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* Get the NAND bank 3 register value */
|
||
|
tmpr = Device->PMEM3;
|
||
|
}
|
||
|
|
||
|
/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
|
||
|
FSMC_PMEM2_MEMHIZ2));
|
||
|
|
||
|
/* Set FSMC_NAND device timing parameters */
|
||
|
tmpr |= (uint32_t)(Timing->SetupTime |\
|
||
|
((Timing->WaitSetupTime) << 8U) |\
|
||
|
((Timing->HoldSetupTime) << 16U) |\
|
||
|
((Timing->HiZSetupTime) << 24U)
|
||
|
);
|
||
|
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* NAND bank 2 registers configuration */
|
||
|
Device->PMEM2 = tmpr;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* NAND bank 3 registers configuration */
|
||
|
Device->PMEM3 = tmpr;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
|
||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param Timing: Pointer to NAND timing structure
|
||
|
* @param Bank: NAND bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||
|
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* Get the NAND bank 2 register value */
|
||
|
tmpr = Device->PATT2;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* Get the NAND bank 3 register value */
|
||
|
tmpr = Device->PATT3;
|
||
|
}
|
||
|
|
||
|
/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
|
||
|
FSMC_PATT2_ATTHIZ2));
|
||
|
|
||
|
/* Set FSMC_NAND device timing parameters */
|
||
|
tmpr |= (uint32_t)(Timing->SetupTime |\
|
||
|
((Timing->WaitSetupTime) << 8U) |\
|
||
|
((Timing->HoldSetupTime) << 16U) |\
|
||
|
((Timing->HiZSetupTime) << 24U)
|
||
|
);
|
||
|
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* NAND bank 2 registers configuration */
|
||
|
Device->PATT2 = tmpr;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* NAND bank 3 registers configuration */
|
||
|
Device->PATT3 = tmpr;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief DeInitializes the FSMC_NAND device
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param Bank: NAND bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
||
|
{
|
||
|
/* Disable the NAND Bank */
|
||
|
__FSMC_NAND_DISABLE(Device, Bank);
|
||
|
|
||
|
/* De-initialize the NAND Bank */
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* Set the FSMC_NAND_BANK2 registers to their reset values */
|
||
|
Device->PCR2 = 0x00000018U;
|
||
|
Device->SR2 = 0x00000040U;
|
||
|
Device->PMEM2 = 0xFCFCFCFCU;
|
||
|
Device->PATT2 = 0xFCFCFCFCU;
|
||
|
}
|
||
|
/* FSMC_Bank3_NAND */
|
||
|
else
|
||
|
{
|
||
|
/* Set the FSMC_NAND_BANK3 registers to their reset values */
|
||
|
Device->PCR3 = 0x00000018U;
|
||
|
Device->SR3 = 0x00000040U;
|
||
|
Device->PMEM3 = 0xFCFCFCFCU;
|
||
|
Device->PATT3 = 0xFCFCFCFCU;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
|
||
|
* @brief management functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### FSMC_NAND Control functions #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This subsection provides a set of functions allowing to control dynamically
|
||
|
the FSMC NAND interface.
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Enables dynamically FSMC_NAND ECC feature.
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param Bank: NAND bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
||
|
{
|
||
|
/* Enable ECC feature */
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
Device->PCR2 |= FSMC_PCR2_ECCEN;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
Device->PCR3 |= FSMC_PCR3_ECCEN;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Disables dynamically FSMC_NAND ECC feature.
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param Bank: NAND bank number
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
||
|
{
|
||
|
/* Disable ECC feature */
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
Device->PCR2 &= ~FSMC_PCR2_ECCEN;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
Device->PCR3 &= ~FSMC_PCR3_ECCEN;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Disables dynamically FSMC_NAND ECC feature.
|
||
|
* @param Device: Pointer to NAND device instance
|
||
|
* @param ECCval: Pointer to ECC value
|
||
|
* @param Bank: NAND bank number
|
||
|
* @param Timeout: Timeout wait value
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
|
||
|
{
|
||
|
uint32_t tickstart = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||
|
|
||
|
/* Get tick */
|
||
|
tickstart = HAL_GetTick();
|
||
|
|
||
|
/* Wait until FIFO is empty */
|
||
|
while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
|
||
|
{
|
||
|
/* Check for the Timeout */
|
||
|
if(Timeout != HAL_MAX_DELAY)
|
||
|
{
|
||
|
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
|
||
|
{
|
||
|
return HAL_TIMEOUT;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if(Bank == FSMC_NAND_BANK2)
|
||
|
{
|
||
|
/* Get the ECCR2 register value */
|
||
|
*ECCval = (uint32_t)Device->ECCR2;
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
/* Get the ECCR3 register value */
|
||
|
*ECCval = (uint32_t)Device->ECCR3;
|
||
|
}
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/** @addtogroup FSMC_LL_PCCARD
|
||
|
* @brief PCCARD Controller functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### How to use PCCARD device driver #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
|
||
|
to run the PCCARD/compact flash external devices.
|
||
|
|
||
|
(+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
|
||
|
(+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
|
||
|
(+) FSMC PCCARD bank common space timing configuration using the function
|
||
|
FSMC_PCCARD_CommonSpace_Timing_Init()
|
||
|
(+) FSMC PCCARD bank attribute space timing configuration using the function
|
||
|
FSMC_PCCARD_AttributeSpace_Timing_Init()
|
||
|
(+) FSMC PCCARD bank IO space timing configuration using the function
|
||
|
FSMC_PCCARD_IOSpace_Timing_Init()
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
|
||
|
* @brief Initialization and Configuration functions
|
||
|
*
|
||
|
@verbatim
|
||
|
==============================================================================
|
||
|
##### Initialization and de_initialization functions #####
|
||
|
==============================================================================
|
||
|
[..]
|
||
|
This section provides functions allowing to:
|
||
|
(+) Initialize and configure the FSMC PCCARD interface
|
||
|
(+) De-initialize the FSMC PCCARD interface
|
||
|
(+) Configure the FSMC clock and associated GPIOs
|
||
|
|
||
|
@endverbatim
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_PCCARD device according to the specified
|
||
|
* control parameters in the FSMC_PCCARD_HandleTypeDef
|
||
|
* @param Device: Pointer to PCCARD device instance
|
||
|
* @param Init: Pointer to PCCARD Initialization structure
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
||
|
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
||
|
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
||
|
|
||
|
/* Get PCCARD control register value */
|
||
|
tmpr = Device->PCR4;
|
||
|
|
||
|
/* Clear TAR, TCLR, PWAITEN and PWID bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
|
||
|
FSMC_PCR4_PWID));
|
||
|
|
||
|
/* Set FSMC_PCCARD device control parameters */
|
||
|
tmpr |= (uint32_t)(Init->Waitfeature |\
|
||
|
FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
|
||
|
(Init->TCLRSetupTime << 9U) |\
|
||
|
(Init->TARSetupTime << 13U));
|
||
|
|
||
|
Device->PCR4 = tmpr;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
|
||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||
|
* @param Device: Pointer to PCCARD device instance
|
||
|
* @param Timing: Pointer to PCCARD timing structure
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||
|
|
||
|
/* Get PCCARD common space timing register value */
|
||
|
tmpr = Device->PMEM4;
|
||
|
|
||
|
/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
|
||
|
FSMC_PMEM4_MEMHIZ4));
|
||
|
/* Set PCCARD timing parameters */
|
||
|
tmpr |= (uint32_t)((Timing->SetupTime |\
|
||
|
((Timing->WaitSetupTime) << 8U) |\
|
||
|
(Timing->HoldSetupTime) << 16U) |\
|
||
|
((Timing->HiZSetupTime) << 24U));
|
||
|
|
||
|
Device->PMEM4 = tmpr;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
|
||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||
|
* @param Device: Pointer to PCCARD device instance
|
||
|
* @param Timing: Pointer to PCCARD timing structure
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||
|
|
||
|
/* Get PCCARD timing parameters */
|
||
|
tmpr = Device->PATT4;
|
||
|
|
||
|
/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
|
||
|
FSMC_PATT4_ATTHIZ4));
|
||
|
|
||
|
/* Set PCCARD timing parameters */
|
||
|
tmpr |= (uint32_t)(Timing->SetupTime |\
|
||
|
((Timing->WaitSetupTime) << 8U) |\
|
||
|
((Timing->HoldSetupTime) << 16U) |\
|
||
|
((Timing->HiZSetupTime) << 24U));
|
||
|
Device->PATT4 = tmpr;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
|
||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||
|
* @param Device: Pointer to PCCARD device instance
|
||
|
* @param Timing: Pointer to PCCARD timing structure
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||
|
{
|
||
|
uint32_t tmpr = 0U;
|
||
|
|
||
|
/* Check the parameters */
|
||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||
|
|
||
|
/* Get FSMC_PCCARD device timing parameters */
|
||
|
tmpr = Device->PIO4;
|
||
|
|
||
|
/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
|
||
|
tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
|
||
|
FSMC_PIO4_IOHIZ4));
|
||
|
|
||
|
/* Set FSMC_PCCARD device timing parameters */
|
||
|
tmpr |= (uint32_t)(Timing->SetupTime |\
|
||
|
((Timing->WaitSetupTime) << 8U) |\
|
||
|
((Timing->HoldSetupTime) << 16U) |\
|
||
|
((Timing->HiZSetupTime) << 24U));
|
||
|
|
||
|
Device->PIO4 = tmpr;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief DeInitializes the FSMC_PCCARD device
|
||
|
* @param Device: Pointer to PCCARD device instance
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
|
||
|
{
|
||
|
/* Disable the FSMC_PCCARD device */
|
||
|
__FSMC_PCCARD_DISABLE(Device);
|
||
|
|
||
|
/* De-initialize the FSMC_PCCARD device */
|
||
|
Device->PCR4 = 0x00000018U;
|
||
|
Device->SR4 = 0x00000000U;
|
||
|
Device->PMEM4 = 0xFCFCFCFCU;
|
||
|
Device->PATT4 = 0xFCFCFCFCU;
|
||
|
Device->PIO4 = 0xFCFCFCFCU;
|
||
|
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
|
||
|
#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|