2017-10-11 21:53:29 +00:00
|
|
|
#include STM32_HAL_H
|
|
|
|
|
2017-10-14 10:44:36 +00:00
|
|
|
#include "lowlevel.h"
|
|
|
|
|
2017-10-11 21:53:29 +00:00
|
|
|
#define WANTED_WRP (OB_WRP_SECTOR_0 | OB_WRP_SECTOR_1 | OB_WRP_SECTOR_2)
|
|
|
|
#define WANTED_RDP (OB_RDP_LEVEL_2)
|
|
|
|
#define WANTED_BOR (OB_BOR_LEVEL3)
|
|
|
|
|
|
|
|
void flash_set_option_bytes(void)
|
|
|
|
{
|
|
|
|
FLASH_OBProgramInitTypeDef opts;
|
|
|
|
|
2017-10-20 12:42:51 +00:00
|
|
|
for(;;) {
|
2017-10-19 23:06:58 +00:00
|
|
|
HAL_FLASHEx_OBGetConfig(&opts);
|
2017-10-11 21:53:29 +00:00
|
|
|
|
2017-10-19 23:06:58 +00:00
|
|
|
opts.OptionType = 0;
|
2017-10-11 21:53:29 +00:00
|
|
|
|
2017-10-19 23:06:58 +00:00
|
|
|
if (opts.WRPSector != WANTED_WRP) {
|
|
|
|
opts.OptionType |= OPTIONBYTE_WRP;
|
|
|
|
opts.WRPState = OB_WRPSTATE_ENABLE;
|
|
|
|
opts.WRPSector = WANTED_WRP;
|
|
|
|
opts.Banks = FLASH_BANK_1;
|
|
|
|
}
|
2017-10-11 21:53:29 +00:00
|
|
|
|
2017-10-19 23:06:58 +00:00
|
|
|
if (opts.RDPLevel != WANTED_RDP) {
|
|
|
|
opts.OptionType |= OPTIONBYTE_RDP;
|
|
|
|
opts.RDPLevel = WANTED_RDP;
|
|
|
|
}
|
2017-10-11 21:53:29 +00:00
|
|
|
|
2017-10-19 23:06:58 +00:00
|
|
|
if (opts.BORLevel != WANTED_BOR) {
|
|
|
|
opts.OptionType |= OPTIONBYTE_BOR;
|
|
|
|
opts.BORLevel = WANTED_BOR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (opts.OptionType == 0) {
|
|
|
|
break; // protections are configured
|
|
|
|
}
|
|
|
|
|
2017-10-20 12:42:51 +00:00
|
|
|
// attempt to lock down the boardloader sectors
|
2017-10-11 21:53:29 +00:00
|
|
|
HAL_FLASHEx_OBProgram(&opts);
|
|
|
|
}
|
|
|
|
}
|
2017-10-14 10:44:36 +00:00
|
|
|
|
|
|
|
bool flash_check_option_bytes(void)
|
|
|
|
{
|
|
|
|
return
|
|
|
|
((FLASH->OPTCR & FLASH_OPTCR_nWRP) == (FLASH_OPTCR_nWRP_0 | FLASH_OPTCR_nWRP_1 | FLASH_OPTCR_nWRP_2)) &&
|
|
|
|
((FLASH->OPTCR & FLASH_OPTCR_RDP) == FLASH_OPTCR_RDP_2) &&
|
|
|
|
((FLASH->OPTCR & FLASH_OPTCR_BOR_LEV) == (FLASH_OPTCR_BOR_LEV_0 | FLASH_OPTCR_BOR_LEV_1));
|
|
|
|
}
|
2017-10-17 09:44:53 +00:00
|
|
|
|
|
|
|
void periph_init(void)
|
|
|
|
{
|
|
|
|
// STM32F4xx HAL library initialization:
|
|
|
|
// - configure the Flash prefetch, instruction and data caches
|
|
|
|
// - configure the Systick to generate an interrupt each 1 msec
|
|
|
|
// - set NVIC Group Priority to 4
|
|
|
|
// - global MSP (MCU Support Package) initialization
|
|
|
|
HAL_Init();
|
|
|
|
|
|
|
|
// Enable GPIO clocks
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
|
|
|
2017-10-22 15:44:06 +00:00
|
|
|
// enable the PVD (programmable voltage detector).
|
|
|
|
// select the "2.7V" threshold (level 5). the typical electrical
|
|
|
|
// characteristic values are similar to BOR level 3.
|
|
|
|
// this detector will be active regardless of the
|
|
|
|
// flash option byte BOR setting.
|
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
|
PWR_PVDTypeDef pvd_config;
|
|
|
|
pvd_config.PVDLevel = PWR_PVDLEVEL_5;
|
|
|
|
pvd_config.Mode = PWR_PVD_MODE_IT_RISING_FALLING;
|
|
|
|
HAL_PWR_ConfigPVD(&pvd_config);
|
|
|
|
HAL_PWR_EnablePVD();
|
|
|
|
NVIC_EnableIRQ(PVD_IRQn);
|
|
|
|
|
2017-10-17 09:44:53 +00:00
|
|
|
// Clear the reset flags
|
|
|
|
RCC->CSR |= RCC_CSR_RMVF;
|
|
|
|
}
|