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124 lines
3.1 KiB
124 lines
3.1 KiB
![]()
1 year ago
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/* TREZORv2 firmware linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C050000, LENGTH = 3648K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 768K - (0x100 + 4)
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BOOT_ARGS (wal) : ORIGIN = 0x300BFEFC, LENGTH = (0x100 + 4)
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SRAM2 (wal) : ORIGIN = 0x300C0000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x300D0000, LENGTH = 832K
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SRAM5 (wal) : ORIGIN = 0x301A0000, LENGTH = 832K
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SRAM6 (wal) : ORIGIN = 0x30270000, LENGTH = 0
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2) + 0x100;
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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sensitive_lma = LOADADDR(.sensitive);
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sensitive_vma = ADDR(.sensitive);
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sensitive_size = SIZEOF(.sensitive);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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g_boot_args = (boot_args_start + 4);
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g_boot_flag= boot_args_start;
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
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_flash_start = ORIGIN(FLASH);
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_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
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_heap_start = ADDR(.heap);
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_heap_end = ADDR(.heap) + SIZEOF(.heap);
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SECTIONS {
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.vendorheader : ALIGN(4) {
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KEEP(*(.vendorheader))
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} >FLASH AT>FLASH
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(4);
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KEEP(*(.bootloader));
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*(.bootloader*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.data_ccm : ALIGN(4) {
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*(.no_dma_buffers*);
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. = ALIGN(4);
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} >SRAM1
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.heap : ALIGN(4) {
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. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
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. = ABSOLUTE(sram1_end); /* this explicitly sets the end of the heap */
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} >SRAM1
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.stack : ALIGN(8) {
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. = 16K + 0x100; /* Exactly 16K allocated for stack. Overflow causes MemManage fault (when using MPU). */
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} >SRAM2
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.sensitive : ALIGN(512) {
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*(.sensitive*);
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. = ALIGN(512);
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} >SRAM2 AT>FLASH
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.fb1 : ALIGN(4) {
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__fb_start = .;
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*(.fb1*);
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*(.gfxmmu_table*);
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*(.framebuffer_select*);
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. = ALIGN(4);
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} >SRAM3
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.fb2 : ALIGN(4) {
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*(.fb2*);
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__fb_end = .;
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. = ALIGN(4);
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} >SRAM5
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}
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