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Merge pull request #25 from fuzhli/segmented_address_fix

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Segmented address presentation fix
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0xAX 2015-01-05 18:03:48 +06:00
commit e8e180dbe8
2 changed files with 3 additions and 2 deletions
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1
contributors.md
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@ -8,3 +8,4 @@ Thank you to all contributors:
* [Chris Costes](https://github.com/ccostes) * [Chris Costes](https://github.com/ccostes)
* [nathansoz](https://github.com/nathansoz) * [nathansoz](https://github.com/nathansoz)
* [RubanDeventhiran](https://github.com/RubanDeventhiran) * [RubanDeventhiran](https://github.com/RubanDeventhiran)
* [fuzhli](https://github.com/fuzhli)

4
linux-bootstrap-1.md
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@ -61,13 +61,13 @@ Ok, now we know about real mode and memory addressing, let's get back to registe
`CS` register has two parts: the visible segment selector and hidden base address. We know predefined `CS` base and `IP` value, so our logical address will be: `CS` register has two parts: the visible segment selector and hidden base address. We know predefined `CS` base and `IP` value, so our logical address will be:
``` ```
0xffff0000:0xfff0 0x0ffff000:0xfff0
``` ```
which we can translate to the physical address: which we can translate to the physical address:
```python ```python
>>> hex((0xffff000 << 4) + 0xfff0) >>> hex((0x0ffff000 << 4) + 0xfff0)
'0xfffffff0' '0xfffffff0'
``` ```