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9793 Commits

Author SHA1 Message Date
Gabriele Gristina
bcc351068f
Metal Backend:
- added support to 2D/3D Compute
- improved compute workloads calculation
Makefile:
- updated MACOSX_DEPLOYMENT_TARGET to 15.0
Unit tests:
- updated install_modules.sh with Crypt::Argon2

Argon2 start works with Apple Metal
2025-07-03 22:06:32 +02:00
Jens Steube
b9b20c3340
Merge pull request #4286 from matrix/metal_3d
support 2D/3D kernel invocation with Metal
2025-07-03 10:36:28 +02:00
Gabriele Gristina
4d39f881fd
support 2D/3D kernel invocation with Metal 2025-07-03 10:26:51 +02:00
Jens Steube
e8cf8bd146 Fix OpenCL spawning unnecessary work-item due to redundant multiplication in new OPTS_TYPE_THREAD_MULTI_DISABLE mode.
Prepare Metal section in run_kernel() for 2D kernel invocation related to new salt->salt_dimy variable.
Move reusable Argon2 module code into separate file argon2_commit.c, similar to scrypt_commit.c, and update headers.
Update existing hash mode 34000 to use argon2_commit.c.
2025-07-03 08:10:30 +02:00
Jens Steube
2e185b5450
Merge pull request #4285 from matrix/argon2_metal
porting Argon2 to metal and fix OpenCL bug on hc__shfl
2025-07-02 22:44:50 +02:00
Gabriele Gristina
8a91fccefd
porting to metal and fix OpenCL bug on hc__shfl 2025-07-02 22:19:39 +02:00
Jens Steube
d9918d7e44 Add Argon2 support for OpenCL and HIP
=====================================

This patch modifies the existing Argon2 plugin, which was initially
designed to work only with CUDA. Supporting OpenCL and HIP required
broader architectural changes.

1. The tmps[] structure no longer holds the "large buffer". This
buffer stored the scratch areas for all password candidates in one
chunk. But we do not need to hold scratch areas for all candidates
simultaneously. All we need to do is hold chunks large enough
per password.

To simplify logic, the buffer is not divided by password count, but
divided by four, which fits within the "1/4 global memory" limit on
some OpenCL runtimes.

Hashcat already had logic to support this, but the buffer needed to be
moved to a different buffer type. It has now been relocated from the
"tmp buffer" to the "extra tmp buffer", following the same strategy
used in newer SCRYPT plugins.

This improves handling across several subcomponents:

  - Hashcat backend divides into four asymmetric buffers, hence the
    name "4-buffer strategy"
  - If the candidate count isn't divisible by 4, leftover candidates are
    assigned to the first (and possibly second and third) buffer
  - No code in the plugin is required, as this was designed for exactly
    such cases where future algorithms require a lot of memory
  - Plugin was rewritten to report the size needed in
    module_extra_tmp_size(), which triggers the "4-buffer" strategy
  - The split is not even, but each part is large enough to hold
    a multiple of a full scratch buffer for a password
  - The kernel code in m34000_init/loop/comp now uses a code block
    that finds its buffer by doing "group_id % 4"
  - Prevents the need to over-allocate memory to avoid OOB access
  - The original "tmps buffer" now holds a small dummy state buffer

2. Replaced warp shuffle instruction

The instruction __shfl_sync() is not available in runtimes
other than CUDA. Some have alternatives, some do not.

To prevent branching per backend runtime, the new general macro
hc__shfl_sync() replaces all calls to __shfl_sync().
This allows us to implement runtime-specific solutions and
take effect at compile time to prevent regressions.

- CUDA:
  We simply map to the original __shfl_sync()

- HIP:
  We map to shfl(), a built-in intrinsic. This instruction doesn't
  support masks like __shfl_sync() does, but masks are not needed
  in Argon2 anyway. It requires an additional parameter, the wavefront
  size. This is natively 64, but we hardcode this to 32 so it aligns
  with NVIDIA's warp size.

- OpenCL:
  - AMD: We have access to the instruction __builtin_amdgcn_ds_bpermute().
    This instruction only supports 32-bit integers, requiring us to
    pack and unpack the 64-bit values manually
  - NVIDIA: We use inline assembly with "shfl.sync.idx.b32". Same as
    with AMD, we need to pack and unpack 32-bit integers. The 64-bit
    support in CUDA is just overloaded and internally does the same thing.
  - Others: We use a shared memory pool and combine it with a barrier.
    This LOCAL_VK pool must be sized at compile time and transported to
    the Argon2 code in "inc_hash_argon2.cl". This required changing all
    function declarations that use shuffles slightly.

Unlock full threading for init and comp kernels
===============================================

This is implemented using a new flag:
  OPTS_TYPE_THREAD_MULTI_DISABLE

Behavior is similar to:
  OPTS_TYPE_MP_MULTI_DISABLE

It simply disables the multiplier normally applied to password batch size.

But attention, this change completely unbinds this effect from the
real threads spawned on the compute device. If the thread count is not
set to 1 in the plugin, it will start autotuning it.

In the case of Argon2, we hard-code it to 32 instead, which also changes
how "warp size" was used in the original implementation, and which is not
compatible with HIP and/or OpenCL. However, we need to maintain this thread
size to utilize warp shuffle and its alternatives in other runtimes.

Benefits:

  - Enables full threading for init and comp kernels (1667 H/s to 1722 H/s)
  - Allows future algorithms to enable parallel processing of single
    password candidates, if supported

Plugin changes:

  - Removed the "hack" where thread count = 1 disabled the multiplier
  - Removed per-device warp count detection code and struct changes
  - Removed warp handling and "num_elements / thread_count" division in
    the run_kernel() function

Simplified autotune logic for Argon2
====================================

The goal is to calculate the maximum number of password candidates that
can run in parallel, constrained only by device memory.

  - Removed all code related to Argon2 from autotune
  - Implemented in "module_extra_tuningdb_block()" (like SCRYPT)
  - We create a tuningdb entry at runtime!
  - Still allows override via tuningdb or CLI
  - Considers register spilling (read at startup)
  - Prevents global-to-host memory swap performance issues

Add Argon2I and ArgonD support
==============================

The kernel prepared from NFI already had support for the different Argon
types. No change was needed.

To support the other Argon2 types, the tokenizer had to be improved to
support a variety of different signatures in the same hash-mode.

Bugfixes
========

- Fixed missing entries in "switch_buffer_by_offset_8x4_le_S()"
- Fixed benchmark hash misdetection for scrypt. This was due to
  outdated logic used in scrypt to detect whether the plugin was
  called from a benchmark session or a regular one
- Fixed a bug in "module_hash_encode()" where Base64 padding '=' was
  retained
- Fixed missing "GLOBAL_AS" / "PRIVATE_AS" casts for OpenCL
- Fixed compiler warnings (e.g., "index_u32x4()", "get_group_id()")
  by adding return values
- Fixed a bug in token.len_max[6], which was allowing decoding
  of a 256-byte data into a 16-byte buffer (digest)

Other improvements
==================

- Added unit test module for automated testing
- Added support to the tokenizer to allow multiple signatures.
  Leave out TOKEN_ATTR_FIXED_LENGTH to enable this in your plugins
- Updated "hc_umulhi()", also exists for HIP
- Renamed "gid" to "bid" when using "get_group_id()" for clarity
- Removed "#ifdef IS_CUDA" as all backends are now supported
- Removed deprecated "OPTS_TYPE_MAXIMUM_ACCEL" attribute

Performance note
================

For testing, I used the self-test hash configured according to the
RFC 9106 recommendation: m=65536, t=3, p=1.

In my benchmarks, the AMD RX 7900 XTX achieved 1401 H/s using the same
hash that was used to test NVIDIA's RTX 4090. The RTX 4090 reached
1722 H/s, making it faster in absolute terms. However, at the time of
writing, it is more than three times as expensive as the 7900 XTX.

It's also worth noting that an older NVIDIA GTX 1080 Ti still reached
565 H/s with the same test vector, and may be found at significantly
lower cost.

Across all tested Argon2 configurations, the performance gap between
the RX 7900 XTX and the RTX 4090 remained proportionally consistent,
indicating a clear linear scaling relationship between the two GPUs.
2025-07-02 11:02:57 +02:00
Jens Steube
96e3b6581d
Merge pull request #4284 from fse-a/argon2id-support
Support for Argon2id on NVIDIA CUDA GPUs
2025-07-02 10:55:16 +02:00
Pelle Kuiters
3c1649ccc8 GPU support for Argon2id for NVIDIA CUDA 2025-07-02 10:47:00 +02:00
Jens Steube
5c1ae6a1f6
Merge pull request #4273 from matrix/backend_ctx_devices_init_splitted
Backend: Splitting backend_ctx_devices_init into smaller runtime-specific functions
2025-07-01 20:24:43 +02:00
Jens Steube
9aa7c94ede
Merge pull request #4278 from matrix/hwmon_ctx_init_split
Refactoring Hardware Monitor
2025-07-01 20:24:20 +02:00
Jens Steube
4d4bb71d48 Use a combination of device_processor == 1 and CL_DEVICE_HOST_UNIFIED_MEMORY == 1 to determine if the device is an APU. In that case, overwrite the device_processor count with 64 to correct the invalid value of 1 reported by the HIP and OpenCL runtimes. The value 64 is obtained from rocminfo. This might not be accurate for other APUs beyond the one used as a reference, but oversubscribing an APU does not negatively affect performance, so this should be acceptable.
Also fixed a syntax error in inc_vendor.h related to funnel shift.
2025-07-01 16:02:40 +02:00
Jens Steube
696fa3b2ad Modified the automatic kernel-accel count reduction routine to also reduce kernel-thread count if insufficient device or host memory is available.
Reduced the fixed memory reservation size from 1GiB to 64MiB as a result.
Added a warning when the user sets a thread count on the command line higher than recommended by the runtime (based on available registers and shared memory).
Added host-side logic to detect true funnel shift support and disable kernels using it if not supported on the device.
Updated more plugins to limit register count to 128 on NVIDIA GPUs.
2025-06-30 19:38:54 +02:00
Gabriele Gristina
cbb92d4897
Merge branch 'master' into hwmon_ctx_init_split 2025-06-30 13:40:46 +02:00
Jens Steube
f8df94f457 Switched all async and non-blocking calls to synchronous and blocking ones. Kept the original async bindings intact. This avoids race conditions like the one fixed in the previous commit, with no performance impact.
Fixed a typedef issue for clEnqueueReadBuffer().
Updated Python/hcshared.py with missing entry for new salt_dimy attribute in salt_t struct.
Fixed a bug in the autotuner when determining the starting value for kernel loops, in cases where the iteration count is N-1 and not a multiple of 1024.
Updated additional plugins to use OPTI_TYPE_REGISTER_LIMIT.
2025-06-30 11:26:05 +02:00
Jens Steube
5f28414822
Merge pull request #4277 from matrix/selftest_race_condition
Fixed race condition in selftest_init on OpenCL with non-blocking write
2025-06-30 06:40:01 +02:00
Gabriele Gristina
f848163b0a
Fixed race condition in selftest_init on OpenCL with non-blocking write 2025-06-29 23:08:43 +02:00
Gabriele Gristina
1978231c88
- Fixed bug in Hardware Monitor: prevent disable if ADL fail
- Hardware Monitor: Splitting hwmon_ctx_init function into smaller library-specific functions
2025-06-29 22:51:08 +02:00
Gabriele Gristina
0830bc4b9f
set backend_ctx before macro preprocessor, into backend_ctx_devices_init_metal 2025-06-29 18:29:39 +02:00
Gabriele Gristina
907e58c27d
move is_virtualized and virtmulti into runtime-specific functions to simplify parameters 2025-06-29 18:26:17 +02:00
Jens Steube
57c8ac4b54
Merge pull request #4274 from matrix/selftest_splitted
Selftest: rename selftest function to process_selftest and splitting into 3 smaller functions
2025-06-29 17:56:55 +02:00
Gabriele Gristina
ca71119968
Selftest: rename selftest function to process_selftest and splitting into 3 smaller functions 2025-06-29 16:59:39 +02:00
Gabriele Gristina
78c8180e12
set static void to runtime-specific functions and simplify parameters 2025-06-29 15:33:59 +02:00
Jens Steube
c59d3b8f34
Merge pull request #4271 from matrix/backend_info_machine_readable
Backend Info: Added --machine-readable format
2025-06-29 14:58:49 +02:00
Jens Steube
0c2ed0d199 Update plugins that benefit from an artificially limited register count (NVIDIA).
Update default hash settings to 64MiB:3:4 for Argon2 in -m 70000, following RFC 9106 recommendations.
Add option OPTS_TYPE_THREAD_MULTI_DISABLE: allows plugin developers to disable scaling the password candidate batch size based on device thread count. This can be useful for super slow hash algorithms that utilize threads differently, e.g., when the algorithm allows parallelization. Note: thread count for the device can still be set normally.
Add options OPTI_TYPE_SLOW_HASH_DIMY_INIT/LOOP/COMP: enable 2D launches for slow hash init/loop/comp kernel with dimensions X and Y. The Y value must be set via salt->salt_dimy attribute.
Change autotune kernel-loops start value to the lowest multiple of the target hash iteration count, if kernel_loops_min permits.
Fixed a bug in autotune where kernel_threads_max was not respected during initial init and loop-prepare kernel runs.
2025-06-29 14:39:14 +02:00
Gabriele Gristina
7e2c65cc98
Backend: Splitting backend_ctx_devices_init into smaller runtime-specific functions 2025-06-29 13:28:31 +02:00
Jens Steube
237d784742
Merge pull request #4272 from matrix/regsPerBlock_workaround
workaround for HIP bug and avoiding a potential same bug on CUDA
2025-06-28 23:03:13 +02:00
Gabriele Gristina
c275c35ced
workaround for HIP bug and avoiding a potential same bug on CUDA 2025-06-28 22:54:36 +02:00
Gabriele Gristina
92b2f996b2
update docs/changes.txt 2025-06-28 10:45:24 +02:00
Gabriele Gristina
45b8672270
add --machine-readable format to --backend-info 2025-06-28 10:42:47 +02:00
Jens Steube
7fff4c929a Fixed a division by zero bug in fast hashes caused by hashes->st_salts_buf->salt_iter not being used. 2025-06-28 07:04:44 +02:00
Jens Steube
d5050d1f32
Merge pull request #4218 from matrix/ripemd320
Added hash-modes: RIPEMD-320, HMAC-RIPEMD320 (key = $pass), HMAC-RIPEMD320 (key = $salt)
2025-06-27 22:05:50 +02:00
Jens Steube
92ed2c6524
Merge pull request #4269 from matrix/user_options_bench_info
do not allow --benchmark and --backend-info
2025-06-27 22:02:47 +02:00
Jens Steube
974934dcdf Trying out a tweak to autotune behavior related to -u loop tuning.
Since loop values increase by doubling in autotune, a slow hash-mode
with, for example, 1000 iterations can end up with a suboptimal -u count.
Currently, autotuning starts at 1 and doubles (2, 4, 8, ..., 512, 1024).
If the maximum is 1000, autotune stops at 512, resulting in two kernel
calls: one with 512 iterations and another with 488.

The tweak attempts to find the smallest factor that, when repeatedly
doubled, reaches the target exactly.  For 1000, this would be 125
and for 1024, it would be 1.

However, this logic doesn’t align well with how hashcat handles slow
hash iterations. For instance, PBKDF2-based plugins typically set the
iteration count to N-1, since the first iteration is handled by the
`_init` kernel. So, a plugin might set 1023 instead of 1024, and in such
cases, the logic would incorrectly assume 1023 is the minimum factor
which leads to suboptimal tuning.

To work around this, the factor-finder is executed twice: once with
the original iteration count and once with `iteration count + 1`.
The configuration that results in a lower starting point is used.

Other stuff:

- Fixed a critical bug in the autotuner

This bug was introduced a few days ago. The autotuner has the ability
to overtune the maximum allowed thread count under certain conditions.
For example, in unoptimized -a 0 cracking mode when using rules.
Several parts of the hashcat core require strict adherence to this limit,
especially when shared memory is involved.
To resolve this while retaining overtuning for compatible modes,
a new attribute `device_param->overtune_unfriendly` was introduced.
When set to true, it prevents the autotuner from modifying
`kernel_threads_max` and `kernel_accel_max`.
Four sections in `backend.c` have been updated to set this flag,
though additional areas may also require it.

- Moved the code that aligns `kernel_accel` to a multiple of the compute
  unit count into the overtune section.

- Fixed a bug in the HIP dynloader. It now reports actual error strings,
  provided the API returns them.
2025-06-27 21:52:57 +02:00
Gabriele Gristina
fcc2844880
do not allow --benchmark and --backend-info 2025-06-26 22:12:50 +02:00
Gabriele Gristina
0869e7c1bb
change KERNEL_FQ to KERNEL_FQ KERNEL_FA statements 2025-06-26 21:55:07 +02:00
Jens Steube
bdc47abbe0
Merge pull request #4268 from matrix/modules_unstable_warning_fix
restore module_unstable_warning, excluding AMD Radeon
2025-06-26 21:44:31 +02:00
Gabriele Gristina
a3afca56b8
Merge remote-tracking branch 'upstream/master' into ripemd320 2025-06-26 21:37:40 +02:00
Gabriele Gristina
a5fd75f6ab
restore module_unstable_warning, excluding AMD Radeon 2025-06-26 21:35:11 +02:00
Jens Steube
3182af1bc9 - Renamed shuffle() in inc_hash_scrypt.cl to avoid name collision with
shuffle() present in some OpenCL runtimes
- Updated autotune logic: if the best kernel-loop is not yet found and
  the current kernel-loops setting resulting in a kernel runtime which
  is already above a certain threshold, do not skip to kernel-threads
  or kernel-accel section if no variance is possible
- Revised all plugin module_unstable_warning() checks for
  AMD Radeon Pro W5700X GPU on Metal: rechecked with the latest
  Metal version and removed those now fixed
- Inform the user on startup when backend runtimes and devices are
  initialized
- Fixed some file permissions in the tools/ folder
2025-06-26 19:36:06 +02:00
Jens Steube
825491aa6c Rewrote the SCRYPT core to work around a segmentation fault bug in the Intel OpenCL CPU runtime, without negatively affecting other runtimes.
Fixed the automatic kernel acceleration adjustment routine to account for some OpenCL runtime's buffer size limitation (1/4).
Added a missing license header to scrypt_commit.c (MIT).
2025-06-26 09:47:36 +02:00
Jens Steube
58fa783095 Enhanced the auto-tune engine: when a kernel runs with a single thread and no accel, it should finish quickly (ideally under 1 ms). If it doesn't, the kernel is likely overloaded with code. If such a kernel also uses barriers (e.g., to load shared storage with multiple threads), high iteration counts cause unnecessary thread waiting. To address this, we now skip increasing the loop count if the runtime exceeds either 1/8 of the target time (based on the -w setting) or a hard-coded threshold of 4 ms.
Improved shared memory handling for -m 10700. Removed the hard-coded limit of 256 threads and now dynamically check the device's shared memory pool to adapt threads accordingly.
Implemented a feature request to display non-default session names early during startup.
Added a check for the number of registers required by a kernel (CUDA and HIP only). This allows us to estimate the max threads per block before entering the auto-tune engine and make pre-adjustments.
Fixed Metal command encoder argument to work with the new auto-tuner's extra kernel invocation.
Fixed incorrect host memory calculation logic during automatic kernel-accel reduction for scrypt-based algorithms. This ensures memory constraints are respected.
Improved several plugins by setting maximum loop counts and others using the OPTS_TYPE_NATIVE_THREADS option.
Fixed compilation on Apple platforms by excluding '#include <sys/sysinfo.h>'.
2025-06-25 22:10:29 +02:00
Jens Steube
62a5a85dd6 Added 'next_power_of_two()' and moved both 'next_power_of_two()' and 'previous_power_of_two()' to 'shared.c'
Improved autotuner tweak logic and added boundary checks for accel and threads
Fixed available host memory detection on Windows
Fixed compilation error in MSYS2 native shell
Introduced an 8 GiB host memory usage limit per GPU, even if more is available
Replaced fixed-size host memory detection per GPU with a dynamic kernel-accel based method (similar to GPU memory detection)
Disabled hash-mode autodetection in the python bridge
Removed default invocation of 'rocm-smi' in 'benchmark_deep.pl' to avoid skewed initial results
Reduced default runtime in 'benchmark_deep.pl' scripts due to improved benchmark accuracy in hashcat in general
2025-06-25 11:21:51 +02:00
Jens Steube
669bd619cd
Merge pull request #4267 from lhywk/fix/socket-leak-brain-server
Fix socket leak in brain_server()
2025-06-25 07:24:45 +02:00
lhywk
45a3820560 Fix: close server_fd on brain_server() 2025-06-25 04:47:03 +00:00
Jens Steube
189e8acdf9 Small tweak for new autotuner 2025-06-24 22:21:47 +02:00
Jens Steube
69a585fa4a Autotune refactoring II: dynamic threads-per-block
- Integrated occupancy hints from vendor APIs (CUDA, HIP) to set a
  dynamic threads-per-block limit per kernel instead of using static
  values.
- Added `find_tuning_function()` to identify the relevant kernel.
- Autotuner now runs in three stages: threads -> loops -> accel. The
  first two stages now stop increasing when the tested kernel runtime
  gets too close to the target runtime (96ms for `-w 3`), leaving
  headroom for the next stage to adjust in a finer sense.
- Accel tuning now uses a capped floating-point multiplier instead of
  powers of two.
- Removed workarounds for missing thread autotuning in plugins.
- Removed the hardcoded 4GiB host memory limit for accel. Added a
  cross-platform `get_free_memory()` to check actual free RAM during GPU
  initialization, preventing underutilization of high-end GPUs like the
  4090. If needed, users can still cap memory usage with `-T` or `-n`.
- Updated enums for ROCm 6.4.x and CUDA 12.9.
- Added code to detect kernel register spilling. That's relevant so we
  can keep free enough global memory on the runtime for the runtime to
  handle spills efficiently.
2025-06-24 20:19:42 +02:00
Jens Steube
b241439cf0
Merge pull request #4251 from matrix/module_unstable_warning_AMD-EPYC
Modules: Updated module_unstable_warning for hash-mode 1500, 3000, 14000, 19200
2025-06-23 22:41:54 +02:00
Jens Steube
fd98bbb075
Merge pull request #4263 from matrix/memory_leaks_2025
fix memory leaks
2025-06-23 22:32:08 +02:00
Jens Steube
13a7b56feb Improve the logic for when to use funnelshift and when not to. Some algorithms, such as SHA1-HMAC and DCC1, do not work well with it, so it has been disabled for them.
Fix the automatic reduction of the kernel-accel maximum based on available memory per device by accounting for the additional size needed to handle register spilling.
Fix the tools/benchmark_deep.pl script to recognize benchmark masks more reliably.
2025-06-23 12:30:12 +02:00