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Andrei Vlad LUTAS e26971b4f0 Added missing Default 64 flag for the ENTER instruction. ... On AMD, operand size is never forced to 64 bit - instead, it only defaults to 64 bit, which means that 0x66 can be used to encode 16 bit version of the instructions.		4 years ago
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instructions.h	Added missing Default 64 flag for the ENTER instruction.	4 years ago
mnemonics.h	Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).	4 years ago
nd_crt.h	Don't use reserved identifiers for include guards	4 years ago
prefixes.h	Don't use reserved identifiers for include guards	4 years ago
table_evex.h	Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).	4 years ago
table_root.h	Disassemble 4X90 as NOP as long as Rex.B is 0. Disassemble as XCHG only if Rex.B bit is set (promoting the use of R8 register).	4 years ago
table_vex.h	Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).	4 years ago
table_xop.h	Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).	4 years ago
tabledefs.h	Disassemble 4X90 as NOP as long as Rex.B is 0. Disassemble as XCHG only if Rex.B bit is set (promoting the use of R8 register).	4 years ago