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6dda2c122c
bddisasm/bddisasm_test/avx512/avx512vnni_64.asm
Andrei Vlad LUTAS 76d92e73c2 Multiple changes 
- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
- Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
- Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
- Several other minor fixes and improvements
2021-07-08 12:40:39 +03:00

183 lines
7.3 KiB
NASM
Raw Blame History

bits 64
vpdpbusd xmm2, xmm7, xmm0
vpdpbusd xmm2, xmm7, [rbx]
vpdpbusd xmm2, xmm7, [rbx]{1to4}
vpdpbusd xmm2, xmm7, [rbx+r11*8+256]
vpdpbusd xmm2, xmm7, [rbx+r11*8-256]
vpdpbusd xmm2{k5}, xmm7, xmm0
vpdpbusd xmm2{k5}, xmm7, [rbx]
vpdpbusd xmm2{k5}, xmm7, [rbx]{1to4}
vpdpbusd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpbusd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpbusd xmm2{k5}{z}, xmm7, xmm0
vpdpbusd xmm2{k5}{z}, xmm7, [rbx]
vpdpbusd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpdpbusd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpdpbusd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpdpbusd ymm16, ymm13, ymm15
vpdpbusd ymm16, ymm13, [rbx]
vpdpbusd ymm16, ymm13, [rbx]{1to8}
vpdpbusd ymm16, ymm13, [rbx+r11*8+256]
vpdpbusd ymm16, ymm13, [rbx+r11*8-256]
vpdpbusd ymm16{k5}, ymm13, ymm15
vpdpbusd ymm16{k5}, ymm13, [rbx]
vpdpbusd ymm16{k5}, ymm13, [rbx]{1to8}
vpdpbusd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpbusd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpbusd ymm16{k5}{z}, ymm13, ymm15
vpdpbusd ymm16{k5}{z}, ymm13, [rbx]
vpdpbusd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpdpbusd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpdpbusd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpdpbusd zmm24, zmm24, zmm31
vpdpbusd zmm24, zmm24, [rbx]
vpdpbusd zmm24, zmm24, [rbx]{1to16}
vpdpbusd zmm24, zmm24, [rbx+r11*8+256]
vpdpbusd zmm24, zmm24, [rbx+r11*8-256]
vpdpbusd zmm24{k5}, zmm24, zmm31
vpdpbusd zmm24{k5}, zmm24, [rbx]
vpdpbusd zmm24{k5}, zmm24, [rbx]{1to16}
vpdpbusd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpbusd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpbusd zmm24{k5}{z}, zmm24, zmm31
vpdpbusd zmm24{k5}{z}, zmm24, [rbx]
vpdpbusd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpdpbusd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpdpbusd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpdpbusds xmm2, xmm7, xmm0
vpdpbusds xmm2, xmm7, [rbx]
vpdpbusds xmm2, xmm7, [rbx]{1to4}
vpdpbusds xmm2, xmm7, [rbx+r11*8+256]
vpdpbusds xmm2, xmm7, [rbx+r11*8-256]
vpdpbusds xmm2{k5}, xmm7, xmm0
vpdpbusds xmm2{k5}, xmm7, [rbx]
vpdpbusds xmm2{k5}, xmm7, [rbx]{1to4}
vpdpbusds xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpbusds xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpbusds xmm2{k5}{z}, xmm7, xmm0
vpdpbusds xmm2{k5}{z}, xmm7, [rbx]
vpdpbusds xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpdpbusds xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpdpbusds xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpdpbusds ymm16, ymm13, ymm15
vpdpbusds ymm16, ymm13, [rbx]
vpdpbusds ymm16, ymm13, [rbx]{1to8}
vpdpbusds ymm16, ymm13, [rbx+r11*8+256]
vpdpbusds ymm16, ymm13, [rbx+r11*8-256]
vpdpbusds ymm16{k5}, ymm13, ymm15
vpdpbusds ymm16{k5}, ymm13, [rbx]
vpdpbusds ymm16{k5}, ymm13, [rbx]{1to8}
vpdpbusds ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpbusds ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpbusds ymm16{k5}{z}, ymm13, ymm15
vpdpbusds ymm16{k5}{z}, ymm13, [rbx]
vpdpbusds ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpdpbusds ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpdpbusds ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpdpbusds zmm24, zmm24, zmm31
vpdpbusds zmm24, zmm24, [rbx]
vpdpbusds zmm24, zmm24, [rbx]{1to16}
vpdpbusds zmm24, zmm24, [rbx+r11*8+256]
vpdpbusds zmm24, zmm24, [rbx+r11*8-256]
vpdpbusds zmm24{k5}, zmm24, zmm31
vpdpbusds zmm24{k5}, zmm24, [rbx]
vpdpbusds zmm24{k5}, zmm24, [rbx]{1to16}
vpdpbusds zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpbusds zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpbusds zmm24{k5}{z}, zmm24, zmm31
vpdpbusds zmm24{k5}{z}, zmm24, [rbx]
vpdpbusds zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpdpbusds zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpdpbusds zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpdpwssd xmm2, xmm7, xmm0
vpdpwssd xmm2, xmm7, [rbx]
vpdpwssd xmm2, xmm7, [rbx]{1to4}
vpdpwssd xmm2, xmm7, [rbx+r11*8+256]
vpdpwssd xmm2, xmm7, [rbx+r11*8-256]
vpdpwssd xmm2{k5}, xmm7, xmm0
vpdpwssd xmm2{k5}, xmm7, [rbx]
vpdpwssd xmm2{k5}, xmm7, [rbx]{1to4}
vpdpwssd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpwssd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpwssd xmm2{k5}{z}, xmm7, xmm0
vpdpwssd xmm2{k5}{z}, xmm7, [rbx]
vpdpwssd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpdpwssd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpdpwssd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpdpwssd ymm16, ymm13, ymm15
vpdpwssd ymm16, ymm13, [rbx]
vpdpwssd ymm16, ymm13, [rbx]{1to8}
vpdpwssd ymm16, ymm13, [rbx+r11*8+256]
vpdpwssd ymm16, ymm13, [rbx+r11*8-256]
vpdpwssd ymm16{k5}, ymm13, ymm15
vpdpwssd ymm16{k5}, ymm13, [rbx]
vpdpwssd ymm16{k5}, ymm13, [rbx]{1to8}
vpdpwssd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpwssd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpwssd ymm16{k5}{z}, ymm13, ymm15
vpdpwssd ymm16{k5}{z}, ymm13, [rbx]
vpdpwssd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpdpwssd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpdpwssd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpdpwssd zmm24, zmm24, zmm31
vpdpwssd zmm24, zmm24, [rbx]
vpdpwssd zmm24, zmm24, [rbx]{1to16}
vpdpwssd zmm24, zmm24, [rbx+r11*8+256]
vpdpwssd zmm24, zmm24, [rbx+r11*8-256]
vpdpwssd zmm24{k5}, zmm24, zmm31
vpdpwssd zmm24{k5}, zmm24, [rbx]
vpdpwssd zmm24{k5}, zmm24, [rbx]{1to16}
vpdpwssd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpwssd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpwssd zmm24{k5}{z}, zmm24, zmm31
vpdpwssd zmm24{k5}{z}, zmm24, [rbx]
vpdpwssd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpdpwssd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpdpwssd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpdpwssds xmm2, xmm7, xmm0
vpdpwssds xmm2, xmm7, [rbx]
vpdpwssds xmm2, xmm7, [rbx]{1to4}
vpdpwssds xmm2, xmm7, [rbx+r11*8+256]
vpdpwssds xmm2, xmm7, [rbx+r11*8-256]
vpdpwssds xmm2{k5}, xmm7, xmm0
vpdpwssds xmm2{k5}, xmm7, [rbx]
vpdpwssds xmm2{k5}, xmm7, [rbx]{1to4}
vpdpwssds xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpwssds xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpwssds xmm2{k5}{z}, xmm7, xmm0
vpdpwssds xmm2{k5}{z}, xmm7, [rbx]
vpdpwssds xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpdpwssds xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpdpwssds xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpdpwssds ymm16, ymm13, ymm15
vpdpwssds ymm16, ymm13, [rbx]
vpdpwssds ymm16, ymm13, [rbx]{1to8}
vpdpwssds ymm16, ymm13, [rbx+r11*8+256]
vpdpwssds ymm16, ymm13, [rbx+r11*8-256]
vpdpwssds ymm16{k5}, ymm13, ymm15
vpdpwssds ymm16{k5}, ymm13, [rbx]
vpdpwssds ymm16{k5}, ymm13, [rbx]{1to8}
vpdpwssds ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpwssds ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpwssds ymm16{k5}{z}, ymm13, ymm15
vpdpwssds ymm16{k5}{z}, ymm13, [rbx]
vpdpwssds ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpdpwssds ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpdpwssds ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpdpwssds zmm24, zmm24, zmm31
vpdpwssds zmm24, zmm24, [rbx]
vpdpwssds zmm24, zmm24, [rbx]{1to16}
vpdpwssds zmm24, zmm24, [rbx+r11*8+256]
vpdpwssds zmm24, zmm24, [rbx+r11*8-256]
vpdpwssds zmm24{k5}, zmm24, zmm31
vpdpwssds zmm24{k5}, zmm24, [rbx]
vpdpwssds zmm24{k5}, zmm24, [rbx]{1to16}
vpdpwssds zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpwssds zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpwssds zmm24{k5}{z}, zmm24, zmm31
vpdpwssds zmm24{k5}{z}, zmm24, [rbx]
vpdpwssds zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpdpwssds zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpdpwssds zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
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