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bddisasm/bddisasm_test/avx512/avx512fma_64.asm
Andrei Vlad LUTAS 76d92e73c2 Multiple changes
- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
- Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
- Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
- Several other minor fixes and improvements
2021-07-08 12:40:39 +03:00

93 lines
3.9 KiB
NASM

bits 64
vpmadd52huq xmm2, xmm7, xmm0
vpmadd52huq xmm2, xmm7, [rbx]
vpmadd52huq xmm2, xmm7, [rbx]{1to2}
vpmadd52huq xmm2, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2, xmm7, [rbx+r11*8-256]
vpmadd52huq xmm2{k5}, xmm7, xmm0
vpmadd52huq xmm2{k5}, xmm7, [rbx]
vpmadd52huq xmm2{k5}, xmm7, [rbx]{1to2}
vpmadd52huq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmadd52huq xmm2{k5}{z}, xmm7, xmm0
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx]
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmadd52huq ymm16, ymm13, ymm15
vpmadd52huq ymm16, ymm13, [rbx]
vpmadd52huq ymm16, ymm13, [rbx]{1to4}
vpmadd52huq ymm16, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16, ymm13, [rbx+r11*8-256]
vpmadd52huq ymm16{k5}, ymm13, ymm15
vpmadd52huq ymm16{k5}, ymm13, [rbx]
vpmadd52huq ymm16{k5}, ymm13, [rbx]{1to4}
vpmadd52huq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmadd52huq ymm16{k5}{z}, ymm13, ymm15
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx]
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmadd52huq zmm24, zmm24, zmm31
vpmadd52huq zmm24, zmm24, [rbx]
vpmadd52huq zmm24, zmm24, [rbx]{1to8}
vpmadd52huq zmm24, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24, zmm24, [rbx+r11*8-256]
vpmadd52huq zmm24{k5}, zmm24, zmm31
vpmadd52huq zmm24{k5}, zmm24, [rbx]
vpmadd52huq zmm24{k5}, zmm24, [rbx]{1to8}
vpmadd52huq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmadd52huq zmm24{k5}{z}, zmm24, zmm31
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx]
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmadd52luq xmm2, xmm7, xmm0
vpmadd52luq xmm2, xmm7, [rbx]
vpmadd52luq xmm2, xmm7, [rbx]{1to2}
vpmadd52luq xmm2, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2, xmm7, [rbx+r11*8-256]
vpmadd52luq xmm2{k5}, xmm7, xmm0
vpmadd52luq xmm2{k5}, xmm7, [rbx]
vpmadd52luq xmm2{k5}, xmm7, [rbx]{1to2}
vpmadd52luq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmadd52luq xmm2{k5}{z}, xmm7, xmm0
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx]
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmadd52luq ymm16, ymm13, ymm15
vpmadd52luq ymm16, ymm13, [rbx]
vpmadd52luq ymm16, ymm13, [rbx]{1to4}
vpmadd52luq ymm16, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16, ymm13, [rbx+r11*8-256]
vpmadd52luq ymm16{k5}, ymm13, ymm15
vpmadd52luq ymm16{k5}, ymm13, [rbx]
vpmadd52luq ymm16{k5}, ymm13, [rbx]{1to4}
vpmadd52luq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmadd52luq ymm16{k5}{z}, ymm13, ymm15
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx]
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmadd52luq zmm24, zmm24, zmm31
vpmadd52luq zmm24, zmm24, [rbx]
vpmadd52luq zmm24, zmm24, [rbx]{1to8}
vpmadd52luq zmm24, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24, zmm24, [rbx+r11*8-256]
vpmadd52luq zmm24{k5}, zmm24, zmm31
vpmadd52luq zmm24{k5}, zmm24, [rbx]
vpmadd52luq zmm24{k5}, zmm24, [rbx]{1to8}
vpmadd52luq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmadd52luq zmm24{k5}{z}, zmm24, zmm31
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx]
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]