mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-12-22 22:18:09 +00:00
76d92e73c2
- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
99 lines
3.4 KiB
NASM
99 lines
3.4 KiB
NASM
bits 64
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vpopcntb xmm2, xmm0
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vpopcntb xmm2, [rbx]
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vpopcntb xmm2, [rbx+r11*8+256]
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vpopcntb xmm2, [rbx+r11*8-256]
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vpopcntb xmm2{k5}, xmm0
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vpopcntb xmm2{k5}, [rbx]
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vpopcntb xmm2{k5}, [rbx+r11*8+256]
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vpopcntb xmm2{k5}, [rbx+r11*8-256]
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vpopcntb xmm2{k5}{z}, xmm0
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vpopcntb xmm2{k5}{z}, [rbx]
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vpopcntb xmm2{k5}{z}, [rbx+r11*8+256]
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vpopcntb xmm2{k5}{z}, [rbx+r11*8-256]
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vpopcntb ymm16, ymm15
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vpopcntb ymm16, [rbx]
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vpopcntb ymm16, [rbx+r11*8+256]
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vpopcntb ymm16, [rbx+r11*8-256]
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vpopcntb ymm16{k5}, ymm15
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vpopcntb ymm16{k5}, [rbx]
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vpopcntb ymm16{k5}, [rbx+r11*8+256]
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vpopcntb ymm16{k5}, [rbx+r11*8-256]
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vpopcntb ymm16{k5}{z}, ymm15
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vpopcntb ymm16{k5}{z}, [rbx]
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vpopcntb ymm16{k5}{z}, [rbx+r11*8+256]
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vpopcntb ymm16{k5}{z}, [rbx+r11*8-256]
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vpopcntb zmm24, zmm31
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vpopcntb zmm24, [rbx]
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vpopcntb zmm24, [rbx+r11*8+256]
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vpopcntb zmm24, [rbx+r11*8-256]
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vpopcntb zmm24{k5}, zmm31
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vpopcntb zmm24{k5}, [rbx]
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vpopcntb zmm24{k5}, [rbx+r11*8+256]
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vpopcntb zmm24{k5}, [rbx+r11*8-256]
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vpopcntb zmm24{k5}{z}, zmm31
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vpopcntb zmm24{k5}{z}, [rbx]
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vpopcntb zmm24{k5}{z}, [rbx+r11*8+256]
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vpopcntb zmm24{k5}{z}, [rbx+r11*8-256]
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vpopcntw xmm2, xmm0
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vpopcntw xmm2, [rbx]
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vpopcntw xmm2, [rbx+r11*8+256]
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vpopcntw xmm2, [rbx+r11*8-256]
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vpopcntw xmm2{k5}, xmm0
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vpopcntw xmm2{k5}, [rbx]
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vpopcntw xmm2{k5}, [rbx+r11*8+256]
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vpopcntw xmm2{k5}, [rbx+r11*8-256]
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vpopcntw xmm2{k5}{z}, xmm0
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vpopcntw xmm2{k5}{z}, [rbx]
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vpopcntw xmm2{k5}{z}, [rbx+r11*8+256]
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vpopcntw xmm2{k5}{z}, [rbx+r11*8-256]
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vpopcntw ymm16, ymm15
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vpopcntw ymm16, [rbx]
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vpopcntw ymm16, [rbx+r11*8+256]
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vpopcntw ymm16, [rbx+r11*8-256]
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vpopcntw ymm16{k5}, ymm15
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vpopcntw ymm16{k5}, [rbx]
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vpopcntw ymm16{k5}, [rbx+r11*8+256]
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vpopcntw ymm16{k5}, [rbx+r11*8-256]
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vpopcntw ymm16{k5}{z}, ymm15
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vpopcntw ymm16{k5}{z}, [rbx]
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vpopcntw ymm16{k5}{z}, [rbx+r11*8+256]
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vpopcntw ymm16{k5}{z}, [rbx+r11*8-256]
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vpopcntw zmm24, zmm31
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vpopcntw zmm24, [rbx]
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vpopcntw zmm24, [rbx+r11*8+256]
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vpopcntw zmm24, [rbx+r11*8-256]
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vpopcntw zmm24{k5}, zmm31
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vpopcntw zmm24{k5}, [rbx]
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vpopcntw zmm24{k5}, [rbx+r11*8+256]
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vpopcntw zmm24{k5}, [rbx+r11*8-256]
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vpopcntw zmm24{k5}{z}, zmm31
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vpopcntw zmm24{k5}{z}, [rbx]
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vpopcntw zmm24{k5}{z}, [rbx+r11*8+256]
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vpopcntw zmm24{k5}{z}, [rbx+r11*8-256]
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vpshufbitqmb k3, xmm7, xmm0
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vpshufbitqmb k3, xmm7, [rbx]
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vpshufbitqmb k3, xmm7, [rbx+r11*8+256]
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vpshufbitqmb k3, xmm7, [rbx+r11*8-256]
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vpshufbitqmb k3, ymm13, ymm15
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vpshufbitqmb k3, ymm13, [rbx]
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vpshufbitqmb k3, ymm13, [rbx+r11*8+256]
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vpshufbitqmb k3, ymm13, [rbx+r11*8-256]
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vpshufbitqmb k3, zmm24, zmm31
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vpshufbitqmb k3, zmm24, [rbx]
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vpshufbitqmb k3, zmm24, [rbx+r11*8+256]
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vpshufbitqmb k3, zmm24, [rbx+r11*8-256]
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vpshufbitqmb k3{k5}, xmm7, xmm0
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vpshufbitqmb k3{k5}, xmm7, [rbx]
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vpshufbitqmb k3{k5}, xmm7, [rbx+r11*8+256]
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vpshufbitqmb k3{k5}, xmm7, [rbx+r11*8-256]
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vpshufbitqmb k3{k5}, ymm13, ymm15
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vpshufbitqmb k3{k5}, ymm13, [rbx]
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vpshufbitqmb k3{k5}, ymm13, [rbx+r11*8+256]
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vpshufbitqmb k3{k5}, ymm13, [rbx+r11*8-256]
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vpshufbitqmb k3{k5}, zmm24, zmm31
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vpshufbitqmb k3{k5}, zmm24, [rbx]
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vpshufbitqmb k3{k5}, zmm24, [rbx+r11*8+256]
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vpshufbitqmb k3{k5}, zmm24, [rbx+r11*8-256]
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