mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-11-26 09:28:07 +00:00
76d92e73c2
- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
189 lines
6.5 KiB
NASM
189 lines
6.5 KiB
NASM
bits 64
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vpbroadcastmb2q xmm2, k1
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vpbroadcastmb2q ymm16, k1
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vpbroadcastmb2q zmm24, k1
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vpbroadcastmw2d xmm2, k1
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vpbroadcastmw2d ymm16, k1
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vpbroadcastmw2d zmm24, k1
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vpconflictd xmm2, xmm0
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vpconflictd xmm2, [rbx]
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vpconflictd xmm2, [rbx]{1to4}
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vpconflictd xmm2, [rbx+r11*8+256]
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vpconflictd xmm2, [rbx+r11*8-256]
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vpconflictd xmm2{k5}, xmm0
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vpconflictd xmm2{k5}, [rbx]
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vpconflictd xmm2{k5}, [rbx]{1to4}
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vpconflictd xmm2{k5}, [rbx+r11*8+256]
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vpconflictd xmm2{k5}, [rbx+r11*8-256]
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vpconflictd xmm2{k5}{z}, xmm0
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vpconflictd xmm2{k5}{z}, [rbx]
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vpconflictd xmm2{k5}{z}, [rbx]{1to4}
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vpconflictd xmm2{k5}{z}, [rbx+r11*8+256]
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vpconflictd xmm2{k5}{z}, [rbx+r11*8-256]
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vpconflictd ymm16, ymm15
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vpconflictd ymm16, [rbx]
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vpconflictd ymm16, [rbx]{1to8}
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vpconflictd ymm16, [rbx+r11*8+256]
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vpconflictd ymm16, [rbx+r11*8-256]
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vpconflictd ymm16{k5}, ymm15
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vpconflictd ymm16{k5}, [rbx]
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vpconflictd ymm16{k5}, [rbx]{1to8}
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vpconflictd ymm16{k5}, [rbx+r11*8+256]
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vpconflictd ymm16{k5}, [rbx+r11*8-256]
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vpconflictd ymm16{k5}{z}, ymm15
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vpconflictd ymm16{k5}{z}, [rbx]
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vpconflictd ymm16{k5}{z}, [rbx]{1to8}
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vpconflictd ymm16{k5}{z}, [rbx+r11*8+256]
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vpconflictd ymm16{k5}{z}, [rbx+r11*8-256]
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vpconflictd zmm24, zmm31
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vpconflictd zmm24, [rbx]
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vpconflictd zmm24, [rbx]{1to16}
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vpconflictd zmm24, [rbx+r11*8+256]
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vpconflictd zmm24, [rbx+r11*8-256]
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vpconflictd zmm24{k5}, zmm31
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vpconflictd zmm24{k5}, [rbx]
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vpconflictd zmm24{k5}, [rbx]{1to16}
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vpconflictd zmm24{k5}, [rbx+r11*8+256]
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vpconflictd zmm24{k5}, [rbx+r11*8-256]
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vpconflictd zmm24{k5}{z}, zmm31
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vpconflictd zmm24{k5}{z}, [rbx]
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vpconflictd zmm24{k5}{z}, [rbx]{1to16}
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vpconflictd zmm24{k5}{z}, [rbx+r11*8+256]
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vpconflictd zmm24{k5}{z}, [rbx+r11*8-256]
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vpconflictq xmm2, xmm0
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vpconflictq xmm2, [rbx]
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vpconflictq xmm2, [rbx]{1to2}
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vpconflictq xmm2, [rbx+r11*8+256]
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vpconflictq xmm2, [rbx+r11*8-256]
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vpconflictq xmm2{k5}, xmm0
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vpconflictq xmm2{k5}, [rbx]
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vpconflictq xmm2{k5}, [rbx]{1to2}
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vpconflictq xmm2{k5}, [rbx+r11*8+256]
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vpconflictq xmm2{k5}, [rbx+r11*8-256]
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vpconflictq xmm2{k5}{z}, xmm0
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vpconflictq xmm2{k5}{z}, [rbx]
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vpconflictq xmm2{k5}{z}, [rbx]{1to2}
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vpconflictq xmm2{k5}{z}, [rbx+r11*8+256]
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vpconflictq xmm2{k5}{z}, [rbx+r11*8-256]
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vpconflictq ymm16, ymm15
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vpconflictq ymm16, [rbx]
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vpconflictq ymm16, [rbx]{1to4}
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vpconflictq ymm16, [rbx+r11*8+256]
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vpconflictq ymm16, [rbx+r11*8-256]
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vpconflictq ymm16{k5}, ymm15
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vpconflictq ymm16{k5}, [rbx]
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vpconflictq ymm16{k5}, [rbx]{1to4}
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vpconflictq ymm16{k5}, [rbx+r11*8+256]
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vpconflictq ymm16{k5}, [rbx+r11*8-256]
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vpconflictq ymm16{k5}{z}, ymm15
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vpconflictq ymm16{k5}{z}, [rbx]
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vpconflictq ymm16{k5}{z}, [rbx]{1to4}
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vpconflictq ymm16{k5}{z}, [rbx+r11*8+256]
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vpconflictq ymm16{k5}{z}, [rbx+r11*8-256]
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vpconflictq zmm24, zmm31
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vpconflictq zmm24, [rbx]
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vpconflictq zmm24, [rbx]{1to8}
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vpconflictq zmm24, [rbx+r11*8+256]
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vpconflictq zmm24, [rbx+r11*8-256]
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vpconflictq zmm24{k5}, zmm31
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vpconflictq zmm24{k5}, [rbx]
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vpconflictq zmm24{k5}, [rbx]{1to8}
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vpconflictq zmm24{k5}, [rbx+r11*8+256]
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vpconflictq zmm24{k5}, [rbx+r11*8-256]
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vpconflictq zmm24{k5}{z}, zmm31
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vpconflictq zmm24{k5}{z}, [rbx]
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vpconflictq zmm24{k5}{z}, [rbx]{1to8}
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vpconflictq zmm24{k5}{z}, [rbx+r11*8+256]
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vpconflictq zmm24{k5}{z}, [rbx+r11*8-256]
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vplzcntd xmm2, xmm0
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vplzcntd xmm2, [rbx]
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vplzcntd xmm2, [rbx]{1to4}
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vplzcntd xmm2, [rbx+r11*8+256]
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vplzcntd xmm2, [rbx+r11*8-256]
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vplzcntd xmm2{k5}, xmm0
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vplzcntd xmm2{k5}, [rbx]
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vplzcntd xmm2{k5}, [rbx]{1to4}
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vplzcntd xmm2{k5}, [rbx+r11*8+256]
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vplzcntd xmm2{k5}, [rbx+r11*8-256]
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vplzcntd xmm2{k5}{z}, xmm0
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vplzcntd xmm2{k5}{z}, [rbx]
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vplzcntd xmm2{k5}{z}, [rbx]{1to4}
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vplzcntd xmm2{k5}{z}, [rbx+r11*8+256]
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vplzcntd xmm2{k5}{z}, [rbx+r11*8-256]
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vplzcntd ymm16, ymm15
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vplzcntd ymm16, [rbx]
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vplzcntd ymm16, [rbx]{1to8}
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vplzcntd ymm16, [rbx+r11*8+256]
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vplzcntd ymm16, [rbx+r11*8-256]
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vplzcntd ymm16{k5}, ymm15
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vplzcntd ymm16{k5}, [rbx]
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vplzcntd ymm16{k5}, [rbx]{1to8}
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vplzcntd ymm16{k5}, [rbx+r11*8+256]
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vplzcntd ymm16{k5}, [rbx+r11*8-256]
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vplzcntd ymm16{k5}{z}, ymm15
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vplzcntd ymm16{k5}{z}, [rbx]
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vplzcntd ymm16{k5}{z}, [rbx]{1to8}
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vplzcntd ymm16{k5}{z}, [rbx+r11*8+256]
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vplzcntd ymm16{k5}{z}, [rbx+r11*8-256]
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vplzcntd zmm24, zmm31
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vplzcntd zmm24, [rbx]
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vplzcntd zmm24, [rbx]{1to16}
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vplzcntd zmm24, [rbx+r11*8+256]
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vplzcntd zmm24, [rbx+r11*8-256]
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vplzcntd zmm24{k5}, zmm31
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vplzcntd zmm24{k5}, [rbx]
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vplzcntd zmm24{k5}, [rbx]{1to16}
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vplzcntd zmm24{k5}, [rbx+r11*8+256]
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vplzcntd zmm24{k5}, [rbx+r11*8-256]
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vplzcntd zmm24{k5}{z}, zmm31
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vplzcntd zmm24{k5}{z}, [rbx]
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vplzcntd zmm24{k5}{z}, [rbx]{1to16}
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vplzcntd zmm24{k5}{z}, [rbx+r11*8+256]
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vplzcntd zmm24{k5}{z}, [rbx+r11*8-256]
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vplzcntq xmm2, xmm0
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vplzcntq xmm2, [rbx]
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vplzcntq xmm2, [rbx]{1to2}
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vplzcntq xmm2, [rbx+r11*8+256]
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vplzcntq xmm2, [rbx+r11*8-256]
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vplzcntq xmm2{k5}, xmm0
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vplzcntq xmm2{k5}, [rbx]
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vplzcntq xmm2{k5}, [rbx]{1to2}
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vplzcntq xmm2{k5}, [rbx+r11*8+256]
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vplzcntq xmm2{k5}, [rbx+r11*8-256]
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vplzcntq xmm2{k5}{z}, xmm0
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vplzcntq xmm2{k5}{z}, [rbx]
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vplzcntq xmm2{k5}{z}, [rbx]{1to2}
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vplzcntq xmm2{k5}{z}, [rbx+r11*8+256]
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vplzcntq xmm2{k5}{z}, [rbx+r11*8-256]
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vplzcntq ymm16, ymm15
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vplzcntq ymm16, [rbx]
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vplzcntq ymm16, [rbx]{1to4}
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vplzcntq ymm16, [rbx+r11*8+256]
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vplzcntq ymm16, [rbx+r11*8-256]
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vplzcntq ymm16{k5}, ymm15
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vplzcntq ymm16{k5}, [rbx]
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vplzcntq ymm16{k5}, [rbx]{1to4}
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vplzcntq ymm16{k5}, [rbx+r11*8+256]
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vplzcntq ymm16{k5}, [rbx+r11*8-256]
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vplzcntq ymm16{k5}{z}, ymm15
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vplzcntq ymm16{k5}{z}, [rbx]
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vplzcntq ymm16{k5}{z}, [rbx]{1to4}
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vplzcntq ymm16{k5}{z}, [rbx+r11*8+256]
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vplzcntq ymm16{k5}{z}, [rbx+r11*8-256]
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vplzcntq zmm24, zmm31
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vplzcntq zmm24, [rbx]
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vplzcntq zmm24, [rbx]{1to8}
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vplzcntq zmm24, [rbx+r11*8+256]
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vplzcntq zmm24, [rbx+r11*8-256]
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vplzcntq zmm24{k5}, zmm31
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vplzcntq zmm24{k5}, [rbx]
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vplzcntq zmm24{k5}, [rbx]{1to8}
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vplzcntq zmm24{k5}, [rbx+r11*8+256]
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vplzcntq zmm24{k5}, [rbx+r11*8-256]
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vplzcntq zmm24{k5}{z}, zmm31
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vplzcntq zmm24{k5}{z}, [rbx]
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vplzcntq zmm24{k5}{z}, [rbx]{1to8}
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vplzcntq zmm24{k5}{z}, [rbx+r11*8+256]
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vplzcntq zmm24{k5}{z}, [rbx+r11*8-256]
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