1
0
mirror of https://github.com/bitdefender/bddisasm.git synced 2024-11-27 01:48:10 +00:00
bddisasm/bddisasm_test/x86/prefetchit/prefetchit_32.result
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 12:22:59 +03:00

31 lines
1.6 KiB
Plaintext

0000000000000000 0f1838 NOP dword ptr [eax]
DSIZE: 32, ASIZE: 32, VLEN: -
ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: --, Type: Memory, Size: 4, RawSize: 4, Encoding: M,
Segment: 3, Base: 0,
0000000000000003 0f183d90909090 NOP dword ptr [0x90909090]
DSIZE: 32, ASIZE: 32, VLEN: -
ISA Set: PPRO, Ins cat: WIDENOP, CET tracked: no
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: --, Type: Memory, Size: 4, RawSize: 4, Encoding: M,
Segment: 3, Displacement: 0xffffffff90909090,