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bddisasm/bddisasm_test/x86
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vlutas c282f06215
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 
* Add support for SIMD exceptions reporting in INSTRUX.
* Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4.

Co-authored-by: ianichitei (Rust bindings)
2024-11-07 12:15:29 +02:00
..
amx Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
apx Improve bddisasm and bdshemu test scripts. 2024-09-16 12:47:03 +03:00
avx Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
avx10 Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
avx512 Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
basic Improve bddisasm and bdshemu test scripts. 2024-09-16 12:47:03 +03:00
cet https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack. 2024-02-26 20:53:42 +02:00
cmpccxadd BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. 2024-02-20 13:39:22 +02:00
fred BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. 2024-02-20 13:39:22 +02:00
kl Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 2022-10-04 12:22:59 +03:00
movrs Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
msr Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
prefetchit Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 2022-10-04 12:22:59 +03:00
rao-int Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 2022-10-04 12:22:59 +03:00
sha512 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE. 2023-07-21 09:38:49 +03:00
simd Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
sm Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
special Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00
tdx Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 2022-10-04 12:22:59 +03:00
tse Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE. 2023-07-21 09:38:49 +03:00
uintr Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 2022-10-04 12:22:59 +03:00
usermsr Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 2024-11-07 12:15:29 +02:00