4 Commits

Author	SHA1	Message	Date
Andrei Vlad LUTAS	f7bf814bbc	Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. ... Bypass self-writes option in bdshemu - if set, bdshemu will not proceed to commit modifications made by the shellcode to itself.	2021-05-17 09:04:34 +03:00
Andrei Vlad LUTAS	e26971b4f0	Added missing Default 64 flag for the ENTER instruction. ... On AMD, operand size is never forced to 64 bit - instead, it only defaults to 64 bit, which means that 0x66 can be used to encode 16 bit version of the instructions.	2020-11-06 14:19:22 +02:00
Andrei Vlad LUTAS	33078e4670	Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.	2020-09-10 11:06:20 +03:00
Andrei Vlad LUTAS	698ba367a1	Initial commit.	2020-07-21 11:19:18 +03:00