BITDEFENDER\vlutas
fe6a937f51
Switched to internally defined types.
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WRUSSD and WRUSSQ cannot be executed when CPL != 0.
2022-01-05 14:03:13 +02:00
BITDEFENDER\vlutas
2f50ce9b4e
Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...
2021-12-03 12:44:57 +02:00
Andrei Vlad LUTAS
fccf11915d
Added support for Intel FRED and LKGS instructions.
2021-03-15 14:05:44 +02:00
Andrei Vlad LUTAS
e26971b4f0
Added missing Default 64 flag for the ENTER instruction.
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On AMD, operand size is never forced to 64 bit - instead, it only defaults to 64 bit, which means that 0x66 can be used to encode 16 bit version of the instructions.
2020-11-06 14:19:22 +02:00
Ionel-Cristinel ANICHITEI
049ecc0ab7
Don't use reserved identifiers for include guards
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This fixes #5
2020-07-27 16:51:16 +03:00
Andrei Vlad LUTAS
698ba367a1
Initial commit.
2020-07-21 11:19:18 +03:00
