5 Commits

Author	SHA1	Message	Date
Andrei Vlad LUTAS	08096172cc	Multiple improvements ... - New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0. - Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions. - Fixed Do Not Track prefix recognition for CALL and JMP in long-mode. - Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load. - Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.	2021-08-31 13:37:50 +03:00
Andrei Vlad LUTAS	33078e4670	Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.	2020-09-10 11:06:20 +03:00
Andrei Vlad LUTAS	4b2f2aee66	Added dedicated Prefetch operand access type. ... Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.	2020-07-25 17:16:35 +03:00
Andrei Vlad LUTAS	94d7894fa5	Added the Shadow Stack Pointer operand to the SYSRET and SYSENTER instructions. ... Regenrated CET test files, as the CPUID feature flag was split as per the last documentation into CET_SS and CET_IBT.	2020-07-22 09:15:29 +03:00
Andrei Vlad LUTAS	698ba367a1	Initial commit.	2020-07-21 11:19:18 +03:00