bddisasm

Author	SHA1	Message	Date
Andrei Vlad LUTAS	33078e4670	Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf .	4 years ago
Andrei Vlad LUTAS	94d7894fa5	Added the Shadow Stack Pointer operand to the SYSRET and SYSENTER instructions. Regenrated CET test files, as the CPUID feature flag was split as per the last documentation into CET_SS and CET_IBT.	4 years ago
Andrei Vlad LUTAS	9ff2543660	Added the Shadow Stack Pointer operand to the SYSCALL and SYSEXIT instructions. Moved the CET test cases in dedicated folders. Improved shadow-stack operand reporting - a distinction can be made between push/pop shadow stack accesses, and other shadow stack accesses. A new field is now present in the memory information - the shadow stack access type, which indicates: explicit access, implicit via SSP, implicit push/pop via SSP or implicit via IA32_PL0_SSP.	4 years ago

Author

SHA1

Message

Date

Andrei Vlad LUTAS

Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf .

Andrei Vlad LUTAS

94d7894fa5

Added the Shadow Stack Pointer operand to the SYSRET and SYSENTER instructions.

Regenrated CET test files, as the CPUID feature flag was split as per the last documentation into CET_SS and CET_IBT.

Andrei Vlad LUTAS

9ff2543660

Added the Shadow Stack Pointer operand to the SYSCALL and SYSEXIT instructions.

Moved the CET test cases in dedicated folders.
Improved shadow-stack operand reporting - a distinction can be made between push/pop shadow stack accesses, and other shadow stack accesses.
A new field is now present in the memory information - the shadow stack access type, which indicates: explicit access, implicit via SSP, implicit push/pop via SSP or implicit via IA32_PL0_SSP.

3 Commits (4f8b030ddd9af992463b255a8d87b02f48ece86e)