mirror of
https://github.com/bitdefender/bddisasm.git
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
This commit is contained in:
Andrei Vlad LUTAS
parent
be0969824c
commit
f53cbc51e2
File diff suppressed because it is too large
Load Diff
@ -10,7 +10,7 @@
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#ifndef MNEMONICS_H
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#ifndef MNEMONICS_H
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#define MNEMONICS_H
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#define MNEMONICS_H
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const char *gMnemonics[1736] =
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const char *gMnemonics[1751] =
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{
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{
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"AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD",
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"AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD",
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"ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX",
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"ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX",
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@ -90,130 +90,130 @@ const char *gMnemonics[1736] =
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"OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW",
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"OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW",
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"PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB",
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"PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB",
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"PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB",
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"PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB",
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"PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB",
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"PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PBNDKB", "PCLMULQDQ",
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"PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB",
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"PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM",
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"PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCONFIG",
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"PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM",
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"PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID",
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"PCONFIG", "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW",
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"PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX",
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"PF2ID", "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT",
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"PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2",
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"PFMAX", "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1",
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"PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR",
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"PFRCPIT2", "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB",
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"PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW",
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"PFSUBR", "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD",
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"PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW",
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"PHSUBSW", "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ",
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"PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB",
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"PINSRW", "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW",
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"PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD",
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"PMAXUB", "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB",
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"PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ",
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"PMINUD", "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW",
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"PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ",
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"PMOVSXDQ", "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW",
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"PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW",
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"PMOVZXDQ", "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW",
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"PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD",
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"PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA",
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"POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE",
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"POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH",
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"PREFETCHIT0", "PREFETCHIT1", "PREFETCHM", "PREFETCHNTA", "PREFETCHT0",
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"PREFETCHE", "PREFETCHIT0", "PREFETCHIT1", "PREFETCHM", "PREFETCHNTA",
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"PREFETCHT1", "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW",
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"PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", "PREFETCHWT1",
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"PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB",
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"PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW",
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"PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH",
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"PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW",
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"PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB",
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"PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW",
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"PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW",
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"PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW",
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"PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ",
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"PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ",
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"PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD",
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"PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ",
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"PUSH", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE",
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"PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW",
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"PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE",
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"PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE",
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"RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND",
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"RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC",
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"RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF",
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"RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC",
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"RETN", "RMPADJUST", "RMPQUERY", "RMPUPDATE", "ROL", "ROR", "RORX",
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"RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPQUERY", "RMPUPDATE",
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"ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT",
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"ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS",
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"RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL",
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"RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS",
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"SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD",
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"SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB",
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"SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI",
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"SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET",
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"SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC",
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"SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE",
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"SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO",
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"SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ",
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"SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1",
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"SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT",
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"SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2",
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"SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1",
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"SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX",
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"SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD",
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"SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMINT",
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"SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB",
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"SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC",
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"SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS",
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"STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ",
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"STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD",
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"STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS",
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"STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD",
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"SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL",
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"SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS",
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"SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS",
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"SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS",
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"TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD",
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"TCMMRLFP16PS", "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD",
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"TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE",
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"TDPBUSD", "TDPBUUD", "TDPFP16PS", "TEST", "TESTUI", "TILELOADD",
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"TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK",
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"TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC",
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"UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR",
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"TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1",
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"UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS",
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"UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS",
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"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH",
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"UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS",
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"VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS",
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"V4FNMADDSS", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH",
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"VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC",
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"VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST",
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"VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS",
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"VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND",
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"VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", "VBLENDMPD",
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"VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS",
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"VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS",
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"VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS",
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"VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8",
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"VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2",
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"VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2",
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"VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4",
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"VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4",
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"VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8",
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"VBROADCASTSD", "VBROADCASTSS", "VCMPPD", "VCMPPH", "VCMPPS",
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"VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS",
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"VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS",
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"VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD",
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"VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS",
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"VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD",
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"VCVTNE2PS2BF16", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS",
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"VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS",
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"VCVTNEOPH2PS", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS",
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"VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16",
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"VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD",
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"VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ",
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"VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ",
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"VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX",
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"VCVTPH2UW", "VCVTPH2W", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH",
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"VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W",
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"VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD",
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"VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ",
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"VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS",
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"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS",
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"VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI",
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"VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD",
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"VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH",
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"VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH",
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"VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ",
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"VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI",
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"VCVTTPD2UQQ", "VCVTTPH2DQ", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ",
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"VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ",
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"VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ",
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"VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W",
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"VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI",
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"VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI",
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"VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS",
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"VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI",
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"VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH",
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"VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH",
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"VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVPD",
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"VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH",
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"VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS",
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"VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD",
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"VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD",
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"VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW",
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"VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
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"VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128",
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"VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
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"VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4",
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"VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS",
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"VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2",
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"VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", "VFCMULCSH", "VFIXUPIMMPD",
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"VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH",
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"VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", "VFMADD132PH",
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"VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS",
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"VFMADD132PS", "VFMADD132SD", "VFMADD132SH", "VFMADD132SS", "VFMADD213PD",
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"VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH",
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"VFMADD213PH", "VFMADD213PS", "VFMADD213SD", "VFMADD213SH", "VFMADD213SS",
|
"VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD",
|
||||||
"VFMADD231PD", "VFMADD231PH", "VFMADD231PS", "VFMADD231SD", "VFMADD231SH",
|
"VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS",
|
||||||
"VFMADD231SS", "VFMADDCPH", "VFMADDCSH", "VFMADDPD", "VFMADDPS",
|
"VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH",
|
||||||
"VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", "VFMADDSUB132PH", "VFMADDSUB132PS",
|
"VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD",
|
||||||
"VFMADDSUB213PD", "VFMADDSUB213PH", "VFMADDSUB213PS", "VFMADDSUB231PD",
|
"VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH",
|
||||||
"VFMADDSUB231PH", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS",
|
"VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS",
|
||||||
"VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SH",
|
"VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS",
|
||||||
"VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH", "VFMSUB213PS", "VFMSUB213SD",
|
"VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH",
|
||||||
"VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PH", "VFMSUB231PS",
|
"VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD",
|
||||||
"VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", "VFMSUBADD132PD",
|
"VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS",
|
||||||
"VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", "VFMSUBADD213PH",
|
"VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD",
|
||||||
"VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", "VFMSUBADD231PS",
|
"VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH",
|
||||||
"VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD",
|
"VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS",
|
||||||
"VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD", "VFNMADD132PH",
|
"VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD",
|
||||||
"VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH", "VFNMADD132SS",
|
"VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH",
|
||||||
"VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS", "VFNMADD213SD",
|
"VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS",
|
||||||
"VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD", "VFNMADD231PH",
|
"VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD",
|
||||||
"VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH", "VFNMADD231SS",
|
"VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH",
|
||||||
"VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD",
|
"VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS",
|
||||||
"VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SH",
|
"VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD",
|
||||||
"VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH", "VFNMSUB213PS",
|
"VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH",
|
||||||
"VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS", "VFNMSUB231PD",
|
"VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS",
|
||||||
"VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD", "VFNMSUB231SH",
|
"VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD",
|
||||||
"VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS",
|
"VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD",
|
||||||
"VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", "VFPCLASSSH",
|
"VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD",
|
||||||
"VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", "VFRCZSS", "VGATHERDPD",
|
"VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD",
|
||||||
"VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD",
|
"VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS",
|
||||||
"VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD",
|
"VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS",
|
||||||
"VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", "VGETEXPPD", "VGETEXPPH",
|
"VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS",
|
||||||
"VGETEXPPS", "VGETEXPSD", "VGETEXPSH", "VGETEXPSS", "VGETMANTPD",
|
"VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH",
|
||||||
"VGETMANTPH", "VGETMANTPS", "VGETMANTSD", "VGETMANTSH", "VGETMANTSS",
|
"VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD",
|
||||||
"VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", "VGF2P8MULB", "VHADDPD",
|
"VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB",
|
||||||
"VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", "VINSERTF32X4",
|
"VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128",
|
||||||
"VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", "VINSERTI128",
|
"VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4",
|
||||||
"VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", "VINSERTI64X4",
|
"VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2",
|
||||||
"VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", "VMASKMOVPD",
|
"VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU",
|
||||||
"VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", "VMAXSH",
|
"VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD",
|
||||||
"VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", "VMINPD",
|
"VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
|
||||||
"VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH",
|
"VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH",
|
||||||
"VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP",
|
"VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP",
|
||||||
"VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16",
|
"VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16",
|
||||||
"VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD",
|
"VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD",
|
||||||
@ -239,77 +239,80 @@ const char *gMnemonics[1736] =
|
|||||||
"VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW",
|
"VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW",
|
||||||
"VPCONFLICTD", "VPCONFLICTQ", "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD",
|
"VPCONFLICTD", "VPCONFLICTQ", "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD",
|
||||||
"VPDPBSUDS", "VPDPBUSD", "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS",
|
"VPDPBSUDS", "VPDPBUSD", "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS",
|
||||||
"VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB",
|
"VPDPWSSD", "VPDPWSSDS", "VPDPWSUD", "VPDPWSUDS", "VPDPWUSD",
|
||||||
"VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
|
"VPDPWUSDS", "VPDPWUUD", "VPDPWUUDS", "VPERM2F128", "VPERM2I128",
|
||||||
"VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS",
|
"VPERMB", "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS",
|
||||||
"VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD",
|
"VPERMI2Q", "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD",
|
||||||
"VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD",
|
"VPERMILPS", "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D",
|
||||||
"VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW",
|
"VPERMT2PD", "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB",
|
||||||
"VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", "VPGATHERQQ", "VPHADDBD",
|
"VPEXPANDD", "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD",
|
||||||
"VPHADDBQ", "VPHADDBW", "VPHADDD", "VPHADDDQ", "VPHADDSW", "VPHADDUBD",
|
"VPEXTRQ", "VPEXTRW", "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD",
|
||||||
"VPHADDUBQ", "VPHADDUBW", "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ",
|
"VPGATHERQQ", "VPHADDBD", "VPHADDBQ", "VPHADDBW", "VPHADDD",
|
||||||
"VPHADDW", "VPHADDWD", "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW",
|
"VPHADDDQ", "VPHADDSW", "VPHADDUBD", "VPHADDUBQ", "VPHADDUBW",
|
||||||
"VPHSUBD", "VPHSUBDQ", "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB",
|
"VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", "VPHADDW", "VPHADDWD",
|
||||||
"VPINSRD", "VPINSRQ", "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD",
|
"VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", "VPHSUBD", "VPHSUBDQ",
|
||||||
"VPMACSDQH", "VPMACSDQL", "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL",
|
"VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", "VPINSRD", "VPINSRQ",
|
||||||
"VPMACSSWD", "VPMACSSWW", "VPMACSWD", "VPMACSWW", "VPMADCSSWD",
|
"VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", "VPMACSDQH", "VPMACSDQL",
|
||||||
"VPMADCSWD", "VPMADD52HUQ", "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD",
|
"VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", "VPMACSSWD", "VPMACSSWW",
|
||||||
"VPMASKMOVD", "VPMASKMOVQ", "VPMAXSB", "VPMAXSD", "VPMAXSQ",
|
"VPMACSWD", "VPMACSWW", "VPMADCSSWD", "VPMADCSWD", "VPMADD52HUQ",
|
||||||
"VPMAXSW", "VPMAXUB", "VPMAXUD", "VPMAXUQ", "VPMAXUW", "VPMINSB",
|
"VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", "VPMASKMOVD", "VPMASKMOVQ",
|
||||||
"VPMINSD", "VPMINSQ", "VPMINSW", "VPMINUB", "VPMINUD", "VPMINUQ",
|
"VPMAXSB", "VPMAXSD", "VPMAXSQ", "VPMAXSW", "VPMAXUB", "VPMAXUD",
|
||||||
"VPMINUW", "VPMOVB2M", "VPMOVD2M", "VPMOVDB", "VPMOVDW", "VPMOVM2B",
|
"VPMAXUQ", "VPMAXUW", "VPMINSB", "VPMINSD", "VPMINSQ", "VPMINSW",
|
||||||
"VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", "VPMOVMSKB", "VPMOVQ2M",
|
"VPMINUB", "VPMINUD", "VPMINUQ", "VPMINUW", "VPMOVB2M", "VPMOVD2M",
|
||||||
"VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", "VPMOVSDW", "VPMOVSQB",
|
"VPMOVDB", "VPMOVDW", "VPMOVM2B", "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W",
|
||||||
"VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", "VPMOVSXBQ",
|
"VPMOVMSKB", "VPMOVQ2M", "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB",
|
||||||
"VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVUSDB",
|
"VPMOVSDW", "VPMOVSQB", "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD",
|
||||||
"VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB",
|
"VPMOVSXBQ", "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ",
|
||||||
"VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXBW",
|
"VPMOVUSDB", "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW",
|
||||||
"VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", "VPMULHRSW",
|
"VPMOVUSWB", "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ",
|
||||||
"VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", "VPMULTISHIFTQB",
|
"VPMOVZXBW", "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ",
|
||||||
"VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", "VPOPCNTW", "VPOR",
|
"VPMULHRSW", "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW",
|
||||||
"VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ",
|
"VPMULTISHIFTQB", "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ",
|
||||||
"VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD",
|
"VPOPCNTW", "VPOR", "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ",
|
||||||
"VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ",
|
"VPROLVD", "VPROLVQ", "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ",
|
||||||
"VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW",
|
"VPROTB", "VPROTD", "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD",
|
||||||
"VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ",
|
"VPSCATTERDQ", "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD",
|
||||||
"VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ",
|
"VPSHAQ", "VPSHAW", "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ",
|
||||||
"VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB",
|
"VPSHLDVD", "VPSHLDVQ", "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW",
|
||||||
"VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW",
|
"VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW",
|
||||||
"VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW",
|
"VPSHUFB", "VPSHUFBITQMB", "VPSHUFD", "VPSHUFHW", "VPSHUFLW",
|
||||||
"VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW",
|
"VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD", "VPSLLDQ", "VPSLLQ",
|
||||||
"VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ",
|
"VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW", "VPSRAD", "VPSRAQ",
|
||||||
"VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB",
|
"VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW", "VPSRLD", "VPSRLDQ",
|
||||||
"VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ",
|
"VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW", "VPSRLW", "VPSUBB",
|
||||||
"VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB",
|
"VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", "VPSUBUSB", "VPSUBUSW",
|
||||||
"VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ",
|
"VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", "VPTEST", "VPTESTMB", "VPTESTMD",
|
||||||
"VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ",
|
"VPTESTMQ", "VPTESTMW", "VPTESTNMB", "VPTESTNMD", "VPTESTNMQ",
|
||||||
"VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS",
|
"VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", "VPUNPCKHQDQ", "VPUNPCKHWD",
|
||||||
"VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS",
|
"VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", "VPUNPCKLWD", "VPXOR",
|
||||||
"VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS",
|
"VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", "VRANGESD", "VRANGESS",
|
||||||
"VRCPSH", "VRCPSS", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD",
|
"VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", "VRCP28PD", "VRCP28PS",
|
||||||
"VREDUCESH", "VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS",
|
"VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS",
|
||||||
"VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
|
"VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH",
|
||||||
"VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD",
|
"VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD",
|
||||||
"VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS",
|
"VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", "VROUNDSD",
|
||||||
"VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD",
|
"VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS",
|
||||||
"VSCALEFPH", "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS",
|
"VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", "VRSQRTPH",
|
||||||
"VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS",
|
"VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD", "VSCALEFPH",
|
||||||
"VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS",
|
"VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD",
|
||||||
"VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS",
|
"VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD",
|
||||||
"VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD",
|
"VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD",
|
||||||
"VSHUFPS", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH",
|
"VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", "VSHA512MSG1",
|
||||||
"VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD",
|
"VSHA512MSG2", "VSHA512RNDS2", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4",
|
||||||
"VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", "VUCOMISH",
|
"VSHUFI64X2", "VSHUFPD", "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2",
|
||||||
"VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS",
|
"VSM4KEY4", "VSM4RNDS4", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD",
|
||||||
"VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD",
|
"VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS",
|
||||||
"WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS",
|
"VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD",
|
||||||
"WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT",
|
"VUCOMISH", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD",
|
||||||
"XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR",
|
"VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT",
|
||||||
"XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", "XOR", "XORPD",
|
"WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST",
|
||||||
"XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64",
|
"WRMSRNS", "WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ",
|
||||||
"XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64",
|
"XABORT", "XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB",
|
||||||
"XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", "XSTORE",
|
"XCRYPTCTR", "XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB",
|
||||||
"XSUSLDTRK", "XTEST",
|
"XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS",
|
||||||
|
"XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT",
|
||||||
|
"XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256",
|
||||||
|
"XSTORE", "XSUSLDTRK", "XTEST",
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -339,13 +339,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1359]
|
(const void *)&gInstructions[1360]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1386]
|
(const void *)&gInstructions[1387]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg =
|
const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg =
|
||||||
@ -399,7 +399,7 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1310]
|
(const void *)&gInstructions[1311]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg =
|
const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg =
|
||||||
@ -429,127 +429,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1824]
|
(const void *)&gInstructions[1825]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1825]
|
(const void *)&gInstructions[1826]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1826]
|
(const void *)&gInstructions[1827]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[1827]
|
(const void *)&gInstructions[1828]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2245]
|
(const void *)&gInstructions[2252]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2246]
|
(const void *)&gInstructions[2253]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2247]
|
(const void *)&gInstructions[2254]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2249]
|
(const void *)&gInstructions[2256]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2251]
|
(const void *)&gInstructions[2258]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2252]
|
(const void *)&gInstructions[2259]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2253]
|
(const void *)&gInstructions[2260]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2254]
|
(const void *)&gInstructions[2261]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2255]
|
(const void *)&gInstructions[2262]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2256]
|
(const void *)&gInstructions[2263]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2258]
|
(const void *)&gInstructions[2265]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2259]
|
(const void *)&gInstructions[2266]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2261]
|
(const void *)&gInstructions[2268]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2263]
|
(const void *)&gInstructions[2270]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2266]
|
(const void *)&gInstructions[2273]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2430]
|
(const void *)&gInstructions[2437]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2431]
|
(const void *)&gInstructions[2438]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_90_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_90_w =
|
||||||
@ -564,13 +564,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2433]
|
(const void *)&gInstructions[2440]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2434]
|
(const void *)&gInstructions[2441]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_92_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_92_w =
|
||||||
@ -585,13 +585,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2436]
|
(const void *)&gInstructions[2443]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2437]
|
(const void *)&gInstructions[2444]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_93_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_93_w =
|
||||||
@ -606,13 +606,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2439]
|
(const void *)&gInstructions[2446]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2440]
|
(const void *)&gInstructions[2447]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_91_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_91_w =
|
||||||
@ -627,13 +627,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2447]
|
(const void *)&gInstructions[2454]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2448]
|
(const void *)&gInstructions[2455]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_98_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_98_w =
|
||||||
@ -648,13 +648,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2449]
|
(const void *)&gInstructions[2456]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2450]
|
(const void *)&gInstructions[2457]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
|
||||||
@ -669,13 +669,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2451]
|
(const void *)&gInstructions[2458]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2452]
|
(const void *)&gInstructions[2459]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
|
||||||
@ -690,13 +690,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2453]
|
(const void *)&gInstructions[2460]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2454]
|
(const void *)&gInstructions[2461]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_99_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_99_w =
|
||||||
@ -711,13 +711,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2455]
|
(const void *)&gInstructions[2462]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2456]
|
(const void *)&gInstructions[2463]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_94_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_94_w =
|
||||||
@ -732,13 +732,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2457]
|
(const void *)&gInstructions[2464]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2468]
|
(const void *)&gInstructions[2475]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_95_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_95_w =
|
||||||
@ -753,13 +753,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2458]
|
(const void *)&gInstructions[2465]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2459]
|
(const void *)&gInstructions[2466]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_96_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_96_w =
|
||||||
@ -774,13 +774,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2466]
|
(const void *)&gInstructions[2473]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2467]
|
(const void *)&gInstructions[2474]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_09_97_w =
|
const ND_TABLE_VEX_W gXopTable_root_09_97_w =
|
||||||
@ -1058,13 +1058,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2117]
|
(const void *)&gInstructions[2118]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2118]
|
(const void *)&gInstructions[2119]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
|
const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
|
||||||
@ -1079,133 +1079,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2147]
|
(const void *)&gInstructions[2148]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2148]
|
(const void *)&gInstructions[2149]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2153]
|
(const void *)&gInstructions[2154]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2154]
|
(const void *)&gInstructions[2155]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2155]
|
(const void *)&gInstructions[2156]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2156]
|
(const void *)&gInstructions[2157]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2157]
|
(const void *)&gInstructions[2158]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2158]
|
(const void *)&gInstructions[2159]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2281]
|
(const void *)&gInstructions[2288]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2282]
|
(const void *)&gInstructions[2289]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2283]
|
(const void *)&gInstructions[2290]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2284]
|
(const void *)&gInstructions[2291]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2285]
|
(const void *)&gInstructions[2292]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2286]
|
(const void *)&gInstructions[2293]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2287]
|
(const void *)&gInstructions[2294]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2288]
|
(const void *)&gInstructions[2295]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2289]
|
(const void *)&gInstructions[2296]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2290]
|
(const void *)&gInstructions[2297]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2291]
|
(const void *)&gInstructions[2298]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2292]
|
(const void *)&gInstructions[2299]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2419]
|
(const void *)&gInstructions[2426]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2420]
|
(const void *)&gInstructions[2427]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
|
const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
|
||||||
@ -1220,25 +1220,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
|
|||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2429]
|
(const void *)&gInstructions[2436]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2432]
|
(const void *)&gInstructions[2439]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2435]
|
(const void *)&gInstructions[2442]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf =
|
const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf =
|
||||||
{
|
{
|
||||||
ND_ILUT_INSTRUCTION,
|
ND_ILUT_INSTRUCTION,
|
||||||
(const void *)&gInstructions[2438]
|
(const void *)&gInstructions[2445]
|
||||||
};
|
};
|
||||||
|
|
||||||
const ND_TABLE_OPCODE gXopTable_root_08_opcode =
|
const ND_TABLE_OPCODE gXopTable_root_08_opcode =
|
||||||
|
|||||||
35
bddisasm_test/x86/avx/avxvnniint16_64.asm
Normal file
35
bddisasm_test/x86/avx/avxvnniint16_64.asm
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
bits 64
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x78, 0xd2, 0xc7 ; VPDPWUUD xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x78, 0xd2, 0x01 ; VPDPWUUD xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x78, 0xd3, 0xc7 ; VPDPWUUDS xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x78, 0xd3, 0x01 ; VPDPWUUDS xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x79, 0xd2, 0xc7 ; VPDPWUSD xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x79, 0xd2, 0x01 ; VPDPWUSD xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x79, 0xd3, 0xc7 ; VPDPWUSDS xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x79, 0xd3, 0x01 ; VPDPWUSDS xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7a, 0xd2, 0xc7 ; VPDPWSUD xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x7a, 0xd2, 0x01 ; VPDPWSUD xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x7a, 0xd3, 0xc7 ; VPDPWSUDS xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x7a, 0xd3, 0x01 ; VPDPWSUDS xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7c, 0xd2, 0xc7 ; VPDPWUUD ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7c, 0xd2, 0x01 ; VPDPWUUD ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x7c, 0xd3, 0xc7 ; VPDPWUUDS ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7c, 0xd3, 0x01 ; VPDPWUUDS ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7d, 0xd2, 0xc7 ; VPDPWUSD ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7d, 0xd2, 0x01 ; VPDPWUSD ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x7d, 0xd3, 0xc7 ; VPDPWUSDS ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7d, 0xd3, 0x01 ; VPDPWUSDS ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7e, 0xd2, 0xc7 ; VPDPWSUD ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7e, 0xd2, 0x01 ; VPDPWSUD ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x7e, 0xd3, 0xc7 ; VPDPWSUDS ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7e, 0xd3, 0x01 ; VPDPWSUDS ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
444
bddisasm_test/x86/avx/avxvnniint16_64.result
Normal file
444
bddisasm_test/x86/avx/avxvnniint16_64.result
Normal file
@ -0,0 +1,444 @@
|
|||||||
|
0000000000000000 c46278d2c7 VPDPWUUD xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000005 c46278d201 VPDPWUUD xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000000A c46278d3c7 VPDPWUUDS xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000000F c46278d301 VPDPWUUDS xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000014 c46279d2c7 VPDPWUSD xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000019 c46279d201 VPDPWUSD xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000001E c46279d3c7 VPDPWUSDS xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000023 c46279d301 VPDPWUSDS xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000028 c4627ad2c7 VPDPWSUD xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000002D c4627ad201 VPDPWSUD xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000032 c4627ad3c7 VPDPWSUDS xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000037 c4627ad301 VPDPWSUDS xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000003C c4627cd2c7 VPDPWUUD ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000041 c4627cd201 VPDPWUUD ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000046 c4627cd3c7 VPDPWUUDS ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000004B c4627cd301 VPDPWUUDS ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000050 c4627dd2c7 VPDPWUSD ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000055 c4627dd201 VPDPWUSD ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000005A c4627dd3c7 VPDPWUSDS ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000005F c4627dd301 VPDPWUSDS ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000064 c4627ed2c7 VPDPWSUD ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000069 c4627ed201 VPDPWSUD ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000006E c4627ed3c7 VPDPWSUDS ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000073 c4627ed301 VPDPWSUDS ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
1
bddisasm_test/x86/avx/avxvnniint16_64.test
Normal file
1
bddisasm_test/x86/avx/avxvnniint16_64.test
Normal file
@ -0,0 +1 @@
|
|||||||
|
ﾄbxﾒﾇﾄbxﾒﾄbxﾓﾇﾄbxﾓﾄbyﾒﾇﾄbyﾒﾄbyﾓﾇﾄbyﾓﾄbzﾒﾇﾄbzﾒﾄbzﾓﾇﾄbzﾓﾄb|ﾒﾇﾄb|ﾒﾄb|ﾓﾇﾄb|ﾓﾄb}ﾒﾇﾄb}ﾒﾄb}ﾓﾇﾄb}ﾓﾄb~ﾒﾇﾄb~ﾒﾄb~ﾓﾇﾄb~ﾓ
|
||||||
7
bddisasm_test/x86/sha512/sha512_64.asm
Normal file
7
bddisasm_test/x86/sha512/sha512_64.asm
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
bits 64
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7f, 0xcb, 0xc7 ; VSHA512RNDS2 ymm8, ymm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x7f, 0xcc, 0xc7 ; VSHA512MSG1 ymm8, xmm7
|
||||||
|
db 0xc4, 0x62, 0x7f, 0xcd, 0xc7 ; VSHA512MSG2 ymm8, ymm7
|
||||||
|
db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
|
||||||
|
db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
|
||||||
91
bddisasm_test/x86/sha512/sha512_64.result
Normal file
91
bddisasm_test/x86/sha512/sha512_64.result
Normal file
@ -0,0 +1,91 @@
|
|||||||
|
0000000000000000 c4627fcbc7 VSHA512RNDS2 ymm8, ymm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000005 c4627fccc7 VSHA512MSG1 ymm8, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000000A c4627fcdc7 VSHA512MSG2 ymm8, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000000F c46379dec7ef VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||||
|
|
||||||
|
0000000000000015 c46379de01ef VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||||
|
|
||||||
1
bddisasm_test/x86/sha512/sha512_64.test
Normal file
1
bddisasm_test/x86/sha512/sha512_64.test
Normal file
@ -0,0 +1 @@
|
|||||||
|
ΔbΛΗΔbΜΗΔbΝΗΔcyήΗοΔcyήο
|
||||||
19
bddisasm_test/x86/sm/sm_64.asm
Normal file
19
bddisasm_test/x86/sm/sm_64.asm
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
bits 64
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x78, 0xda, 0xc7 ; VSM3MSG1 xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x78, 0xda, 0x01 ; VSM3MSG1 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x79, 0xda, 0xc7 ; VSM3MSG2 xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x79, 0xda, 0x01 ; VSM3MSG2 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7a, 0xda, 0xc7 ; VSM4KEY4 xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x7a, 0xda, 0x01 ; VSM4KEY4 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x7b, 0xda, 0xc7 ; VSM4RNDS4 xmm8, xmm0, xmm7
|
||||||
|
db 0xc4, 0x62, 0x7b, 0xda, 0x01 ; VSM4RNDS4 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x62, 0x7e, 0xda, 0xc7 ; VSM4KEY4 ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7e, 0xda, 0x01 ; VSM4KEY4 ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
db 0xc4, 0x62, 0x7f, 0xda, 0xc7 ; VSM4RNDS4 ymm8, ymm0, ymm7
|
||||||
|
db 0xc4, 0x62, 0x7f, 0xda, 0x01 ; VSM4RNDS4 ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
|
||||||
|
db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
|
||||||
|
db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
|
||||||
261
bddisasm_test/x86/sm/sm_64.result
Normal file
261
bddisasm_test/x86/sm/sm_64.result
Normal file
@ -0,0 +1,261 @@
|
|||||||
|
0000000000000000 c46278dac7 VSM3MSG1 xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000005 c46278da01 VSM3MSG1 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000000A c46279dac7 VSM3MSG2 xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000000F c46279da01 VSM3MSG2 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000014 c4627adac7 VSM4KEY4 xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000019 c4627ada01 VSM4KEY4 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000001E c4627bdac7 VSM4RNDS4 xmm8, xmm0, xmm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000023 c4627bda01 VSM4RNDS4 xmm8, xmm0, xmmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000028 c4627edac7 VSM4KEY4 ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
000000000000002D c4627eda01 VSM4KEY4 ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
0000000000000032 c4627fdac7 VSM4RNDS4 ymm8, ymm0, ymm7
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 7, RegCount: 1
|
||||||
|
|
||||||
|
0000000000000037 c4627fda01 VSM4RNDS4 ymm8, ymm0, ymmword ptr [rcx]
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||||
|
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||||
|
Exception class: SSE/VEX, exception type: 6
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
|
||||||
|
000000000000003C c46379dec7ef VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 7, RegCount: 1
|
||||||
|
Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||||
|
|
||||||
|
0000000000000042 c46379de01ef VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||||
|
ISA Set: SM3, Ins cat: SM3, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
|
||||||
|
Exception class: SSE/VEX, exception type: 4
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: yes, R2: yes, R3: yes
|
||||||
|
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 8, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||||
|
Segment: 3, Base: 1,
|
||||||
|
Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||||
|
|
||||||
1
bddisasm_test/x86/sm/sm_64.test
Normal file
1
bddisasm_test/x86/sm/sm_64.test
Normal file
@ -0,0 +1 @@
|
|||||||
|
ΔbxΪΗΔbxΪΔbyΪΗΔbyΪΔbzΪΗΔbzΪΔb{ΪΗΔb{ΪΔb~ΪΗΔb~ΪΔbΪΗΔbΪΔcyήΗοΔcyήο
|
||||||
3
bddisasm_test/x86/tse/tse_64.asm
Normal file
3
bddisasm_test/x86/tse/tse_64.asm
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
bits 64
|
||||||
|
|
||||||
|
db 0x0f, 0x01, 0xc7 ; PBNDKB
|
||||||
20
bddisasm_test/x86/tse/tse_64.result
Normal file
20
bddisasm_test/x86/tse/tse_64.result
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
0000000000000000 0f01c7 PBNDKB
|
||||||
|
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||||
|
ISA Set: TSE, Ins cat: SYSTEM, CET tracked: no
|
||||||
|
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ebx, bit: 1
|
||||||
|
FLAGS access
|
||||||
|
CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
|
||||||
|
Valid modes
|
||||||
|
R0: yes, R1: no, R2: no, R3: no
|
||||||
|
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||||
|
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||||
|
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||||
|
Valid prefixes
|
||||||
|
REP: no, REPcc: no, LOCK: no
|
||||||
|
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||||
|
BND: no, BHINT: no, DNT: no
|
||||||
|
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1
|
||||||
|
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||||
|
Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
|
||||||
|
|
||||||
1
bddisasm_test/x86/tse/tse_64.test
Normal file
1
bddisasm_test/x86/tse/tse_64.test
Normal file
@ -0,0 +1 @@
|
|||||||
|
ا
|
||||||
@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
|
|||||||
from codecs import open
|
from codecs import open
|
||||||
|
|
||||||
VERSION = (0, 3, 0)
|
VERSION = (0, 3, 0)
|
||||||
LIBRARY_VERSION = (1, 37, 0)
|
LIBRARY_VERSION = (1, 38, 0)
|
||||||
DIR_INCLUDE = '../../inc'
|
DIR_INCLUDE = '../../inc'
|
||||||
|
|
||||||
here = os.path.abspath(os.path.dirname(__file__))
|
here = os.path.abspath(os.path.dirname(__file__))
|
||||||
|
|||||||
@ -136,6 +136,7 @@ set_to_string(
|
|||||||
case ND_SET_AVXNECONVERT: return "AVXNECONVERT";
|
case ND_SET_AVXNECONVERT: return "AVXNECONVERT";
|
||||||
case ND_SET_AVXVNNI: return "AVXVNNI";
|
case ND_SET_AVXVNNI: return "AVXVNNI";
|
||||||
case ND_SET_AVXVNNIINT8: return "AVXVNNIINT8";
|
case ND_SET_AVXVNNIINT8: return "AVXVNNIINT8";
|
||||||
|
case ND_SET_AVXVNNIINT16: return "AVXVNNIINT16";
|
||||||
case ND_SET_BMI1: return "BMI1";
|
case ND_SET_BMI1: return "BMI1";
|
||||||
case ND_SET_BMI2: return "BMI2";
|
case ND_SET_BMI2: return "BMI2";
|
||||||
case ND_SET_CET_SS: return "CET_SS";
|
case ND_SET_CET_SS: return "CET_SS";
|
||||||
@ -201,6 +202,9 @@ set_to_string(
|
|||||||
case ND_SET_SERIALIZE: return "SERIALIZE";
|
case ND_SET_SERIALIZE: return "SERIALIZE";
|
||||||
case ND_SET_SGX: return "SGX";
|
case ND_SET_SGX: return "SGX";
|
||||||
case ND_SET_SHA: return "SHA";
|
case ND_SET_SHA: return "SHA";
|
||||||
|
case ND_SET_SHA512: return "SHA512";
|
||||||
|
case ND_SET_SM3: return "SM3";
|
||||||
|
case ND_SET_SM4: return "SM4";
|
||||||
case ND_SET_SMAP: return "SMAP";
|
case ND_SET_SMAP: return "SMAP";
|
||||||
case ND_SET_SMX: return "SMX";
|
case ND_SET_SMX: return "SMX";
|
||||||
case ND_SET_SNP: return "SNP";
|
case ND_SET_SNP: return "SNP";
|
||||||
@ -214,6 +218,7 @@ set_to_string(
|
|||||||
case ND_SET_SVM: return "SVM";
|
case ND_SET_SVM: return "SVM";
|
||||||
case ND_SET_TBM: return "TBM";
|
case ND_SET_TBM: return "TBM";
|
||||||
case ND_SET_TDX: return "TDX";
|
case ND_SET_TDX: return "TDX";
|
||||||
|
case ND_SET_TSE: return "TSE";
|
||||||
case ND_SET_TSX: return "TSX";
|
case ND_SET_TSX: return "TSX";
|
||||||
case ND_SET_TSXLDTRK: return "TSXLDTRK";
|
case ND_SET_TSXLDTRK: return "TSXLDTRK";
|
||||||
case ND_SET_UD: return "UD";
|
case ND_SET_UD: return "UD";
|
||||||
@ -258,6 +263,7 @@ category_to_string(
|
|||||||
case ND_CAT_AVXIFMA: return "AVXIFMA";
|
case ND_CAT_AVXIFMA: return "AVXIFMA";
|
||||||
case ND_CAT_AVXVNNI: return "AVXVNNI";
|
case ND_CAT_AVXVNNI: return "AVXVNNI";
|
||||||
case ND_CAT_AVXVNNIINT8: return "AVXVNNIINT8";
|
case ND_CAT_AVXVNNIINT8: return "AVXVNNIINT8";
|
||||||
|
case ND_CAT_AVXVNNIINT16: return "AVXVNNIINT16";
|
||||||
case ND_CAT_AVXNECONVERT: return "AVXNECONVERT";
|
case ND_CAT_AVXNECONVERT: return "AVXNECONVERT";
|
||||||
case ND_CAT_BITBYTE: return "BITBYTE";
|
case ND_CAT_BITBYTE: return "BITBYTE";
|
||||||
case ND_CAT_BLEND: return "BLEND";
|
case ND_CAT_BLEND: return "BLEND";
|
||||||
@ -321,7 +327,10 @@ category_to_string(
|
|||||||
case ND_CAT_SEMAPHORE: return "SEMAPHORE";
|
case ND_CAT_SEMAPHORE: return "SEMAPHORE";
|
||||||
case ND_CAT_SGX: return "SGX";
|
case ND_CAT_SGX: return "SGX";
|
||||||
case ND_CAT_SHA: return "SHA";
|
case ND_CAT_SHA: return "SHA";
|
||||||
|
case ND_CAT_SHA512: return "SHA512";
|
||||||
case ND_CAT_SHIFT: return "SHIFT";
|
case ND_CAT_SHIFT: return "SHIFT";
|
||||||
|
case ND_CAT_SM3: return "SM3";
|
||||||
|
case ND_CAT_SM4: return "SM4";
|
||||||
case ND_CAT_SMAP: return "SMAP";
|
case ND_CAT_SMAP: return "SMAP";
|
||||||
case ND_CAT_SSE: return "SSE";
|
case ND_CAT_SSE: return "SSE";
|
||||||
case ND_CAT_SSE2: return "SSE2";
|
case ND_CAT_SSE2: return "SSE2";
|
||||||
|
|||||||
@ -70,7 +70,9 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_INVALID: return "invalid";
|
case ND_INS_INVALID: return "invalid";
|
||||||
case ND_INS_AAA: return "aaa";
|
case ND_INS_AAA: return "aaa";
|
||||||
case ND_INS_AAD: return "aad";
|
case ND_INS_AAD: return "aad";
|
||||||
|
case ND_INS_AADD: return "aadd";
|
||||||
case ND_INS_AAM: return "aam";
|
case ND_INS_AAM: return "aam";
|
||||||
|
case ND_INS_AAND: return "aand";
|
||||||
case ND_INS_AAS: return "aas";
|
case ND_INS_AAS: return "aas";
|
||||||
case ND_INS_ADC: return "adc";
|
case ND_INS_ADC: return "adc";
|
||||||
case ND_INS_ADCX: return "adcx";
|
case ND_INS_ADCX: return "adcx";
|
||||||
@ -85,15 +87,15 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_AESDEC: return "aesdec";
|
case ND_INS_AESDEC: return "aesdec";
|
||||||
case ND_INS_AESDEC128KL: return "aesdec128kl";
|
case ND_INS_AESDEC128KL: return "aesdec128kl";
|
||||||
case ND_INS_AESDEC256KL: return "aesdec256kl";
|
case ND_INS_AESDEC256KL: return "aesdec256kl";
|
||||||
|
case ND_INS_AESDECLAST: return "aesdeclast";
|
||||||
case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl";
|
case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl";
|
||||||
case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl";
|
case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl";
|
||||||
case ND_INS_AESDECLAST: return "aesdeclast";
|
|
||||||
case ND_INS_AESENC: return "aesenc";
|
case ND_INS_AESENC: return "aesenc";
|
||||||
case ND_INS_AESENC128KL: return "aesenc128kl";
|
case ND_INS_AESENC128KL: return "aesenc128kl";
|
||||||
case ND_INS_AESENC256KL: return "aesenc256kl";
|
case ND_INS_AESENC256KL: return "aesenc256kl";
|
||||||
|
case ND_INS_AESENCLAST: return "aesenclast";
|
||||||
case ND_INS_AESENCWIDE128KL: return "aesencwide128kl";
|
case ND_INS_AESENCWIDE128KL: return "aesencwide128kl";
|
||||||
case ND_INS_AESENCWIDE256KL: return "aesencwide256kl";
|
case ND_INS_AESENCWIDE256KL: return "aesencwide256kl";
|
||||||
case ND_INS_AESENCLAST: return "aesenclast";
|
|
||||||
case ND_INS_AESIMC: return "aesimc";
|
case ND_INS_AESIMC: return "aesimc";
|
||||||
case ND_INS_AESKEYGENASSIST: return "aeskeygenassist";
|
case ND_INS_AESKEYGENASSIST: return "aeskeygenassist";
|
||||||
case ND_INS_ALTINST: return "altinst";
|
case ND_INS_ALTINST: return "altinst";
|
||||||
@ -103,7 +105,9 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_ANDNPS: return "andnps";
|
case ND_INS_ANDNPS: return "andnps";
|
||||||
case ND_INS_ANDPD: return "andpd";
|
case ND_INS_ANDPD: return "andpd";
|
||||||
case ND_INS_ANDPS: return "andps";
|
case ND_INS_ANDPS: return "andps";
|
||||||
|
case ND_INS_AOR: return "aor";
|
||||||
case ND_INS_ARPL: return "arpl";
|
case ND_INS_ARPL: return "arpl";
|
||||||
|
case ND_INS_AXOR: return "axor";
|
||||||
case ND_INS_BEXTR: return "bextr";
|
case ND_INS_BEXTR: return "bextr";
|
||||||
case ND_INS_BLCFILL: return "blcfill";
|
case ND_INS_BLCFILL: return "blcfill";
|
||||||
case ND_INS_BLCI: return "blci";
|
case ND_INS_BLCI: return "blci";
|
||||||
@ -154,19 +158,36 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_CLI: return "cli";
|
case ND_INS_CLI: return "cli";
|
||||||
case ND_INS_CLRSSBSY: return "clrssbsy";
|
case ND_INS_CLRSSBSY: return "clrssbsy";
|
||||||
case ND_INS_CLTS: return "clts";
|
case ND_INS_CLTS: return "clts";
|
||||||
|
case ND_INS_CLUI: return "clui";
|
||||||
case ND_INS_CLWB: return "clwb";
|
case ND_INS_CLWB: return "clwb";
|
||||||
case ND_INS_CLZERO: return "clzero";
|
case ND_INS_CLZERO: return "clzero";
|
||||||
case ND_INS_CMC: return "cmc";
|
case ND_INS_CMC: return "cmc";
|
||||||
case ND_INS_CMOVcc: return "cmovcc";
|
case ND_INS_CMOVcc: return "cmovcc";
|
||||||
case ND_INS_CMP: return "cmp";
|
case ND_INS_CMP: return "cmp";
|
||||||
|
case ND_INS_CMPBEXADD: return "cmpbexadd";
|
||||||
|
case ND_INS_CMPCXADD: return "cmpcxadd";
|
||||||
|
case ND_INS_CMPLEXADD: return "cmplexadd";
|
||||||
|
case ND_INS_CMPLXADD: return "cmplxadd";
|
||||||
|
case ND_INS_CMPNBEXADD: return "cmpnbexadd";
|
||||||
|
case ND_INS_CMPNCXADD: return "cmpncxadd";
|
||||||
|
case ND_INS_CMPNLEXADD: return "cmpnlexadd";
|
||||||
|
case ND_INS_CMPNLXADD: return "cmpnlxadd";
|
||||||
|
case ND_INS_CMPNOXADD: return "cmpnoxadd";
|
||||||
|
case ND_INS_CMPNPXADD: return "cmpnpxadd";
|
||||||
|
case ND_INS_CMPNSXADD: return "cmpnsxadd";
|
||||||
|
case ND_INS_CMPNZXADD: return "cmpnzxadd";
|
||||||
|
case ND_INS_CMPOXADD: return "cmpoxadd";
|
||||||
case ND_INS_CMPPD: return "cmppd";
|
case ND_INS_CMPPD: return "cmppd";
|
||||||
case ND_INS_CMPPS: return "cmpps";
|
case ND_INS_CMPPS: return "cmpps";
|
||||||
|
case ND_INS_CMPPXADD: return "cmppxadd";
|
||||||
case ND_INS_CMPS: return "cmps";
|
case ND_INS_CMPS: return "cmps";
|
||||||
case ND_INS_CMPSD: return "cmpsd";
|
case ND_INS_CMPSD: return "cmpsd";
|
||||||
case ND_INS_CMPSS: return "cmpss";
|
case ND_INS_CMPSS: return "cmpss";
|
||||||
|
case ND_INS_CMPSXADD: return "cmpsxadd";
|
||||||
case ND_INS_CMPXCHG: return "cmpxchg";
|
case ND_INS_CMPXCHG: return "cmpxchg";
|
||||||
case ND_INS_CMPXCHG16B: return "cmpxchg16b";
|
case ND_INS_CMPXCHG16B: return "cmpxchg16b";
|
||||||
case ND_INS_CMPXCHG8B: return "cmpxchg8b";
|
case ND_INS_CMPXCHG8B: return "cmpxchg8b";
|
||||||
|
case ND_INS_CMPZXADD: return "cmpzxadd";
|
||||||
case ND_INS_COMISD: return "comisd";
|
case ND_INS_COMISD: return "comisd";
|
||||||
case ND_INS_COMISS: return "comiss";
|
case ND_INS_COMISS: return "comiss";
|
||||||
case ND_INS_CPUID: return "cpuid";
|
case ND_INS_CPUID: return "cpuid";
|
||||||
@ -328,6 +349,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_HADDPD: return "haddpd";
|
case ND_INS_HADDPD: return "haddpd";
|
||||||
case ND_INS_HADDPS: return "haddps";
|
case ND_INS_HADDPS: return "haddps";
|
||||||
case ND_INS_HLT: return "hlt";
|
case ND_INS_HLT: return "hlt";
|
||||||
|
case ND_INS_HRESET: return "hreset";
|
||||||
case ND_INS_HSUBPD: return "hsubpd";
|
case ND_INS_HSUBPD: return "hsubpd";
|
||||||
case ND_INS_HSUBPS: return "hsubps";
|
case ND_INS_HSUBPS: return "hsubps";
|
||||||
case ND_INS_IDIV: return "idiv";
|
case ND_INS_IDIV: return "idiv";
|
||||||
@ -501,6 +523,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_PAVGW: return "pavgw";
|
case ND_INS_PAVGW: return "pavgw";
|
||||||
case ND_INS_PBLENDVB: return "pblendvb";
|
case ND_INS_PBLENDVB: return "pblendvb";
|
||||||
case ND_INS_PBLENDW: return "pblendw";
|
case ND_INS_PBLENDW: return "pblendw";
|
||||||
|
case ND_INS_PBNDKB: return "pbndkb";
|
||||||
case ND_INS_PCLMULQDQ: return "pclmulqdq";
|
case ND_INS_PCLMULQDQ: return "pclmulqdq";
|
||||||
case ND_INS_PCMPEQB: return "pcmpeqb";
|
case ND_INS_PCMPEQB: return "pcmpeqb";
|
||||||
case ND_INS_PCMPEQD: return "pcmpeqd";
|
case ND_INS_PCMPEQD: return "pcmpeqd";
|
||||||
@ -598,6 +621,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_POR: return "por";
|
case ND_INS_POR: return "por";
|
||||||
case ND_INS_PREFETCH: return "prefetch";
|
case ND_INS_PREFETCH: return "prefetch";
|
||||||
case ND_INS_PREFETCHE: return "prefetche";
|
case ND_INS_PREFETCHE: return "prefetche";
|
||||||
|
case ND_INS_PREFETCHIT0: return "prefetchit0";
|
||||||
|
case ND_INS_PREFETCHIT1: return "prefetchit1";
|
||||||
case ND_INS_PREFETCHM: return "prefetchm";
|
case ND_INS_PREFETCHM: return "prefetchm";
|
||||||
case ND_INS_PREFETCHNTA: return "prefetchnta";
|
case ND_INS_PREFETCHNTA: return "prefetchnta";
|
||||||
case ND_INS_PREFETCHT0: return "prefetcht0";
|
case ND_INS_PREFETCHT0: return "prefetcht0";
|
||||||
@ -657,6 +682,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_RDFSBASE: return "rdfsbase";
|
case ND_INS_RDFSBASE: return "rdfsbase";
|
||||||
case ND_INS_RDGSBASE: return "rdgsbase";
|
case ND_INS_RDGSBASE: return "rdgsbase";
|
||||||
case ND_INS_RDMSR: return "rdmsr";
|
case ND_INS_RDMSR: return "rdmsr";
|
||||||
|
case ND_INS_RDMSRLIST: return "rdmsrlist";
|
||||||
case ND_INS_RDPID: return "rdpid";
|
case ND_INS_RDPID: return "rdpid";
|
||||||
case ND_INS_RDPKRU: return "rdpkru";
|
case ND_INS_RDPKRU: return "rdpkru";
|
||||||
case ND_INS_RDPMC: return "rdpmc";
|
case ND_INS_RDPMC: return "rdpmc";
|
||||||
@ -669,6 +695,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_RETF: return "retf";
|
case ND_INS_RETF: return "retf";
|
||||||
case ND_INS_RETN: return "retn";
|
case ND_INS_RETN: return "retn";
|
||||||
case ND_INS_RMPADJUST: return "rmpadjust";
|
case ND_INS_RMPADJUST: return "rmpadjust";
|
||||||
|
case ND_INS_RMPQUERY: return "rmpquery";
|
||||||
case ND_INS_RMPUPDATE: return "rmpupdate";
|
case ND_INS_RMPUPDATE: return "rmpupdate";
|
||||||
case ND_INS_ROL: return "rol";
|
case ND_INS_ROL: return "rol";
|
||||||
case ND_INS_ROR: return "ror";
|
case ND_INS_ROR: return "ror";
|
||||||
@ -696,6 +723,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_SEAMOPS: return "seamops";
|
case ND_INS_SEAMOPS: return "seamops";
|
||||||
case ND_INS_SEAMCALL: return "seamcall";
|
case ND_INS_SEAMCALL: return "seamcall";
|
||||||
case ND_INS_SEAMRET: return "seamret";
|
case ND_INS_SEAMRET: return "seamret";
|
||||||
|
case ND_INS_SENDUIPI: return "senduipi";
|
||||||
case ND_INS_SERIALIZE: return "serialize";
|
case ND_INS_SERIALIZE: return "serialize";
|
||||||
case ND_INS_SETSSBSY: return "setssbsy";
|
case ND_INS_SETSSBSY: return "setssbsy";
|
||||||
case ND_INS_SETcc: return "setcc";
|
case ND_INS_SETcc: return "setcc";
|
||||||
@ -736,6 +764,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_STOS: return "stos";
|
case ND_INS_STOS: return "stos";
|
||||||
case ND_INS_STR: return "str";
|
case ND_INS_STR: return "str";
|
||||||
case ND_INS_STTILECFG: return "sttilecfg";
|
case ND_INS_STTILECFG: return "sttilecfg";
|
||||||
|
case ND_INS_STUI: return "stui";
|
||||||
case ND_INS_SUB: return "sub";
|
case ND_INS_SUB: return "sub";
|
||||||
case ND_INS_SUBPD: return "subpd";
|
case ND_INS_SUBPD: return "subpd";
|
||||||
case ND_INS_SUBPS: return "subps";
|
case ND_INS_SUBPS: return "subps";
|
||||||
@ -750,13 +779,17 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_SYSEXIT: return "sysexit";
|
case ND_INS_SYSEXIT: return "sysexit";
|
||||||
case ND_INS_SYSRET: return "sysret";
|
case ND_INS_SYSRET: return "sysret";
|
||||||
case ND_INS_T1MSKC: return "t1mskc";
|
case ND_INS_T1MSKC: return "t1mskc";
|
||||||
|
case ND_INS_TCMMIMFP16PS: return "tcmmimfp16ps";
|
||||||
|
case ND_INS_TCMMRLFP16PS: return "tcmmrlfp16ps";
|
||||||
case ND_INS_TDCALL: return "tdcall";
|
case ND_INS_TDCALL: return "tdcall";
|
||||||
case ND_INS_TDPBF16PS: return "tdpbf16ps";
|
case ND_INS_TDPBF16PS: return "tdpbf16ps";
|
||||||
case ND_INS_TDPBSSD: return "tdpbssd";
|
case ND_INS_TDPBSSD: return "tdpbssd";
|
||||||
case ND_INS_TDPBSUD: return "tdpbsud";
|
case ND_INS_TDPBSUD: return "tdpbsud";
|
||||||
case ND_INS_TDPBUSD: return "tdpbusd";
|
case ND_INS_TDPBUSD: return "tdpbusd";
|
||||||
case ND_INS_TDPBUUD: return "tdpbuud";
|
case ND_INS_TDPBUUD: return "tdpbuud";
|
||||||
|
case ND_INS_TDPFP16PS: return "tdpfp16ps";
|
||||||
case ND_INS_TEST: return "test";
|
case ND_INS_TEST: return "test";
|
||||||
|
case ND_INS_TESTUI: return "testui";
|
||||||
case ND_INS_TILELOADD: return "tileloadd";
|
case ND_INS_TILELOADD: return "tileloadd";
|
||||||
case ND_INS_TILELOADDT1: return "tileloaddt1";
|
case ND_INS_TILELOADDT1: return "tileloaddt1";
|
||||||
case ND_INS_TILERELEASE: return "tilerelease";
|
case ND_INS_TILERELEASE: return "tilerelease";
|
||||||
@ -771,6 +804,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_UD0: return "ud0";
|
case ND_INS_UD0: return "ud0";
|
||||||
case ND_INS_UD1: return "ud1";
|
case ND_INS_UD1: return "ud1";
|
||||||
case ND_INS_UD2: return "ud2";
|
case ND_INS_UD2: return "ud2";
|
||||||
|
case ND_INS_UIRET: return "uiret";
|
||||||
case ND_INS_UMONITOR: return "umonitor";
|
case ND_INS_UMONITOR: return "umonitor";
|
||||||
case ND_INS_UMWAIT: return "umwait";
|
case ND_INS_UMWAIT: return "umwait";
|
||||||
case ND_INS_UNPCKHPD: return "unpckhpd";
|
case ND_INS_UNPCKHPD: return "unpckhpd";
|
||||||
@ -782,8 +816,10 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_V4FNMADDPS: return "v4fnmaddps";
|
case ND_INS_V4FNMADDPS: return "v4fnmaddps";
|
||||||
case ND_INS_V4FNMADDSS: return "v4fnmaddss";
|
case ND_INS_V4FNMADDSS: return "v4fnmaddss";
|
||||||
case ND_INS_VADDPD: return "vaddpd";
|
case ND_INS_VADDPD: return "vaddpd";
|
||||||
|
case ND_INS_VADDPH: return "vaddph";
|
||||||
case ND_INS_VADDPS: return "vaddps";
|
case ND_INS_VADDPS: return "vaddps";
|
||||||
case ND_INS_VADDSD: return "vaddsd";
|
case ND_INS_VADDSD: return "vaddsd";
|
||||||
|
case ND_INS_VADDSH: return "vaddsh";
|
||||||
case ND_INS_VADDSS: return "vaddss";
|
case ND_INS_VADDSS: return "vaddss";
|
||||||
case ND_INS_VADDSUBPD: return "vaddsubpd";
|
case ND_INS_VADDSUBPD: return "vaddsubpd";
|
||||||
case ND_INS_VADDSUBPS: return "vaddsubps";
|
case ND_INS_VADDSUBPS: return "vaddsubps";
|
||||||
@ -799,6 +835,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VANDNPS: return "vandnps";
|
case ND_INS_VANDNPS: return "vandnps";
|
||||||
case ND_INS_VANDPD: return "vandpd";
|
case ND_INS_VANDPD: return "vandpd";
|
||||||
case ND_INS_VANDPS: return "vandps";
|
case ND_INS_VANDPS: return "vandps";
|
||||||
|
case ND_INS_VBCSTNEBF162PS: return "vbcstnebf162ps";
|
||||||
|
case ND_INS_VBCSTNESH2PS: return "vbcstnesh2ps";
|
||||||
case ND_INS_VBLENDMPD: return "vblendmpd";
|
case ND_INS_VBLENDMPD: return "vblendmpd";
|
||||||
case ND_INS_VBLENDMPS: return "vblendmps";
|
case ND_INS_VBLENDMPS: return "vblendmps";
|
||||||
case ND_INS_VBLENDPD: return "vblendpd";
|
case ND_INS_VBLENDPD: return "vblendpd";
|
||||||
@ -820,61 +858,102 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VBROADCASTSD: return "vbroadcastsd";
|
case ND_INS_VBROADCASTSD: return "vbroadcastsd";
|
||||||
case ND_INS_VBROADCASTSS: return "vbroadcastss";
|
case ND_INS_VBROADCASTSS: return "vbroadcastss";
|
||||||
case ND_INS_VCMPPD: return "vcmppd";
|
case ND_INS_VCMPPD: return "vcmppd";
|
||||||
|
case ND_INS_VCMPPH: return "vcmpph";
|
||||||
case ND_INS_VCMPPS: return "vcmpps";
|
case ND_INS_VCMPPS: return "vcmpps";
|
||||||
case ND_INS_VCMPSD: return "vcmpsd";
|
case ND_INS_VCMPSD: return "vcmpsd";
|
||||||
|
case ND_INS_VCMPSH: return "vcmpsh";
|
||||||
case ND_INS_VCMPSS: return "vcmpss";
|
case ND_INS_VCMPSS: return "vcmpss";
|
||||||
case ND_INS_VCOMISD: return "vcomisd";
|
case ND_INS_VCOMISD: return "vcomisd";
|
||||||
|
case ND_INS_VCOMISH: return "vcomish";
|
||||||
case ND_INS_VCOMISS: return "vcomiss";
|
case ND_INS_VCOMISS: return "vcomiss";
|
||||||
case ND_INS_VCOMPRESSPD: return "vcompresspd";
|
case ND_INS_VCOMPRESSPD: return "vcompresspd";
|
||||||
case ND_INS_VCOMPRESSPS: return "vcompressps";
|
case ND_INS_VCOMPRESSPS: return "vcompressps";
|
||||||
case ND_INS_VCVTDQ2PD: return "vcvtdq2pd";
|
case ND_INS_VCVTDQ2PD: return "vcvtdq2pd";
|
||||||
|
case ND_INS_VCVTDQ2PH: return "vcvtdq2ph";
|
||||||
case ND_INS_VCVTDQ2PS: return "vcvtdq2ps";
|
case ND_INS_VCVTDQ2PS: return "vcvtdq2ps";
|
||||||
case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16";
|
case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16";
|
||||||
|
case ND_INS_VCVTNEEBF162PS: return "vcvtneebf162ps";
|
||||||
|
case ND_INS_VCVTNEEPH2PS: return "vcvtneeph2ps";
|
||||||
|
case ND_INS_VCVTNEOBF162PS: return "vcvtneobf162ps";
|
||||||
|
case ND_INS_VCVTNEOPH2PS: return "vcvtneoph2ps";
|
||||||
case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16";
|
case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16";
|
||||||
case ND_INS_VCVTPD2DQ: return "vcvtpd2dq";
|
case ND_INS_VCVTPD2DQ: return "vcvtpd2dq";
|
||||||
|
case ND_INS_VCVTPD2PH: return "vcvtpd2ph";
|
||||||
case ND_INS_VCVTPD2PS: return "vcvtpd2ps";
|
case ND_INS_VCVTPD2PS: return "vcvtpd2ps";
|
||||||
case ND_INS_VCVTPD2QQ: return "vcvtpd2qq";
|
case ND_INS_VCVTPD2QQ: return "vcvtpd2qq";
|
||||||
case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq";
|
case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq";
|
||||||
case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq";
|
case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq";
|
||||||
|
case ND_INS_VCVTPH2DQ: return "vcvtph2dq";
|
||||||
|
case ND_INS_VCVTPH2PD: return "vcvtph2pd";
|
||||||
case ND_INS_VCVTPH2PS: return "vcvtph2ps";
|
case ND_INS_VCVTPH2PS: return "vcvtph2ps";
|
||||||
|
case ND_INS_VCVTPH2PSX: return "vcvtph2psx";
|
||||||
|
case ND_INS_VCVTPH2QQ: return "vcvtph2qq";
|
||||||
|
case ND_INS_VCVTPH2UDQ: return "vcvtph2udq";
|
||||||
|
case ND_INS_VCVTPH2UQQ: return "vcvtph2uqq";
|
||||||
|
case ND_INS_VCVTPH2UW: return "vcvtph2uw";
|
||||||
|
case ND_INS_VCVTPH2W: return "vcvtph2w";
|
||||||
case ND_INS_VCVTPS2DQ: return "vcvtps2dq";
|
case ND_INS_VCVTPS2DQ: return "vcvtps2dq";
|
||||||
case ND_INS_VCVTPS2PD: return "vcvtps2pd";
|
case ND_INS_VCVTPS2PD: return "vcvtps2pd";
|
||||||
case ND_INS_VCVTPS2PH: return "vcvtps2ph";
|
case ND_INS_VCVTPS2PH: return "vcvtps2ph";
|
||||||
|
case ND_INS_VCVTPS2PHX: return "vcvtps2phx";
|
||||||
case ND_INS_VCVTPS2QQ: return "vcvtps2qq";
|
case ND_INS_VCVTPS2QQ: return "vcvtps2qq";
|
||||||
case ND_INS_VCVTPS2UDQ: return "vcvtps2udq";
|
case ND_INS_VCVTPS2UDQ: return "vcvtps2udq";
|
||||||
case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq";
|
case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq";
|
||||||
case ND_INS_VCVTQQ2PD: return "vcvtqq2pd";
|
case ND_INS_VCVTQQ2PD: return "vcvtqq2pd";
|
||||||
|
case ND_INS_VCVTQQ2PH: return "vcvtqq2ph";
|
||||||
case ND_INS_VCVTQQ2PS: return "vcvtqq2ps";
|
case ND_INS_VCVTQQ2PS: return "vcvtqq2ps";
|
||||||
|
case ND_INS_VCVTSD2SH: return "vcvtsd2sh";
|
||||||
case ND_INS_VCVTSD2SI: return "vcvtsd2si";
|
case ND_INS_VCVTSD2SI: return "vcvtsd2si";
|
||||||
case ND_INS_VCVTSD2SS: return "vcvtsd2ss";
|
case ND_INS_VCVTSD2SS: return "vcvtsd2ss";
|
||||||
case ND_INS_VCVTSD2USI: return "vcvtsd2usi";
|
case ND_INS_VCVTSD2USI: return "vcvtsd2usi";
|
||||||
|
case ND_INS_VCVTSH2SD: return "vcvtsh2sd";
|
||||||
|
case ND_INS_VCVTSH2SI: return "vcvtsh2si";
|
||||||
|
case ND_INS_VCVTSH2SS: return "vcvtsh2ss";
|
||||||
|
case ND_INS_VCVTSH2USI: return "vcvtsh2usi";
|
||||||
case ND_INS_VCVTSI2SD: return "vcvtsi2sd";
|
case ND_INS_VCVTSI2SD: return "vcvtsi2sd";
|
||||||
|
case ND_INS_VCVTSI2SH: return "vcvtsi2sh";
|
||||||
case ND_INS_VCVTSI2SS: return "vcvtsi2ss";
|
case ND_INS_VCVTSI2SS: return "vcvtsi2ss";
|
||||||
case ND_INS_VCVTSS2SD: return "vcvtss2sd";
|
case ND_INS_VCVTSS2SD: return "vcvtss2sd";
|
||||||
|
case ND_INS_VCVTSS2SH: return "vcvtss2sh";
|
||||||
case ND_INS_VCVTSS2SI: return "vcvtss2si";
|
case ND_INS_VCVTSS2SI: return "vcvtss2si";
|
||||||
case ND_INS_VCVTSS2USI: return "vcvtss2usi";
|
case ND_INS_VCVTSS2USI: return "vcvtss2usi";
|
||||||
case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq";
|
case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq";
|
||||||
case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq";
|
case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq";
|
||||||
case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq";
|
case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq";
|
||||||
case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq";
|
case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq";
|
||||||
|
case ND_INS_VCVTTPH2DQ: return "vcvttph2dq";
|
||||||
|
case ND_INS_VCVTTPH2QQ: return "vcvttph2qq";
|
||||||
|
case ND_INS_VCVTTPH2UDQ: return "vcvttph2udq";
|
||||||
|
case ND_INS_VCVTTPH2UQQ: return "vcvttph2uqq";
|
||||||
|
case ND_INS_VCVTTPH2UW: return "vcvttph2uw";
|
||||||
|
case ND_INS_VCVTTPH2W: return "vcvttph2w";
|
||||||
case ND_INS_VCVTTPS2DQ: return "vcvttps2dq";
|
case ND_INS_VCVTTPS2DQ: return "vcvttps2dq";
|
||||||
case ND_INS_VCVTTPS2QQ: return "vcvttps2qq";
|
case ND_INS_VCVTTPS2QQ: return "vcvttps2qq";
|
||||||
case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq";
|
case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq";
|
||||||
case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq";
|
case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq";
|
||||||
case ND_INS_VCVTTSD2SI: return "vcvttsd2si";
|
case ND_INS_VCVTTSD2SI: return "vcvttsd2si";
|
||||||
case ND_INS_VCVTTSD2USI: return "vcvttsd2usi";
|
case ND_INS_VCVTTSD2USI: return "vcvttsd2usi";
|
||||||
|
case ND_INS_VCVTTSH2SI: return "vcvttsh2si";
|
||||||
|
case ND_INS_VCVTTSH2USI: return "vcvttsh2usi";
|
||||||
case ND_INS_VCVTTSS2SI: return "vcvttss2si";
|
case ND_INS_VCVTTSS2SI: return "vcvttss2si";
|
||||||
case ND_INS_VCVTTSS2USI: return "vcvttss2usi";
|
case ND_INS_VCVTTSS2USI: return "vcvttss2usi";
|
||||||
case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd";
|
case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd";
|
||||||
|
case ND_INS_VCVTUDQ2PH: return "vcvtudq2ph";
|
||||||
case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps";
|
case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps";
|
||||||
case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd";
|
case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd";
|
||||||
|
case ND_INS_VCVTUQQ2PH: return "vcvtuqq2ph";
|
||||||
case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps";
|
case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps";
|
||||||
case ND_INS_VCVTUSI2SD: return "vcvtusi2sd";
|
case ND_INS_VCVTUSI2SD: return "vcvtusi2sd";
|
||||||
|
case ND_INS_VCVTUSI2SH: return "vcvtusi2sh";
|
||||||
case ND_INS_VCVTUSI2SS: return "vcvtusi2ss";
|
case ND_INS_VCVTUSI2SS: return "vcvtusi2ss";
|
||||||
|
case ND_INS_VCVTUW2PH: return "vcvtuw2ph";
|
||||||
|
case ND_INS_VCVTW2PH: return "vcvtw2ph";
|
||||||
case ND_INS_VDBPSADBW: return "vdbpsadbw";
|
case ND_INS_VDBPSADBW: return "vdbpsadbw";
|
||||||
case ND_INS_VDIVPD: return "vdivpd";
|
case ND_INS_VDIVPD: return "vdivpd";
|
||||||
|
case ND_INS_VDIVPH: return "vdivph";
|
||||||
case ND_INS_VDIVPS: return "vdivps";
|
case ND_INS_VDIVPS: return "vdivps";
|
||||||
case ND_INS_VDIVSD: return "vdivsd";
|
case ND_INS_VDIVSD: return "vdivsd";
|
||||||
|
case ND_INS_VDIVSH: return "vdivsh";
|
||||||
case ND_INS_VDIVSS: return "vdivss";
|
case ND_INS_VDIVSS: return "vdivss";
|
||||||
case ND_INS_VDPBF16PS: return "vdpbf16ps";
|
case ND_INS_VDPBF16PS: return "vdpbf16ps";
|
||||||
case ND_INS_VDPPD: return "vdppd";
|
case ND_INS_VDPPD: return "vdppd";
|
||||||
@ -896,51 +975,75 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VEXTRACTI64X2: return "vextracti64x2";
|
case ND_INS_VEXTRACTI64X2: return "vextracti64x2";
|
||||||
case ND_INS_VEXTRACTI64X4: return "vextracti64x4";
|
case ND_INS_VEXTRACTI64X4: return "vextracti64x4";
|
||||||
case ND_INS_VEXTRACTPS: return "vextractps";
|
case ND_INS_VEXTRACTPS: return "vextractps";
|
||||||
|
case ND_INS_VFCMADDCPH: return "vfcmaddcph";
|
||||||
|
case ND_INS_VFCMADDCSH: return "vfcmaddcsh";
|
||||||
|
case ND_INS_VFCMULCPH: return "vfcmulcph";
|
||||||
|
case ND_INS_VFCMULCSH: return "vfcmulcsh";
|
||||||
case ND_INS_VFIXUPIMMPD: return "vfixupimmpd";
|
case ND_INS_VFIXUPIMMPD: return "vfixupimmpd";
|
||||||
case ND_INS_VFIXUPIMMPS: return "vfixupimmps";
|
case ND_INS_VFIXUPIMMPS: return "vfixupimmps";
|
||||||
case ND_INS_VFIXUPIMMSD: return "vfixupimmsd";
|
case ND_INS_VFIXUPIMMSD: return "vfixupimmsd";
|
||||||
case ND_INS_VFIXUPIMMSS: return "vfixupimmss";
|
case ND_INS_VFIXUPIMMSS: return "vfixupimmss";
|
||||||
case ND_INS_VFMADD132PD: return "vfmadd132pd";
|
case ND_INS_VFMADD132PD: return "vfmadd132pd";
|
||||||
|
case ND_INS_VFMADD132PH: return "vfmadd132ph";
|
||||||
case ND_INS_VFMADD132PS: return "vfmadd132ps";
|
case ND_INS_VFMADD132PS: return "vfmadd132ps";
|
||||||
case ND_INS_VFMADD132SD: return "vfmadd132sd";
|
case ND_INS_VFMADD132SD: return "vfmadd132sd";
|
||||||
|
case ND_INS_VFMADD132SH: return "vfmadd132sh";
|
||||||
case ND_INS_VFMADD132SS: return "vfmadd132ss";
|
case ND_INS_VFMADD132SS: return "vfmadd132ss";
|
||||||
case ND_INS_VFMADD213PD: return "vfmadd213pd";
|
case ND_INS_VFMADD213PD: return "vfmadd213pd";
|
||||||
|
case ND_INS_VFMADD213PH: return "vfmadd213ph";
|
||||||
case ND_INS_VFMADD213PS: return "vfmadd213ps";
|
case ND_INS_VFMADD213PS: return "vfmadd213ps";
|
||||||
case ND_INS_VFMADD213SD: return "vfmadd213sd";
|
case ND_INS_VFMADD213SD: return "vfmadd213sd";
|
||||||
|
case ND_INS_VFMADD213SH: return "vfmadd213sh";
|
||||||
case ND_INS_VFMADD213SS: return "vfmadd213ss";
|
case ND_INS_VFMADD213SS: return "vfmadd213ss";
|
||||||
case ND_INS_VFMADD231PD: return "vfmadd231pd";
|
case ND_INS_VFMADD231PD: return "vfmadd231pd";
|
||||||
|
case ND_INS_VFMADD231PH: return "vfmadd231ph";
|
||||||
case ND_INS_VFMADD231PS: return "vfmadd231ps";
|
case ND_INS_VFMADD231PS: return "vfmadd231ps";
|
||||||
case ND_INS_VFMADD231SD: return "vfmadd231sd";
|
case ND_INS_VFMADD231SD: return "vfmadd231sd";
|
||||||
|
case ND_INS_VFMADD231SH: return "vfmadd231sh";
|
||||||
case ND_INS_VFMADD231SS: return "vfmadd231ss";
|
case ND_INS_VFMADD231SS: return "vfmadd231ss";
|
||||||
|
case ND_INS_VFMADDCPH: return "vfmaddcph";
|
||||||
|
case ND_INS_VFMADDCSH: return "vfmaddcsh";
|
||||||
case ND_INS_VFMADDPD: return "vfmaddpd";
|
case ND_INS_VFMADDPD: return "vfmaddpd";
|
||||||
case ND_INS_VFMADDPS: return "vfmaddps";
|
case ND_INS_VFMADDPS: return "vfmaddps";
|
||||||
case ND_INS_VFMADDSD: return "vfmaddsd";
|
case ND_INS_VFMADDSD: return "vfmaddsd";
|
||||||
case ND_INS_VFMADDSS: return "vfmaddss";
|
case ND_INS_VFMADDSS: return "vfmaddss";
|
||||||
case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd";
|
case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd";
|
||||||
|
case ND_INS_VFMADDSUB132PH: return "vfmaddsub132ph";
|
||||||
case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps";
|
case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps";
|
||||||
case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd";
|
case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd";
|
||||||
|
case ND_INS_VFMADDSUB213PH: return "vfmaddsub213ph";
|
||||||
case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps";
|
case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps";
|
||||||
case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd";
|
case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd";
|
||||||
|
case ND_INS_VFMADDSUB231PH: return "vfmaddsub231ph";
|
||||||
case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps";
|
case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps";
|
||||||
case ND_INS_VFMADDSUBPD: return "vfmaddsubpd";
|
case ND_INS_VFMADDSUBPD: return "vfmaddsubpd";
|
||||||
case ND_INS_VFMADDSUBPS: return "vfmaddsubps";
|
case ND_INS_VFMADDSUBPS: return "vfmaddsubps";
|
||||||
case ND_INS_VFMSUB132PD: return "vfmsub132pd";
|
case ND_INS_VFMSUB132PD: return "vfmsub132pd";
|
||||||
|
case ND_INS_VFMSUB132PH: return "vfmsub132ph";
|
||||||
case ND_INS_VFMSUB132PS: return "vfmsub132ps";
|
case ND_INS_VFMSUB132PS: return "vfmsub132ps";
|
||||||
case ND_INS_VFMSUB132SD: return "vfmsub132sd";
|
case ND_INS_VFMSUB132SD: return "vfmsub132sd";
|
||||||
|
case ND_INS_VFMSUB132SH: return "vfmsub132sh";
|
||||||
case ND_INS_VFMSUB132SS: return "vfmsub132ss";
|
case ND_INS_VFMSUB132SS: return "vfmsub132ss";
|
||||||
case ND_INS_VFMSUB213PD: return "vfmsub213pd";
|
case ND_INS_VFMSUB213PD: return "vfmsub213pd";
|
||||||
|
case ND_INS_VFMSUB213PH: return "vfmsub213ph";
|
||||||
case ND_INS_VFMSUB213PS: return "vfmsub213ps";
|
case ND_INS_VFMSUB213PS: return "vfmsub213ps";
|
||||||
case ND_INS_VFMSUB213SD: return "vfmsub213sd";
|
case ND_INS_VFMSUB213SD: return "vfmsub213sd";
|
||||||
|
case ND_INS_VFMSUB213SH: return "vfmsub213sh";
|
||||||
case ND_INS_VFMSUB213SS: return "vfmsub213ss";
|
case ND_INS_VFMSUB213SS: return "vfmsub213ss";
|
||||||
case ND_INS_VFMSUB231PD: return "vfmsub231pd";
|
case ND_INS_VFMSUB231PD: return "vfmsub231pd";
|
||||||
|
case ND_INS_VFMSUB231PH: return "vfmsub231ph";
|
||||||
case ND_INS_VFMSUB231PS: return "vfmsub231ps";
|
case ND_INS_VFMSUB231PS: return "vfmsub231ps";
|
||||||
case ND_INS_VFMSUB231SD: return "vfmsub231sd";
|
case ND_INS_VFMSUB231SD: return "vfmsub231sd";
|
||||||
|
case ND_INS_VFMSUB231SH: return "vfmsub231sh";
|
||||||
case ND_INS_VFMSUB231SS: return "vfmsub231ss";
|
case ND_INS_VFMSUB231SS: return "vfmsub231ss";
|
||||||
case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd";
|
case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd";
|
||||||
|
case ND_INS_VFMSUBADD132PH: return "vfmsubadd132ph";
|
||||||
case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps";
|
case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps";
|
||||||
case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd";
|
case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd";
|
||||||
|
case ND_INS_VFMSUBADD213PH: return "vfmsubadd213ph";
|
||||||
case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps";
|
case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps";
|
||||||
case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd";
|
case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd";
|
||||||
|
case ND_INS_VFMSUBADD231PH: return "vfmsubadd231ph";
|
||||||
case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps";
|
case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps";
|
||||||
case ND_INS_VFMSUBADDPD: return "vfmsubaddpd";
|
case ND_INS_VFMSUBADDPD: return "vfmsubaddpd";
|
||||||
case ND_INS_VFMSUBADDPS: return "vfmsubaddps";
|
case ND_INS_VFMSUBADDPS: return "vfmsubaddps";
|
||||||
@ -948,41 +1051,57 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VFMSUBPS: return "vfmsubps";
|
case ND_INS_VFMSUBPS: return "vfmsubps";
|
||||||
case ND_INS_VFMSUBSD: return "vfmsubsd";
|
case ND_INS_VFMSUBSD: return "vfmsubsd";
|
||||||
case ND_INS_VFMSUBSS: return "vfmsubss";
|
case ND_INS_VFMSUBSS: return "vfmsubss";
|
||||||
|
case ND_INS_VFMULCPH: return "vfmulcph";
|
||||||
|
case ND_INS_VFMULCSH: return "vfmulcsh";
|
||||||
case ND_INS_VFNMADD132PD: return "vfnmadd132pd";
|
case ND_INS_VFNMADD132PD: return "vfnmadd132pd";
|
||||||
|
case ND_INS_VFNMADD132PH: return "vfnmadd132ph";
|
||||||
case ND_INS_VFNMADD132PS: return "vfnmadd132ps";
|
case ND_INS_VFNMADD132PS: return "vfnmadd132ps";
|
||||||
case ND_INS_VFNMADD132SD: return "vfnmadd132sd";
|
case ND_INS_VFNMADD132SD: return "vfnmadd132sd";
|
||||||
|
case ND_INS_VFNMADD132SH: return "vfnmadd132sh";
|
||||||
case ND_INS_VFNMADD132SS: return "vfnmadd132ss";
|
case ND_INS_VFNMADD132SS: return "vfnmadd132ss";
|
||||||
case ND_INS_VFNMADD213PD: return "vfnmadd213pd";
|
case ND_INS_VFNMADD213PD: return "vfnmadd213pd";
|
||||||
|
case ND_INS_VFNMADD213PH: return "vfnmadd213ph";
|
||||||
case ND_INS_VFNMADD213PS: return "vfnmadd213ps";
|
case ND_INS_VFNMADD213PS: return "vfnmadd213ps";
|
||||||
case ND_INS_VFNMADD213SD: return "vfnmadd213sd";
|
case ND_INS_VFNMADD213SD: return "vfnmadd213sd";
|
||||||
|
case ND_INS_VFNMADD213SH: return "vfnmadd213sh";
|
||||||
case ND_INS_VFNMADD213SS: return "vfnmadd213ss";
|
case ND_INS_VFNMADD213SS: return "vfnmadd213ss";
|
||||||
case ND_INS_VFNMADD231PD: return "vfnmadd231pd";
|
case ND_INS_VFNMADD231PD: return "vfnmadd231pd";
|
||||||
|
case ND_INS_VFNMADD231PH: return "vfnmadd231ph";
|
||||||
case ND_INS_VFNMADD231PS: return "vfnmadd231ps";
|
case ND_INS_VFNMADD231PS: return "vfnmadd231ps";
|
||||||
case ND_INS_VFNMADD231SD: return "vfnmadd231sd";
|
case ND_INS_VFNMADD231SD: return "vfnmadd231sd";
|
||||||
|
case ND_INS_VFNMADD231SH: return "vfnmadd231sh";
|
||||||
case ND_INS_VFNMADD231SS: return "vfnmadd231ss";
|
case ND_INS_VFNMADD231SS: return "vfnmadd231ss";
|
||||||
case ND_INS_VFNMADDPD: return "vfnmaddpd";
|
case ND_INS_VFNMADDPD: return "vfnmaddpd";
|
||||||
case ND_INS_VFNMADDPS: return "vfnmaddps";
|
case ND_INS_VFNMADDPS: return "vfnmaddps";
|
||||||
case ND_INS_VFNMADDSD: return "vfnmaddsd";
|
case ND_INS_VFNMADDSD: return "vfnmaddsd";
|
||||||
case ND_INS_VFNMADDSS: return "vfnmaddss";
|
case ND_INS_VFNMADDSS: return "vfnmaddss";
|
||||||
case ND_INS_VFNMSUB132PD: return "vfnmsub132pd";
|
case ND_INS_VFNMSUB132PD: return "vfnmsub132pd";
|
||||||
|
case ND_INS_VFNMSUB132PH: return "vfnmsub132ph";
|
||||||
case ND_INS_VFNMSUB132PS: return "vfnmsub132ps";
|
case ND_INS_VFNMSUB132PS: return "vfnmsub132ps";
|
||||||
case ND_INS_VFNMSUB132SD: return "vfnmsub132sd";
|
case ND_INS_VFNMSUB132SD: return "vfnmsub132sd";
|
||||||
|
case ND_INS_VFNMSUB132SH: return "vfnmsub132sh";
|
||||||
case ND_INS_VFNMSUB132SS: return "vfnmsub132ss";
|
case ND_INS_VFNMSUB132SS: return "vfnmsub132ss";
|
||||||
case ND_INS_VFNMSUB213PD: return "vfnmsub213pd";
|
case ND_INS_VFNMSUB213PD: return "vfnmsub213pd";
|
||||||
|
case ND_INS_VFNMSUB213PH: return "vfnmsub213ph";
|
||||||
case ND_INS_VFNMSUB213PS: return "vfnmsub213ps";
|
case ND_INS_VFNMSUB213PS: return "vfnmsub213ps";
|
||||||
case ND_INS_VFNMSUB213SD: return "vfnmsub213sd";
|
case ND_INS_VFNMSUB213SD: return "vfnmsub213sd";
|
||||||
|
case ND_INS_VFNMSUB213SH: return "vfnmsub213sh";
|
||||||
case ND_INS_VFNMSUB213SS: return "vfnmsub213ss";
|
case ND_INS_VFNMSUB213SS: return "vfnmsub213ss";
|
||||||
case ND_INS_VFNMSUB231PD: return "vfnmsub231pd";
|
case ND_INS_VFNMSUB231PD: return "vfnmsub231pd";
|
||||||
|
case ND_INS_VFNMSUB231PH: return "vfnmsub231ph";
|
||||||
case ND_INS_VFNMSUB231PS: return "vfnmsub231ps";
|
case ND_INS_VFNMSUB231PS: return "vfnmsub231ps";
|
||||||
case ND_INS_VFNMSUB231SD: return "vfnmsub231sd";
|
case ND_INS_VFNMSUB231SD: return "vfnmsub231sd";
|
||||||
|
case ND_INS_VFNMSUB231SH: return "vfnmsub231sh";
|
||||||
case ND_INS_VFNMSUB231SS: return "vfnmsub231ss";
|
case ND_INS_VFNMSUB231SS: return "vfnmsub231ss";
|
||||||
case ND_INS_VFNMSUBPD: return "vfnmsubpd";
|
case ND_INS_VFNMSUBPD: return "vfnmsubpd";
|
||||||
case ND_INS_VFNMSUBPS: return "vfnmsubps";
|
case ND_INS_VFNMSUBPS: return "vfnmsubps";
|
||||||
case ND_INS_VFNMSUBSD: return "vfnmsubsd";
|
case ND_INS_VFNMSUBSD: return "vfnmsubsd";
|
||||||
case ND_INS_VFNMSUBSS: return "vfnmsubss";
|
case ND_INS_VFNMSUBSS: return "vfnmsubss";
|
||||||
case ND_INS_VFPCLASSPD: return "vfpclasspd";
|
case ND_INS_VFPCLASSPD: return "vfpclasspd";
|
||||||
|
case ND_INS_VFPCLASSPH: return "vfpclassph";
|
||||||
case ND_INS_VFPCLASSPS: return "vfpclassps";
|
case ND_INS_VFPCLASSPS: return "vfpclassps";
|
||||||
case ND_INS_VFPCLASSSD: return "vfpclasssd";
|
case ND_INS_VFPCLASSSD: return "vfpclasssd";
|
||||||
|
case ND_INS_VFPCLASSSH: return "vfpclasssh";
|
||||||
case ND_INS_VFPCLASSSS: return "vfpclassss";
|
case ND_INS_VFPCLASSSS: return "vfpclassss";
|
||||||
case ND_INS_VFRCZPD: return "vfrczpd";
|
case ND_INS_VFRCZPD: return "vfrczpd";
|
||||||
case ND_INS_VFRCZPS: return "vfrczps";
|
case ND_INS_VFRCZPS: return "vfrczps";
|
||||||
@ -1001,12 +1120,16 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VGATHERQPD: return "vgatherqpd";
|
case ND_INS_VGATHERQPD: return "vgatherqpd";
|
||||||
case ND_INS_VGATHERQPS: return "vgatherqps";
|
case ND_INS_VGATHERQPS: return "vgatherqps";
|
||||||
case ND_INS_VGETEXPPD: return "vgetexppd";
|
case ND_INS_VGETEXPPD: return "vgetexppd";
|
||||||
|
case ND_INS_VGETEXPPH: return "vgetexpph";
|
||||||
case ND_INS_VGETEXPPS: return "vgetexpps";
|
case ND_INS_VGETEXPPS: return "vgetexpps";
|
||||||
case ND_INS_VGETEXPSD: return "vgetexpsd";
|
case ND_INS_VGETEXPSD: return "vgetexpsd";
|
||||||
|
case ND_INS_VGETEXPSH: return "vgetexpsh";
|
||||||
case ND_INS_VGETEXPSS: return "vgetexpss";
|
case ND_INS_VGETEXPSS: return "vgetexpss";
|
||||||
case ND_INS_VGETMANTPD: return "vgetmantpd";
|
case ND_INS_VGETMANTPD: return "vgetmantpd";
|
||||||
|
case ND_INS_VGETMANTPH: return "vgetmantph";
|
||||||
case ND_INS_VGETMANTPS: return "vgetmantps";
|
case ND_INS_VGETMANTPS: return "vgetmantps";
|
||||||
case ND_INS_VGETMANTSD: return "vgetmantsd";
|
case ND_INS_VGETMANTSD: return "vgetmantsd";
|
||||||
|
case ND_INS_VGETMANTSH: return "vgetmantsh";
|
||||||
case ND_INS_VGETMANTSS: return "vgetmantss";
|
case ND_INS_VGETMANTSS: return "vgetmantss";
|
||||||
case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb";
|
case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb";
|
||||||
case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb";
|
case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb";
|
||||||
@ -1032,16 +1155,20 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VMASKMOVPD: return "vmaskmovpd";
|
case ND_INS_VMASKMOVPD: return "vmaskmovpd";
|
||||||
case ND_INS_VMASKMOVPS: return "vmaskmovps";
|
case ND_INS_VMASKMOVPS: return "vmaskmovps";
|
||||||
case ND_INS_VMAXPD: return "vmaxpd";
|
case ND_INS_VMAXPD: return "vmaxpd";
|
||||||
|
case ND_INS_VMAXPH: return "vmaxph";
|
||||||
case ND_INS_VMAXPS: return "vmaxps";
|
case ND_INS_VMAXPS: return "vmaxps";
|
||||||
case ND_INS_VMAXSD: return "vmaxsd";
|
case ND_INS_VMAXSD: return "vmaxsd";
|
||||||
|
case ND_INS_VMAXSH: return "vmaxsh";
|
||||||
case ND_INS_VMAXSS: return "vmaxss";
|
case ND_INS_VMAXSS: return "vmaxss";
|
||||||
case ND_INS_VMCALL: return "vmcall";
|
case ND_INS_VMCALL: return "vmcall";
|
||||||
case ND_INS_VMCLEAR: return "vmclear";
|
case ND_INS_VMCLEAR: return "vmclear";
|
||||||
case ND_INS_VMFUNC: return "vmfunc";
|
case ND_INS_VMFUNC: return "vmfunc";
|
||||||
case ND_INS_VMGEXIT: return "vmgexit";
|
case ND_INS_VMGEXIT: return "vmgexit";
|
||||||
case ND_INS_VMINPD: return "vminpd";
|
case ND_INS_VMINPD: return "vminpd";
|
||||||
|
case ND_INS_VMINPH: return "vminph";
|
||||||
case ND_INS_VMINPS: return "vminps";
|
case ND_INS_VMINPS: return "vminps";
|
||||||
case ND_INS_VMINSD: return "vminsd";
|
case ND_INS_VMINSD: return "vminsd";
|
||||||
|
case ND_INS_VMINSH: return "vminsh";
|
||||||
case ND_INS_VMINSS: return "vminss";
|
case ND_INS_VMINSS: return "vminss";
|
||||||
case ND_INS_VMLAUNCH: return "vmlaunch";
|
case ND_INS_VMLAUNCH: return "vmlaunch";
|
||||||
case ND_INS_VMLOAD: return "vmload";
|
case ND_INS_VMLOAD: return "vmload";
|
||||||
@ -1072,11 +1199,13 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VMOVNTPS: return "vmovntps";
|
case ND_INS_VMOVNTPS: return "vmovntps";
|
||||||
case ND_INS_VMOVQ: return "vmovq";
|
case ND_INS_VMOVQ: return "vmovq";
|
||||||
case ND_INS_VMOVSD: return "vmovsd";
|
case ND_INS_VMOVSD: return "vmovsd";
|
||||||
|
case ND_INS_VMOVSH: return "vmovsh";
|
||||||
case ND_INS_VMOVSHDUP: return "vmovshdup";
|
case ND_INS_VMOVSHDUP: return "vmovshdup";
|
||||||
case ND_INS_VMOVSLDUP: return "vmovsldup";
|
case ND_INS_VMOVSLDUP: return "vmovsldup";
|
||||||
case ND_INS_VMOVSS: return "vmovss";
|
case ND_INS_VMOVSS: return "vmovss";
|
||||||
case ND_INS_VMOVUPD: return "vmovupd";
|
case ND_INS_VMOVUPD: return "vmovupd";
|
||||||
case ND_INS_VMOVUPS: return "vmovups";
|
case ND_INS_VMOVUPS: return "vmovups";
|
||||||
|
case ND_INS_VMOVW: return "vmovw";
|
||||||
case ND_INS_VMPSADBW: return "vmpsadbw";
|
case ND_INS_VMPSADBW: return "vmpsadbw";
|
||||||
case ND_INS_VMPTRLD: return "vmptrld";
|
case ND_INS_VMPTRLD: return "vmptrld";
|
||||||
case ND_INS_VMPTRST: return "vmptrst";
|
case ND_INS_VMPTRST: return "vmptrst";
|
||||||
@ -1085,8 +1214,10 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VMRUN: return "vmrun";
|
case ND_INS_VMRUN: return "vmrun";
|
||||||
case ND_INS_VMSAVE: return "vmsave";
|
case ND_INS_VMSAVE: return "vmsave";
|
||||||
case ND_INS_VMULPD: return "vmulpd";
|
case ND_INS_VMULPD: return "vmulpd";
|
||||||
|
case ND_INS_VMULPH: return "vmulph";
|
||||||
case ND_INS_VMULPS: return "vmulps";
|
case ND_INS_VMULPS: return "vmulps";
|
||||||
case ND_INS_VMULSD: return "vmulsd";
|
case ND_INS_VMULSD: return "vmulsd";
|
||||||
|
case ND_INS_VMULSH: return "vmulsh";
|
||||||
case ND_INS_VMULSS: return "vmulss";
|
case ND_INS_VMULSS: return "vmulss";
|
||||||
case ND_INS_VMWRITE: return "vmwrite";
|
case ND_INS_VMWRITE: return "vmwrite";
|
||||||
case ND_INS_VMXOFF: return "vmxoff";
|
case ND_INS_VMXOFF: return "vmxoff";
|
||||||
@ -1171,10 +1302,22 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VPCOMW: return "vpcomw";
|
case ND_INS_VPCOMW: return "vpcomw";
|
||||||
case ND_INS_VPCONFLICTD: return "vpconflictd";
|
case ND_INS_VPCONFLICTD: return "vpconflictd";
|
||||||
case ND_INS_VPCONFLICTQ: return "vpconflictq";
|
case ND_INS_VPCONFLICTQ: return "vpconflictq";
|
||||||
|
case ND_INS_VPDPBSSD: return "vpdpbssd";
|
||||||
|
case ND_INS_VPDPBSSDS: return "vpdpbssds";
|
||||||
|
case ND_INS_VPDPBSUD: return "vpdpbsud";
|
||||||
|
case ND_INS_VPDPBSUDS: return "vpdpbsuds";
|
||||||
case ND_INS_VPDPBUSD: return "vpdpbusd";
|
case ND_INS_VPDPBUSD: return "vpdpbusd";
|
||||||
case ND_INS_VPDPBUSDS: return "vpdpbusds";
|
case ND_INS_VPDPBUSDS: return "vpdpbusds";
|
||||||
|
case ND_INS_VPDPBUUD: return "vpdpbuud";
|
||||||
|
case ND_INS_VPDPBUUDS: return "vpdpbuuds";
|
||||||
case ND_INS_VPDPWSSD: return "vpdpwssd";
|
case ND_INS_VPDPWSSD: return "vpdpwssd";
|
||||||
case ND_INS_VPDPWSSDS: return "vpdpwssds";
|
case ND_INS_VPDPWSSDS: return "vpdpwssds";
|
||||||
|
case ND_INS_VPDPWSUD: return "vpdpwsud";
|
||||||
|
case ND_INS_VPDPWSUDS: return "vpdpwsuds";
|
||||||
|
case ND_INS_VPDPWUSD: return "vpdpwusd";
|
||||||
|
case ND_INS_VPDPWUSDS: return "vpdpwusds";
|
||||||
|
case ND_INS_VPDPWUUD: return "vpdpwuud";
|
||||||
|
case ND_INS_VPDPWUUDS: return "vpdpwuuds";
|
||||||
case ND_INS_VPERM2F128: return "vperm2f128";
|
case ND_INS_VPERM2F128: return "vperm2f128";
|
||||||
case ND_INS_VPERM2I128: return "vperm2i128";
|
case ND_INS_VPERM2I128: return "vperm2i128";
|
||||||
case ND_INS_VPERMB: return "vpermb";
|
case ND_INS_VPERMB: return "vpermb";
|
||||||
@ -1436,15 +1579,21 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VRCP28PS: return "vrcp28ps";
|
case ND_INS_VRCP28PS: return "vrcp28ps";
|
||||||
case ND_INS_VRCP28SD: return "vrcp28sd";
|
case ND_INS_VRCP28SD: return "vrcp28sd";
|
||||||
case ND_INS_VRCP28SS: return "vrcp28ss";
|
case ND_INS_VRCP28SS: return "vrcp28ss";
|
||||||
|
case ND_INS_VRCPPH: return "vrcpph";
|
||||||
case ND_INS_VRCPPS: return "vrcpps";
|
case ND_INS_VRCPPS: return "vrcpps";
|
||||||
|
case ND_INS_VRCPSH: return "vrcpsh";
|
||||||
case ND_INS_VRCPSS: return "vrcpss";
|
case ND_INS_VRCPSS: return "vrcpss";
|
||||||
case ND_INS_VREDUCEPD: return "vreducepd";
|
case ND_INS_VREDUCEPD: return "vreducepd";
|
||||||
|
case ND_INS_VREDUCEPH: return "vreduceph";
|
||||||
case ND_INS_VREDUCEPS: return "vreduceps";
|
case ND_INS_VREDUCEPS: return "vreduceps";
|
||||||
case ND_INS_VREDUCESD: return "vreducesd";
|
case ND_INS_VREDUCESD: return "vreducesd";
|
||||||
|
case ND_INS_VREDUCESH: return "vreducesh";
|
||||||
case ND_INS_VREDUCESS: return "vreducess";
|
case ND_INS_VREDUCESS: return "vreducess";
|
||||||
case ND_INS_VRNDSCALEPD: return "vrndscalepd";
|
case ND_INS_VRNDSCALEPD: return "vrndscalepd";
|
||||||
|
case ND_INS_VRNDSCALEPH: return "vrndscaleph";
|
||||||
case ND_INS_VRNDSCALEPS: return "vrndscaleps";
|
case ND_INS_VRNDSCALEPS: return "vrndscaleps";
|
||||||
case ND_INS_VRNDSCALESD: return "vrndscalesd";
|
case ND_INS_VRNDSCALESD: return "vrndscalesd";
|
||||||
|
case ND_INS_VRNDSCALESH: return "vrndscalesh";
|
||||||
case ND_INS_VRNDSCALESS: return "vrndscaless";
|
case ND_INS_VRNDSCALESS: return "vrndscaless";
|
||||||
case ND_INS_VROUNDPD: return "vroundpd";
|
case ND_INS_VROUNDPD: return "vroundpd";
|
||||||
case ND_INS_VROUNDPS: return "vroundps";
|
case ND_INS_VROUNDPS: return "vroundps";
|
||||||
@ -1458,11 +1607,15 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VRSQRT28PS: return "vrsqrt28ps";
|
case ND_INS_VRSQRT28PS: return "vrsqrt28ps";
|
||||||
case ND_INS_VRSQRT28SD: return "vrsqrt28sd";
|
case ND_INS_VRSQRT28SD: return "vrsqrt28sd";
|
||||||
case ND_INS_VRSQRT28SS: return "vrsqrt28ss";
|
case ND_INS_VRSQRT28SS: return "vrsqrt28ss";
|
||||||
|
case ND_INS_VRSQRTPH: return "vrsqrtph";
|
||||||
case ND_INS_VRSQRTPS: return "vrsqrtps";
|
case ND_INS_VRSQRTPS: return "vrsqrtps";
|
||||||
|
case ND_INS_VRSQRTSH: return "vrsqrtsh";
|
||||||
case ND_INS_VRSQRTSS: return "vrsqrtss";
|
case ND_INS_VRSQRTSS: return "vrsqrtss";
|
||||||
case ND_INS_VSCALEFPD: return "vscalefpd";
|
case ND_INS_VSCALEFPD: return "vscalefpd";
|
||||||
|
case ND_INS_VSCALEFPH: return "vscalefph";
|
||||||
case ND_INS_VSCALEFPS: return "vscalefps";
|
case ND_INS_VSCALEFPS: return "vscalefps";
|
||||||
case ND_INS_VSCALEFSD: return "vscalefsd";
|
case ND_INS_VSCALEFSD: return "vscalefsd";
|
||||||
|
case ND_INS_VSCALEFSH: return "vscalefsh";
|
||||||
case ND_INS_VSCALEFSS: return "vscalefss";
|
case ND_INS_VSCALEFSS: return "vscalefss";
|
||||||
case ND_INS_VSCATTERDPD: return "vscatterdpd";
|
case ND_INS_VSCATTERDPD: return "vscatterdpd";
|
||||||
case ND_INS_VSCATTERDPS: return "vscatterdps";
|
case ND_INS_VSCATTERDPS: return "vscatterdps";
|
||||||
@ -1476,24 +1629,37 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps";
|
case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps";
|
||||||
case ND_INS_VSCATTERQPD: return "vscatterqpd";
|
case ND_INS_VSCATTERQPD: return "vscatterqpd";
|
||||||
case ND_INS_VSCATTERQPS: return "vscatterqps";
|
case ND_INS_VSCATTERQPS: return "vscatterqps";
|
||||||
|
case ND_INS_VSHA512MSG1: return "vsha512msg1";
|
||||||
|
case ND_INS_VSHA512MSG2: return "vsha512msg2";
|
||||||
|
case ND_INS_VSHA512RNDS2: return "vsha512rnds2";
|
||||||
case ND_INS_VSHUFF32X4: return "vshuff32x4";
|
case ND_INS_VSHUFF32X4: return "vshuff32x4";
|
||||||
case ND_INS_VSHUFF64X2: return "vshuff64x2";
|
case ND_INS_VSHUFF64X2: return "vshuff64x2";
|
||||||
case ND_INS_VSHUFI32X4: return "vshufi32x4";
|
case ND_INS_VSHUFI32X4: return "vshufi32x4";
|
||||||
case ND_INS_VSHUFI64X2: return "vshufi64x2";
|
case ND_INS_VSHUFI64X2: return "vshufi64x2";
|
||||||
case ND_INS_VSHUFPD: return "vshufpd";
|
case ND_INS_VSHUFPD: return "vshufpd";
|
||||||
case ND_INS_VSHUFPS: return "vshufps";
|
case ND_INS_VSHUFPS: return "vshufps";
|
||||||
|
case ND_INS_VSM3MSG1: return "vsm3msg1";
|
||||||
|
case ND_INS_VSM3MSG2: return "vsm3msg2";
|
||||||
|
case ND_INS_VSM3RNDS2: return "vsm3rnds2";
|
||||||
|
case ND_INS_VSM4KEY4: return "vsm4key4";
|
||||||
|
case ND_INS_VSM4RNDS4: return "vsm4rnds4";
|
||||||
case ND_INS_VSQRTPD: return "vsqrtpd";
|
case ND_INS_VSQRTPD: return "vsqrtpd";
|
||||||
|
case ND_INS_VSQRTPH: return "vsqrtph";
|
||||||
case ND_INS_VSQRTPS: return "vsqrtps";
|
case ND_INS_VSQRTPS: return "vsqrtps";
|
||||||
case ND_INS_VSQRTSD: return "vsqrtsd";
|
case ND_INS_VSQRTSD: return "vsqrtsd";
|
||||||
|
case ND_INS_VSQRTSH: return "vsqrtsh";
|
||||||
case ND_INS_VSQRTSS: return "vsqrtss";
|
case ND_INS_VSQRTSS: return "vsqrtss";
|
||||||
case ND_INS_VSTMXCSR: return "vstmxcsr";
|
case ND_INS_VSTMXCSR: return "vstmxcsr";
|
||||||
case ND_INS_VSUBPD: return "vsubpd";
|
case ND_INS_VSUBPD: return "vsubpd";
|
||||||
|
case ND_INS_VSUBPH: return "vsubph";
|
||||||
case ND_INS_VSUBPS: return "vsubps";
|
case ND_INS_VSUBPS: return "vsubps";
|
||||||
case ND_INS_VSUBSD: return "vsubsd";
|
case ND_INS_VSUBSD: return "vsubsd";
|
||||||
|
case ND_INS_VSUBSH: return "vsubsh";
|
||||||
case ND_INS_VSUBSS: return "vsubss";
|
case ND_INS_VSUBSS: return "vsubss";
|
||||||
case ND_INS_VTESTPD: return "vtestpd";
|
case ND_INS_VTESTPD: return "vtestpd";
|
||||||
case ND_INS_VTESTPS: return "vtestps";
|
case ND_INS_VTESTPS: return "vtestps";
|
||||||
case ND_INS_VUCOMISD: return "vucomisd";
|
case ND_INS_VUCOMISD: return "vucomisd";
|
||||||
|
case ND_INS_VUCOMISH: return "vucomish";
|
||||||
case ND_INS_VUCOMISS: return "vucomiss";
|
case ND_INS_VUCOMISS: return "vucomiss";
|
||||||
case ND_INS_VUNPCKHPD: return "vunpckhpd";
|
case ND_INS_VUNPCKHPD: return "vunpckhpd";
|
||||||
case ND_INS_VUNPCKHPS: return "vunpckhps";
|
case ND_INS_VUNPCKHPS: return "vunpckhps";
|
||||||
@ -1509,6 +1675,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_WRFSBASE: return "wrfsbase";
|
case ND_INS_WRFSBASE: return "wrfsbase";
|
||||||
case ND_INS_WRGSBASE: return "wrgsbase";
|
case ND_INS_WRGSBASE: return "wrgsbase";
|
||||||
case ND_INS_WRMSR: return "wrmsr";
|
case ND_INS_WRMSR: return "wrmsr";
|
||||||
|
case ND_INS_WRMSRLIST: return "wrmsrlist";
|
||||||
|
case ND_INS_WRMSRNS: return "wrmsrns";
|
||||||
case ND_INS_WRPKRU: return "wrpkru";
|
case ND_INS_WRPKRU: return "wrpkru";
|
||||||
case ND_INS_WRSHR: return "wrshr";
|
case ND_INS_WRSHR: return "wrshr";
|
||||||
case ND_INS_WRSS: return "wrss";
|
case ND_INS_WRSS: return "wrss";
|
||||||
@ -1528,7 +1696,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_XOR: return "xor";
|
case ND_INS_XOR: return "xor";
|
||||||
case ND_INS_XORPD: return "xorpd";
|
case ND_INS_XORPD: return "xorpd";
|
||||||
case ND_INS_XORPS: return "xorps";
|
case ND_INS_XORPS: return "xorps";
|
||||||
case ND_INS_XRESLDTRK: return "xresldtrik";
|
case ND_INS_XRESLDTRK: return "xresldtrk";
|
||||||
case ND_INS_XRSTOR: return "xrstor";
|
case ND_INS_XRSTOR: return "xrstor";
|
||||||
case ND_INS_XRSTORS: return "xrstors";
|
case ND_INS_XRSTORS: return "xrstors";
|
||||||
case ND_INS_XSAVE: return "xsave";
|
case ND_INS_XSAVE: return "xsave";
|
||||||
@ -1538,56 +1706,9 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
|||||||
case ND_INS_XSETBV: return "xsetbv";
|
case ND_INS_XSETBV: return "xsetbv";
|
||||||
case ND_INS_XSHA1: return "xsha1";
|
case ND_INS_XSHA1: return "xsha1";
|
||||||
case ND_INS_XSHA256: return "xsha256";
|
case ND_INS_XSHA256: return "xsha256";
|
||||||
case ND_INS_XSUSLDTRK: return "xsusldtrk";
|
|
||||||
case ND_INS_XSTORE: return "xstore";
|
case ND_INS_XSTORE: return "xstore";
|
||||||
|
case ND_INS_XSUSLDTRK: return "xsusldtrk";
|
||||||
case ND_INS_XTEST: return "xtest";
|
case ND_INS_XTEST: return "xtest";
|
||||||
case ND_INS_HRESET: return "hreset";
|
|
||||||
case ND_INS_CLUI: return "clui";
|
|
||||||
case ND_INS_STUI: return "stui";
|
|
||||||
case ND_INS_TESTUI: return "testui";
|
|
||||||
case ND_INS_UIRET: return "uiret";
|
|
||||||
case ND_INS_SENDUIPI: return "senduipi";
|
|
||||||
case ND_INS_AADD: return "aadd";
|
|
||||||
case ND_INS_AAND: return "aand";
|
|
||||||
case ND_INS_AOR: return "aor";
|
|
||||||
case ND_INS_AXOR: return "axor";
|
|
||||||
case ND_INS_CMPBEXADD: return "cmpbexadd";
|
|
||||||
case ND_INS_CMPCXADD: return "cmpcxadd";
|
|
||||||
case ND_INS_CMPLEXADD: return "cmplexadd";
|
|
||||||
case ND_INS_CMPLXADD: return "cmplxadd";
|
|
||||||
case ND_INS_CMPNBEXADD: return "cmpnbexadd";
|
|
||||||
case ND_INS_CMPNCXADD: return "cmpncxadd";
|
|
||||||
case ND_INS_CMPNLEXADD: return "cmpnlexadd";
|
|
||||||
case ND_INS_CMPNLXADD: return "cmpnlxadd";
|
|
||||||
case ND_INS_CMPNOXADD: return "cmpnoxadd";
|
|
||||||
case ND_INS_CMPNPXADD: return "cmpnpxadd";
|
|
||||||
case ND_INS_CMPNSXADD: return "cmpnsxadd";
|
|
||||||
case ND_INS_CMPNZXADD: return "cmpnzxadd";
|
|
||||||
case ND_INS_CMPOXADD: return "cmpoxadd";
|
|
||||||
case ND_INS_CMPPXADD: return "cmppxadd";
|
|
||||||
case ND_INS_CMPSXADD: return "cmpsxadd";
|
|
||||||
case ND_INS_CMPZXADD: return "cmpzxadd";
|
|
||||||
case ND_INS_PREFETCHIT0: return "prefetchit0";
|
|
||||||
case ND_INS_PREFETCHIT1: return "prefetchit1";
|
|
||||||
case ND_INS_RDMSRLIST: return "rdmsrlist";
|
|
||||||
case ND_INS_TDPFP16PS: return "tdpfp16ps";
|
|
||||||
case ND_INS_VBCSTNEBF162PS: return "vbcstnebf162ps";
|
|
||||||
case ND_INS_VBCSTNESH2PS: return "vbcstnesh2ps";
|
|
||||||
case ND_INS_VCVTNEEBF162PS: return "vcvtneebf162ps";
|
|
||||||
case ND_INS_VCVTNEEPH2PS: return "vcvtneeph2ps";
|
|
||||||
case ND_INS_VCVTNEOBF162PS: return "vcvtneobf162ps";
|
|
||||||
case ND_INS_VCVTNEOPH2PS: return "vcvtneoph2ps";
|
|
||||||
case ND_INS_VPDPBSSD: return "vpdpbssd";
|
|
||||||
case ND_INS_VPDPBSSDS: return "vpdpbssds";
|
|
||||||
case ND_INS_VPDPBSUD: return "vpdpbsud";
|
|
||||||
case ND_INS_VPDPBSUDS: return "vpdpbsuds";
|
|
||||||
case ND_INS_VPDPBUUD: return "vpdpbuud";
|
|
||||||
case ND_INS_VPDPBUUDS: return "vpdpbuuds";
|
|
||||||
case ND_INS_WRMSRLIST: return "wrmsrlist";
|
|
||||||
case ND_INS_WRMSRNS: return "wrmsrns";
|
|
||||||
case ND_INS_RMPQUERY: return "rmpquery";
|
|
||||||
case ND_INS_TCMMRLFP16PS: return "tcmmrlfp16ps";
|
|
||||||
case ND_INS_TCMMIMFP16PS: return "tcmmimfp16ps";
|
|
||||||
default: return "unhandled!";
|
default: return "unhandled!";
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1609,10 +1730,14 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
|
|||||||
case ND_CAT_AVX2GATHER: return "avx2gather";
|
case ND_CAT_AVX2GATHER: return "avx2gather";
|
||||||
case ND_CAT_AVX512: return "avx512";
|
case ND_CAT_AVX512: return "avx512";
|
||||||
case ND_CAT_AVX512BF16: return "avx512bf16";
|
case ND_CAT_AVX512BF16: return "avx512bf16";
|
||||||
|
case ND_CAT_AVX512FP16: return "avx512fp16";
|
||||||
case ND_CAT_AVX512VBMI: return "avx512vbmi";
|
case ND_CAT_AVX512VBMI: return "avx512vbmi";
|
||||||
case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect";
|
case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect";
|
||||||
case ND_CAT_AVX512FP16: return "avx512fp16";
|
case ND_CAT_AVXIFMA: return "avxifma";
|
||||||
|
case ND_CAT_AVXNECONVERT: return "avxneconvert";
|
||||||
case ND_CAT_AVXVNNI: return "avxvnni";
|
case ND_CAT_AVXVNNI: return "avxvnni";
|
||||||
|
case ND_CAT_AVXVNNIINT16: return "avxvnniint16";
|
||||||
|
case ND_CAT_AVXVNNIINT8: return "avxvnniint8";
|
||||||
case ND_CAT_BITBYTE: return "bitbyte";
|
case ND_CAT_BITBYTE: return "bitbyte";
|
||||||
case ND_CAT_BLEND: return "blend";
|
case ND_CAT_BLEND: return "blend";
|
||||||
case ND_CAT_BMI1: return "bmi1";
|
case ND_CAT_BMI1: return "bmi1";
|
||||||
@ -1622,6 +1747,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
|
|||||||
case ND_CAT_CET: return "cet";
|
case ND_CAT_CET: return "cet";
|
||||||
case ND_CAT_CLDEMOTE: return "cldemote";
|
case ND_CAT_CLDEMOTE: return "cldemote";
|
||||||
case ND_CAT_CMOV: return "cmov";
|
case ND_CAT_CMOV: return "cmov";
|
||||||
|
case ND_CAT_CMPCCXADD: return "cmpccxadd";
|
||||||
case ND_CAT_COMPRESS: return "compress";
|
case ND_CAT_COMPRESS: return "compress";
|
||||||
case ND_CAT_COND_BR: return "cond_br";
|
case ND_CAT_COND_BR: return "cond_br";
|
||||||
case ND_CAT_CONFLICT: return "conflict";
|
case ND_CAT_CONFLICT: return "conflict";
|
||||||
@ -1662,6 +1788,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
|
|||||||
case ND_CAT_PREFETCH: return "prefetch";
|
case ND_CAT_PREFETCH: return "prefetch";
|
||||||
case ND_CAT_PTWRITE: return "ptwrite";
|
case ND_CAT_PTWRITE: return "ptwrite";
|
||||||
case ND_CAT_PUSH: return "push";
|
case ND_CAT_PUSH: return "push";
|
||||||
|
case ND_CAT_RAOINT: return "raoint";
|
||||||
case ND_CAT_RDPID: return "rdpid";
|
case ND_CAT_RDPID: return "rdpid";
|
||||||
case ND_CAT_RDRAND: return "rdrand";
|
case ND_CAT_RDRAND: return "rdrand";
|
||||||
case ND_CAT_RDSEED: return "rdseed";
|
case ND_CAT_RDSEED: return "rdseed";
|
||||||
@ -1673,7 +1800,10 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
|
|||||||
case ND_CAT_SEMAPHORE: return "semaphore";
|
case ND_CAT_SEMAPHORE: return "semaphore";
|
||||||
case ND_CAT_SGX: return "sgx";
|
case ND_CAT_SGX: return "sgx";
|
||||||
case ND_CAT_SHA: return "sha";
|
case ND_CAT_SHA: return "sha";
|
||||||
|
case ND_CAT_SHA512: return "sha512";
|
||||||
case ND_CAT_SHIFT: return "shift";
|
case ND_CAT_SHIFT: return "shift";
|
||||||
|
case ND_CAT_SM3: return "sm3";
|
||||||
|
case ND_CAT_SM4: return "sm4";
|
||||||
case ND_CAT_SMAP: return "smap";
|
case ND_CAT_SMAP: return "smap";
|
||||||
case ND_CAT_SSE: return "sse";
|
case ND_CAT_SSE: return "sse";
|
||||||
case ND_CAT_SSE2: return "sse2";
|
case ND_CAT_SSE2: return "sse2";
|
||||||
@ -1702,11 +1832,6 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
|
|||||||
case ND_CAT_X87_ALU: return "x87_alu";
|
case ND_CAT_X87_ALU: return "x87_alu";
|
||||||
case ND_CAT_XOP: return "xop";
|
case ND_CAT_XOP: return "xop";
|
||||||
case ND_CAT_XSAVE: return "xsave";
|
case ND_CAT_XSAVE: return "xsave";
|
||||||
case ND_CAT_AVXIFMA: return "avxifma";
|
|
||||||
case ND_CAT_AVXVNNIINT8: return "avxvnniint8";
|
|
||||||
case ND_CAT_AVXNECONVERT: return "avxneconvert";
|
|
||||||
case ND_CAT_CMPCCXADD: return "cmpccxass";
|
|
||||||
case ND_CAT_RAOINT: return "rao-int";
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return "<unknown>";
|
return "<unknown>";
|
||||||
@ -1722,9 +1847,10 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_AES: return "aes";
|
case ND_SET_AES: return "aes";
|
||||||
case ND_SET_AMD: return "amd";
|
case ND_SET_AMD: return "amd";
|
||||||
case ND_SET_AMXBF16: return "amxbf16";
|
case ND_SET_AMXBF16: return "amxbf16";
|
||||||
|
case ND_SET_AMXCOMPLEX: return "amxcomplex";
|
||||||
|
case ND_SET_AMXFP16: return "amxfp16";
|
||||||
case ND_SET_AMXINT8: return "amxint8";
|
case ND_SET_AMXINT8: return "amxint8";
|
||||||
case ND_SET_AMXTILE: return "amxtile";
|
case ND_SET_AMXTILE: return "amxtile";
|
||||||
case ND_SET_AMXCOMPLEX: return "amxcomplex";
|
|
||||||
case ND_SET_AVX: return "avx";
|
case ND_SET_AVX: return "avx";
|
||||||
case ND_SET_AVX2: return "avx2";
|
case ND_SET_AVX2: return "avx2";
|
||||||
case ND_SET_AVX2GATHER: return "avx2gather";
|
case ND_SET_AVX2GATHER: return "avx2gather";
|
||||||
@ -1737,6 +1863,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_AVX512DQ: return "avx512dq";
|
case ND_SET_AVX512DQ: return "avx512dq";
|
||||||
case ND_SET_AVX512ER: return "avx512er";
|
case ND_SET_AVX512ER: return "avx512er";
|
||||||
case ND_SET_AVX512F: return "avx512f";
|
case ND_SET_AVX512F: return "avx512f";
|
||||||
|
case ND_SET_AVX512FP16: return "avx512fp16";
|
||||||
case ND_SET_AVX512IFMA: return "avx512ifma";
|
case ND_SET_AVX512IFMA: return "avx512ifma";
|
||||||
case ND_SET_AVX512PF: return "avx512pf";
|
case ND_SET_AVX512PF: return "avx512pf";
|
||||||
case ND_SET_AVX512VBMI: return "avx512vbmi";
|
case ND_SET_AVX512VBMI: return "avx512vbmi";
|
||||||
@ -1744,8 +1871,11 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_AVX512VNNI: return "avx512vnni";
|
case ND_SET_AVX512VNNI: return "avx512vnni";
|
||||||
case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect";
|
case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect";
|
||||||
case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq";
|
case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq";
|
||||||
case ND_SET_AVX512FP16: return "avx512fp16";
|
case ND_SET_AVXIFMA: return "avxifma";
|
||||||
|
case ND_SET_AVXNECONVERT: return "avxneconvert";
|
||||||
case ND_SET_AVXVNNI: return "avxvnni";
|
case ND_SET_AVXVNNI: return "avxvnni";
|
||||||
|
case ND_SET_AVXVNNIINT16: return "avxvnniint16";
|
||||||
|
case ND_SET_AVXVNNIINT8: return "avxvnniint8";
|
||||||
case ND_SET_BMI1: return "bmi1";
|
case ND_SET_BMI1: return "bmi1";
|
||||||
case ND_SET_BMI2: return "bmi2";
|
case ND_SET_BMI2: return "bmi2";
|
||||||
case ND_SET_CET_SS: return "cet_ss";
|
case ND_SET_CET_SS: return "cet_ss";
|
||||||
@ -1755,6 +1885,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_CLFSHOPT: return "clfshopt";
|
case ND_SET_CLFSHOPT: return "clfshopt";
|
||||||
case ND_SET_CLWB: return "clwb";
|
case ND_SET_CLWB: return "clwb";
|
||||||
case ND_SET_CLZERO: return "clzero";
|
case ND_SET_CLZERO: return "clzero";
|
||||||
|
case ND_SET_CMPCCXADD: return "cmpccxadd";
|
||||||
case ND_SET_CMPXCHG16B: return "cmpxchg16b";
|
case ND_SET_CMPXCHG16B: return "cmpxchg16b";
|
||||||
case ND_SET_CYRIX: return "cyrix";
|
case ND_SET_CYRIX: return "cyrix";
|
||||||
case ND_SET_CYRIX_SMM: return "cyrix_smm";
|
case ND_SET_CYRIX_SMM: return "cyrix_smm";
|
||||||
@ -1767,7 +1898,6 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_GFNI: return "gfni";
|
case ND_SET_GFNI: return "gfni";
|
||||||
case ND_SET_HRESET: return "hreset";
|
case ND_SET_HRESET: return "hreset";
|
||||||
case ND_SET_I186: return "i186";
|
case ND_SET_I186: return "i186";
|
||||||
case ND_SET_INVLPGB: return "invlpgb";
|
|
||||||
case ND_SET_I286PROT: return "i286prot";
|
case ND_SET_I286PROT: return "i286prot";
|
||||||
case ND_SET_I286REAL: return "i286real";
|
case ND_SET_I286REAL: return "i286real";
|
||||||
case ND_SET_I386: return "i386";
|
case ND_SET_I386: return "i386";
|
||||||
@ -1775,6 +1905,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_I486REAL: return "i486real";
|
case ND_SET_I486REAL: return "i486real";
|
||||||
case ND_SET_I64: return "i64";
|
case ND_SET_I64: return "i64";
|
||||||
case ND_SET_I86: return "i86";
|
case ND_SET_I86: return "i86";
|
||||||
|
case ND_SET_INVLPGB: return "invlpgb";
|
||||||
case ND_SET_INVPCID: return "invpcid";
|
case ND_SET_INVPCID: return "invpcid";
|
||||||
case ND_SET_KL: return "kl";
|
case ND_SET_KL: return "kl";
|
||||||
case ND_SET_LKGS: return "lkgs";
|
case ND_SET_LKGS: return "lkgs";
|
||||||
@ -1787,6 +1918,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_MOVDIR64B: return "movdir64b";
|
case ND_SET_MOVDIR64B: return "movdir64b";
|
||||||
case ND_SET_MOVDIRI: return "movdiri";
|
case ND_SET_MOVDIRI: return "movdiri";
|
||||||
case ND_SET_MPX: return "mpx";
|
case ND_SET_MPX: return "mpx";
|
||||||
|
case ND_SET_MSRLIST: return "msrlist";
|
||||||
case ND_SET_MWAITT: return "mwaitt";
|
case ND_SET_MWAITT: return "mwaitt";
|
||||||
case ND_SET_PAUSE: return "pause";
|
case ND_SET_PAUSE: return "pause";
|
||||||
case ND_SET_PCLMULQDQ: return "pclmulqdq";
|
case ND_SET_PCLMULQDQ: return "pclmulqdq";
|
||||||
@ -1795,8 +1927,10 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_PKU: return "pku";
|
case ND_SET_PKU: return "pku";
|
||||||
case ND_SET_POPCNT: return "popcnt";
|
case ND_SET_POPCNT: return "popcnt";
|
||||||
case ND_SET_PPRO: return "ppro";
|
case ND_SET_PPRO: return "ppro";
|
||||||
|
case ND_SET_PREFETCHITI: return "prefetchiti";
|
||||||
case ND_SET_PREFETCH_NOP: return "prefetch_nop";
|
case ND_SET_PREFETCH_NOP: return "prefetch_nop";
|
||||||
case ND_SET_PTWRITE: return "ptwrite";
|
case ND_SET_PTWRITE: return "ptwrite";
|
||||||
|
case ND_SET_RAOINT: return "raoint";
|
||||||
case ND_SET_RDPID: return "rdpid";
|
case ND_SET_RDPID: return "rdpid";
|
||||||
case ND_SET_RDPMC: return "rdpmc";
|
case ND_SET_RDPMC: return "rdpmc";
|
||||||
case ND_SET_RDPRU: return "rdpru";
|
case ND_SET_RDPRU: return "rdpru";
|
||||||
@ -1807,6 +1941,9 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_SERIALIZE: return "serialize";
|
case ND_SET_SERIALIZE: return "serialize";
|
||||||
case ND_SET_SGX: return "sgx";
|
case ND_SET_SGX: return "sgx";
|
||||||
case ND_SET_SHA: return "sha";
|
case ND_SET_SHA: return "sha";
|
||||||
|
case ND_SET_SHA512: return "sha512";
|
||||||
|
case ND_SET_SM3: return "sm3";
|
||||||
|
case ND_SET_SM4: return "sm4";
|
||||||
case ND_SET_SMAP: return "smap";
|
case ND_SET_SMAP: return "smap";
|
||||||
case ND_SET_SMX: return "smx";
|
case ND_SET_SMX: return "smx";
|
||||||
case ND_SET_SNP: return "snp";
|
case ND_SET_SNP: return "snp";
|
||||||
@ -1820,6 +1957,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_SVM: return "svm";
|
case ND_SET_SVM: return "svm";
|
||||||
case ND_SET_TBM: return "tbm";
|
case ND_SET_TBM: return "tbm";
|
||||||
case ND_SET_TDX: return "tdx";
|
case ND_SET_TDX: return "tdx";
|
||||||
|
case ND_SET_TSE: return "tse";
|
||||||
case ND_SET_TSX: return "tsx";
|
case ND_SET_TSX: return "tsx";
|
||||||
case ND_SET_TSXLDTRK: return "tsxldtrk";
|
case ND_SET_TSXLDTRK: return "tsxldtrk";
|
||||||
case ND_SET_UD: return "ud";
|
case ND_SET_UD: return "ud";
|
||||||
@ -1830,20 +1968,12 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
|||||||
case ND_SET_VTX: return "vtx";
|
case ND_SET_VTX: return "vtx";
|
||||||
case ND_SET_WAITPKG: return "waitpkg";
|
case ND_SET_WAITPKG: return "waitpkg";
|
||||||
case ND_SET_WBNOINVD: return "wbnoinvd";
|
case ND_SET_WBNOINVD: return "wbnoinvd";
|
||||||
|
case ND_SET_WRMSRNS: return "wrmsrns";
|
||||||
case ND_SET_X87: return "x87";
|
case ND_SET_X87: return "x87";
|
||||||
case ND_SET_XOP: return "xop";
|
case ND_SET_XOP: return "xop";
|
||||||
case ND_SET_XSAVE: return "xsave";
|
case ND_SET_XSAVE: return "xsave";
|
||||||
case ND_SET_XSAVEC: return "xsavec";
|
case ND_SET_XSAVEC: return "xsavec";
|
||||||
case ND_SET_XSAVES: return "xsaves";
|
case ND_SET_XSAVES: return "xsaves";
|
||||||
case ND_SET_AMXFP16: return "AMX-FP16";
|
|
||||||
case ND_SET_AVXIFMA: return "avxifma";
|
|
||||||
case ND_SET_AVXNECONVERT: return "avxneconvert";
|
|
||||||
case ND_SET_AVXVNNIINT8: return "avxvnniint8";
|
|
||||||
case ND_SET_CMPCCXADD: return "cmpccxadd";
|
|
||||||
case ND_SET_MSRLIST: return "msrlist";
|
|
||||||
case ND_SET_PREFETCHITI: return "prefetchiti";
|
|
||||||
case ND_SET_RAOINT: return "raoint";
|
|
||||||
case ND_SET_WRMSRNS: return "wrmsrns";
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return "<unknown>";
|
return "<unknown>";
|
||||||
|
|||||||
@ -469,6 +469,7 @@ typedef enum _ND_INS_CLASS
|
|||||||
ND_INS_PAVGW,
|
ND_INS_PAVGW,
|
||||||
ND_INS_PBLENDVB,
|
ND_INS_PBLENDVB,
|
||||||
ND_INS_PBLENDW,
|
ND_INS_PBLENDW,
|
||||||
|
ND_INS_PBNDKB,
|
||||||
ND_INS_PCLMULQDQ,
|
ND_INS_PCLMULQDQ,
|
||||||
ND_INS_PCMPEQB,
|
ND_INS_PCMPEQB,
|
||||||
ND_INS_PCMPEQD,
|
ND_INS_PCMPEQD,
|
||||||
@ -1257,6 +1258,12 @@ typedef enum _ND_INS_CLASS
|
|||||||
ND_INS_VPDPBUUDS,
|
ND_INS_VPDPBUUDS,
|
||||||
ND_INS_VPDPWSSD,
|
ND_INS_VPDPWSSD,
|
||||||
ND_INS_VPDPWSSDS,
|
ND_INS_VPDPWSSDS,
|
||||||
|
ND_INS_VPDPWSUD,
|
||||||
|
ND_INS_VPDPWSUDS,
|
||||||
|
ND_INS_VPDPWUSD,
|
||||||
|
ND_INS_VPDPWUSDS,
|
||||||
|
ND_INS_VPDPWUUD,
|
||||||
|
ND_INS_VPDPWUUDS,
|
||||||
ND_INS_VPERM2F128,
|
ND_INS_VPERM2F128,
|
||||||
ND_INS_VPERM2I128,
|
ND_INS_VPERM2I128,
|
||||||
ND_INS_VPERMB,
|
ND_INS_VPERMB,
|
||||||
@ -1568,12 +1575,20 @@ typedef enum _ND_INS_CLASS
|
|||||||
ND_INS_VSCATTERPF1QPS,
|
ND_INS_VSCATTERPF1QPS,
|
||||||
ND_INS_VSCATTERQPD,
|
ND_INS_VSCATTERQPD,
|
||||||
ND_INS_VSCATTERQPS,
|
ND_INS_VSCATTERQPS,
|
||||||
|
ND_INS_VSHA512MSG1,
|
||||||
|
ND_INS_VSHA512MSG2,
|
||||||
|
ND_INS_VSHA512RNDS2,
|
||||||
ND_INS_VSHUFF32X4,
|
ND_INS_VSHUFF32X4,
|
||||||
ND_INS_VSHUFF64X2,
|
ND_INS_VSHUFF64X2,
|
||||||
ND_INS_VSHUFI32X4,
|
ND_INS_VSHUFI32X4,
|
||||||
ND_INS_VSHUFI64X2,
|
ND_INS_VSHUFI64X2,
|
||||||
ND_INS_VSHUFPD,
|
ND_INS_VSHUFPD,
|
||||||
ND_INS_VSHUFPS,
|
ND_INS_VSHUFPS,
|
||||||
|
ND_INS_VSM3MSG1,
|
||||||
|
ND_INS_VSM3MSG2,
|
||||||
|
ND_INS_VSM3RNDS2,
|
||||||
|
ND_INS_VSM4KEY4,
|
||||||
|
ND_INS_VSM4RNDS4,
|
||||||
ND_INS_VSQRTPD,
|
ND_INS_VSQRTPD,
|
||||||
ND_INS_VSQRTPH,
|
ND_INS_VSQRTPH,
|
||||||
ND_INS_VSQRTPS,
|
ND_INS_VSQRTPS,
|
||||||
@ -1679,6 +1694,7 @@ typedef enum _ND_INS_SET
|
|||||||
ND_SET_AVXIFMA,
|
ND_SET_AVXIFMA,
|
||||||
ND_SET_AVXNECONVERT,
|
ND_SET_AVXNECONVERT,
|
||||||
ND_SET_AVXVNNI,
|
ND_SET_AVXVNNI,
|
||||||
|
ND_SET_AVXVNNIINT16,
|
||||||
ND_SET_AVXVNNIINT8,
|
ND_SET_AVXVNNIINT8,
|
||||||
ND_SET_BMI1,
|
ND_SET_BMI1,
|
||||||
ND_SET_BMI2,
|
ND_SET_BMI2,
|
||||||
@ -1745,6 +1761,9 @@ typedef enum _ND_INS_SET
|
|||||||
ND_SET_SERIALIZE,
|
ND_SET_SERIALIZE,
|
||||||
ND_SET_SGX,
|
ND_SET_SGX,
|
||||||
ND_SET_SHA,
|
ND_SET_SHA,
|
||||||
|
ND_SET_SHA512,
|
||||||
|
ND_SET_SM3,
|
||||||
|
ND_SET_SM4,
|
||||||
ND_SET_SMAP,
|
ND_SET_SMAP,
|
||||||
ND_SET_SMX,
|
ND_SET_SMX,
|
||||||
ND_SET_SNP,
|
ND_SET_SNP,
|
||||||
@ -1758,6 +1777,7 @@ typedef enum _ND_INS_SET
|
|||||||
ND_SET_SVM,
|
ND_SET_SVM,
|
||||||
ND_SET_TBM,
|
ND_SET_TBM,
|
||||||
ND_SET_TDX,
|
ND_SET_TDX,
|
||||||
|
ND_SET_TSE,
|
||||||
ND_SET_TSX,
|
ND_SET_TSX,
|
||||||
ND_SET_TSXLDTRK,
|
ND_SET_TSXLDTRK,
|
||||||
ND_SET_UD,
|
ND_SET_UD,
|
||||||
@ -1797,6 +1817,7 @@ typedef enum _ND_INS_TYPE
|
|||||||
ND_CAT_AVXIFMA,
|
ND_CAT_AVXIFMA,
|
||||||
ND_CAT_AVXNECONVERT,
|
ND_CAT_AVXNECONVERT,
|
||||||
ND_CAT_AVXVNNI,
|
ND_CAT_AVXVNNI,
|
||||||
|
ND_CAT_AVXVNNIINT16,
|
||||||
ND_CAT_AVXVNNIINT8,
|
ND_CAT_AVXVNNIINT8,
|
||||||
ND_CAT_BITBYTE,
|
ND_CAT_BITBYTE,
|
||||||
ND_CAT_BLEND,
|
ND_CAT_BLEND,
|
||||||
@ -1860,7 +1881,10 @@ typedef enum _ND_INS_TYPE
|
|||||||
ND_CAT_SEMAPHORE,
|
ND_CAT_SEMAPHORE,
|
||||||
ND_CAT_SGX,
|
ND_CAT_SGX,
|
||||||
ND_CAT_SHA,
|
ND_CAT_SHA,
|
||||||
|
ND_CAT_SHA512,
|
||||||
ND_CAT_SHIFT,
|
ND_CAT_SHIFT,
|
||||||
|
ND_CAT_SM3,
|
||||||
|
ND_CAT_SM4,
|
||||||
ND_CAT_SMAP,
|
ND_CAT_SMAP,
|
||||||
ND_CAT_SSE,
|
ND_CAT_SSE,
|
||||||
ND_CAT_SSE2,
|
ND_CAT_SSE2,
|
||||||
|
|||||||
@ -94,6 +94,9 @@
|
|||||||
#define ND_CFF_AVX512FP16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23)
|
#define ND_CFF_AVX512FP16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23)
|
||||||
#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24)
|
#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24)
|
||||||
#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25)
|
#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25)
|
||||||
|
#define ND_CFF_SHA512 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 0)
|
||||||
|
#define ND_CFF_SM3 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 1)
|
||||||
|
#define ND_CFF_SM4 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 2)
|
||||||
#define ND_CFF_RAOINT ND_CFF(0x00000007, 0x00000001, NDR_EAX, 3)
|
#define ND_CFF_RAOINT ND_CFF(0x00000007, 0x00000001, NDR_EAX, 3)
|
||||||
#define ND_CFF_AVXVNNI ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4)
|
#define ND_CFF_AVXVNNI ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4)
|
||||||
#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5)
|
#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5)
|
||||||
@ -105,9 +108,11 @@
|
|||||||
#define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
|
#define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
|
||||||
#define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23)
|
#define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23)
|
||||||
#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
|
#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
|
||||||
|
#define ND_CFF_TSE ND_CFF(0x00000007, 0x00000001, NDR_EBX, 1)
|
||||||
#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
|
#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
|
||||||
#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
|
#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
|
||||||
#define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
|
#define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
|
||||||
|
#define ND_CFF_AVXVNNIINT16 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 10)
|
||||||
#define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14)
|
#define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14)
|
||||||
#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
|
#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
|
||||||
#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
|
#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
|
||||||
|
|||||||
@ -6,7 +6,7 @@
|
|||||||
#define DISASM_VER_H
|
#define DISASM_VER_H
|
||||||
|
|
||||||
#define DISASM_VERSION_MAJOR 1
|
#define DISASM_VERSION_MAJOR 1
|
||||||
#define DISASM_VERSION_MINOR 37
|
#define DISASM_VERSION_MINOR 38
|
||||||
#define DISASM_VERSION_REVISION 0
|
#define DISASM_VERSION_REVISION 0
|
||||||
|
|
||||||
// bdshemu depends on bddisasm. It cannot be used without it.
|
// bdshemu depends on bddisasm. It cannot be used without it.
|
||||||
|
|||||||
@ -95,6 +95,9 @@ AMXTILE : 0x00000007, 0x00000000, EDX, 24
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AMXINT8 : 0x00000007, 0x00000000, EDX, 25
|
AMXINT8 : 0x00000007, 0x00000000, EDX, 25
|
||||||
|
|
||||||
|
|
||||||
|
SHA512 : 0x00000007, 0x00000001, EAX, 0
|
||||||
|
SM3 : 0x00000007, 0x00000001, EAX, 1
|
||||||
|
SM4 : 0x00000007, 0x00000001, EAX, 2
|
||||||
RAOINT : 0x00000007, 0x00000001, EAX, 3
|
RAOINT : 0x00000007, 0x00000001, EAX, 3
|
||||||
AVXVNNI : 0x00000007, 0x00000001, EAX, 4
|
AVXVNNI : 0x00000007, 0x00000001, EAX, 4
|
||||||
AVX512BF16 : 0x00000007, 0x00000001, EAX, 5
|
AVX512BF16 : 0x00000007, 0x00000001, EAX, 5
|
||||||
@ -107,9 +110,12 @@ HRESET : 0x00000007, 0x00000001, EAX, 22
|
|||||||
AVXIFMA : 0x00000007, 0x00000001, EAX, 23
|
AVXIFMA : 0x00000007, 0x00000001, EAX, 23
|
||||||
MSRLIST : 0x00000007, 0x00000001, EAX, 27
|
MSRLIST : 0x00000007, 0x00000001, EAX, 27
|
||||||
|
|
||||||
|
TSE : 0x00000007, 0x00000001, EBX, 1
|
||||||
|
|
||||||
AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4
|
AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4
|
||||||
AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5
|
AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5
|
||||||
AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8
|
AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8
|
||||||
|
AVXVNNIINT16 : 0x00000007, 0x00000001, EDX, 10
|
||||||
PREFETCHITI : 0x00000007, 0x00000001, EDX, 14
|
PREFETCHITI : 0x00000007, 0x00000001, EDX, 14
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@ -29,10 +29,11 @@ VMCALL ; n/a ; n/a ; NP 0x0F 0x01 /0xC
|
|||||||
VMLAUNCH ; n/a ; Fv ; NP 0x0F 0x01 /0xC2 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
VMLAUNCH ; n/a ; Fv ; NP 0x0F 0x01 /0xC2 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
||||||
VMRESUME ; n/a ; Fv ; NP 0x0F 0x01 /0xC3 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
VMRESUME ; n/a ; Fv ; NP 0x0F 0x01 /0xC3 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
||||||
VMXOFF ; n/a ; Fv ; NP 0x0F 0x01 /0xC4 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
VMXOFF ; n/a ; Fv ; NP 0x0F 0x01 /0xC4 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
|
||||||
PCONFIG ; n/a ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xC5 ; s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW, m:NOV86
|
PCONFIG ; n/a ; EAX,RBX,RCX,RDX,Fv ; NP 0x0F 0x01 /0xC5 ; s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW|W, m:KERNEL, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0
|
||||||
WRMSRNS ; n/a ; EAX,EDX,ECX,MSR ; NP 0x0F 0x01 /0xC6 ; s:WRMSRNS, t:SYSTEM, w:R|R|R|W, m:KERNEL
|
WRMSRNS ; n/a ; EAX,EDX,ECX,MSR ; NP 0x0F 0x01 /0xC6 ; s:WRMSRNS, t:SYSTEM, w:R|R|R|W, m:KERNEL
|
||||||
WRMSRLIST ; n/a ; SMT,DMT,ECX ; 0xF3 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|R|RW, m:KERNEL|O64
|
WRMSRLIST ; n/a ; SMT,DMT,ECX ; 0xF3 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|R|RW, m:KERNEL|O64
|
||||||
RDMSRLIST ; n/a ; SMT,DMT,ECX ; 0xF2 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|W|RW, m:KERNEL|O64
|
RDMSRLIST ; n/a ; SMT,DMT,ECX ; 0xF2 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|W|RW, m:KERNEL|O64
|
||||||
|
PBNDKB ; n/a ; EAX,RBX,RCX,Fv ; NP 0x0F 0x01 /0xC7 ; s:TSE, t:SYSTEM, w:W|R|R|W, m:KERNEL|O64, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0
|
||||||
MONITOR ; n/a ; pAXb,ECX,EDX ; NP 0x0F 0x01 /0xC8 ; s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86
|
MONITOR ; n/a ; pAXb,ECX,EDX ; NP 0x0F 0x01 /0xC8 ; s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86
|
||||||
MWAIT ; n/a ; EAX,ECX ; NP 0x0F 0x01 /0xC9 ; s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86
|
MWAIT ; n/a ; EAX,ECX ; NP 0x0F 0x01 /0xC9 ; s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86
|
||||||
CLAC ; n/a ; Fv ; NP 0x0F 0x01 /0xCA ; s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86
|
CLAC ; n/a ; Fv ; NP 0x0F 0x01 /0xCA ; s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86
|
||||||
|
|||||||
@ -218,7 +218,23 @@ VFNMSUB231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0
|
|||||||
VFNMSUB231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
VFNMSUB231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||||
VFNMSUB231SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
VFNMSUB231SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||||
VFNMSUB231SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
VFNMSUB231SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||||
|
|
||||||
|
VSHA512RNDS2 ; Vqq,Hqq,Udq ; n/a ; vex m:2 p:3 l:1 w:0 0xCB /r:reg ; s:SHA512, t:SHA512, w:RW|R|R, e:6
|
||||||
|
VSHA512MSG1 ; Vqq,Udq ; n/a ; vex m:2 p:3 l:1 w:0 0xCC /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6
|
||||||
|
VSHA512MSG2 ; Vqq,Uqq ; n/a ; vex m:2 p:3 l:1 w:0 0xCD /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6
|
||||||
VGF2P8MULB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, w:W|R|R
|
VGF2P8MULB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, w:W|R|R
|
||||||
|
|
||||||
|
VPDPWUUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:0 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
|
||||||
|
VPDPWUSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
|
||||||
|
VPDPWSUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
|
||||||
|
VPDPWUUDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:0 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
|
||||||
|
VPDPWUSDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
|
||||||
|
VPDPWSUDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
|
||||||
|
|
||||||
|
VSM3MSG1 ; Vdq,Hdq,Wdq ; n/a ; vex m:2 p:0 l:0 w:0 0xDA /r ; s:SM3, t:SM3, w:RW|R|R, e:4
|
||||||
|
VSM3MSG2 ; Vdq,Hdq,Wdq ; n/a ; vex m:2 p:1 l:0 w:0 0xDA /r ; s:SM3, t:SM3, w:RW|R|R, e:4
|
||||||
|
VSM4KEY4 ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0xDA /r ; s:SM4, t:SM4, w:W|R|R, e:6
|
||||||
|
VSM4RNDS4 ; Vx,Hx,Wx ; n/a ; vex m:2 p:3 l:x w:0 0xDA /r ; s:SM4, t:SM4, w:W|R|R, e:6
|
||||||
VAESIMC ; Vdq,Wdq ; n/a ; vex m:2 p:1 l:0 w:i 0xDB /r ; s:AES, t:AES, w:W|R, e:4
|
VAESIMC ; Vdq,Wdq ; n/a ; vex m:2 p:1 l:0 w:i 0xDB /r ; s:AES, t:AES, w:W|R, e:4
|
||||||
VAESENC ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDC /r ; s:AES, t:AES, w:W|R|R, e:4
|
VAESENC ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDC /r ; s:AES, t:AES, w:W|R|R, e:4
|
||||||
VAESENCLAST ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDD /r ; s:AES, t:AES, w:W|R|R, e:4
|
VAESENCLAST ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDD /r ; s:AES, t:AES, w:W|R|R, e:4
|
||||||
|
|||||||
@ -124,6 +124,7 @@ VGF2P8AFFINEQB ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:1
|
|||||||
VGF2P8AFFINEINVQB ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4
|
VGF2P8AFFINEINVQB ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4
|
||||||
|
|
||||||
# 0xD0 - 0xDF
|
# 0xD0 - 0xDF
|
||||||
|
VSM3RNDS2 ; Vdq,Hdq,Wdq,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0xDE /r ib ; s:SM3, t:SM3, w:RW|R|R|R, e:4
|
||||||
VAESKEYGENASSIST ; Vdq,Wdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0xDF /r ib ; s:AES, t:AES, w:W|R|R, e:4
|
VAESKEYGENASSIST ; Vdq,Wdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0xDF /r ib ; s:AES, t:AES, w:W|R|R, e:4
|
||||||
|
|
||||||
# 0xF0 - 0xFF
|
# 0xF0 - 0xFF
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user