diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
index 7964a24..8b810a9 100644
--- a/bddisasm/include/instructions.h
+++ b/bddisasm/include/instructions.h
@@ -10,7 +10,7 @@
 #ifndef INSTRUCTIONS_H
 #define INSTRUCTIONS_H
 
-const ND_INSTRUCTION gInstructions[2765] = 
+const ND_INSTRUCTION gInstructions[2780] = 
 {
     // Pos:0 Instruction:"AAA" Encoding:"0x37"/""
     {
@@ -14733,9 +14733,27 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:889 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
+    // Pos:889 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/""
     {
-        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 531, 
+        ND_INS_PBNDKB, ND_CAT_SYSTEM, ND_SET_TSE, 531, 
+        0, 
+        ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_TSE, 
+        0,
+        0|NDR_RFLAG_ZF,
+        0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
+        {
+            OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:890 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
+    {
+        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 532, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, 
@@ -14750,9 +14768,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:890 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
+    // Pos:891 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 532, 
+        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 533, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14766,9 +14784,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:891 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
+    // Pos:892 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 532, 
+        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 533, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14782,9 +14800,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:892 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
+    // Pos:893 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 533, 
+        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 534, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14798,9 +14816,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:893 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
+    // Pos:894 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 533, 
+        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 534, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14814,9 +14832,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:894 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
+    // Pos:895 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
     {
-        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 534, 
+        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 535, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -14830,9 +14848,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:895 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
+    // Pos:896 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 535, 
+        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 536, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14846,9 +14864,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:896 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
+    // Pos:897 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 535, 
+        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 536, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14862,9 +14880,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:897 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
+    // Pos:898 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 536, 
+        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 537, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14883,9 +14901,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:898 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
+    // Pos:899 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 537, 
+        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 538, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14904,9 +14922,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:899 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
+    // Pos:900 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 538, 
+        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 539, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14920,9 +14938,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:900 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
+    // Pos:901 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 538, 
+        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 539, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14936,9 +14954,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:901 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
+    // Pos:902 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 539, 
+        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 540, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -14952,9 +14970,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:902 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
+    // Pos:903 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 539, 
+        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 540, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -14968,9 +14986,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:903 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
+    // Pos:904 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
     {
-        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 540, 
+        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 541, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -14984,9 +15002,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:904 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
+    // Pos:905 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 541, 
+        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 542, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15000,9 +15018,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:905 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
+    // Pos:906 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 541, 
+        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 542, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15016,9 +15034,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:906 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
+    // Pos:907 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 542, 
+        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 543, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -15035,9 +15053,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:907 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
+    // Pos:908 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 543, 
+        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 544, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
@@ -15054,27 +15072,28 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:908 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
+    // Pos:909 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
     {
-        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 544, 
+        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 545, 
         0, 
-        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
-        0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 
-        0,
-        0,
+        ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
+        0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 
         0,
+        0|NDR_RFLAG_ZF,
         0,
+        0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF,
         {
             OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
             OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
             OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
             OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
         },
     }, 
 
-    // Pos:909 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
+    // Pos:910 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 545, 
+        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 546, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -15089,9 +15108,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:910 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
+    // Pos:911 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 546, 
+        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 547, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -15106,9 +15125,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:911 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
+    // Pos:912 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 547, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 548, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15123,9 +15142,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:912 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
+    // Pos:913 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 547, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 548, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15140,9 +15159,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:913 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
+    // Pos:914 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 548, 
+        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 549, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15157,9 +15176,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:914 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
+    // Pos:915 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 548, 
+        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 549, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15174,9 +15193,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:915 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
+    // Pos:916 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 549, 
+        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15191,9 +15210,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:916 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
+    // Pos:917 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 549, 
+        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 550, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15208,9 +15227,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:917 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
+    // Pos:918 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 550, 
+        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15225,9 +15244,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:918 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
+    // Pos:919 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 550, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15242,9 +15261,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:919 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
+    // Pos:920 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 550, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15259,9 +15278,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:920 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
+    // Pos:921 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 550, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 551, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15276,9 +15295,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:921 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
+    // Pos:922 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
     {
-        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 551, 
+        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 552, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15292,9 +15311,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:922 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
+    // Pos:923 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
     {
-        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 552, 
+        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 553, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15308,9 +15327,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:923 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
+    // Pos:924 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
     {
-        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 553, 
+        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 554, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15324,9 +15343,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:924 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
+    // Pos:925 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
     {
-        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 554, 
+        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 555, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15340,9 +15359,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:925 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
+    // Pos:926 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
     {
-        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 555, 
+        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 556, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15356,9 +15375,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:926 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
+    // Pos:927 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
     {
-        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 556, 
+        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 557, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15372,9 +15391,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:927 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
+    // Pos:928 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
     {
-        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 557, 
+        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 558, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15388,9 +15407,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:928 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
+    // Pos:929 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
     {
-        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 558, 
+        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 559, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15404,9 +15423,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:929 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
+    // Pos:930 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
     {
-        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 559, 
+        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 560, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15420,9 +15439,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:930 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
+    // Pos:931 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
     {
-        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 560, 
+        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 561, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15436,9 +15455,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:931 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
+    // Pos:932 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
     {
-        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 561, 
+        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 562, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15452,9 +15471,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:932 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
+    // Pos:933 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
     {
-        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 562, 
+        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 563, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15468,9 +15487,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:933 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
+    // Pos:934 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
     {
-        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 563, 
+        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 564, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15484,9 +15503,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:934 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
+    // Pos:935 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
     {
-        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 564, 
+        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 565, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15500,9 +15519,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:935 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
+    // Pos:936 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
     {
-        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 565, 
+        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 566, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15516,9 +15535,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:936 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
+    // Pos:937 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
     {
-        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 566, 
+        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 567, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 
@@ -15532,9 +15551,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:937 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
+    // Pos:938 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
     {
-        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 567, 
+        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 568, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15548,9 +15567,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:938 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
+    // Pos:939 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
     {
-        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 568, 
+        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 569, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15564,9 +15583,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:939 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
+    // Pos:940 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
     {
-        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 569, 
+        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 570, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 
@@ -15580,9 +15599,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:940 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
+    // Pos:941 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
     {
-        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 570, 
+        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 571, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15596,9 +15615,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:941 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
+    // Pos:942 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
     {
-        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 571, 
+        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 572, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15612,9 +15631,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:942 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
+    // Pos:943 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 572, 
+        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15628,9 +15647,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:943 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
+    // Pos:944 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 572, 
+        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 573, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15644,9 +15663,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:944 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
+    // Pos:945 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 573, 
+        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 574, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15660,9 +15679,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:945 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
+    // Pos:946 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 573, 
+        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 574, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15676,9 +15695,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:946 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
+    // Pos:947 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 574, 
+        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15692,9 +15711,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:947 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
+    // Pos:948 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 574, 
+        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 575, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15708,9 +15727,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:948 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
+    // Pos:949 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
     {
-        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 575, 
+        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 576, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15724,9 +15743,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:949 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
+    // Pos:950 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 576, 
+        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 577, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15740,9 +15759,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:950 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
+    // Pos:951 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 576, 
+        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 577, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15756,9 +15775,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:951 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
+    // Pos:952 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 577, 
+        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 578, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15772,9 +15791,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:952 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
+    // Pos:953 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 577, 
+        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 578, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15788,9 +15807,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:953 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
+    // Pos:954 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 578, 
+        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 579, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -15804,9 +15823,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:954 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
+    // Pos:955 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 578, 
+        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 579, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -15820,9 +15839,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:955 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
+    // Pos:956 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
     {
-        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 579, 
+        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 580, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15836,9 +15855,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:956 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
+    // Pos:957 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
     {
-        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 580, 
+        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 581, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -15852,9 +15871,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:957 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
+    // Pos:958 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 581, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 582, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15869,9 +15888,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:958 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
+    // Pos:959 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 581, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 582, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15886,9 +15905,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:959 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+    // Pos:960 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 582, 
+        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 583, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15903,9 +15922,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:960 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
+    // Pos:961 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 583, 
+        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 584, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -15920,9 +15939,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:961 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
+    // Pos:962 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 584, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 585, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15937,9 +15956,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:962 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
+    // Pos:963 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 584, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 585, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -15954,9 +15973,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:963 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
+    // Pos:964 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 584, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 585, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15971,9 +15990,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:964 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
+    // Pos:965 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 584, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 585, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -15988,9 +16007,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:965 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
+    // Pos:966 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 585, 
+        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 586, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16004,9 +16023,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:966 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
+    // Pos:967 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 585, 
+        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 586, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16020,9 +16039,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:967 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
+    // Pos:968 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 586, 
+        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 587, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16036,9 +16055,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:968 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
+    // Pos:969 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 586, 
+        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 587, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16052,9 +16071,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:969 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
+    // Pos:970 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
     {
-        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 587, 
+        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 588, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16068,9 +16087,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:970 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
+    // Pos:971 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
     {
-        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 588, 
+        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 589, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16084,9 +16103,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:971 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
+    // Pos:972 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 589, 
+        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 590, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16100,9 +16119,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:972 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
+    // Pos:973 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 589, 
+        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 590, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16116,9 +16135,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:973 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
+    // Pos:974 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 590, 
+        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 591, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16132,9 +16151,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:974 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
+    // Pos:975 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 590, 
+        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 591, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16148,9 +16167,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:975 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
+    // Pos:976 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
     {
-        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 591, 
+        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 592, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16164,9 +16183,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:976 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
+    // Pos:977 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
     {
-        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 592, 
+        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 593, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16180,9 +16199,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:977 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
+    // Pos:978 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
     {
-        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 593, 
+        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 594, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16196,9 +16215,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:978 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
+    // Pos:979 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
     {
-        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 594, 
+        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 595, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16212,9 +16231,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:979 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
+    // Pos:980 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 595, 
+        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 596, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16228,9 +16247,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:980 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
+    // Pos:981 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 595, 
+        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 596, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16244,9 +16263,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:981 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
+    // Pos:982 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 596, 
+        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16260,9 +16279,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:982 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
+    // Pos:983 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 596, 
+        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 597, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16276,9 +16295,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:983 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
+    // Pos:984 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
     {
-        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 597, 
+        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 598, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16292,9 +16311,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:984 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
+    // Pos:985 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
     {
-        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 598, 
+        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 599, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16308,9 +16327,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:985 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
+    // Pos:986 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 599, 
+        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -16324,9 +16343,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:986 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
+    // Pos:987 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 599, 
+        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 600, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16340,9 +16359,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:987 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
+    // Pos:988 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
     {
-        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 600, 
+        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 601, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16356,9 +16375,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:988 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
+    // Pos:989 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
     {
-        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 601, 
+        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 602, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16372,9 +16391,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:989 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
+    // Pos:990 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
     {
-        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 602, 
+        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 603, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16388,9 +16407,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:990 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
+    // Pos:991 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
     {
-        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 603, 
+        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 604, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16404,9 +16423,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:991 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
+    // Pos:992 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
     {
-        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 604, 
+        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 605, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16420,9 +16439,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:992 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
+    // Pos:993 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
     {
-        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 605, 
+        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 606, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16436,9 +16455,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:993 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
+    // Pos:994 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
     {
-        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 606, 
+        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 607, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16452,9 +16471,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:994 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
+    // Pos:995 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
     {
-        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 607, 
+        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 608, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16468,9 +16487,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:995 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
+    // Pos:996 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
     {
-        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 608, 
+        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 609, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16484,9 +16503,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:996 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
+    // Pos:997 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
     {
-        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 609, 
+        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 610, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16500,9 +16519,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:997 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
+    // Pos:998 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
     {
-        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 610, 
+        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 611, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16516,9 +16535,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:998 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
+    // Pos:999 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
     {
-        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 611, 
+        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 612, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16532,9 +16551,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:999 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
+    // Pos:1000 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
     {
-        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 612, 
+        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 613, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16548,9 +16567,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1000 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
+    // Pos:1001 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 613, 
+        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 614, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -16564,9 +16583,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1001 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
+    // Pos:1002 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 613, 
+        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 614, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -16580,9 +16599,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1002 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
+    // Pos:1003 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
     {
-        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 614, 
+        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 615, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -16596,9 +16615,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1003 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
+    // Pos:1004 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 615, 
+        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 616, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16612,9 +16631,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1004 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
+    // Pos:1005 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 615, 
+        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 616, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16628,9 +16647,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1005 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
+    // Pos:1006 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 616, 
+        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 617, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16644,9 +16663,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1006 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
+    // Pos:1007 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 616, 
+        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 617, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16660,9 +16679,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1007 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
+    // Pos:1008 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
     {
-        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 617, 
+        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 618, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -16676,9 +16695,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1008 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
+    // Pos:1009 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 618, 
+        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 619, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -16692,9 +16711,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1009 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
+    // Pos:1010 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 618, 
+        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 619, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16708,9 +16727,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1010 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
+    // Pos:1011 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 619, 
+        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 620, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -16724,9 +16743,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1011 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
+    // Pos:1012 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 619, 
+        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 620, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -16740,9 +16759,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1012 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
+    // Pos:1013 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16756,9 +16775,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1013 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
+    // Pos:1014 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16772,9 +16791,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1014 Instruction:"POP ES" Encoding:"0x07"/""
+    // Pos:1015 Instruction:"POP ES" Encoding:"0x07"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16788,9 +16807,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1015 Instruction:"POP SS" Encoding:"0x17"/""
+    // Pos:1016 Instruction:"POP SS" Encoding:"0x17"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16804,9 +16823,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1016 Instruction:"POP DS" Encoding:"0x1F"/""
+    // Pos:1017 Instruction:"POP DS" Encoding:"0x1F"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16820,9 +16839,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1017 Instruction:"POP Zv" Encoding:"0x58"/"O"
+    // Pos:1018 Instruction:"POP Zv" Encoding:"0x58"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16836,9 +16855,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1018 Instruction:"POP Zv" Encoding:"0x59"/"O"
+    // Pos:1019 Instruction:"POP Zv" Encoding:"0x59"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16852,9 +16871,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1019 Instruction:"POP Zv" Encoding:"0x5A"/"O"
+    // Pos:1020 Instruction:"POP Zv" Encoding:"0x5A"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16868,9 +16887,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1020 Instruction:"POP Zv" Encoding:"0x5B"/"O"
+    // Pos:1021 Instruction:"POP Zv" Encoding:"0x5B"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16884,9 +16903,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1021 Instruction:"POP Zv" Encoding:"0x5C"/"O"
+    // Pos:1022 Instruction:"POP Zv" Encoding:"0x5C"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16900,9 +16919,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1022 Instruction:"POP Zv" Encoding:"0x5D"/"O"
+    // Pos:1023 Instruction:"POP Zv" Encoding:"0x5D"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16916,9 +16935,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1023 Instruction:"POP Zv" Encoding:"0x5E"/"O"
+    // Pos:1024 Instruction:"POP Zv" Encoding:"0x5E"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16932,9 +16951,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1024 Instruction:"POP Zv" Encoding:"0x5F"/"O"
+    // Pos:1025 Instruction:"POP Zv" Encoding:"0x5F"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -16948,9 +16967,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1025 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
+    // Pos:1026 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 620, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
@@ -16964,9 +16983,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1026 Instruction:"POPA" Encoding:"ds16 0x61"/""
+    // Pos:1027 Instruction:"POPA" Encoding:"ds16 0x61"/""
     {
-        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 621, 
+        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 622, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16980,9 +16999,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1027 Instruction:"POPAD" Encoding:"ds32 0x61"/""
+    // Pos:1028 Instruction:"POPAD" Encoding:"ds32 0x61"/""
     {
-        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 622, 
+        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 623, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -16996,9 +17015,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1028 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
+    // Pos:1029 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
     {
-        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 623, 
+        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 624, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 
@@ -17013,23 +17032,7 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1029 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
-    {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 624, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
-        0,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:1030 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
+    // Pos:1030 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
     {
         ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 625, 
         0, 
@@ -17045,7 +17048,7 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1031 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
+    // Pos:1031 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
     {
         ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 626, 
         0, 
@@ -17061,9 +17064,25 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1032 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
+    // Pos:1032 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 627, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 627, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:1033 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
+    {
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17077,9 +17096,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1033 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
+    // Pos:1034 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 627, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 628, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17093,9 +17112,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1034 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
+    // Pos:1035 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17108,9 +17127,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1035 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
+    // Pos:1036 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17123,9 +17142,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1036 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
+    // Pos:1037 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17138,9 +17157,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1037 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
+    // Pos:1038 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 628, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17153,9 +17172,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1038 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
+    // Pos:1039 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
     {
-        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 
+        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 630, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17168,9 +17187,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1039 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M"
+    // Pos:1040 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M"
     {
-        ND_INS_PREFETCHIT0, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 630, 
+        ND_INS_PREFETCHIT0, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 631, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, 
@@ -17183,9 +17202,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1040 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M"
+    // Pos:1041 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M"
     {
-        ND_INS_PREFETCHIT1, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 631, 
+        ND_INS_PREFETCHIT1, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 632, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, 
@@ -17198,9 +17217,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1041 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
+    // Pos:1042 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
     {
-        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 632, 
+        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 633, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17213,9 +17232,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1042 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
+    // Pos:1043 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
     {
-        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 633, 
+        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 634, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17228,9 +17247,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1043 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M"
+    // Pos:1044 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M"
     {
-        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 633, 
+        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 634, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17243,9 +17262,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1044 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
+    // Pos:1045 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
     {
-        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 634, 
+        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17258,9 +17277,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1045 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M"
+    // Pos:1046 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M"
     {
-        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 634, 
+        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 635, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17273,9 +17292,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1046 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
+    // Pos:1047 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
     {
-        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 635, 
+        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17288,9 +17307,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1047 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M"
+    // Pos:1048 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M"
     {
-        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 635, 
+        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 636, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17303,9 +17322,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1048 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
+    // Pos:1049 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
     {
-        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 636, 
+        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 637, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17318,9 +17337,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1049 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M"
+    // Pos:1050 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M"
     {
-        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 636, 
+        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 637, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -17333,9 +17352,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1050 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
+    // Pos:1051 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
     {
-        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 637, 
+        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 638, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17348,9 +17367,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1051 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
+    // Pos:1052 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
     {
-        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 638, 
+        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 639, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -17363,9 +17382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1052 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
+    // Pos:1053 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 639, 
+        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 640, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17379,9 +17398,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1053 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
+    // Pos:1054 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 639, 
+        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 640, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17395,9 +17414,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1054 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:1055 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 640, 
+        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 641, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -17411,9 +17430,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1055 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:1056 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 640, 
+        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 641, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -17427,9 +17446,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1056 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1057 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 641, 
+        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 642, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17444,9 +17463,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1057 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1058 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 642, 
+        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 643, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17461,9 +17480,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1058 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1059 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 643, 
+        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 644, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17478,9 +17497,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1059 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1060 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 644, 
+        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 645, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17495,9 +17514,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1060 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1061 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 645, 
+        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 646, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -17511,9 +17530,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1061 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1062 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 645, 
+        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 646, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -17527,9 +17546,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1062 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1063 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 646, 
+        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 647, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -17543,9 +17562,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1063 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1064 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 646, 
+        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 647, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -17559,9 +17578,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1064 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1065 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 647, 
+        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 648, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
@@ -17575,9 +17594,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1065 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1066 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 647, 
+        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 648, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
@@ -17591,9 +17610,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1066 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1067 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 648, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17607,9 +17626,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1067 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1068 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 648, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17623,9 +17642,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1068 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
+    // Pos:1069 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 648, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17639,9 +17658,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1069 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
+    // Pos:1070 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 648, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 649, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17655,9 +17674,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1070 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
+    // Pos:1071 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
     {
-        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 649, 
+        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 650, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17671,9 +17690,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1071 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1072 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 650, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17687,9 +17706,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1072 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1073 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 650, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17703,9 +17722,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1073 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
+    // Pos:1074 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 650, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17719,9 +17738,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1074 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
+    // Pos:1075 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 650, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 651, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17735,9 +17754,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1075 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1076 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 651, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17751,9 +17770,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1076 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1077 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 651, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17767,9 +17786,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1077 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
+    // Pos:1078 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 651, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17783,9 +17802,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1078 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
+    // Pos:1079 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 651, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 652, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17799,9 +17818,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1079 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
+    // Pos:1080 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 652, 
+        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 653, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -17815,9 +17834,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1080 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1081 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 653, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 654, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17831,9 +17850,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1081 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1082 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 653, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 654, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17847,9 +17866,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1082 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
+    // Pos:1083 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 653, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 654, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17863,9 +17882,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1083 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
+    // Pos:1084 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 653, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 654, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17879,9 +17898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1084 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1085 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 654, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 655, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17895,9 +17914,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1085 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1086 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 654, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 655, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17911,9 +17930,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1086 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
+    // Pos:1087 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 654, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 655, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17927,9 +17946,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1087 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
+    // Pos:1088 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 654, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 655, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17943,9 +17962,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1088 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1089 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 655, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17959,9 +17978,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1089 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1090 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 655, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -17975,9 +17994,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1090 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
+    // Pos:1091 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 655, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -17991,9 +18010,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1091 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
+    // Pos:1092 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 655, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 656, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18007,9 +18026,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1092 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
+    // Pos:1093 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
     {
-        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 656, 
+        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 657, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18023,9 +18042,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1093 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1094 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 657, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 658, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18039,9 +18058,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1094 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1095 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 657, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 658, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18055,9 +18074,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1095 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
+    // Pos:1096 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 657, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 658, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18071,9 +18090,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1096 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
+    // Pos:1097 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 657, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 658, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18087,9 +18106,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1097 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1098 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 658, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 659, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18103,9 +18122,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1098 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1099 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 658, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 659, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18119,9 +18138,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1099 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
+    // Pos:1100 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 658, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 659, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18135,9 +18154,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1100 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
+    // Pos:1101 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 658, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 659, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18151,9 +18170,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1101 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
+    // Pos:1102 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 659, 
+        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 660, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18167,9 +18186,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1102 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
+    // Pos:1103 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 659, 
+        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 660, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18183,9 +18202,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1103 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
+    // Pos:1104 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 660, 
+        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18199,9 +18218,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1104 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
+    // Pos:1105 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 660, 
+        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 661, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18215,9 +18234,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1105 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
+    // Pos:1106 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 661, 
+        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 662, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18231,9 +18250,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1106 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
+    // Pos:1107 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 661, 
+        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 662, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18247,9 +18266,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1107 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
+    // Pos:1108 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 662, 
+        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 663, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18263,9 +18282,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1108 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
+    // Pos:1109 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 662, 
+        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 663, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18279,9 +18298,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1109 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
+    // Pos:1110 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 663, 
+        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18295,9 +18314,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1110 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
+    // Pos:1111 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 663, 
+        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 664, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18311,9 +18330,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1111 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
+    // Pos:1112 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 664, 
+        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 665, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18327,9 +18346,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1112 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
+    // Pos:1113 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 664, 
+        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 665, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18343,9 +18362,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1113 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
+    // Pos:1114 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 665, 
+        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 666, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18359,9 +18378,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1114 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
+    // Pos:1115 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 665, 
+        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 666, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18375,9 +18394,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1115 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
+    // Pos:1116 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 666, 
+        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18391,9 +18410,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1116 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
+    // Pos:1117 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 666, 
+        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 667, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18407,9 +18426,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1117 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
+    // Pos:1118 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
     {
-        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 667, 
+        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 668, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
@@ -18423,9 +18442,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1118 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
+    // Pos:1119 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
     {
-        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 668, 
+        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 669, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -18440,9 +18459,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1119 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
+    // Pos:1120 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
     {
-        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 669, 
+        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 670, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, 
@@ -18455,9 +18474,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1120 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
+    // Pos:1121 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 670, 
+        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 671, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18471,9 +18490,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1121 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
+    // Pos:1122 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 670, 
+        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 671, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18487,9 +18506,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1122 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
+    // Pos:1123 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 671, 
+        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 672, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18503,9 +18522,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1123 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
+    // Pos:1124 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 671, 
+        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 672, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18519,9 +18538,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1124 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
+    // Pos:1125 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
     {
-        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 672, 
+        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 673, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18535,9 +18554,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1125 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
+    // Pos:1126 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 673, 
+        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 674, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18551,9 +18570,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1126 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
+    // Pos:1127 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 673, 
+        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 674, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18567,9 +18586,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1127 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
+    // Pos:1128 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 674, 
+        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 675, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18583,9 +18602,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1128 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
+    // Pos:1129 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 674, 
+        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 675, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18599,9 +18618,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1129 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
+    // Pos:1130 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 675, 
+        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 676, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18615,9 +18634,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1130 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
+    // Pos:1131 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 675, 
+        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 676, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18631,9 +18650,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1131 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
+    // Pos:1132 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
     {
-        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 676, 
+        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 677, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18647,9 +18666,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1132 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
+    // Pos:1133 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 677, 
+        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 678, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -18663,9 +18682,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1133 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
+    // Pos:1134 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 677, 
+        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 678, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -18679,9 +18698,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1134 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
+    // Pos:1135 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18695,9 +18714,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1135 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
+    // Pos:1136 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18711,9 +18730,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1136 Instruction:"PUSH ES" Encoding:"0x06"/""
+    // Pos:1137 Instruction:"PUSH ES" Encoding:"0x06"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18727,9 +18746,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1137 Instruction:"PUSH CS" Encoding:"0x0E"/""
+    // Pos:1138 Instruction:"PUSH CS" Encoding:"0x0E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18743,9 +18762,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1138 Instruction:"PUSH SS" Encoding:"0x16"/""
+    // Pos:1139 Instruction:"PUSH SS" Encoding:"0x16"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18759,9 +18778,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1139 Instruction:"PUSH DS" Encoding:"0x1E"/""
+    // Pos:1140 Instruction:"PUSH DS" Encoding:"0x1E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18775,9 +18794,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1140 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
+    // Pos:1141 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18791,9 +18810,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1141 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
+    // Pos:1142 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18807,9 +18826,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1142 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
+    // Pos:1143 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18823,9 +18842,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1143 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
+    // Pos:1144 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18839,9 +18858,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1144 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
+    // Pos:1145 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18855,9 +18874,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1145 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
+    // Pos:1146 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18871,9 +18890,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1146 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
+    // Pos:1147 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18887,9 +18906,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1147 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
+    // Pos:1148 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18903,9 +18922,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1148 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
+    // Pos:1149 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18919,9 +18938,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1149 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
+    // Pos:1150 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
@@ -18935,9 +18954,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1150 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
+    // Pos:1151 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 678, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
@@ -18951,9 +18970,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1151 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
+    // Pos:1152 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
     {
-        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 679, 
+        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 680, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18967,9 +18986,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1152 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
+    // Pos:1153 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
     {
-        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 680, 
+        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 681, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
@@ -18983,23 +19002,7 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1153 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
-    {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 681, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
-        0,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), 
-            OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
-        },
-    }, 
-
-    // Pos:1154 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
+    // Pos:1154 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
     {
         ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 682, 
         0, 
@@ -19015,7 +19018,7 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1155 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
+    // Pos:1155 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
     {
         ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 683, 
         0, 
@@ -19031,9 +19034,25 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1156 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
+    // Pos:1156 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
     {
-        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 684, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 684, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), 
+        },
+    }, 
+
+    // Pos:1157 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
+    {
+        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 685, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 
@@ -19049,9 +19068,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1157 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
+    // Pos:1158 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 685, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
@@ -19065,9 +19084,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1158 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
+    // Pos:1159 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 685, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 686, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -19081,9 +19100,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1159 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
+    // Pos:1160 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19098,9 +19117,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1160 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
+    // Pos:1161 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19115,9 +19134,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1161 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
+    // Pos:1162 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19132,9 +19151,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1162 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
+    // Pos:1163 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19149,9 +19168,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1163 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
+    // Pos:1164 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19166,9 +19185,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1164 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
+    // Pos:1165 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 686, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19183,9 +19202,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1165 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
+    // Pos:1166 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 687, 
+        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 688, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -19199,9 +19218,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1166 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
+    // Pos:1167 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 688, 
+        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 689, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -19215,9 +19234,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1167 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
+    // Pos:1168 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19232,9 +19251,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1168 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
+    // Pos:1169 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19249,9 +19268,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1169 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
+    // Pos:1170 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19266,9 +19285,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1170 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
+    // Pos:1171 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19283,9 +19302,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1171 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
+    // Pos:1172 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19300,9 +19319,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1172 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
+    // Pos:1173 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 689, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19317,9 +19336,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1173 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
+    // Pos:1174 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
     {
-        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 690, 
+        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 691, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -19333,9 +19352,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1174 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
+    // Pos:1175 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
     {
-        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 691, 
+        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 692, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -19349,9 +19368,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1175 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
+    // Pos:1176 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
     {
-        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 692, 
+        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 693, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, 
@@ -19367,9 +19386,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1176 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/""
+    // Pos:1177 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/""
     {
-        ND_INS_RDMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 693, 
+        ND_INS_RDMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 694, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, 
@@ -19384,9 +19403,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1177 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1178 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 694, 
+        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 695, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, 
@@ -19400,9 +19419,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1178 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
+    // Pos:1179 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
     {
-        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 695, 
+        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 696, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
@@ -19418,9 +19437,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1179 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
+    // Pos:1180 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
     {
-        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 696, 
+        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 697, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19436,9 +19455,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1180 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
+    // Pos:1181 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
     {
-        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 697, 
+        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 698, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 
@@ -19454,9 +19473,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1181 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
+    // Pos:1182 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 698, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 699, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 
@@ -19470,9 +19489,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1182 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
+    // Pos:1183 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 698, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 699, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 
@@ -19486,9 +19505,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1183 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
+    // Pos:1184 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 699, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 
@@ -19502,9 +19521,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1184 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1185 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 699, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 700, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 
@@ -19518,9 +19537,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1185 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
+    // Pos:1186 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
     {
-        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 700, 
+        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 701, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19533,9 +19552,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1186 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M"
+    // Pos:1187 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 701, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 702, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -19549,9 +19568,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1187 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
+    // Pos:1188 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 702, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -19565,9 +19584,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1188 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
+    // Pos:1189 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
     {
-        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 703, 
+        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 704, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19582,9 +19601,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1189 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
+    // Pos:1190 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
     {
-        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 704, 
+        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 705, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, 
@@ -19601,9 +19620,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1190 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
+    // Pos:1191 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 705, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 706, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19620,9 +19639,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1191 Instruction:"RETF" Encoding:"0xCB"/""
+    // Pos:1192 Instruction:"RETF" Encoding:"0xCB"/""
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 705, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 706, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -19638,9 +19657,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1192 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
+    // Pos:1193 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 706, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 707, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -19657,9 +19676,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1193 Instruction:"RETN" Encoding:"0xC3"/""
+    // Pos:1194 Instruction:"RETN" Encoding:"0xC3"/""
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 706, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 707, 
         ND_PREF_BND, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
@@ -19674,9 +19693,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1194 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
+    // Pos:1195 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 707, 
+        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 708, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -19693,9 +19712,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1195 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/""
+    // Pos:1196 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/""
     {
-        ND_INS_RMPQUERY, ND_CAT_SYSTEM, ND_SET_SNP, 708, 
+        ND_INS_RMPQUERY, ND_CAT_SYSTEM, ND_SET_SNP, 709, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RMPQUERY, 
@@ -19712,9 +19731,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1196 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
+    // Pos:1197 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 709, 
+        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 710, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
@@ -19729,9 +19748,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1197 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
+    // Pos:1198 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19746,9 +19765,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1198 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
+    // Pos:1199 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19763,9 +19782,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1199 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
+    // Pos:1200 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19780,9 +19799,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1200 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
+    // Pos:1201 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19797,9 +19816,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1201 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
+    // Pos:1202 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19814,9 +19833,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1202 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
+    // Pos:1203 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 710, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19831,9 +19850,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1203 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
+    // Pos:1204 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19848,9 +19867,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1204 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
+    // Pos:1205 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19865,9 +19884,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1205 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
+    // Pos:1206 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19882,9 +19901,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1206 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
+    // Pos:1207 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19899,9 +19918,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1207 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
+    // Pos:1208 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19916,9 +19935,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1208 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
+    // Pos:1209 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 711, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -19933,9 +19952,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1209 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
+    // Pos:1210 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
     {
-        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 712, 
+        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 713, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -19950,9 +19969,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1210 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
+    // Pos:1211 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 713, 
+        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 714, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19967,9 +19986,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1211 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
+    // Pos:1212 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 714, 
+        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 715, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -19984,9 +20003,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1212 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
+    // Pos:1213 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
     {
-        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 715, 
+        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 716, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -20001,9 +20020,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1213 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
+    // Pos:1214 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
     {
-        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 716, 
+        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 717, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
@@ -20018,9 +20037,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1214 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
+    // Pos:1215 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
     {
-        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 717, 
+        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 718, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20034,9 +20053,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1215 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
+    // Pos:1216 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
     {
-        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 718, 
+        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 719, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20049,9 +20068,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1216 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
+    // Pos:1217 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
     {
-        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 719, 
+        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 720, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -20066,9 +20085,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1217 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
+    // Pos:1218 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 720, 
+        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 721, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20082,9 +20101,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1218 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
+    // Pos:1219 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 721, 
+        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 722, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -20098,9 +20117,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1219 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
+    // Pos:1220 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
     {
-        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 722, 
+        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 723, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -20114,9 +20133,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1220 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
+    // Pos:1221 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
     {
-        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 723, 
+        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 724, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20129,9 +20148,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1221 Instruction:"SAHF" Encoding:"0x9E"/""
+    // Pos:1222 Instruction:"SAHF" Encoding:"0x9E"/""
     {
-        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 724, 
+        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 725, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20145,9 +20164,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1222 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
+    // Pos:1223 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20162,9 +20181,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1223 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
+    // Pos:1224 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20179,9 +20198,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1224 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
+    // Pos:1225 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20196,9 +20215,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1225 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
+    // Pos:1226 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20213,9 +20232,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1226 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
+    // Pos:1227 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20230,9 +20249,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1227 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
+    // Pos:1228 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 725, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20247,9 +20266,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1228 Instruction:"SALC" Encoding:"0xD6"/""
+    // Pos:1229 Instruction:"SALC" Encoding:"0xD6"/""
     {
-        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 726, 
+        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 727, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20263,9 +20282,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1229 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
+    // Pos:1230 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20280,9 +20299,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1230 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
+    // Pos:1231 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20297,9 +20316,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1231 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
+    // Pos:1232 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20314,9 +20333,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1232 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
+    // Pos:1233 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20331,9 +20350,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1233 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
+    // Pos:1234 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20348,9 +20367,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1234 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
+    // Pos:1235 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 727, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20365,9 +20384,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1235 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1236 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 728, 
+        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 729, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -20382,9 +20401,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1236 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
+    // Pos:1237 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
     {
-        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 729, 
+        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 730, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -20398,9 +20417,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1237 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
+    // Pos:1238 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20415,9 +20434,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1238 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
+    // Pos:1239 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20432,9 +20451,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1239 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
+    // Pos:1240 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20449,9 +20468,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1240 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
+    // Pos:1241 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20466,9 +20485,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1241 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
+    // Pos:1242 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20483,9 +20502,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1242 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
+    // Pos:1243 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20500,9 +20519,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1243 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
+    // Pos:1244 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20517,9 +20536,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1244 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
+    // Pos:1245 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20534,9 +20553,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1245 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
+    // Pos:1246 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -20551,9 +20570,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1246 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
+    // Pos:1247 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 730, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -20568,9 +20587,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1247 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
+    // Pos:1248 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20586,9 +20605,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1248 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
+    // Pos:1249 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 731, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20605,9 +20624,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1249 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
+    // Pos:1250 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20623,9 +20642,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1250 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
+    // Pos:1251 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20642,9 +20661,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1251 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
+    // Pos:1252 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20660,9 +20679,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1252 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
+    // Pos:1253 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20679,9 +20698,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1253 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
+    // Pos:1254 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 735, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20697,9 +20716,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1254 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
+    // Pos:1255 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 735, 
         ND_PREF_REPC, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -20716,9 +20735,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1255 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
+    // Pos:1256 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/""
     {
-        ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 735, 
+        ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 736, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -20731,9 +20750,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1256 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
+    // Pos:1257 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/""
     {
-        ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 736, 
+        ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 737, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -20750,9 +20769,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1257 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
+    // Pos:1258 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/""
     {
-        ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 737, 
+        ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 738, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -20765,9 +20784,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1258 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M"
+    // Pos:1259 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 738, 
+        ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 739, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -20780,9 +20799,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1259 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
+    // Pos:1260 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 739, 
+        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 740, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, 
@@ -20795,28 +20814,28 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1260 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
-    {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 740, 
-        0, 
-        ND_MOD_ANY, 
-        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
-        0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
-        0,
-        0,
-        0,
-        {
-            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
-            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
-        },
-    }, 
-
-    // Pos:1261 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
+    // Pos:1261 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
     {
         ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
+        0|NDR_RFLAG_CF|NDR_RFLAG_ZF,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:1262 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
+    {
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, 
+        0, 
+        ND_MOD_ANY, 
+        0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|NDR_RFLAG_CF,
         0,
         0,
@@ -20827,9 +20846,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1262 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
+    // Pos:1263 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20843,9 +20862,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1263 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
+    // Pos:1264 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20859,9 +20878,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1264 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
+    // Pos:1265 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20875,9 +20894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1265 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
+    // Pos:1266 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20891,9 +20910,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1266 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
+    // Pos:1267 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20907,9 +20926,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1267 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
+    // Pos:1268 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20923,9 +20942,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1268 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
+    // Pos:1269 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20939,9 +20958,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1269 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
+    // Pos:1270 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20955,9 +20974,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1270 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
+    // Pos:1271 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20971,9 +20990,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1271 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
+    // Pos:1272 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -20987,9 +21006,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1272 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
+    // Pos:1273 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -21003,9 +21022,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1273 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
+    // Pos:1274 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 754, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -21019,9 +21038,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1274 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
+    // Pos:1275 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 754, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 755, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -21035,9 +21054,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1275 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
+    // Pos:1276 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 755, 
+        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 756, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -21051,9 +21070,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1276 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
+    // Pos:1277 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 756, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 757, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
@@ -21067,9 +21086,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1277 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
+    // Pos:1278 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
     {
-        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 757, 
+        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 758, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
@@ -21082,9 +21101,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1278 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
+    // Pos:1279 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
     {
-        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 758, 
+        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 759, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21098,9 +21117,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1279 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
+    // Pos:1280 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
     {
-        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 759, 
+        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 760, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21114,9 +21133,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1280 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
+    // Pos:1281 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
     {
-        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 760, 
+        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 761, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21130,9 +21149,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1281 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
+    // Pos:1282 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
     {
-        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 761, 
+        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 762, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21146,9 +21165,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1282 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
+    // Pos:1283 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
     {
-        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 762, 
+        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 763, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21163,9 +21182,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1283 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
+    // Pos:1284 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
     {
-        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 763, 
+        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 764, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21179,9 +21198,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1284 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
+    // Pos:1285 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
     {
-        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 764, 
+        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 765, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21195,9 +21214,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1285 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
+    // Pos:1286 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
     {
-        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 765, 
+        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 766, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
@@ -21212,9 +21231,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1286 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
+    // Pos:1287 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21229,9 +21248,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1287 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
+    // Pos:1288 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21246,9 +21265,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1288 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
+    // Pos:1289 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21263,9 +21282,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1289 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
+    // Pos:1290 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21280,9 +21299,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1290 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
+    // Pos:1291 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21297,9 +21316,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1291 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
+    // Pos:1292 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 766, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21314,9 +21333,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1292 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
+    // Pos:1293 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 767, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 768, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21332,9 +21351,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1293 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
+    // Pos:1294 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 767, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 768, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21350,9 +21369,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1294 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1295 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 768, 
+        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 769, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -21367,9 +21386,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1295 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
+    // Pos:1296 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21384,9 +21403,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1296 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
+    // Pos:1297 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21401,9 +21420,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1297 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
+    // Pos:1298 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21418,9 +21437,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1298 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
+    // Pos:1299 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21435,9 +21454,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1299 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
+    // Pos:1300 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21452,9 +21471,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1300 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
+    // Pos:1301 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 769, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21469,9 +21488,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1301 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
+    // Pos:1302 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 770, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 771, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21487,9 +21506,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1302 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
+    // Pos:1303 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 770, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 771, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21505,9 +21524,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1303 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1304 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 771, 
+        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 772, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
@@ -21522,9 +21541,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1304 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1305 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 772, 
+        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 773, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21539,9 +21558,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1305 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1306 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 773, 
+        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 774, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21556,9 +21575,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1306 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
+    // Pos:1307 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
     {
-        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 774, 
+        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 775, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21572,9 +21591,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1307 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
+    // Pos:1308 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
     {
-        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 775, 
+        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 776, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -21587,9 +21606,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1308 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
+    // Pos:1309 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 776, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 777, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21603,9 +21622,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1309 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
+    // Pos:1310 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 776, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 777, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21619,9 +21638,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1310 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
+    // Pos:1311 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
     {
-        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 777, 
+        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 778, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
@@ -21634,9 +21653,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1311 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
+    // Pos:1312 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
     {
-        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 778, 
+        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 779, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21649,9 +21668,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1312 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
+    // Pos:1313 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 779, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 780, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21665,9 +21684,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1313 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
+    // Pos:1314 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 779, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 780, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21681,9 +21700,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1314 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
+    // Pos:1315 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
     {
-        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 780, 
+        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 781, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -21696,9 +21715,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1315 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
+    // Pos:1316 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 781, 
+        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 782, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21712,9 +21731,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1316 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
+    // Pos:1317 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 782, 
+        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 783, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21728,9 +21747,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1317 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
+    // Pos:1318 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 783, 
+        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 784, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -21744,9 +21763,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1318 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
+    // Pos:1319 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 784, 
+        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 785, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -21760,9 +21779,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1319 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
+    // Pos:1320 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
     {
-        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 785, 
+        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 786, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 
@@ -21775,9 +21794,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1320 Instruction:"STC" Encoding:"0xF9"/""
+    // Pos:1321 Instruction:"STC" Encoding:"0xF9"/""
     {
-        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 786, 
+        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 787, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21790,9 +21809,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1321 Instruction:"STD" Encoding:"0xFD"/""
+    // Pos:1322 Instruction:"STD" Encoding:"0xFD"/""
     {
-        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 787, 
+        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 788, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21805,9 +21824,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1322 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
+    // Pos:1323 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
     {
-        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 788, 
+        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 789, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -21820,9 +21839,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1323 Instruction:"STI" Encoding:"0xFB"/""
+    // Pos:1324 Instruction:"STI" Encoding:"0xFB"/""
     {
-        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 789, 
+        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 790, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21835,9 +21854,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1324 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
+    // Pos:1325 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
     {
-        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 790, 
+        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 791, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
@@ -21851,9 +21870,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1325 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
+    // Pos:1326 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21869,9 +21888,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1326 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
+    // Pos:1327 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 791, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21888,9 +21907,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1327 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
+    // Pos:1328 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21906,9 +21925,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1328 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
+    // Pos:1329 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21925,9 +21944,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1329 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
+    // Pos:1330 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21943,9 +21962,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1330 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
+    // Pos:1331 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21962,9 +21981,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1331 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
+    // Pos:1332 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 795, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21980,9 +21999,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1332 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
+    // Pos:1333 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 795, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21999,9 +22018,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1333 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
+    // Pos:1334 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 795, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 796, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22015,9 +22034,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1334 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
+    // Pos:1335 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 795, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 796, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22031,9 +22050,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1335 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:1336 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 796, 
+        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 797, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22046,9 +22065,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1336 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/""
+    // Pos:1337 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/""
     {
-        ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 797, 
+        ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 798, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -22061,9 +22080,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1337 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
+    // Pos:1338 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22078,9 +22097,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1338 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
+    // Pos:1339 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22095,9 +22114,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1339 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
+    // Pos:1340 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22112,9 +22131,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1340 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
+    // Pos:1341 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22129,9 +22148,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1341 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
+    // Pos:1342 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -22146,9 +22165,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1342 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
+    // Pos:1343 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -22163,9 +22182,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1343 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
+    // Pos:1344 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22180,9 +22199,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1344 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
+    // Pos:1345 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22197,9 +22216,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1345 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
+    // Pos:1346 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -22214,9 +22233,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1346 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
+    // Pos:1347 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 798, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22231,9 +22250,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1347 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
+    // Pos:1348 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 799, 
+        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 800, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22247,9 +22266,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1348 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
+    // Pos:1349 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 800, 
+        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 801, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22263,9 +22282,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1349 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
+    // Pos:1350 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 801, 
+        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 802, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22279,9 +22298,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1350 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
+    // Pos:1351 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 802, 
+        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 803, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22295,9 +22314,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1351 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
+    // Pos:1352 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
     {
-        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 803, 
+        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22311,9 +22330,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1352 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
+    // Pos:1353 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
     {
-        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, 
+        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 805, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22326,9 +22345,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1353 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
+    // Pos:1354 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
     {
-        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 805, 
+        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 806, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22341,9 +22360,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1354 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
+    // Pos:1355 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
     {
-        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 806, 
+        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 807, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
@@ -22357,9 +22376,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1355 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
+    // Pos:1356 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
     {
-        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 807, 
+        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 808, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT, ND_CFF_FSC, 
@@ -22381,9 +22400,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1356 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
+    // Pos:1357 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
     {
-        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 808, 
+        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 809, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, ND_CFF_SEP, 
@@ -22404,9 +22423,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1357 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
+    // Pos:1358 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
     {
-        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 809, 
+        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 810, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, 
@@ -22423,9 +22442,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1358 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
+    // Pos:1359 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
     {
-        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 810, 
+        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 811, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, 
@@ -22445,9 +22464,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1359 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
+    // Pos:1360 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
     {
-        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 811, 
+        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 812, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -22461,9 +22480,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1360 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/""
+    // Pos:1361 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/""
     {
-        ND_INS_TCMMIMFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 812, 
+        ND_INS_TCMMIMFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 813, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXCOMPLEX, 
@@ -22478,9 +22497,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1361 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/""
+    // Pos:1362 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/""
     {
-        ND_INS_TCMMRLFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 813, 
+        ND_INS_TCMMRLFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 814, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXCOMPLEX, 
@@ -22495,9 +22514,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1362 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
+    // Pos:1363 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/""
     {
-        ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 814, 
+        ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 815, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22510,9 +22529,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1363 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
+    // Pos:1364 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
     {
-        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 815, 
+        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 816, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, 
@@ -22527,9 +22546,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1364 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1365 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 816, 
+        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 817, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -22544,9 +22563,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1365 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1366 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 817, 
+        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 818, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -22561,9 +22580,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1366 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1367 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 818, 
+        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 819, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -22578,9 +22597,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1367 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1368 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 819, 
+        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 820, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
@@ -22595,9 +22614,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1368 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/""
+    // Pos:1369 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/""
     {
-        ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 820, 
+        ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 821, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXFP16, 
@@ -22612,9 +22631,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1369 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
+    // Pos:1370 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22629,9 +22648,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1370 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
+    // Pos:1371 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22646,9 +22665,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1371 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
+    // Pos:1372 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -22663,9 +22682,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1372 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
+    // Pos:1373 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -22680,9 +22699,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1373 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
+    // Pos:1374 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22697,9 +22716,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1374 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
+    // Pos:1375 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22714,9 +22733,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1375 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
+    // Pos:1376 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22731,9 +22750,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1376 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
+    // Pos:1377 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 821, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22748,9 +22767,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1377 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/""
+    // Pos:1378 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/""
     {
-        ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 822, 
+        ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 823, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -22764,9 +22783,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1378 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1379 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 823, 
+        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 824, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22780,9 +22799,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1379 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1380 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 824, 
+        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 825, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22796,9 +22815,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1380 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
+    // Pos:1381 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
     {
-        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 825, 
+        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 826, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22811,9 +22830,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1381 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1382 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 826, 
+        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 827, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22827,9 +22846,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1382 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
+    // Pos:1383 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
     {
-        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 827, 
+        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 828, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
@@ -22842,9 +22861,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1383 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
+    // Pos:1384 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
     {
-        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 828, 
+        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 829, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
@@ -22857,9 +22876,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1384 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
+    // Pos:1385 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 829, 
+        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 830, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -22875,9 +22894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1385 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
+    // Pos:1386 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
     {
-        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 830, 
+        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 831, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
@@ -22892,9 +22911,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1386 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
+    // Pos:1387 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
     {
-        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 831, 
+        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 832, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
@@ -22908,9 +22927,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1387 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
+    // Pos:1388 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 832, 
+        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 833, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -22925,9 +22944,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1388 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
+    // Pos:1389 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 833, 
+        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 834, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -22942,9 +22961,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1389 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
+    // Pos:1390 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
     {
-        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 834, 
+        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 835, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22958,9 +22977,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1390 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
+    // Pos:1391 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
     {
-        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 835, 
+        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 836, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -22974,9 +22993,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1391 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
+    // Pos:1392 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
     {
-        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 836, 
+        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 837, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -22989,9 +23008,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1392 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/""
+    // Pos:1393 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/""
     {
-        ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 837, 
+        ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 838, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 
@@ -23009,9 +23028,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1393 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
+    // Pos:1394 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 838, 
+        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 839, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -23025,9 +23044,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1394 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
+    // Pos:1395 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 839, 
+        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 840, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
@@ -23042,9 +23061,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1395 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
+    // Pos:1396 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 840, 
+        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 841, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -23058,9 +23077,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1396 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
+    // Pos:1397 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 841, 
+        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 842, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -23074,9 +23093,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1397 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
+    // Pos:1398 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 842, 
+        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 843, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -23090,9 +23109,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1398 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
+    // Pos:1399 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 843, 
+        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 844, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -23106,9 +23125,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1399 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
+    // Pos:1400 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 844, 
+        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 845, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -23124,9 +23143,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1400 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
+    // Pos:1401 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 845, 
+        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 846, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -23142,9 +23161,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1401 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
+    // Pos:1402 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 846, 
+        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 847, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -23160,9 +23179,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1402 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
+    // Pos:1403 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 847, 
+        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 848, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
@@ -23178,9 +23197,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1403 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
+    // Pos:1404 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 848, 
+        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 849, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23196,9 +23215,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1404 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1405 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 848, 
+        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 849, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23213,9 +23232,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1405 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM"
+    // Pos:1406 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 849, 
+        ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 850, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -23231,9 +23250,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1406 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
+    // Pos:1407 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 850, 
+        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 851, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23249,9 +23268,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1407 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1408 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 850, 
+        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 851, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23266,9 +23285,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1408 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
+    // Pos:1409 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 851, 
+        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 852, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23284,9 +23303,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1409 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1410 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 851, 
+        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 852, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23301,9 +23320,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1410 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM"
+    // Pos:1411 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 852, 
+        ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 853, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -23319,9 +23338,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1411 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
+    // Pos:1412 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 853, 
+        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 854, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23337,9 +23356,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1412 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1413 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 853, 
+        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 854, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23354,9 +23373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1413 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1414 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 854, 
+        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 855, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23371,9 +23390,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1414 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1415 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 855, 
+        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 856, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23388,9 +23407,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1415 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1416 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 856, 
+        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 857, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -23405,9 +23424,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1416 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1417 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 856, 
+        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 857, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -23422,9 +23441,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1417 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1418 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 857, 
+        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 858, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -23439,9 +23458,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1418 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1419 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 857, 
+        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 858, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -23456,9 +23475,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1419 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1420 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 858, 
+        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 859, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -23473,9 +23492,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1420 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1421 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 858, 
+        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 859, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -23490,9 +23509,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1421 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1422 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 859, 
+        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
@@ -23507,9 +23526,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1422 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1423 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 859, 
+        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 860, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -23524,9 +23543,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1423 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
+    // Pos:1424 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
     {
-        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 860, 
+        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 861, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -23540,9 +23559,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1424 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
+    // Pos:1425 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
     {
-        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 861, 
+        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 862, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
@@ -23557,9 +23576,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1425 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
+    // Pos:1426 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 862, 
+        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 863, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23576,9 +23595,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1426 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
+    // Pos:1427 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 863, 
+        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 864, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23595,9 +23614,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1427 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
+    // Pos:1428 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 864, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 865, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23613,9 +23632,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1428 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1429 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 864, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 865, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23630,9 +23649,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1429 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
+    // Pos:1430 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 865, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 866, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23648,9 +23667,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1430 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1431 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 865, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 866, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23665,9 +23684,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1431 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
+    // Pos:1432 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 866, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 867, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23683,9 +23702,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1432 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1433 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 866, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 867, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23700,9 +23719,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1433 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
+    // Pos:1434 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 867, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 868, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23718,9 +23737,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1434 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1435 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 867, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 868, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23735,9 +23754,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1435 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM"
+    // Pos:1436 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM"
     {
-        ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 868, 
+        ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 869, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -23751,9 +23770,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1436 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM"
+    // Pos:1437 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM"
     {
-        ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 869, 
+        ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 870, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -23767,9 +23786,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1437 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
+    // Pos:1438 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 870, 
+        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 871, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23785,9 +23804,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1438 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
+    // Pos:1439 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 871, 
+        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 872, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23803,9 +23822,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1439 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
+    // Pos:1440 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 872, 
+        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 873, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23821,9 +23840,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1440 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
+    // Pos:1441 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 873, 
+        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 874, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23839,9 +23858,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1441 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
+    // Pos:1442 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 874, 
+        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 875, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23857,9 +23876,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1442 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
+    // Pos:1443 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 875, 
+        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 876, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23875,9 +23894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1443 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
+    // Pos:1444 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 876, 
+        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 877, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -23891,9 +23910,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1444 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
+    // Pos:1445 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 877, 
+        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 878, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23908,9 +23927,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1445 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
+    // Pos:1446 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 878, 
+        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 879, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23925,9 +23944,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1446 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
+    // Pos:1447 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 879, 
+        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 880, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23942,9 +23961,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1447 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
+    // Pos:1448 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 880, 
+        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 881, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -23959,9 +23978,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1448 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
+    // Pos:1449 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 881, 
+        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 882, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -23976,9 +23995,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1449 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
+    // Pos:1450 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 882, 
+        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 883, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -23992,9 +24011,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1450 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
+    // Pos:1451 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
     {
-        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 883, 
+        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 884, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24009,9 +24028,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1451 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
+    // Pos:1452 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 884, 
+        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 885, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24026,9 +24045,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1452 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
+    // Pos:1453 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 885, 
+        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 886, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24043,9 +24062,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1453 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
+    // Pos:1454 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 886, 
+        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 887, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24060,9 +24079,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1454 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
+    // Pos:1455 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 887, 
+        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 888, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24077,9 +24096,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1455 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
+    // Pos:1456 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 888, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 889, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24094,9 +24113,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1456 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
+    // Pos:1457 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 888, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 889, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24110,9 +24129,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1457 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
+    // Pos:1458 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 889, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 890, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24127,9 +24146,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1458 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
+    // Pos:1459 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 889, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 890, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24143,9 +24162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1459 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1460 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 890, 
+        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 891, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24162,9 +24181,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1460 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1461 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 890, 
+        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 891, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24180,9 +24199,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1461 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1462 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 891, 
+        ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 892, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24199,9 +24218,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1462 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1463 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 892, 
+        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 893, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24218,9 +24237,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1463 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1464 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 892, 
+        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 893, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24236,9 +24255,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1464 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1465 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 893, 
+        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 894, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24255,9 +24274,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1465 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1466 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 893, 
+        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 894, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24273,9 +24292,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1466 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1467 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 894, 
+        ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 895, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24292,9 +24311,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1467 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1468 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 895, 
+        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 896, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24311,9 +24330,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1468 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1469 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 895, 
+        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 896, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24329,9 +24348,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1469 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
+    // Pos:1470 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 896, 
+        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 897, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24346,9 +24365,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1470 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
+    // Pos:1471 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 896, 
+        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 897, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24363,9 +24382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1471 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM"
+    // Pos:1472 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 897, 
+        ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 898, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24380,9 +24399,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1472 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
+    // Pos:1473 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 898, 
+        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 899, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24397,9 +24416,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1473 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
+    // Pos:1474 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 898, 
+        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 899, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24414,9 +24433,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1474 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
+    // Pos:1475 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 899, 
+        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 900, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24431,9 +24450,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1475 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
+    // Pos:1476 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 900, 
+        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 901, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24448,9 +24467,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1476 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
+    // Pos:1477 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 901, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24465,9 +24484,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1477 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
+    // Pos:1478 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 901, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 902, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24481,9 +24500,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1478 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
+    // Pos:1479 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 901, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 902, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24497,9 +24516,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1479 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1480 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 902, 
+        ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 903, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24514,9 +24533,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1480 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1481 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 903, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 904, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24531,9 +24550,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1481 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
+    // Pos:1482 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 903, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 904, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24547,9 +24566,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1482 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
+    // Pos:1483 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
     {
-        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 904, 
+        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 905, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -24565,9 +24584,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1483 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM"
+    // Pos:1484 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM"
     {
-        ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 905, 
+        ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -24581,9 +24600,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1484 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM"
+    // Pos:1485 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM"
     {
-        ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, 
+        ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 907, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -24597,9 +24616,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1485 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM"
+    // Pos:1486 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM"
     {
-        ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 907, 
+        ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 908, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -24613,9 +24632,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1486 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM"
+    // Pos:1487 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM"
     {
-        ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 908, 
+        ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 909, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -24629,9 +24648,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1487 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
+    // Pos:1488 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
     {
-        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 909, 
+        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 910, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -24646,9 +24665,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1488 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM"
+    // Pos:1489 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM"
     {
-        ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 909, 
+        ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 910, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 
@@ -24662,9 +24681,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1489 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1490 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 910, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 911, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24679,9 +24698,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1490 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1491 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 910, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 911, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24695,9 +24714,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1491 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM"
+    // Pos:1492 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 911, 
+        ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 912, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24712,9 +24731,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1492 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
+    // Pos:1493 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 912, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 913, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24729,9 +24748,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1493 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1494 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 912, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 913, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24745,9 +24764,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1494 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1495 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 912, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 913, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -24761,9 +24780,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1495 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
+    // Pos:1496 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 913, 
+        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 914, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24778,9 +24797,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1496 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1497 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 914, 
+        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 915, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24795,9 +24814,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1497 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1498 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 915, 
+        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 916, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -24812,9 +24831,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1498 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1499 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 916, 
+        ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24829,9 +24848,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1499 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM"
+    // Pos:1500 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, 
+        ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 918, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24846,9 +24865,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1500 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
+    // Pos:1501 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 918, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 919, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -24863,9 +24882,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1501 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
+    // Pos:1502 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 918, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 919, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -24879,9 +24898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1502 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
+    // Pos:1503 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 918, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 919, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -24895,9 +24914,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1503 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM"
+    // Pos:1504 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM"
     {
-        ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 919, 
+        ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24912,9 +24931,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1504 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM"
+    // Pos:1505 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, 
+        ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24929,9 +24948,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1505 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1506 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, 
+        ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 922, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24946,9 +24965,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1506 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1507 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 922, 
+        ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 923, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24963,9 +24982,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1507 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM"
+    // Pos:1508 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM"
     {
-        ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 923, 
+        ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 924, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24980,9 +24999,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1508 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM"
+    // Pos:1509 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM"
     {
-        ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 924, 
+        ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 925, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -24997,9 +25016,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1509 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1510 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 925, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 926, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25014,9 +25033,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1510 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
+    // Pos:1511 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 925, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 926, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25030,9 +25049,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1511 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
+    // Pos:1512 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 926, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 927, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25047,9 +25066,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1512 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1513 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 926, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 927, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25063,9 +25082,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1513 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1514 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 926, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 927, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25079,9 +25098,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1514 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
+    // Pos:1515 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 927, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25097,9 +25116,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1515 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
+    // Pos:1516 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 927, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -25114,9 +25133,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1516 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
+    // Pos:1517 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 927, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 928, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
@@ -25131,9 +25150,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1517 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM"
+    // Pos:1518 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM"
     {
-        ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 928, 
+        ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 929, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25148,9 +25167,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1518 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
+    // Pos:1519 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 929, 
+        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 930, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25165,9 +25184,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1519 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1520 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 930, 
+        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 931, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25182,9 +25201,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1520 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1521 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 931, 
+        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 932, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25199,9 +25218,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1521 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1522 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 932, 
+        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 933, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25216,9 +25235,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1522 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM"
+    // Pos:1523 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 933, 
+        ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 934, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25233,9 +25252,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1523 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
+    // Pos:1524 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 934, 
+        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 935, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25250,9 +25269,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1524 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM"
+    // Pos:1525 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 935, 
+        ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 936, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25268,9 +25287,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1525 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1526 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 936, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 937, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25284,9 +25303,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1526 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1527 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 936, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 937, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25300,9 +25319,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1527 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
+    // Pos:1528 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 937, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 938, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25318,9 +25337,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1528 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1529 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 937, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 938, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25335,9 +25354,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1529 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
+    // Pos:1530 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 938, 
+        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 939, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25351,9 +25370,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1530 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM"
+    // Pos:1531 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 939, 
+        ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 940, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25369,9 +25388,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1531 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1532 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 940, 
+        ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25385,9 +25404,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1532 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM"
+    // Pos:1533 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM"
     {
-        ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, 
+        ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 942, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25403,9 +25422,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1533 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM"
+    // Pos:1534 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 942, 
+        ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 943, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25419,9 +25438,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1534 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
+    // Pos:1535 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 943, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25436,9 +25455,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1535 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
+    // Pos:1536 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 943, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25453,9 +25472,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1536 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1537 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 943, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 944, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25470,9 +25489,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1537 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1538 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 944, 
+        ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 945, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25487,9 +25506,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1538 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1539 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 945, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 946, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25504,9 +25523,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1539 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1540 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 945, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 946, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25521,9 +25540,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1540 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
+    // Pos:1541 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 946, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 947, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25539,9 +25558,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1541 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1542 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 946, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 947, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25556,9 +25575,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1542 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM"
+    // Pos:1543 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM"
     {
-        ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 947, 
+        ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 948, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25574,9 +25593,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1543 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1544 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 948, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 949, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25590,9 +25609,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1544 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1545 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 948, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 949, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25606,9 +25625,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1545 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
+    // Pos:1546 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 949, 
+        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 950, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25622,9 +25641,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1546 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1547 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 950, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 951, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25639,9 +25658,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1547 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1548 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 950, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 951, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25655,9 +25674,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1548 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1549 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 951, 
+        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 952, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25672,9 +25691,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1549 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1550 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 952, 
+        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 953, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25689,9 +25708,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1550 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1551 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 953, 
+        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 954, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25706,9 +25725,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1551 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1552 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 954, 
+        ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25723,9 +25742,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1552 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1553 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, 
+        ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25740,9 +25759,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1553 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1554 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, 
+        ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 957, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25757,9 +25776,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1554 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1555 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 957, 
+        ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 958, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25774,9 +25793,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1555 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM"
+    // Pos:1556 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM"
     {
-        ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 958, 
+        ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 959, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25791,9 +25810,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1556 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM"
+    // Pos:1557 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM"
     {
-        ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 959, 
+        ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 960, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25808,9 +25827,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1557 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1558 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 960, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 961, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25825,9 +25844,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1558 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
+    // Pos:1559 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 960, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 961, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25841,9 +25860,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1559 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1560 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 961, 
+        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 962, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25858,9 +25877,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1560 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1561 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 962, 
+        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 963, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25875,9 +25894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1561 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1562 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 963, 
+        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 964, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -25892,9 +25911,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1562 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1563 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 964, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 965, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25908,9 +25927,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1563 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1564 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 964, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 965, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -25924,9 +25943,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1564 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
+    // Pos:1565 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 965, 
+        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 966, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25940,9 +25959,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1565 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1566 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 966, 
+        ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 967, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25956,9 +25975,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1566 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM"
+    // Pos:1567 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 967, 
+        ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 968, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -25972,9 +25991,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1567 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1568 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 968, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 969, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -25988,9 +26007,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1568 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1569 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 968, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 969, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26004,9 +26023,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1569 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
+    // Pos:1570 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 969, 
+        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 970, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26020,9 +26039,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1570 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1571 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 970, 
+        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 971, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26037,9 +26056,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1571 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1572 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 971, 
+        ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 972, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26054,9 +26073,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1572 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1573 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 972, 
+        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 973, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26071,9 +26090,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1573 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1574 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 973, 
+        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 974, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -26088,9 +26107,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1574 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1575 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 974, 
+        ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 975, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26105,9 +26124,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1575 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1576 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 975, 
+        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 976, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -26122,9 +26141,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1576 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
+    // Pos:1577 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 976, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 977, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26139,9 +26158,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1577 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
+    // Pos:1578 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 976, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 977, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26156,9 +26175,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1578 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM"
+    // Pos:1579 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 977, 
+        ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 978, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26173,9 +26192,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1579 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
+    // Pos:1580 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 978, 
+        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 979, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26190,9 +26209,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1580 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM"
+    // Pos:1581 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM"
     {
-        ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 979, 
+        ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 980, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26207,9 +26226,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1581 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM"
+    // Pos:1582 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM"
     {
-        ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 980, 
+        ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 981, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26224,9 +26243,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1582 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
+    // Pos:1583 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
     {
-        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 981, 
+        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 982, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -26243,9 +26262,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1583 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
+    // Pos:1584 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 982, 
+        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 983, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26261,9 +26280,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1584 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1585 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 982, 
+        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 983, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26278,9 +26297,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1585 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM"
+    // Pos:1586 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 983, 
+        ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 984, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26296,9 +26315,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1586 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
+    // Pos:1587 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 984, 
+        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 985, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26314,9 +26333,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1587 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1588 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 984, 
+        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 985, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26331,9 +26350,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1588 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
+    // Pos:1589 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 985, 
+        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 986, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26349,9 +26368,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1589 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1590 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 985, 
+        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 986, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26366,9 +26385,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1590 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM"
+    // Pos:1591 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 986, 
+        ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 987, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26384,9 +26403,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1591 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
+    // Pos:1592 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 987, 
+        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 988, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26402,9 +26421,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1592 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1593 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 987, 
+        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 988, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26419,9 +26438,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1593 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:1594 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 988, 
+        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 989, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
@@ -26437,9 +26456,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1594 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
+    // Pos:1595 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
     {
-        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 989, 
+        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 990, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26455,9 +26474,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1595 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
+    // Pos:1596 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
     {
-        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 990, 
+        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 991, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26473,9 +26492,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1596 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
+    // Pos:1597 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
     {
-        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 991, 
+        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 992, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -26489,9 +26508,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1597 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
+    // Pos:1598 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
     {
-        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 992, 
+        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 993, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -26505,9 +26524,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1598 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
+    // Pos:1599 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 993, 
+        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 994, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -26522,9 +26541,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1599 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
+    // Pos:1600 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 994, 
+        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 995, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -26539,9 +26558,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1600 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
+    // Pos:1601 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 995, 
+        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 996, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26556,9 +26575,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1601 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
+    // Pos:1602 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 996, 
+        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 997, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26573,9 +26592,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1602 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
+    // Pos:1603 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 997, 
+        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 998, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26590,9 +26609,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1603 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
+    // Pos:1604 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 998, 
+        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 999, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26608,9 +26627,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1604 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
+    // Pos:1605 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 999, 
+        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1000, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -26626,9 +26645,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1605 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
+    // Pos:1606 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1000, 
+        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1001, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -26644,9 +26663,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1606 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
+    // Pos:1607 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1001, 
+        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1002, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26662,9 +26681,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1607 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
+    // Pos:1608 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 1002, 
+        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 1003, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -26679,9 +26698,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1608 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
+    // Pos:1609 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1003, 
+        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1004, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26697,9 +26716,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1609 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
+    // Pos:1610 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1004, 
+        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1005, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -26715,9 +26734,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1610 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
+    // Pos:1611 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1005, 
+        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1006, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -26733,9 +26752,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1611 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
+    // Pos:1612 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1006, 
+        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1007, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26751,9 +26770,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1612 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1613 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1007, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26768,9 +26787,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1613 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1614 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1007, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26785,9 +26804,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1614 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1615 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1007, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26802,9 +26821,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1615 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1616 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1007, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1008, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -26819,9 +26838,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1616 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM"
+    // Pos:1617 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM"
     {
-        ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1008, 
+        ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1009, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26837,9 +26856,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1617 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM"
+    // Pos:1618 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM"
     {
-        ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1009, 
+        ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1010, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26855,9 +26874,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1618 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM"
+    // Pos:1619 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM"
     {
-        ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1010, 
+        ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1011, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26873,9 +26892,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1619 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM"
+    // Pos:1620 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM"
     {
-        ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1011, 
+        ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1012, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -26891,9 +26910,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1620 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
+    // Pos:1621 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1012, 
+        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1013, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26910,9 +26929,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1621 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
+    // Pos:1622 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1013, 
+        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1014, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26929,9 +26948,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1622 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
+    // Pos:1623 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1014, 
+        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1015, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26948,9 +26967,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1623 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
+    // Pos:1624 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1015, 
+        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1016, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26967,9 +26986,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1624 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
+    // Pos:1625 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1016, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1017, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -26985,9 +27004,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1625 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
+    // Pos:1626 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1016, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1017, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27002,9 +27021,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1626 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM"
+    // Pos:1627 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1017, 
+        ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1018, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27020,9 +27039,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1627 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
+    // Pos:1628 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1018, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1019, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27038,9 +27057,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1628 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
+    // Pos:1629 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1018, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1019, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27055,9 +27074,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1629 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
+    // Pos:1630 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1019, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1020, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27073,9 +27092,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1630 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
+    // Pos:1631 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1019, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1020, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27090,9 +27109,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1631 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM"
+    // Pos:1632 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1020, 
+        ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1021, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27108,9 +27127,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1632 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
+    // Pos:1633 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1021, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1022, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27126,9 +27145,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1633 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
+    // Pos:1634 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1021, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1022, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27143,9 +27162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1634 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
+    // Pos:1635 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1022, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1023, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27161,9 +27180,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1635 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
+    // Pos:1636 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1022, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1023, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27178,9 +27197,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1636 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM"
+    // Pos:1637 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1023, 
+        ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1024, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27196,9 +27215,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1637 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
+    // Pos:1638 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1024, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1025, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27214,9 +27233,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1638 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
+    // Pos:1639 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1024, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1025, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27231,9 +27250,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1639 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
+    // Pos:1640 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1025, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1026, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27249,9 +27268,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1640 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
+    // Pos:1641 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1025, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1026, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27266,9 +27285,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1641 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM"
+    // Pos:1642 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1026, 
+        ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1027, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27284,9 +27303,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1642 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
+    // Pos:1643 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1027, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1028, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27302,9 +27321,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1643 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
+    // Pos:1644 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1027, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1028, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27319,9 +27338,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1644 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
+    // Pos:1645 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1028, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1029, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27337,9 +27356,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1645 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
+    // Pos:1646 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1028, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1029, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27354,9 +27373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1646 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM"
+    // Pos:1647 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1029, 
+        ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1030, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27372,9 +27391,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1647 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
+    // Pos:1648 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1030, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1031, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27390,9 +27409,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1648 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
+    // Pos:1649 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1030, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1031, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27407,9 +27426,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1649 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
+    // Pos:1650 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1031, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1032, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27425,9 +27444,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1650 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
+    // Pos:1651 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1031, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1032, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27442,9 +27461,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1651 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM"
+    // Pos:1652 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1032, 
+        ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1033, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27460,9 +27479,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1652 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
+    // Pos:1653 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1033, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1034, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27478,9 +27497,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1653 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
+    // Pos:1654 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1033, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1034, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27495,9 +27514,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1654 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM"
+    // Pos:1655 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM"
     {
-        ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1034, 
+        ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1035, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27513,9 +27532,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1655 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM"
+    // Pos:1656 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM"
     {
-        ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1035, 
+        ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1036, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27531,9 +27550,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1656 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
+    // Pos:1657 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1036, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1037, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27549,9 +27568,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1657 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
+    // Pos:1658 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1036, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1037, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27567,9 +27586,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1658 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
+    // Pos:1659 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1037, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1038, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27585,9 +27604,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1659 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
+    // Pos:1660 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1037, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1038, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27603,9 +27622,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1660 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
+    // Pos:1661 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1038, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1039, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27621,9 +27640,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1661 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
+    // Pos:1662 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1038, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1039, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27639,9 +27658,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1662 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
+    // Pos:1663 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1039, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1040, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27657,9 +27676,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1663 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
+    // Pos:1664 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1039, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1040, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27675,9 +27694,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1664 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
+    // Pos:1665 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1040, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1041, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27693,9 +27712,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1665 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
+    // Pos:1666 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1040, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1041, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27710,9 +27729,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1666 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM"
+    // Pos:1667 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1041, 
+        ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1042, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27728,9 +27747,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1667 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
+    // Pos:1668 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1042, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1043, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27746,9 +27765,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1668 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
+    // Pos:1669 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1042, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1043, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27763,9 +27782,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1669 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
+    // Pos:1670 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1043, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1044, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27781,9 +27800,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1670 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
+    // Pos:1671 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1043, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1044, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27798,9 +27817,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1671 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM"
+    // Pos:1672 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1044, 
+        ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1045, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27816,9 +27835,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1672 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
+    // Pos:1673 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1045, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1046, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27834,9 +27853,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1673 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
+    // Pos:1674 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1045, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1046, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27851,9 +27870,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1674 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
+    // Pos:1675 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1046, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1047, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27869,9 +27888,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1675 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
+    // Pos:1676 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1046, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1047, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27886,9 +27905,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1676 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM"
+    // Pos:1677 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1047, 
+        ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1048, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -27904,9 +27923,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1677 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
+    // Pos:1678 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1048, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1049, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -27922,9 +27941,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1678 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
+    // Pos:1679 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1048, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1049, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -27939,9 +27958,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1679 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
+    // Pos:1680 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1049, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1050, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27957,9 +27976,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1680 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
+    // Pos:1681 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1049, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1050, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27975,9 +27994,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1681 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
+    // Pos:1682 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1050, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1051, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -27993,9 +28012,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1682 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
+    // Pos:1683 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1050, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1051, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28011,9 +28030,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1683 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
+    // Pos:1684 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1051, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1052, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28029,9 +28048,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1684 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
+    // Pos:1685 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1051, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1052, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28046,9 +28065,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1685 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM"
+    // Pos:1686 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1052, 
+        ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1053, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28064,9 +28083,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1686 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
+    // Pos:1687 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1053, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1054, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28082,9 +28101,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1687 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
+    // Pos:1688 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1053, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1054, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28099,9 +28118,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1688 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
+    // Pos:1689 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1054, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1055, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28117,9 +28136,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1689 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
+    // Pos:1690 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1054, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1055, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28134,9 +28153,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1690 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM"
+    // Pos:1691 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1055, 
+        ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1056, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28152,9 +28171,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1691 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
+    // Pos:1692 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1056, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1057, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28170,9 +28189,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1692 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
+    // Pos:1693 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1056, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1057, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28187,9 +28206,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1693 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
+    // Pos:1694 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1057, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28205,9 +28224,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1694 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
+    // Pos:1695 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1057, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1058, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28222,9 +28241,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1695 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM"
+    // Pos:1696 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1058, 
+        ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1059, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28240,9 +28259,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1696 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
+    // Pos:1697 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1059, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1060, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28258,9 +28277,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1697 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
+    // Pos:1698 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1059, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1060, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28275,9 +28294,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1698 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
+    // Pos:1699 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1060, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1061, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28293,9 +28312,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1699 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
+    // Pos:1700 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1060, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1061, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28310,9 +28329,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1700 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM"
+    // Pos:1701 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1061, 
+        ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1062, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28328,9 +28347,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1701 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
+    // Pos:1702 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1062, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1063, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28346,9 +28365,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1702 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
+    // Pos:1703 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1062, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1063, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28363,9 +28382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1703 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
+    // Pos:1704 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1063, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1064, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28381,9 +28400,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1704 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
+    // Pos:1705 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1063, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1064, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28398,9 +28417,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1705 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM"
+    // Pos:1706 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1064, 
+        ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1065, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28416,9 +28435,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1706 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
+    // Pos:1707 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1065, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1066, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28434,9 +28453,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1707 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
+    // Pos:1708 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1065, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1066, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28451,9 +28470,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1708 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
+    // Pos:1709 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1066, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1067, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28469,9 +28488,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1709 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
+    // Pos:1710 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1066, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1067, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28486,9 +28505,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1710 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM"
+    // Pos:1711 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1067, 
+        ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1068, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28504,9 +28523,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1711 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
+    // Pos:1712 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1068, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1069, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28522,9 +28541,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1712 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
+    // Pos:1713 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1068, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1069, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28539,9 +28558,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1713 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
+    // Pos:1714 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1069, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1070, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28557,9 +28576,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1714 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
+    // Pos:1715 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1069, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1070, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28574,9 +28593,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1715 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM"
+    // Pos:1716 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1070, 
+        ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1071, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28592,9 +28611,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1716 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
+    // Pos:1717 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1071, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1072, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28610,9 +28629,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1717 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
+    // Pos:1718 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1071, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1072, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28627,9 +28646,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1718 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
+    // Pos:1719 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1072, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1073, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28645,9 +28664,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1719 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
+    // Pos:1720 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1072, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1073, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28662,9 +28681,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1720 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM"
+    // Pos:1721 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1073, 
+        ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1074, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28680,9 +28699,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1721 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
+    // Pos:1722 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1074, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1075, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28698,9 +28717,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1722 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
+    // Pos:1723 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1074, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1075, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28715,9 +28734,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1723 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
+    // Pos:1724 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1075, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1076, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28733,9 +28752,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1724 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
+    // Pos:1725 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1075, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1076, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28750,9 +28769,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1725 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM"
+    // Pos:1726 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1076, 
+        ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1077, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -28768,9 +28787,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1726 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
+    // Pos:1727 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1077, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1078, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -28786,9 +28805,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1727 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
+    // Pos:1728 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1077, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1078, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -28803,9 +28822,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1728 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
+    // Pos:1729 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1078, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28821,9 +28840,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1729 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
+    // Pos:1730 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1078, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1079, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28839,9 +28858,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1730 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
+    // Pos:1731 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1079, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28857,9 +28876,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1731 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
+    // Pos:1732 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1079, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1080, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28875,9 +28894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1732 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
+    // Pos:1733 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1080, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28893,9 +28912,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1733 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
+    // Pos:1734 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1080, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1081, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28911,9 +28930,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1734 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
+    // Pos:1735 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1081, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28929,9 +28948,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1735 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
+    // Pos:1736 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1081, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1082, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28947,9 +28966,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1736 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
+    // Pos:1737 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1082, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1083, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28965,9 +28984,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1737 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
+    // Pos:1738 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1082, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1083, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -28983,9 +29002,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1738 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
+    // Pos:1739 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1083, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1084, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29001,9 +29020,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1739 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
+    // Pos:1740 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1083, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1084, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29019,9 +29038,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1740 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM"
+    // Pos:1741 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM"
     {
-        ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1084, 
+        ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1085, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29037,9 +29056,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1741 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM"
+    // Pos:1742 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM"
     {
-        ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1085, 
+        ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1086, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29055,9 +29074,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1742 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
+    // Pos:1743 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1086, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29073,9 +29092,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1743 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
+    // Pos:1744 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1086, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1087, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29090,9 +29109,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1744 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM"
+    // Pos:1745 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1087, 
+        ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1088, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29108,9 +29127,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1745 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
+    // Pos:1746 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1088, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29126,9 +29145,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1746 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
+    // Pos:1747 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1088, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1089, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29143,9 +29162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1747 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
+    // Pos:1748 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1089, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1090, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29161,9 +29180,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1748 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
+    // Pos:1749 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1089, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1090, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29178,9 +29197,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1749 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM"
+    // Pos:1750 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1090, 
+        ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1091, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29196,9 +29215,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1750 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
+    // Pos:1751 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1091, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29214,9 +29233,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1751 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
+    // Pos:1752 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1091, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1092, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29231,9 +29250,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1752 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
+    // Pos:1753 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1092, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29249,9 +29268,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1753 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
+    // Pos:1754 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1092, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1093, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29266,9 +29285,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1754 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM"
+    // Pos:1755 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1093, 
+        ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1094, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29284,9 +29303,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1755 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
+    // Pos:1756 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1094, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29302,9 +29321,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1756 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
+    // Pos:1757 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1094, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1095, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29319,9 +29338,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1757 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
+    // Pos:1758 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1095, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29337,9 +29356,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1758 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
+    // Pos:1759 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1095, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1096, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29354,9 +29373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1759 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM"
+    // Pos:1760 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1096, 
+        ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1097, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29372,9 +29391,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1760 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
+    // Pos:1761 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1097, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1098, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29390,9 +29409,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1761 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
+    // Pos:1762 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1097, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1098, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29407,9 +29426,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1762 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
+    // Pos:1763 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1098, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29425,9 +29444,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1763 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
+    // Pos:1764 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1098, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1099, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29442,9 +29461,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1764 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM"
+    // Pos:1765 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1099, 
+        ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1100, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29460,9 +29479,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1765 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
+    // Pos:1766 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1100, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1101, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29478,9 +29497,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1766 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
+    // Pos:1767 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1100, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1101, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29495,9 +29514,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1767 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
+    // Pos:1768 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1101, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29513,9 +29532,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1768 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
+    // Pos:1769 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1101, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1102, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29530,9 +29549,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1769 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM"
+    // Pos:1770 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1102, 
+        ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1103, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29548,9 +29567,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1770 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
+    // Pos:1771 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1103, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29566,9 +29585,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1771 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
+    // Pos:1772 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1103, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1104, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29583,9 +29602,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1772 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
+    // Pos:1773 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1104, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1105, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29601,9 +29620,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1773 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
+    // Pos:1774 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1104, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1105, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29619,9 +29638,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1774 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
+    // Pos:1775 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1105, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1106, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29637,9 +29656,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1775 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
+    // Pos:1776 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1105, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1106, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29655,9 +29674,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1776 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
+    // Pos:1777 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1106, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29673,9 +29692,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1777 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
+    // Pos:1778 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1106, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1107, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29691,9 +29710,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1778 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
+    // Pos:1779 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1107, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29709,9 +29728,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1779 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
+    // Pos:1780 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1107, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1108, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -29727,9 +29746,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1780 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
+    // Pos:1781 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1108, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29745,9 +29764,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1781 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
+    // Pos:1782 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1108, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1109, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29762,9 +29781,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1782 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM"
+    // Pos:1783 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1109, 
+        ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1110, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29780,9 +29799,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1783 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
+    // Pos:1784 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1110, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29798,9 +29817,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1784 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
+    // Pos:1785 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1110, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1111, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29815,9 +29834,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1785 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
+    // Pos:1786 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1111, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1112, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29833,9 +29852,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1786 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
+    // Pos:1787 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1111, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1112, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29850,9 +29869,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1787 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM"
+    // Pos:1788 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1112, 
+        ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1113, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29868,9 +29887,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1788 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
+    // Pos:1789 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1113, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29886,9 +29905,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1789 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
+    // Pos:1790 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1113, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1114, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29903,9 +29922,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1790 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
+    // Pos:1791 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1114, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29921,9 +29940,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1791 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
+    // Pos:1792 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1114, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1115, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29938,9 +29957,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1792 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM"
+    // Pos:1793 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1115, 
+        ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1116, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -29956,9 +29975,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1793 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
+    // Pos:1794 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1116, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1117, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -29974,9 +29993,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1794 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
+    // Pos:1795 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1116, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1117, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -29991,9 +30010,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1795 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
+    // Pos:1796 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1117, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1118, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30009,9 +30028,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1796 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
+    // Pos:1797 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1117, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1118, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -30026,9 +30045,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1797 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM"
+    // Pos:1798 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1118, 
+        ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1119, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30044,9 +30063,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1798 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
+    // Pos:1799 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1119, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1120, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30062,9 +30081,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1799 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
+    // Pos:1800 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1119, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1120, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -30079,9 +30098,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1800 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
+    // Pos:1801 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1120, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1121, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30097,9 +30116,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1801 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
+    // Pos:1802 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1120, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1121, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -30114,9 +30133,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1802 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM"
+    // Pos:1803 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1121, 
+        ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1122, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30132,9 +30151,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1803 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
+    // Pos:1804 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1122, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1123, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30150,9 +30169,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1804 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
+    // Pos:1805 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1122, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1123, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -30167,9 +30186,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1805 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
+    // Pos:1806 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1123, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1124, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30185,9 +30204,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1806 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
+    // Pos:1807 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1123, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1124, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -30202,9 +30221,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1807 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM"
+    // Pos:1808 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1124, 
+        ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1125, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30220,9 +30239,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1808 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
+    // Pos:1809 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1125, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1126, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30238,9 +30257,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1809 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
+    // Pos:1810 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1125, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1126, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
@@ -30255,9 +30274,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1810 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
+    // Pos:1811 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1126, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1127, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30273,9 +30292,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1811 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
+    // Pos:1812 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1126, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1127, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30291,9 +30310,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1812 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
+    // Pos:1813 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1127, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1128, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30309,9 +30328,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1813 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
+    // Pos:1814 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1127, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1128, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30327,9 +30346,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1814 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
+    // Pos:1815 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1128, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1129, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30345,9 +30364,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1815 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
+    // Pos:1816 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1128, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1129, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30363,9 +30382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1816 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
+    // Pos:1817 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1129, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1130, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30381,9 +30400,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1817 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
+    // Pos:1818 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1129, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1130, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
@@ -30399,9 +30418,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1818 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
+    // Pos:1819 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1130, 
+        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1131, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -30417,9 +30436,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1819 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI"
+    // Pos:1820 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1131, 
+        ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1132, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30435,9 +30454,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1820 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
+    // Pos:1821 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1132, 
+        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1133, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -30453,9 +30472,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1821 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
+    // Pos:1822 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1133, 
+        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1134, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -30471,9 +30490,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1822 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI"
+    // Pos:1823 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1134, 
+        ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1135, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30489,9 +30508,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1823 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
+    // Pos:1824 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1135, 
+        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1136, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -30507,9 +30526,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1824 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
+    // Pos:1825 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
     {
-        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1136, 
+        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1137, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -30523,9 +30542,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1825 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
+    // Pos:1826 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
     {
-        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1137, 
+        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1138, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -30539,9 +30558,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1826 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
+    // Pos:1827 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
     {
-        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1138, 
+        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1139, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -30555,9 +30574,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1827 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
+    // Pos:1828 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
     {
-        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1139, 
+        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1140, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -30571,9 +30590,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1828 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
+    // Pos:1829 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1140, 
+        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1141, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30588,9 +30607,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1829 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
+    // Pos:1830 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1140, 
+        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1141, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -30605,9 +30624,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1830 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
+    // Pos:1831 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1141, 
+        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1142, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30622,9 +30641,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1831 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
+    // Pos:1832 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1141, 
+        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1142, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -30639,9 +30658,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1832 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
+    // Pos:1833 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1142, 
+        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30655,9 +30674,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1833 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
+    // Pos:1834 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, 
+        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30671,9 +30690,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1834 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
+    // Pos:1835 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, 
+        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30687,9 +30706,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1835 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
+    // Pos:1836 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, 
+        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30703,9 +30722,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1836 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
+    // Pos:1837 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, 
+        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1147, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30719,9 +30738,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1837 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
+    // Pos:1838 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1147, 
+        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1148, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30735,9 +30754,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1838 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
+    // Pos:1839 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1148, 
+        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1149, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30751,9 +30770,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1839 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
+    // Pos:1840 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1149, 
+        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1150, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -30767,9 +30786,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1840 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
+    // Pos:1841 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1150, 
+        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1151, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30784,9 +30803,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1841 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
+    // Pos:1842 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1150, 
+        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1151, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -30801,9 +30820,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1842 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
+    // Pos:1843 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1151, 
+        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1152, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30818,9 +30837,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1843 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
+    // Pos:1844 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1151, 
+        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1152, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -30835,9 +30854,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1844 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
+    // Pos:1845 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1152, 
+        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1153, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30852,9 +30871,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1845 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM"
+    // Pos:1846 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1153, 
+        ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1154, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30869,9 +30888,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1846 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
+    // Pos:1847 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1154, 
+        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1155, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30886,9 +30905,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1847 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
+    // Pos:1848 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1155, 
+        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1156, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30904,9 +30923,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1848 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM"
+    // Pos:1849 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1156, 
+        ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1157, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30922,9 +30941,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1849 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
+    // Pos:1850 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1157, 
+        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1158, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30940,9 +30959,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1850 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
+    // Pos:1851 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1158, 
+        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1159, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30958,9 +30977,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1851 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI"
+    // Pos:1852 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1159, 
+        ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1160, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -30976,9 +30995,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1852 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
+    // Pos:1853 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1160, 
+        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1161, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -30994,9 +31013,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1853 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
+    // Pos:1854 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1161, 
+        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1162, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31013,9 +31032,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1854 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI"
+    // Pos:1855 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1162, 
+        ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1163, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -31032,9 +31051,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1855 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
+    // Pos:1856 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1163, 
+        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1164, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31051,9 +31070,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1856 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
+    // Pos:1857 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1164, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -31070,9 +31089,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1857 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
+    // Pos:1858 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1164, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -31088,9 +31107,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1858 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
+    // Pos:1859 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1166, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -31107,9 +31126,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1859 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
+    // Pos:1860 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1166, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -31125,9 +31144,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1860 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
+    // Pos:1861 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1166, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1167, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -31143,9 +31162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1861 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
+    // Pos:1862 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1166, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1167, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
@@ -31160,9 +31179,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1862 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1863 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1167, 
+        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1168, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31177,9 +31196,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1863 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1864 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1168, 
+        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1169, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31194,9 +31213,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1864 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1865 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1169, 
+        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1170, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31211,9 +31230,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1865 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1866 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1170, 
+        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1171, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31228,9 +31247,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1866 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
+    // Pos:1867 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1171, 
+        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1172, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31246,9 +31265,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1867 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
+    // Pos:1868 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1172, 
+        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1173, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31265,9 +31284,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1868 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
+    // Pos:1869 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1173, 
+        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1174, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31284,9 +31303,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1869 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
+    // Pos:1870 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1174, 
+        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1175, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31303,9 +31322,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1870 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
+    // Pos:1871 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1175, 
+        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1176, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31322,9 +31341,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1871 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
+    // Pos:1872 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1176, 
+        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1177, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -31340,9 +31359,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1872 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
+    // Pos:1873 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1177, 
+        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31359,9 +31378,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1873 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
+    // Pos:1874 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1178, 
+        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1179, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31378,9 +31397,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1874 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
+    // Pos:1875 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1179, 
+        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1180, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -31397,9 +31416,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1875 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
+    // Pos:1876 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1180, 
+        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1181, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31416,9 +31435,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1876 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1877 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1181, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31434,9 +31453,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1877 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1878 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1181, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31452,9 +31471,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1878 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1879 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1181, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31470,9 +31489,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1879 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1880 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1181, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1182, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31488,9 +31507,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1880 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
+    // Pos:1881 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
     {
-        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1182, 
+        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1183, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31504,9 +31523,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1881 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
+    // Pos:1882 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
     {
-        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1183, 
+        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1184, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
@@ -31520,9 +31539,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1882 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
+    // Pos:1883 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
     {
-        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1184, 
+        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1185, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31537,9 +31556,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1883 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
+    // Pos:1884 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1185, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1186, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31554,9 +31573,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1884 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
+    // Pos:1885 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1185, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1186, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31571,9 +31590,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1885 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
+    // Pos:1886 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1186, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1187, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31588,9 +31607,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1886 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
+    // Pos:1887 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1186, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1187, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31605,9 +31624,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1887 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
+    // Pos:1888 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1187, 
+        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1188, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31623,9 +31642,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1888 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1889 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1187, 
+        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1188, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31640,9 +31659,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1889 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM"
+    // Pos:1890 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1188, 
+        ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1189, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -31658,9 +31677,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1890 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
+    // Pos:1891 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1189, 
+        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1190, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31676,9 +31695,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1891 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1892 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1189, 
+        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1190, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31693,9 +31712,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1892 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
+    // Pos:1893 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1190, 
+        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1191, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31711,9 +31730,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1893 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1894 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1190, 
+        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1191, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31728,9 +31747,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1894 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM"
+    // Pos:1895 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1191, 
+        ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1192, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -31746,9 +31765,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1895 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
+    // Pos:1896 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1192, 
+        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1193, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31764,9 +31783,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1896 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1897 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1192, 
+        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1193, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31781,9 +31800,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1897 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/""
+    // Pos:1898 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/""
     {
-        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1193, 
+        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1194, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31796,9 +31815,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1898 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1899 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1194, 
+        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1195, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31812,9 +31831,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1899 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
+    // Pos:1900 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
     {
-        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1195, 
+        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1196, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -31827,9 +31846,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1900 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
+    // Pos:1901 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1196, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1197, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -31842,9 +31861,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1901 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
+    // Pos:1902 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1196, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1197, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -31857,9 +31876,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1902 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
+    // Pos:1903 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1197, 
+        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1198, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31875,9 +31894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1903 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1904 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1197, 
+        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1198, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31892,9 +31911,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1904 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM"
+    // Pos:1905 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1198, 
+        ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -31910,9 +31929,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1905 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
+    // Pos:1906 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1199, 
+        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31928,9 +31947,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1906 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1907 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1199, 
+        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1200, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31945,9 +31964,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1907 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
+    // Pos:1908 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 
+        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1201, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -31963,9 +31982,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1908 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1909 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1200, 
+        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1201, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -31980,9 +31999,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1909 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM"
+    // Pos:1910 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1201, 
+        ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1202, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -31998,9 +32017,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1910 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
+    // Pos:1911 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1202, 
+        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1203, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32016,9 +32035,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1911 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1912 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1202, 
+        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1203, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32033,9 +32052,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1912 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/""
+    // Pos:1913 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/""
     {
-        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1203, 
+        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1204, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -32048,9 +32067,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1913 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
+    // Pos:1914 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
     {
-        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1204, 
+        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1205, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -32063,9 +32082,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1914 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
+    // Pos:1915 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1205, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1206, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -32078,9 +32097,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1915 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
+    // Pos:1916 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1205, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1206, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -32093,9 +32112,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1916 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
+    // Pos:1917 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32110,9 +32129,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1917 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
+    // Pos:1918 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1206, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32127,9 +32146,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1918 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
+    // Pos:1919 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1206, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32143,9 +32162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1919 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
+    // Pos:1920 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1206, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32159,9 +32178,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1920 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
+    // Pos:1921 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32176,9 +32195,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1921 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
+    // Pos:1922 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32193,9 +32212,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1922 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
+    // Pos:1923 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32209,9 +32228,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1923 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
+    // Pos:1924 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32225,9 +32244,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1924 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1925 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32241,9 +32260,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1925 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1926 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32257,9 +32276,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1926 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1927 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1209, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32273,9 +32292,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1927 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1928 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1209, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32289,9 +32308,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1928 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
+    // Pos:1929 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32306,9 +32325,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1929 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
+    // Pos:1930 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32323,9 +32342,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1930 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
+    // Pos:1931 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32340,9 +32359,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1931 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
+    // Pos:1932 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1209, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32356,9 +32375,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1932 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
+    // Pos:1933 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1209, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32372,9 +32391,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1933 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
+    // Pos:1934 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1211, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32388,9 +32407,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1934 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
+    // Pos:1935 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1211, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32404,9 +32423,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1935 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1936 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1211, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32421,9 +32440,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1936 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1937 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1211, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32438,9 +32457,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1937 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1938 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32455,9 +32474,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1938 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1939 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32472,9 +32491,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1939 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
+    // Pos:1940 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1213, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1214, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32488,9 +32507,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1940 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
+    // Pos:1941 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1213, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1214, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32504,9 +32523,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1941 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1942 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1214, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32521,9 +32540,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1942 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1943 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1214, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32538,9 +32557,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1943 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1944 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1215, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32555,9 +32574,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1944 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1945 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1215, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32572,9 +32591,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1945 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1946 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32589,9 +32608,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1946 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1947 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32606,9 +32625,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1947 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1948 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1217, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1218, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32623,9 +32642,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1948 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1949 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1217, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1218, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -32640,9 +32659,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1949 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
+    // Pos:1950 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1218, 
+        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32657,9 +32676,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1950 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
+    // Pos:1951 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1218, 
+        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1219, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32674,9 +32693,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1951 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
+    // Pos:1952 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32691,9 +32710,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1952 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
+    // Pos:1953 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32707,9 +32726,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1953 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1954 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1219, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32724,9 +32743,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1954 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1955 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1219, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32740,9 +32759,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1955 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
+    // Pos:1956 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32757,9 +32776,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1956 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
+    // Pos:1957 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32773,9 +32792,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1957 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1958 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32790,9 +32809,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1958 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1959 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32806,9 +32825,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1959 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
+    // Pos:1960 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 
+        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32823,9 +32842,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1960 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
+    // Pos:1961 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1221, 
+        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1222, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32840,9 +32859,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1961 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
+    // Pos:1962 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1222, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32857,9 +32876,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1962 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
+    // Pos:1963 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1222, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32873,9 +32892,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1963 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1964 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1222, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32890,9 +32909,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1964 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1965 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1222, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32906,9 +32925,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1965 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
+    // Pos:1966 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32923,9 +32942,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1966 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
+    // Pos:1967 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -32939,9 +32958,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1967 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1968 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32956,9 +32975,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1968 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1969 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1224, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32972,9 +32991,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1969 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1970 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1224, 
+        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1225, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -32988,9 +33007,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1970 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1971 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1225, 
+        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1226, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33004,9 +33023,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1971 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
+    // Pos:1972 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1226, 
+        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33020,9 +33039,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1972 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
+    // Pos:1973 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1226, 
+        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1227, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33036,9 +33055,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1973 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
+    // Pos:1974 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 
+        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33052,9 +33071,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1974 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
+    // Pos:1975 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1227, 
+        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1228, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33068,9 +33087,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1975 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
+    // Pos:1976 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 
+        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33084,9 +33103,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1976 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1977 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1228, 
+        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1229, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33100,9 +33119,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1977 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
+    // Pos:1978 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 
+        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33116,9 +33135,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1978 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1979 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1229, 
+        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1230, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33132,9 +33151,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1979 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1980 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33148,9 +33167,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1980 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1981 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33164,9 +33183,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1981 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
+    // Pos:1982 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33180,9 +33199,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1982 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
+    // Pos:1983 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33196,9 +33215,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1983 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1984 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33212,9 +33231,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1984 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1985 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33228,9 +33247,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1985 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
+    // Pos:1986 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33244,9 +33263,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1986 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
+    // Pos:1987 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1230, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33260,9 +33279,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1987 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
+    // Pos:1988 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33277,9 +33296,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1988 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
+    // Pos:1989 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33295,9 +33314,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1989 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
+    // Pos:1990 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33312,9 +33331,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1990 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
+    // Pos:1991 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33330,9 +33349,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1991 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1992 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33347,9 +33366,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1992 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1993 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33363,9 +33382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1993 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1994 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33380,9 +33399,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1994 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1995 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33396,9 +33415,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1995 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+    // Pos:1996 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1232, 
+        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33413,9 +33432,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1996 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+    // Pos:1997 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1232, 
+        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33431,9 +33450,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1997 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+    // Pos:1998 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1232, 
+        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33448,9 +33467,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1998 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+    // Pos:1999 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1232, 
+        ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33466,9 +33485,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:1999 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
+    // Pos:2000 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1233, 
+        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33483,9 +33502,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2000 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
+    // Pos:2001 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1233, 
+        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1234, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33499,9 +33518,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2001 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
+    // Pos:2002 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 
+        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33516,9 +33535,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2002 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
+    // Pos:2003 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1234, 
+        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1235, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33532,9 +33551,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2003 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+    // Pos:2004 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33549,9 +33568,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2004 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+    // Pos:2005 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33567,9 +33586,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2005 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+    // Pos:2006 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33584,9 +33603,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2006 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+    // Pos:2007 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33602,9 +33621,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2007 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:2008 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33619,9 +33638,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2008 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:2009 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33635,9 +33654,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2009 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:2010 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33652,9 +33671,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2010 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:2011 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1235, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33668,9 +33687,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2011 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
+    // Pos:2012 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33685,9 +33704,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2012 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
+    // Pos:2013 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33702,9 +33721,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2013 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
+    // Pos:2014 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33718,9 +33737,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2014 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
+    // Pos:2015 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1237, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33734,9 +33753,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2015 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
+    // Pos:2016 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33751,9 +33770,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2016 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
+    // Pos:2017 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33768,9 +33787,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2017 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
+    // Pos:2018 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1237, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33784,9 +33803,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2018 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
+    // Pos:2019 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1237, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1238, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33800,9 +33819,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2019 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM"
+    // Pos:2020 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM"
     {
-        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1238, 
+        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33816,9 +33835,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2020 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM"
+    // Pos:2021 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM"
     {
-        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1238, 
+        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33832,9 +33851,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2021 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR"
+    // Pos:2022 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR"
     {
-        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1238, 
+        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33848,9 +33867,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2022 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR"
+    // Pos:2023 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR"
     {
-        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1238, 
+        ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -33864,9 +33883,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2023 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
+    // Pos:2024 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
     {
-        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1239, 
+        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1240, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -33882,9 +33901,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2024 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
+    // Pos:2025 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1240, 
+        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1241, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -33898,9 +33917,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2025 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
+    // Pos:2026 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
     {
-        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1241, 
+        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1242, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -33914,9 +33933,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2026 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
+    // Pos:2027 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
     {
-        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1242, 
+        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1243, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -33931,9 +33950,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2027 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/""
+    // Pos:2028 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/""
     {
-        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1243, 
+        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1244, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -33946,9 +33965,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2028 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
+    // Pos:2029 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
     {
-        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1244, 
+        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1245, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -33961,9 +33980,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2029 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
+    // Pos:2030 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
     {
-        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1245, 
+        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1246, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
@@ -33976,9 +33995,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2030 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
+    // Pos:2031 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1246, 
+        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1247, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -33994,9 +34013,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2031 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
+    // Pos:2032 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1246, 
+        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1247, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34011,9 +34030,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2032 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM"
+    // Pos:2033 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1247, 
+        ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1248, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -34029,9 +34048,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2033 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
+    // Pos:2034 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1248, 
+        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1249, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34047,9 +34066,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2034 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
+    // Pos:2035 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1248, 
+        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1249, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34064,9 +34083,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2035 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
+    // Pos:2036 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1249, 
+        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1250, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34082,9 +34101,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2036 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
+    // Pos:2037 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1249, 
+        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1250, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34099,9 +34118,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2037 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM"
+    // Pos:2038 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1250, 
+        ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1251, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -34117,9 +34136,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2038 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
+    // Pos:2039 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1251, 
+        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1252, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34135,9 +34154,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2039 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
+    // Pos:2040 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1251, 
+        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1252, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34152,9 +34171,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2040 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
+    // Pos:2041 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
     {
-        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1252, 
+        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1253, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -34169,9 +34188,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2041 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/""
+    // Pos:2042 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/""
     {
-        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1253, 
+        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1254, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -34184,9 +34203,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2042 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
+    // Pos:2043 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1254, 
+        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1255, 
         0, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
@@ -34200,9 +34219,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2043 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
+    // Pos:2044 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1255, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1256, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -34218,9 +34237,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2044 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
+    // Pos:2045 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1255, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1256, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34235,9 +34254,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2045 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
+    // Pos:2046 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1256, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1257, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -34253,9 +34272,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2046 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
+    // Pos:2047 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1256, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1257, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34270,9 +34289,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2047 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
+    // Pos:2048 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1257, 
+        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1258, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
@@ -34287,9 +34306,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2048 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
+    // Pos:2049 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1258, 
+        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1259, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
@@ -34304,9 +34323,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2049 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
+    // Pos:2050 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1259, 
+        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1260, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
@@ -34322,9 +34341,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2050 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
+    // Pos:2051 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1260, 
+        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1261, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
@@ -34340,9 +34359,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2051 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
+    // Pos:2052 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1261, 
+        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1262, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34357,9 +34376,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2052 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
+    // Pos:2053 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1261, 
+        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1262, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34373,9 +34392,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2053 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
+    // Pos:2054 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1262, 
+        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1263, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34390,9 +34409,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2054 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
+    // Pos:2055 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1262, 
+        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1263, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34406,9 +34425,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2055 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
+    // Pos:2056 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
     {
-        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1263, 
+        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1264, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34423,9 +34442,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2056 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
+    // Pos:2057 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1264, 
+        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34440,9 +34459,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2057 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
+    // Pos:2058 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1264, 
+        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1265, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34456,9 +34475,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2058 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
+    // Pos:2059 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34474,9 +34493,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2059 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
+    // Pos:2060 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1265, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1266, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34491,9 +34510,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2060 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
+    // Pos:2061 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34509,9 +34528,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2061 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
+    // Pos:2062 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1266, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1267, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34526,9 +34545,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2062 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
+    // Pos:2063 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34544,9 +34563,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2063 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
+    // Pos:2064 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1267, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1268, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34561,9 +34580,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2064 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
+    // Pos:2065 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34579,9 +34598,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2065 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
+    // Pos:2066 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1268, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1269, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34596,9 +34615,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2066 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
+    // Pos:2067 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, 
+        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34614,9 +34633,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2067 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
+    // Pos:2068 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1269, 
+        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1270, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34631,9 +34650,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2068 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
+    // Pos:2069 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1270, 
+        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1271, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34649,9 +34668,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2069 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
+    // Pos:2070 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1270, 
+        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1271, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34666,9 +34685,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2070 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
+    // Pos:2071 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1271, 
+        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1272, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34684,9 +34703,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2071 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
+    // Pos:2072 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1271, 
+        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1272, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34701,9 +34720,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2072 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
+    // Pos:2073 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, 
+        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34719,9 +34738,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2073 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
+    // Pos:2074 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1272, 
+        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1273, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34736,9 +34755,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2074 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
+    // Pos:2075 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 
+        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34754,9 +34773,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2075 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
+    // Pos:2076 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1273, 
+        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1274, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34771,9 +34790,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2076 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
+    // Pos:2077 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, 
+        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34789,9 +34808,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2077 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:2078 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1274, 
+        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1275, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34806,9 +34825,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2078 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
+    // Pos:2079 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 
+        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34824,9 +34843,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2079 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:2080 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1275, 
+        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1276, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34841,9 +34860,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2080 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
+    // Pos:2081 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, 
+        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1277, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34859,9 +34878,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2081 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
+    // Pos:2082 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1276, 
+        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1277, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34876,9 +34895,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2082 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
+    // Pos:2083 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1277, 
+        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1278, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -34895,9 +34914,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2083 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
+    // Pos:2084 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1277, 
+        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1278, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34913,9 +34932,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2084 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
+    // Pos:2085 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
     {
-        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1278, 
+        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1279, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34930,9 +34949,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2085 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
+    // Pos:2086 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1279, 
+        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1280, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34948,9 +34967,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2086 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:2087 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1280, 
+        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1281, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -34965,9 +34984,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2087 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
+    // Pos:2088 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1281, 
+        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1282, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -34983,9 +35002,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2088 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
+    // Pos:2089 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1282, 
+        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1283, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35001,9 +35020,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2089 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
+    // Pos:2090 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1283, 
+        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1284, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35019,9 +35038,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2090 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
+    // Pos:2091 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1284, 
+        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1285, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35037,9 +35056,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2091 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
+    // Pos:2092 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1284, 
+        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1285, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35054,9 +35073,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2092 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
+    // Pos:2093 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1285, 
+        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35072,9 +35091,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2093 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
+    // Pos:2094 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1285, 
+        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1286, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35089,9 +35108,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2094 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
+    // Pos:2095 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1286, 
+        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1287, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35107,9 +35126,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2095 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:2096 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1287, 
+        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1288, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35125,9 +35144,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2096 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
+    // Pos:2097 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1288, 
+        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1289, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35143,9 +35162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2097 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
+    // Pos:2098 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1289, 
+        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1290, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35161,9 +35180,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2098 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
+    // Pos:2099 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1290, 
+        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1291, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35179,9 +35198,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2099 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
+    // Pos:2100 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
     {
-        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1291, 
+        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1292, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35197,9 +35216,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2100 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
+    // Pos:2101 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1292, 
+        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1293, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35215,9 +35234,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2101 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:2102 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1293, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35232,9 +35251,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2102 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
+    // Pos:2103 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1293, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35249,9 +35268,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2103 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
+    // Pos:2104 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1293, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1294, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35265,9 +35284,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2104 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
+    // Pos:2105 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1294, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35282,9 +35301,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2105 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
+    // Pos:2106 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1294, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35299,9 +35318,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2106 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
+    // Pos:2107 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1294, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1295, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35315,9 +35334,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2107 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
+    // Pos:2108 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1295, 
+        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1296, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -35331,9 +35350,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2108 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
+    // Pos:2109 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1296, 
+        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1297, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -35347,9 +35366,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2109 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
+    // Pos:2110 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1297, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35364,9 +35383,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2110 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
+    // Pos:2111 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1297, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35381,9 +35400,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2111 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
+    // Pos:2112 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1297, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1298, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35397,9 +35416,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2112 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:2113 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1298, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1299, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35414,9 +35433,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2113 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
+    // Pos:2114 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1298, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1299, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35431,9 +35450,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2114 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
+    // Pos:2115 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1298, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1299, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -35447,9 +35466,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2115 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:2116 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1299, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1300, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
@@ -35465,9 +35484,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2116 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:2117 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1299, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1300, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
@@ -35483,9 +35502,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2117 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
+    // Pos:2118 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1300, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1301, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35501,9 +35520,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2118 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
+    // Pos:2119 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1300, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1301, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -35519,9 +35538,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2119 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
+    // Pos:2120 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1301, 
+        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1302, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35538,9 +35557,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2120 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
+    // Pos:2121 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1302, 
+        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1303, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35557,9 +35576,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2121 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
+    // Pos:2122 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1303, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1304, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35575,9 +35594,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2122 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
+    // Pos:2123 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1303, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1304, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35592,9 +35611,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2123 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
+    // Pos:2124 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1304, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1305, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35610,9 +35629,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2124 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
+    // Pos:2125 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1304, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1305, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35627,9 +35646,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2125 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
+    // Pos:2126 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1305, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1306, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35645,9 +35664,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2126 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
+    // Pos:2127 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1305, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1306, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35662,9 +35681,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2127 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
+    // Pos:2128 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1306, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1307, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35680,9 +35699,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2128 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
+    // Pos:2129 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1306, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1307, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35697,9 +35716,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2129 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
+    // Pos:2130 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1307, 
+        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1308, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35718,9 +35737,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2130 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
+    // Pos:2131 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1308, 
+        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1309, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35739,9 +35758,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2131 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
+    // Pos:2132 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1309, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35757,9 +35776,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2132 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
+    // Pos:2133 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1309, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1310, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35774,9 +35793,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2133 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:2134 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1310, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1311, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35792,9 +35811,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2134 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
+    // Pos:2135 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1310, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1311, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35809,9 +35828,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2135 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
+    // Pos:2136 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1311, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35827,9 +35846,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2136 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
+    // Pos:2137 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1311, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1312, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35844,9 +35863,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2137 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
+    // Pos:2138 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1312, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1313, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35862,9 +35881,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2138 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
+    // Pos:2139 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1312, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1313, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35879,9 +35898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2139 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
+    // Pos:2140 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1313, 
+        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1314, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35898,9 +35917,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2140 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
+    // Pos:2141 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1314, 
+        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1315, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -35917,9 +35936,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2141 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
+    // Pos:2142 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1315, 
+        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1316, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35936,9 +35955,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2142 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
+    // Pos:2143 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1316, 
+        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1317, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -35955,9 +35974,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2143 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
+    // Pos:2144 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1317, 
+        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1318, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35974,9 +35993,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2144 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
+    // Pos:2145 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1318, 
+        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1319, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -35993,9 +36012,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2145 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
+    // Pos:2146 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1319, 
+        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1320, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36012,9 +36031,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2146 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
+    // Pos:2147 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1320, 
+        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1321, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36031,9 +36050,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2147 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
+    // Pos:2148 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1321, 
+        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1322, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36049,9 +36068,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2148 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
+    // Pos:2149 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1322, 
+        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1323, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36067,9 +36086,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2149 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
+    // Pos:2150 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1323, 
+        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1324, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -36084,9 +36103,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2150 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
+    // Pos:2151 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1324, 
+        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1325, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36101,9 +36120,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2151 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
+    // Pos:2152 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1325, 
+        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1326, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36118,9 +36137,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2152 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
+    // Pos:2153 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1326, 
+        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1327, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -36135,9 +36154,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2153 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
+    // Pos:2154 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1327, 
+        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1328, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36153,9 +36172,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2154 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
+    // Pos:2155 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1328, 
+        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1329, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36171,9 +36190,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2155 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
+    // Pos:2156 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1329, 
+        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1330, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36189,9 +36208,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2156 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
+    // Pos:2157 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1330, 
+        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1331, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36207,9 +36226,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2157 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
+    // Pos:2158 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1331, 
+        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1332, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36225,9 +36244,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2158 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
+    // Pos:2159 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
     {
-        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1332, 
+        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1333, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36243,9 +36262,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2159 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
+    // Pos:2160 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1333, 
+        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1334, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -36260,9 +36279,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2160 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
+    // Pos:2161 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1334, 
+        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1335, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -36277,9 +36296,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2161 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM"
+    // Pos:2162 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM"
     {
-        ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1335, 
+        ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1336, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 
@@ -36294,9 +36313,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2162 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM"
+    // Pos:2163 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM"
     {
-        ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1336, 
+        ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1337, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 
@@ -36311,9 +36330,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2163 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM"
+    // Pos:2164 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM"
     {
-        ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1337, 
+        ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1338, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 
@@ -36328,9 +36347,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2164 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM"
+    // Pos:2165 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM"
     {
-        ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1338, 
+        ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1339, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 
@@ -36345,9 +36364,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2165 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
+    // Pos:2166 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1339, 
+        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -36363,9 +36382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2166 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM"
+    // Pos:2167 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM"
     {
-        ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1339, 
+        ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1340, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -36380,9 +36399,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2167 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
+    // Pos:2168 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1340, 
+        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -36398,9 +36417,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2168 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM"
+    // Pos:2169 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM"
     {
-        ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1340, 
+        ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1341, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -36415,9 +36434,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2169 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM"
+    // Pos:2170 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM"
     {
-        ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1341, 
+        ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1342, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 
@@ -36432,9 +36451,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2170 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM"
+    // Pos:2171 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM"
     {
-        ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1342, 
+        ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1343, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 
@@ -36449,9 +36468,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2171 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:2172 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1343, 
+        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -36467,9 +36486,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2172 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM"
+    // Pos:2173 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM"
     {
-        ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1343, 
+        ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1344, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -36484,9 +36503,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2173 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
+    // Pos:2174 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1344, 
+        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
@@ -36502,9 +36521,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2174 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM"
+    // Pos:2175 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM"
     {
-        ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1344, 
+        ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1345, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 
@@ -36519,9 +36538,111 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2175 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
+    // Pos:2176 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM"
     {
-        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1345, 
+        ND_INS_VPDPWSUD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1346, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2177 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM"
+    {
+        ND_INS_VPDPWSUDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1347, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2178 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM"
+    {
+        ND_INS_VPDPWUSD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1348, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2179 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM"
+    {
+        ND_INS_VPDPWUSDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1349, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2180 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM"
+    {
+        ND_INS_VPDPWUUD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1350, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2181 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM"
+    {
+        ND_INS_VPDPWUUDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1351, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2182 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
+    {
+        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1352, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36537,9 +36658,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2176 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
+    // Pos:2183 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1346, 
+        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1353, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36555,9 +36676,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2177 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
+    // Pos:2184 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1347, 
+        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1354, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -36573,9 +36694,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2178 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
+    // Pos:2185 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1348, 
+        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36591,9 +36712,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2179 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
+    // Pos:2186 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1348, 
+        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1355, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -36608,9 +36729,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2180 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
+    // Pos:2187 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1349, 
+        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1356, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -36626,9 +36747,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2181 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
+    // Pos:2188 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1350, 
+        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36644,9 +36765,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2182 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
+    // Pos:2189 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1351, 
+        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36662,9 +36783,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2183 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
+    // Pos:2190 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1352, 
+        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36680,9 +36801,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2184 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
+    // Pos:2191 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1353, 
+        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1360, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36698,9 +36819,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2185 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
+    // Pos:2192 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1354, 
+        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1361, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -36716,9 +36837,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2186 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
+    // Pos:2193 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
     {
-        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1355, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1362, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36735,9 +36856,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2187 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
+    // Pos:2194 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
     {
-        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1355, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1362, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36754,9 +36875,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2188 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
+    // Pos:2195 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
     {
-        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1356, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1363, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36773,9 +36894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2189 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
+    // Pos:2196 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
     {
-        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1356, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1363, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -36792,9 +36913,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2190 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
+    // Pos:2197 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36810,9 +36931,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2191 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
+    // Pos:2198 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36828,9 +36949,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2192 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
+    // Pos:2199 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1357, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36845,9 +36966,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2193 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
+    // Pos:2200 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1357, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1364, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36862,9 +36983,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2194 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
+    // Pos:2201 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36880,9 +37001,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2195 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
+    // Pos:2202 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36898,9 +37019,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2196 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
+    // Pos:2203 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1358, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36915,9 +37036,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2197 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
+    // Pos:2204 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1358, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1365, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -36932,9 +37053,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2198 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
+    // Pos:2205 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36950,9 +37071,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2199 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
+    // Pos:2206 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36968,9 +37089,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2200 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
+    // Pos:2207 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -36986,9 +37107,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2201 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
+    // Pos:2208 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1359, 
+        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1366, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37003,9 +37124,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2202 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
+    // Pos:2209 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1360, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37021,9 +37142,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2203 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
+    // Pos:2210 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1360, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37039,9 +37160,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2204 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
+    // Pos:2211 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1360, 
+        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1367, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37056,9 +37177,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2205 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
+    // Pos:2212 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1361, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37074,9 +37195,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2206 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
+    // Pos:2213 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1361, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37092,9 +37213,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2207 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
+    // Pos:2214 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1361, 
+        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1368, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -37109,9 +37230,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2208 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
+    // Pos:2215 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1362, 
+        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1369, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -37127,9 +37248,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2209 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
+    // Pos:2216 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1363, 
+        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1370, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37145,9 +37266,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2210 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
+    // Pos:2217 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 
+        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1371, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37163,9 +37284,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2211 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
+    // Pos:2218 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, 
+        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1372, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37181,9 +37302,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2212 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
+    // Pos:2219 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 
+        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1373, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37199,9 +37320,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2213 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
+    // Pos:2220 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1367, 
+        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37217,9 +37338,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2214 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
+    // Pos:2221 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1368, 
+        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1375, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37235,9 +37356,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2215 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
+    // Pos:2222 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1369, 
+        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1376, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -37252,9 +37373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2216 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
+    // Pos:2223 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1370, 
+        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1377, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37269,9 +37390,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2217 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
+    // Pos:2224 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1371, 
+        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1378, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37286,9 +37407,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2218 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
+    // Pos:2225 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1372, 
+        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1379, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -37303,9 +37424,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2219 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2226 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37320,9 +37441,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2220 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2227 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1373, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37337,9 +37458,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2221 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2228 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1373, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37354,9 +37475,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2222 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2229 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1373, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1380, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37371,9 +37492,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2223 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
+    // Pos:2230 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1374, 
+        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -37388,9 +37509,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2224 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
+    // Pos:2231 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1374, 
+        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -37405,9 +37526,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2225 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
+    // Pos:2232 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1374, 
+        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37422,9 +37543,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2226 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
+    // Pos:2233 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1374, 
+        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1381, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37439,9 +37560,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2227 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
+    // Pos:2234 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1375, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -37456,9 +37577,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2228 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
+    // Pos:2235 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1375, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -37473,9 +37594,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2229 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
+    // Pos:2236 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1375, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37490,9 +37611,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2230 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
+    // Pos:2237 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1375, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1382, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37507,9 +37628,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2231 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2238 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1376, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37524,9 +37645,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2232 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2239 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1376, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37541,9 +37662,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2233 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2240 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1376, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -37558,9 +37679,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2234 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2241 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1376, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37575,9 +37696,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2235 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2242 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1376, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37592,9 +37713,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2236 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2243 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1376, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37609,9 +37730,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2237 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
+    // Pos:2244 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1377, 
+        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1384, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37626,9 +37747,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2238 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
+    // Pos:2245 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1377, 
+        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1384, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -37643,9 +37764,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2239 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
+    // Pos:2246 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1378, 
+        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1385, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37660,9 +37781,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2240 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
+    // Pos:2247 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1378, 
+        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1385, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -37677,9 +37798,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2241 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
+    // Pos:2248 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1379, 
+        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1386, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37694,9 +37815,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2242 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
+    // Pos:2249 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1379, 
+        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1386, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -37711,9 +37832,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2243 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
+    // Pos:2250 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1380, 
+        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1387, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -37728,9 +37849,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2244 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
+    // Pos:2251 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1380, 
+        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1387, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
@@ -37745,9 +37866,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2245 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
+    // Pos:2252 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
     {
-        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1381, 
+        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1388, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37761,9 +37882,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2246 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
+    // Pos:2253 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
     {
-        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1382, 
+        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1389, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37777,9 +37898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2247 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
+    // Pos:2254 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
     {
-        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1383, 
+        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1390, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37793,9 +37914,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2248 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
+    // Pos:2255 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
     {
-        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1384, 
+        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1391, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37810,9 +37931,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2249 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
+    // Pos:2256 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
     {
-        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1385, 
+        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1392, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37826,9 +37947,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2250 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
+    // Pos:2257 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
     {
-        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1386, 
+        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1393, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37843,9 +37964,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2251 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
+    // Pos:2258 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
     {
-        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1387, 
+        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1394, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37859,9 +37980,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2252 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
+    // Pos:2259 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
     {
-        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1388, 
+        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1395, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37875,9 +37996,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2253 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
+    // Pos:2260 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
     {
-        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1389, 
+        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1396, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37891,9 +38012,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2254 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
+    // Pos:2261 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
     {
-        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1390, 
+        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1397, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37907,9 +38028,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2255 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
+    // Pos:2262 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
     {
-        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1391, 
+        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1398, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37923,9 +38044,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2256 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
+    // Pos:2263 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
     {
-        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1392, 
+        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1399, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37939,9 +38060,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2257 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
+    // Pos:2264 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
     {
-        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1393, 
+        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1400, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -37956,9 +38077,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2258 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
+    // Pos:2265 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
     {
-        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1394, 
+        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1401, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37972,9 +38093,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2259 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
+    // Pos:2266 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
     {
-        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1395, 
+        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1402, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -37988,9 +38109,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2260 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
+    // Pos:2267 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
     {
-        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1396, 
+        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1403, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38004,9 +38125,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2261 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
+    // Pos:2268 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
     {
-        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1397, 
+        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1404, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38020,9 +38141,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2262 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
+    // Pos:2269 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
     {
-        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1398, 
+        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1405, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38037,9 +38158,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2263 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
+    // Pos:2270 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
     {
-        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1399, 
+        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1406, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38053,9 +38174,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2264 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
+    // Pos:2271 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
     {
-        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1400, 
+        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1407, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38070,9 +38191,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2265 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
+    // Pos:2272 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
     {
-        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1401, 
+        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1408, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38087,9 +38208,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2266 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
+    // Pos:2273 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
     {
-        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1402, 
+        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1409, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38103,9 +38224,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2267 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2274 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38121,9 +38242,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2268 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2275 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38139,9 +38260,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2269 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2276 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1403, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38157,9 +38278,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2270 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2277 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1403, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1410, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38175,9 +38296,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2271 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2278 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1404, 
+        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1411, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -38193,9 +38314,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2272 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2279 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1404, 
+        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1411, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38211,9 +38332,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2273 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2280 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1405, 
+        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1412, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -38229,9 +38350,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2274 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2281 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1405, 
+        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1412, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38247,9 +38368,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2275 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2282 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38265,9 +38386,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2276 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2283 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38283,9 +38404,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2277 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2284 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1406, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38301,9 +38422,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2278 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2285 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1406, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1413, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38319,9 +38440,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2279 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
+    // Pos:2286 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1407, 
+        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1414, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -38336,9 +38457,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2280 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
+    // Pos:2287 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1408, 
+        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1415, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
@@ -38353,9 +38474,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2281 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
+    // Pos:2288 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
     {
-        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1409, 
+        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1416, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38371,9 +38492,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2282 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
+    // Pos:2289 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1410, 
+        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1417, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38389,9 +38510,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2283 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
+    // Pos:2290 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1411, 
+        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1418, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38407,9 +38528,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2284 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
+    // Pos:2291 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1412, 
+        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1419, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38425,9 +38546,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2285 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
+    // Pos:2292 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1413, 
+        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1420, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38443,9 +38564,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2286 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
+    // Pos:2293 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1414, 
+        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1421, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38461,9 +38582,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2287 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
+    // Pos:2294 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1415, 
+        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1422, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38479,9 +38600,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2288 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
+    // Pos:2295 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1416, 
+        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1423, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38497,9 +38618,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2289 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
+    // Pos:2296 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1417, 
+        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1424, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38515,9 +38636,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2290 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
+    // Pos:2297 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1418, 
+        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1425, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38533,9 +38654,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2291 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
+    // Pos:2298 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1419, 
+        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1426, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38551,9 +38672,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2292 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
+    // Pos:2299 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1420, 
+        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1427, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -38569,9 +38690,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2293 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
+    // Pos:2300 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
     {
-        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1421, 
+        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1428, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
@@ -38587,9 +38708,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2294 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM"
+    // Pos:2301 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM"
     {
-        ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1421, 
+        ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1428, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, 
@@ -38604,9 +38725,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2295 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
+    // Pos:2302 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
     {
-        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1422, 
+        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
@@ -38622,9 +38743,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2296 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM"
+    // Pos:2303 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM"
     {
-        ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1422, 
+        ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1429, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, 
@@ -38639,9 +38760,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2297 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
+    // Pos:2304 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1423, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38657,9 +38778,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2298 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
+    // Pos:2305 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1423, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1430, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38674,9 +38795,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2299 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
+    // Pos:2306 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1424, 
+        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38692,9 +38813,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2300 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
+    // Pos:2307 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1424, 
+        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1431, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38709,9 +38830,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2301 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
+    // Pos:2308 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1425, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1432, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -38726,9 +38847,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2302 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
+    // Pos:2309 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1425, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1432, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -38743,9 +38864,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2303 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
+    // Pos:2310 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1426, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -38760,9 +38881,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2304 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
+    // Pos:2311 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1426, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1433, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -38777,9 +38898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2305 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
+    // Pos:2312 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1427, 
+        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38795,9 +38916,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2306 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
+    // Pos:2313 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1427, 
+        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1434, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38812,9 +38933,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2307 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
+    // Pos:2314 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1428, 
+        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1435, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38830,9 +38951,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2308 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
+    // Pos:2315 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1428, 
+        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1435, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38847,9 +38968,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2309 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
+    // Pos:2316 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1429, 
+        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1436, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38865,9 +38986,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2310 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
+    // Pos:2317 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, 
+        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38883,9 +39004,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2311 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
+    // Pos:2318 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1430, 
+        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1437, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38900,9 +39021,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2312 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
+    // Pos:2319 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 
+        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -38918,9 +39039,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2313 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:2320 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1431, 
+        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1438, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38935,9 +39056,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2314 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
+    // Pos:2321 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1432, 
+        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1439, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38953,9 +39074,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2315 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
+    // Pos:2322 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1432, 
+        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1439, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -38970,9 +39091,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2316 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
+    // Pos:2323 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1433, 
+        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1440, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -38988,9 +39109,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2317 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
+    // Pos:2324 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 
+        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1441, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39006,9 +39127,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2318 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
+    // Pos:2325 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1434, 
+        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1441, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39023,9 +39144,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2319 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
+    // Pos:2326 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1435, 
+        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1442, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39041,9 +39162,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2320 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
+    // Pos:2327 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1435, 
+        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1442, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39058,9 +39179,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2321 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
+    // Pos:2328 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1436, 
+        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1443, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39076,9 +39197,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2322 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
+    // Pos:2329 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1436, 
+        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1443, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39093,9 +39214,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2323 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
+    // Pos:2330 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1437, 
+        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1444, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39111,9 +39232,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2324 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
+    // Pos:2331 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 
+        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1445, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39129,9 +39250,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2325 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
+    // Pos:2332 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1438, 
+        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1445, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39146,9 +39267,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2326 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
+    // Pos:2333 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1439, 
+        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1446, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39164,9 +39285,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2327 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
+    // Pos:2334 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1439, 
+        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1446, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39181,9 +39302,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2328 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
+    // Pos:2335 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1440, 
+        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1447, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39199,9 +39320,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2329 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
+    // Pos:2336 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1440, 
+        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1447, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39216,9 +39337,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2330 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
+    // Pos:2337 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1441, 
+        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1448, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39234,9 +39355,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2331 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
+    // Pos:2338 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1442, 
+        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1449, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39252,9 +39373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2332 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
+    // Pos:2339 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1442, 
+        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1449, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39269,9 +39390,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2333 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
+    // Pos:2340 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1443, 
+        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1450, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39285,9 +39406,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2334 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
+    // Pos:2341 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1444, 
+        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1451, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -39301,9 +39422,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2335 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
+    // Pos:2342 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
     {
-        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1445, 
+        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1452, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39318,9 +39439,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2336 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
+    // Pos:2343 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
     {
-        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1446, 
+        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39335,9 +39456,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2337 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
+    // Pos:2344 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1447, 
+        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1454, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39351,9 +39472,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2338 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
+    // Pos:2345 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1448, 
+        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1455, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -39367,9 +39488,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2339 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
+    // Pos:2346 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1449, 
+        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1456, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -39383,9 +39504,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2340 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
+    // Pos:2347 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1450, 
+        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1457, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39399,9 +39520,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2341 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
+    // Pos:2348 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
     {
-        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1451, 
+        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1458, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39415,9 +39536,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2342 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
+    // Pos:2349 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1452, 
+        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1459, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -39431,9 +39552,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2343 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
+    // Pos:2350 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
     {
-        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, 
+        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39448,9 +39569,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2344 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
+    // Pos:2351 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
     {
-        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1454, 
+        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1461, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39465,9 +39586,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2345 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
+    // Pos:2352 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
     {
-        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1455, 
+        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1462, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39482,9 +39603,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2346 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
+    // Pos:2353 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
     {
-        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1456, 
+        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39499,9 +39620,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2347 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
+    // Pos:2354 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
     {
-        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1457, 
+        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1464, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39516,9 +39637,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2348 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
+    // Pos:2355 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
     {
-        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1458, 
+        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39533,9 +39654,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2349 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
+    // Pos:2356 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
     {
-        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1459, 
+        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39550,9 +39671,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2350 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
+    // Pos:2357 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
     {
-        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, 
+        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39567,9 +39688,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2351 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
+    // Pos:2358 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
     {
-        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1461, 
+        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1468, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39584,9 +39705,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2352 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
+    // Pos:2359 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1462, 
+        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39601,9 +39722,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2353 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
+    // Pos:2360 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1462, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1469, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39617,9 +39738,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2354 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
+    // Pos:2361 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1462, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1469, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39633,9 +39754,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2355 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
+    // Pos:2362 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, 
+        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1470, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39650,9 +39771,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2356 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
+    // Pos:2363 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1463, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1470, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39666,9 +39787,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2357 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
+    // Pos:2364 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1463, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1470, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39682,9 +39803,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2358 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
+    // Pos:2365 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1464, 
+        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1471, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39699,9 +39820,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2359 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
+    // Pos:2366 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1464, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1471, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39715,9 +39836,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2360 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
+    // Pos:2367 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1464, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1471, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39731,9 +39852,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2361 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
+    // Pos:2368 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, 
+        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1472, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39748,9 +39869,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2362 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
+    // Pos:2369 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1465, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1472, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39764,9 +39885,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2363 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
+    // Pos:2370 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1465, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1472, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39780,9 +39901,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2364 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
+    // Pos:2371 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, 
+        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1473, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39797,9 +39918,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2365 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
+    // Pos:2372 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1466, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1473, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39813,9 +39934,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2366 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
+    // Pos:2373 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1466, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1473, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39829,9 +39950,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2367 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
+    // Pos:2374 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, 
+        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1474, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39846,9 +39967,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2368 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
+    // Pos:2375 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1467, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1474, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -39862,9 +39983,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2369 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
+    // Pos:2376 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1467, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1474, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -39878,9 +39999,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2370 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
+    // Pos:2377 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1468, 
+        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1475, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39895,9 +40016,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2371 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
+    // Pos:2378 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, 
+        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1476, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39912,9 +40033,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2372 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
+    // Pos:2379 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1470, 
+        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39929,9 +40050,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2373 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
+    // Pos:2380 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1471, 
+        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1478, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39946,9 +40067,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2374 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
+    // Pos:2381 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1472, 
+        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1479, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -39963,9 +40084,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2375 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
+    // Pos:2382 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
     {
-        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1473, 
+        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1480, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39980,9 +40101,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2376 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
+    // Pos:2383 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1474, 
+        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1481, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -39996,9 +40117,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2377 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
+    // Pos:2384 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
     {
-        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1475, 
+        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1482, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40013,9 +40134,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2378 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
+    // Pos:2385 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1476, 
+        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40030,9 +40151,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2379 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
+    // Pos:2386 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1476, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40046,9 +40167,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2380 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
+    // Pos:2387 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1476, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1483, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -40062,9 +40183,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2381 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
+    // Pos:2388 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, 
+        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1484, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40079,9 +40200,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2382 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
+    // Pos:2389 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1477, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1484, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40095,9 +40216,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2383 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
+    // Pos:2390 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1477, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1484, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -40111,9 +40232,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2384 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
+    // Pos:2391 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1478, 
+        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1485, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40128,9 +40249,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2385 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
+    // Pos:2392 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1478, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1485, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40144,9 +40265,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2386 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
+    // Pos:2393 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1478, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1485, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -40160,9 +40281,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2387 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
+    // Pos:2394 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1479, 
+        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1486, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40177,9 +40298,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2388 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
+    // Pos:2395 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1479, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1486, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40193,9 +40314,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2389 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
+    // Pos:2396 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1479, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1486, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -40209,9 +40330,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2390 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
+    // Pos:2397 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1480, 
+        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1487, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40226,9 +40347,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2391 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
+    // Pos:2398 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1480, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1487, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40242,9 +40363,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2392 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
+    // Pos:2399 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1480, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1487, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -40258,9 +40379,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2393 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
+    // Pos:2400 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1481, 
+        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1488, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40275,9 +40396,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2394 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
+    // Pos:2401 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1481, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1488, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40291,9 +40412,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2395 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
+    // Pos:2402 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1481, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1488, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -40307,9 +40428,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2396 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
+    // Pos:2403 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1482, 
+        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1489, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40325,9 +40446,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2397 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
+    // Pos:2404 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1482, 
+        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1489, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40342,9 +40463,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2398 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
+    // Pos:2405 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1483, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1490, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40360,9 +40481,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2399 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
+    // Pos:2406 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1483, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1490, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40377,9 +40498,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2400 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
+    // Pos:2407 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1484, 
+        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1491, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40395,9 +40516,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2401 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
+    // Pos:2408 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1484, 
+        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1491, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40412,9 +40533,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2402 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
+    // Pos:2409 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1485, 
+        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1492, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40430,9 +40551,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2403 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
+    // Pos:2410 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1485, 
+        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1492, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40447,9 +40568,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2404 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
+    // Pos:2411 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1486, 
+        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1493, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40465,9 +40586,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2405 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
+    // Pos:2412 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1486, 
+        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1493, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40482,9 +40603,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2406 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
+    // Pos:2413 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1487, 
+        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1494, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -40500,9 +40621,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2407 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
+    // Pos:2414 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1488, 
+        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1495, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -40518,9 +40639,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2408 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
+    // Pos:2415 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1488, 
+        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1495, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40535,9 +40656,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2409 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
+    // Pos:2416 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
     {
-        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1489, 
+        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1496, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
@@ -40553,9 +40674,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2410 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
+    // Pos:2417 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1490, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40571,9 +40692,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2411 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
+    // Pos:2418 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1490, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1497, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40588,9 +40709,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2412 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
+    // Pos:2419 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1491, 
+        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1498, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -40605,9 +40726,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2413 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
+    // Pos:2420 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1492, 
+        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1499, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
@@ -40622,9 +40743,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2414 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
+    // Pos:2421 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1493, 
+        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1500, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
@@ -40639,9 +40760,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2415 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
+    // Pos:2422 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1494, 
+        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1501, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -40656,9 +40777,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2416 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
+    // Pos:2423 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
     {
-        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1495, 
+        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1502, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -40673,9 +40794,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2417 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
+    // Pos:2424 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1496, 
+        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1503, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40691,9 +40812,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2418 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
+    // Pos:2425 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1497, 
+        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1504, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40709,9 +40830,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2419 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
+    // Pos:2426 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1498, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1505, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40727,9 +40848,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2420 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
+    // Pos:2427 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1498, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1505, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40745,9 +40866,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2421 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
+    // Pos:2428 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 
+        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1506, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40763,9 +40884,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2422 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
+    // Pos:2429 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 
+        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1507, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40781,9 +40902,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2423 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2430 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 
+        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1508, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40799,9 +40920,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2424 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2431 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 
+        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1509, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40817,9 +40938,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2425 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
+    // Pos:2432 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1503, 
+        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1510, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40835,9 +40956,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2426 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
+    // Pos:2433 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1504, 
+        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1511, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40853,9 +40974,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2427 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2434 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1505, 
+        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1512, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40871,9 +40992,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2428 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2435 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1506, 
+        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1513, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -40889,9 +41010,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2429 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
+    // Pos:2436 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1507, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40906,9 +41027,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2430 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
+    // Pos:2437 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1507, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40923,9 +41044,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2431 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
+    // Pos:2438 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1507, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40940,9 +41061,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2432 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
+    // Pos:2439 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1508, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40957,9 +41078,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2433 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
+    // Pos:2440 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1508, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40974,9 +41095,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2434 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
+    // Pos:2441 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1508, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -40991,9 +41112,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2435 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
+    // Pos:2442 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1509, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41008,9 +41129,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2436 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
+    // Pos:2443 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1509, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41025,9 +41146,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2437 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
+    // Pos:2444 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1509, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41042,9 +41163,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2438 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
+    // Pos:2445 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1510, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41059,9 +41180,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2439 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
+    // Pos:2446 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1510, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41076,9 +41197,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2440 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
+    // Pos:2447 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1510, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41093,9 +41214,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2441 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2448 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1511, 
+        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1518, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -41110,9 +41231,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2442 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2449 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1511, 
+        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1518, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41127,9 +41248,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2443 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2450 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1512, 
+        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1519, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41144,9 +41265,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2444 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2451 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1513, 
+        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1520, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41161,9 +41282,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2445 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2452 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1514, 
+        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1521, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41178,9 +41299,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2446 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2453 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1515, 
+        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1522, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41195,9 +41316,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2447 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
+    // Pos:2454 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1516, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41212,9 +41333,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2448 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
+    // Pos:2455 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1516, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1523, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41229,9 +41350,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2449 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
+    // Pos:2456 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1517, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1524, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41246,9 +41367,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2450 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
+    // Pos:2457 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1517, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1524, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41263,9 +41384,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2451 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
+    // Pos:2458 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1518, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1525, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41280,9 +41401,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2452 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
+    // Pos:2459 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1518, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1525, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41297,9 +41418,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2453 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
+    // Pos:2460 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1519, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1526, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41314,9 +41435,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2454 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
+    // Pos:2461 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1519, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1526, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41331,9 +41452,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2455 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
+    // Pos:2462 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1520, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41348,9 +41469,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2456 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
+    // Pos:2463 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1520, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41365,9 +41486,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2457 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
+    // Pos:2464 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1520, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41382,9 +41503,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2458 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
+    // Pos:2465 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1520, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41399,9 +41520,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2459 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
+    // Pos:2466 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
     {
-        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1521, 
+        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1528, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41416,9 +41537,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2460 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
+    // Pos:2467 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1522, 
+        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1529, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41435,9 +41556,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2461 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
+    // Pos:2468 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1523, 
+        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41454,9 +41575,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2462 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
+    // Pos:2469 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1524, 
+        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41472,9 +41593,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2463 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
+    // Pos:2470 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1525, 
+        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41490,9 +41611,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2464 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
+    // Pos:2471 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1526, 
+        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1533, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41508,9 +41629,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2465 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
+    // Pos:2472 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1527, 
+        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1534, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41527,9 +41648,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2466 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
+    // Pos:2473 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1528, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1535, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41544,9 +41665,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2467 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
+    // Pos:2474 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1528, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1535, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41561,9 +41682,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2468 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
+    // Pos:2475 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
     {
-        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1529, 
+        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1536, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
@@ -41578,9 +41699,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2469 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
+    // Pos:2476 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, 
+        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1537, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41597,9 +41718,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2470 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
+    // Pos:2477 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, 
+        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1538, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41616,9 +41737,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2471 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
+    // Pos:2478 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, 
+        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1539, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41634,9 +41755,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2472 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
+    // Pos:2479 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1533, 
+        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1540, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41652,9 +41773,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2473 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
+    // Pos:2480 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1534, 
+        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1541, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41670,9 +41791,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2474 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
+    // Pos:2481 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1535, 
+        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1542, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
@@ -41689,9 +41810,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2475 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
+    // Pos:2482 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1536, 
+        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1543, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -41707,9 +41828,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2476 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
+    // Pos:2483 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1536, 
+        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1543, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41724,9 +41845,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2477 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
+    // Pos:2484 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
     {
-        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1537, 
+        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1544, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
@@ -41742,9 +41863,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2478 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
+    // Pos:2485 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1538, 
+        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1545, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41760,9 +41881,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2479 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2486 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1538, 
+        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1545, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41777,9 +41898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2480 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2487 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1539, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1546, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -41795,9 +41916,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2481 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2488 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1539, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1546, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41812,9 +41933,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2482 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2489 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1540, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -41830,9 +41951,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2483 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2490 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1540, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1547, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41847,9 +41968,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2484 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
+    // Pos:2491 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
     {
-        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1541, 
+        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1548, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41864,9 +41985,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2485 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
+    // Pos:2492 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
     {
-        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1542, 
+        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1549, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41881,9 +42002,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2486 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
+    // Pos:2493 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
     {
-        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1543, 
+        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1550, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41898,9 +42019,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2487 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
+    // Pos:2494 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1544, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41916,9 +42037,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2488 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
+    // Pos:2495 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1544, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -41934,9 +42055,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2489 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
+    // Pos:2496 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1544, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1551, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41951,9 +42072,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2490 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
+    // Pos:2497 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1544, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1551, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -41968,9 +42089,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2491 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
+    // Pos:2498 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1545, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1552, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -41985,9 +42106,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2492 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
+    // Pos:2499 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1545, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1552, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42002,9 +42123,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2493 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
+    // Pos:2500 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1546, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1553, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42020,9 +42141,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2494 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
+    // Pos:2501 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1546, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1553, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42038,9 +42159,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2495 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
+    // Pos:2502 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1546, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1553, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42055,9 +42176,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2496 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
+    // Pos:2503 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1546, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1553, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42072,9 +42193,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2497 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
+    // Pos:2504 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1547, 
+        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42090,9 +42211,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2498 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
+    // Pos:2505 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1547, 
+        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1554, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -42107,9 +42228,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2499 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
+    // Pos:2506 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1548, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1555, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42125,9 +42246,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2500 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
+    // Pos:2507 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1548, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1555, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -42142,9 +42263,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2501 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
+    // Pos:2508 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
     {
-        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1549, 
+        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1556, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42160,9 +42281,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2502 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
+    // Pos:2509 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1550, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1557, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42178,9 +42299,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2503 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
+    // Pos:2510 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1550, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1557, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42196,9 +42317,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2504 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
+    // Pos:2511 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1550, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1557, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42213,9 +42334,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2505 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
+    // Pos:2512 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1550, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1557, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42230,9 +42351,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2506 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
+    // Pos:2513 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42248,9 +42369,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2507 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
+    // Pos:2514 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42266,9 +42387,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2508 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
+    // Pos:2515 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1551, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1558, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42283,9 +42404,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2509 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
+    // Pos:2516 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1551, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1558, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42300,9 +42421,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2510 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
+    // Pos:2517 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1552, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42318,9 +42439,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2511 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
+    // Pos:2518 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1552, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42336,9 +42457,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2512 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
+    // Pos:2519 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1553, 
+        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1560, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42354,9 +42475,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2513 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
+    // Pos:2520 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1553, 
+        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1560, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -42371,9 +42492,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2514 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
+    // Pos:2521 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1554, 
+        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1561, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42389,9 +42510,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2515 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
+    // Pos:2522 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
     {
-        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1555, 
+        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1562, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42407,9 +42528,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2516 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
+    // Pos:2523 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1556, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42425,9 +42546,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2517 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
+    // Pos:2524 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1556, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42443,9 +42564,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2518 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
+    // Pos:2525 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1556, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1563, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42460,9 +42581,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2519 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
+    // Pos:2526 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1556, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1563, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42477,9 +42598,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2520 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
+    // Pos:2527 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1557, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1564, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42495,9 +42616,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2521 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
+    // Pos:2528 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1557, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1564, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42513,9 +42634,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2522 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
+    // Pos:2529 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1557, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1564, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42530,9 +42651,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2523 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
+    // Pos:2530 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1557, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1564, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42547,9 +42668,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2524 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
+    // Pos:2531 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1558, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1565, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42564,9 +42685,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2525 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
+    // Pos:2532 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1558, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1565, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42581,9 +42702,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2526 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
+    // Pos:2533 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42599,9 +42720,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2527 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
+    // Pos:2534 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42617,9 +42738,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2528 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
+    // Pos:2535 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1559, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1566, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42634,9 +42755,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2529 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
+    // Pos:2536 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1559, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1566, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42651,9 +42772,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2530 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
+    // Pos:2537 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1560, 
+        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1567, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42669,9 +42790,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2531 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
+    // Pos:2538 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1560, 
+        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1567, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -42686,9 +42807,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2532 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
+    // Pos:2539 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1561, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1568, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42704,9 +42825,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2533 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
+    // Pos:2540 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1561, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1568, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
@@ -42721,9 +42842,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2534 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
+    // Pos:2541 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
     {
-        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1562, 
+        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1569, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42739,9 +42860,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2535 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
+    // Pos:2542 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42757,9 +42878,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2536 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
+    // Pos:2543 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42775,9 +42896,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2537 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
+    // Pos:2544 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1563, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1570, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42792,9 +42913,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2538 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
+    // Pos:2545 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1563, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1570, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42809,9 +42930,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2539 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
+    // Pos:2546 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1564, 
+        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1571, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42827,9 +42948,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2540 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
+    // Pos:2547 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1564, 
+        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1571, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42844,9 +42965,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2541 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
+    // Pos:2548 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1565, 
+        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1572, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42862,9 +42983,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2542 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
+    // Pos:2549 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1565, 
+        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1572, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42879,9 +43000,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2543 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
+    // Pos:2550 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, 
+        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1573, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -42897,9 +43018,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2544 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
+    // Pos:2551 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1566, 
+        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1573, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42914,9 +43035,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2545 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
+    // Pos:2552 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1567, 
+        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1574, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42932,9 +43053,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2546 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
+    // Pos:2553 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1567, 
+        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1574, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42949,9 +43070,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2547 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
+    // Pos:2554 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1568, 
+        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1575, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -42967,9 +43088,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2548 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
+    // Pos:2555 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1568, 
+        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1575, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -42984,9 +43105,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2549 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
+    // Pos:2556 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1569, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1576, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43002,9 +43123,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2550 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
+    // Pos:2557 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1569, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1576, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43019,9 +43140,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2551 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
+    // Pos:2558 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1577, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43037,9 +43158,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2552 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
+    // Pos:2559 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1570, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1577, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43054,9 +43175,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2553 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
+    // Pos:2560 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1571, 
+        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1578, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43072,9 +43193,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2554 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
+    // Pos:2561 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1571, 
+        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1578, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43089,9 +43210,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2555 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
+    // Pos:2562 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1572, 
+        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1579, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43108,9 +43229,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2556 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
+    // Pos:2563 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1573, 
+        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1580, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43127,9 +43248,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2557 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
+    // Pos:2564 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
     {
-        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1574, 
+        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1581, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43144,9 +43265,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2558 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2565 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1575, 
+        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1582, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43162,9 +43283,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2559 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2566 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1576, 
+        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1583, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43180,9 +43301,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2560 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2567 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1577, 
+        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1584, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43198,9 +43319,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2561 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2568 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1578, 
+        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1585, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43216,9 +43337,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2562 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2569 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1579, 
+        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1586, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43234,9 +43355,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2563 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2570 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1580, 
+        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1587, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43252,9 +43373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2564 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2571 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1581, 
+        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1588, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43270,9 +43391,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2565 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2572 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1582, 
+        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1589, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43288,9 +43409,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2566 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
+    // Pos:2573 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1583, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1590, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43306,9 +43427,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2567 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
+    // Pos:2574 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1583, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1590, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43323,9 +43444,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2568 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
+    // Pos:2575 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1584, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1591, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43341,9 +43462,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2569 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
+    // Pos:2576 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1584, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1591, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43358,9 +43479,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2570 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
+    // Pos:2577 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1585, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1592, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43376,9 +43497,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2571 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
+    // Pos:2578 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1585, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1592, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43393,9 +43514,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2572 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
+    // Pos:2579 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1586, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1593, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43411,9 +43532,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2573 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
+    // Pos:2580 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1586, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1593, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43428,9 +43549,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2574 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
+    // Pos:2581 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1587, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1594, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43446,9 +43567,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2575 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
+    // Pos:2582 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1587, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1594, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43463,9 +43584,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2576 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
+    // Pos:2583 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1588, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1595, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43481,9 +43602,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2577 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
+    // Pos:2584 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1588, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1595, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43498,9 +43619,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2578 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
+    // Pos:2585 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1589, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1596, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43516,9 +43637,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2579 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
+    // Pos:2586 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1589, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1596, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43533,9 +43654,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2580 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
+    // Pos:2587 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1590, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
@@ -43551,9 +43672,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2581 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
+    // Pos:2588 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1590, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1597, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43568,9 +43689,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2582 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
+    // Pos:2589 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
     {
-        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1591, 
+        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1598, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43585,9 +43706,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2583 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
+    // Pos:2590 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1592, 
+        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1599, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43603,9 +43724,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2584 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
+    // Pos:2591 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1593, 
+        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1600, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43621,9 +43742,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2585 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
+    // Pos:2592 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1594, 
+        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1601, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43640,9 +43761,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2586 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
+    // Pos:2593 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1595, 
+        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1602, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43659,9 +43780,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2587 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
+    // Pos:2594 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1596, 
+        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1603, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43678,9 +43799,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2588 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
+    // Pos:2595 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1597, 
+        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1604, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43697,9 +43818,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2589 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
+    // Pos:2596 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1598, 
+        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1605, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43714,9 +43835,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2590 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
+    // Pos:2597 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1599, 
+        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1606, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43731,9 +43852,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2591 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
+    // Pos:2598 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1600, 
+        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1607, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43749,9 +43870,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2592 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
+    // Pos:2599 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1601, 
+        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1608, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -43767,9 +43888,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2593 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
+    // Pos:2600 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1602, 
+        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1609, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -43784,9 +43905,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2594 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
+    // Pos:2601 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1603, 
+        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1610, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -43801,9 +43922,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2595 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
+    // Pos:2602 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1604, 
+        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1611, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -43819,9 +43940,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2596 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
+    // Pos:2603 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1605, 
+        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1612, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -43837,9 +43958,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2597 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM"
+    // Pos:2604 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM"
     {
-        ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1606, 
+        ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1613, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -43854,9 +43975,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2598 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
+    // Pos:2605 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
     {
-        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1607, 
+        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1614, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43870,9 +43991,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2599 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM"
+    // Pos:2606 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1608, 
+        ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1615, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -43888,9 +44009,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2600 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
+    // Pos:2607 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
     {
-        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1609, 
+        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1616, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -43905,9 +44026,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2601 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
+    // Pos:2608 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1610, 
+        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1617, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43923,9 +44044,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2602 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI"
+    // Pos:2609 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1611, 
+        ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1618, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -43941,9 +44062,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2603 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
+    // Pos:2610 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1612, 
+        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1619, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43959,9 +44080,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2604 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
+    // Pos:2611 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1613, 
+        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1620, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -43978,9 +44099,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2605 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI"
+    // Pos:2612 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1614, 
+        ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1621, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -43997,9 +44118,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2606 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
+    // Pos:2613 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1615, 
+        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1622, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -44016,9 +44137,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2607 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
+    // Pos:2614 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1616, 
+        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1623, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44034,9 +44155,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2608 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI"
+    // Pos:2615 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1617, 
+        ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1624, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44052,9 +44173,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2609 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
+    // Pos:2616 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1618, 
+        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1625, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44070,9 +44191,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2610 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
+    // Pos:2617 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1619, 
+        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1626, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44089,9 +44210,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2611 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI"
+    // Pos:2618 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1620, 
+        ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1627, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44108,9 +44229,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2612 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
+    // Pos:2619 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1621, 
+        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1628, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44127,9 +44248,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2613 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
+    // Pos:2620 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1622, 
+        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1629, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44144,9 +44265,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2614 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
+    // Pos:2621 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1623, 
+        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1630, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44161,9 +44282,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2615 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
+    // Pos:2622 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1624, 
+        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1631, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44179,9 +44300,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2616 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
+    // Pos:2623 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1625, 
+        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1632, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44197,9 +44318,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2617 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
+    // Pos:2624 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1626, 
+        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1633, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44214,9 +44335,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2618 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
+    // Pos:2625 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1627, 
+        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1634, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44231,9 +44352,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2619 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
+    // Pos:2626 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1628, 
+        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1635, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44249,9 +44370,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2620 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
+    // Pos:2627 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1629, 
+        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1636, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44267,9 +44388,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2621 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
+    // Pos:2628 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1630, 
+        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1637, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -44284,9 +44405,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2622 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
+    // Pos:2629 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1631, 
+        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1638, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -44301,9 +44422,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2623 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
+    // Pos:2630 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1632, 
+        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1639, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -44319,9 +44440,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2624 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
+    // Pos:2631 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1633, 
+        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1640, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
@@ -44337,9 +44458,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2625 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM"
+    // Pos:2632 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1634, 
+        ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1641, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44354,9 +44475,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2626 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
+    // Pos:2633 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
     {
-        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1635, 
+        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1642, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44370,9 +44491,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2627 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM"
+    // Pos:2634 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1636, 
+        ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1643, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44388,9 +44509,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2628 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
+    // Pos:2635 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
     {
-        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1637, 
+        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1644, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44405,9 +44526,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2629 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
+    // Pos:2636 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1638, 
+        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1645, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44423,9 +44544,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2630 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM"
+    // Pos:2637 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1639, 
+        ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1646, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44441,9 +44562,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2631 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
+    // Pos:2638 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1640, 
+        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1647, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44459,9 +44580,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2632 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
+    // Pos:2639 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1641, 
+        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1648, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44477,9 +44598,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2633 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM"
+    // Pos:2640 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1642, 
+        ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1649, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44495,9 +44616,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2634 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
+    // Pos:2641 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1643, 
+        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1650, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44513,9 +44634,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2635 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2642 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1644, 
+        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1651, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44530,9 +44651,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2636 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2643 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1645, 
+        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1652, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44547,9 +44668,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2637 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
+    // Pos:2644 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1646, 
+        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1653, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44563,9 +44684,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2638 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
+    // Pos:2645 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1647, 
+        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1654, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44579,9 +44700,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2639 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
+    // Pos:2646 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1648, 
+        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1655, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44595,9 +44716,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2640 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
+    // Pos:2647 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1649, 
+        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1656, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44611,9 +44732,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2641 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
+    // Pos:2648 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1650, 
+        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1657, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44627,9 +44748,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2642 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
+    // Pos:2649 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1651, 
+        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1658, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44643,9 +44764,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2643 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
+    // Pos:2650 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1652, 
+        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1659, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44659,9 +44780,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2644 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
+    // Pos:2651 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1653, 
+        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1660, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
@@ -44675,9 +44796,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2645 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2652 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1654, 
+        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1661, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44692,9 +44813,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2646 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2653 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1655, 
+        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1662, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44709,9 +44830,58 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2647 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
+    // Pos:2654 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM"
     {
-        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1656, 
+        ND_INS_VSHA512MSG1, ND_CAT_SHA512, ND_SET_SHA512, 1663, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2655 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM"
+    {
+        ND_INS_VSHA512MSG2, ND_CAT_SHA512, ND_SET_SHA512, 1664, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_U, ND_OPS_qq, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2656 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM"
+    {
+        ND_INS_VSHA512RNDS2, ND_CAT_SHA512, ND_SET_SHA512, 1665, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2657 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
+    {
+        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1666, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44728,9 +44898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2648 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
+    // Pos:2658 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1657, 
+        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1667, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44747,9 +44917,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2649 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
+    // Pos:2659 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1658, 
+        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1668, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44766,9 +44936,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2650 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
+    // Pos:2660 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1659, 
+        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1669, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44785,9 +44955,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2651 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
+    // Pos:2661 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1660, 
+        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1670, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44804,9 +44974,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2652 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2662 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1660, 
+        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1670, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44822,9 +44992,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2653 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
+    // Pos:2663 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1661, 
+        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1671, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44841,9 +45011,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2654 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2664 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1661, 
+        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1671, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44859,9 +45029,95 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2655 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
+    // Pos:2665 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1662, 
+        ND_INS_VSM3MSG1, ND_CAT_SM3, ND_SET_SM3, 1672, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2666 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM"
+    {
+        ND_INS_VSM3MSG2, ND_CAT_SM3, ND_SET_SM3, 1673, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2667 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI"
+    {
+        ND_INS_VSM3RNDS2, ND_CAT_SM3, ND_SET_SM3, 1674, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2668 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM"
+    {
+        ND_INS_VSM4KEY4, ND_CAT_SM4, ND_SET_SM4, 1675, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM4, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2669 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM"
+    {
+        ND_INS_VSM4RNDS4, ND_CAT_SM4, ND_SET_SM4, 1676, 
+        0, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
+        0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM4, 
+        0,
+        0,
+        0,
+        0,
+        {
+            OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), 
+            OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+            OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), 
+        },
+    }, 
+
+    // Pos:2670 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
+    {
+        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1677, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44876,9 +45132,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2656 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
+    // Pos:2671 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1662, 
+        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1677, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44892,9 +45148,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2657 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM"
+    // Pos:2672 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1663, 
+        ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1678, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44909,9 +45165,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2658 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
+    // Pos:2673 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1664, 
+        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44926,9 +45182,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2659 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
+    // Pos:2674 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1664, 
+        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1679, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44942,9 +45198,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2660 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
+    // Pos:2675 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1665, 
+        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1680, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -44960,9 +45216,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2661 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2676 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1665, 
+        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1680, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -44977,9 +45233,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2662 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM"
+    // Pos:2677 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1666, 
+        ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1681, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -44995,9 +45251,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2663 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
+    // Pos:2678 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1667, 
+        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1682, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45013,9 +45269,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2664 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2679 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1667, 
+        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1682, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45030,9 +45286,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2665 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
+    // Pos:2680 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
     {
-        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1668, 
+        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1683, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
@@ -45046,9 +45302,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2666 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
+    // Pos:2681 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1669, 
+        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1684, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45064,9 +45320,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2667 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2682 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1669, 
+        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1684, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45081,9 +45337,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2668 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM"
+    // Pos:2683 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1670, 
+        ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1685, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -45099,9 +45355,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2669 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
+    // Pos:2684 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1671, 
+        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1686, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45117,9 +45373,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2670 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2685 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1671, 
+        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1686, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45134,9 +45390,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2671 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
+    // Pos:2686 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1672, 
+        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1687, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45152,9 +45408,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2672 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2687 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1672, 
+        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1687, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45169,9 +45425,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2673 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM"
+    // Pos:2688 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1673, 
+        ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1688, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -45187,9 +45443,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2674 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
+    // Pos:2689 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1674, 
+        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1689, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45205,9 +45461,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2675 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2690 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1674, 
+        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1689, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45222,9 +45478,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2676 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
+    // Pos:2691 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
     {
-        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1675, 
+        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1690, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45239,9 +45495,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2677 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
+    // Pos:2692 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
     {
-        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1676, 
+        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1691, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45256,9 +45512,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2678 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
+    // Pos:2693 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1677, 
+        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1692, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45273,9 +45529,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2679 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
+    // Pos:2694 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1677, 
+        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1692, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45290,9 +45546,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2680 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM"
+    // Pos:2695 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1678, 
+        ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1693, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 
@@ -45307,9 +45563,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2681 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
+    // Pos:2696 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1679, 
+        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1694, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45324,9 +45580,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2682 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
+    // Pos:2697 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1679, 
+        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1694, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45341,9 +45597,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2683 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2698 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1680, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1695, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45359,9 +45615,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2684 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2699 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1680, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1695, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45376,9 +45632,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2685 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2700 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1681, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1696, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45394,9 +45650,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2686 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2701 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1681, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1696, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45411,9 +45667,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2687 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2702 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1682, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1697, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45429,9 +45685,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2688 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2703 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1682, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1697, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45446,9 +45702,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2689 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2704 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1683, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1698, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
@@ -45464,9 +45720,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2690 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2705 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1683, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1698, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45481,9 +45737,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2691 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
+    // Pos:2706 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1684, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1699, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -45499,9 +45755,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2692 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2707 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1684, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1699, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45516,9 +45772,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2693 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
+    // Pos:2708 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1685, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1700, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
@@ -45534,9 +45790,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2694 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2709 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1685, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1700, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
@@ -45551,9 +45807,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2695 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
+    // Pos:2710 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
     {
-        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1686, 
+        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1701, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
@@ -45566,9 +45822,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2696 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
+    // Pos:2711 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
     {
-        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1687, 
+        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1702, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 
         0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
@@ -45581,9 +45837,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2697 Instruction:"WAIT" Encoding:"0x9B"/""
+    // Pos:2712 Instruction:"WAIT" Encoding:"0x9B"/""
     {
-        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1688, 
+        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1703, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, 
@@ -45596,9 +45852,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2698 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
+    // Pos:2713 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
     {
-        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1689, 
+        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1704, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
@@ -45611,9 +45867,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2699 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
+    // Pos:2714 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
     {
-        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1690, 
+        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1705, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, 
@@ -45626,9 +45882,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2700 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
+    // Pos:2715 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
     {
-        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1691, 
+        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1706, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -45642,9 +45898,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2701 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
+    // Pos:2716 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
     {
-        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1692, 
+        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1707, 
         0, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
@@ -45658,9 +45914,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2702 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
+    // Pos:2717 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
     {
-        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1693, 
+        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1708, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, 
@@ -45676,9 +45932,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2703 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/""
+    // Pos:2718 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/""
     {
-        ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1694, 
+        ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1709, 
         0, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, 
@@ -45693,9 +45949,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2704 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/""
+    // Pos:2719 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/""
     {
-        ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1695, 
+        ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1710, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WRMSRNS, 
@@ -45711,9 +45967,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2705 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
+    // Pos:2720 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
     {
-        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1696, 
+        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1711, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
@@ -45729,9 +45985,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2706 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
+    // Pos:2721 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
     {
-        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1697, 
+        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1712, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -45744,9 +46000,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2707 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2722 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1698, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1713, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -45760,9 +46016,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2708 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2723 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1699, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1714, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -45776,9 +46032,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2709 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2724 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1700, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1715, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -45792,9 +46048,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2710 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2725 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1701, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1716, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
@@ -45808,9 +46064,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2711 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
+    // Pos:2726 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
     {
-        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1702, 
+        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1717, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -45825,9 +46081,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2712 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
+    // Pos:2727 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1703, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1718, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -45842,9 +46098,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2713 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
+    // Pos:2728 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1703, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1718, 
         ND_PREF_LOCK|ND_PREF_HLE, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -45859,9 +46115,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2714 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
+    // Pos:2729 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
     {
-        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1704, 
+        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1719, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -45876,9 +46132,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2715 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
+    // Pos:2730 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -45892,9 +46148,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2716 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
+    // Pos:2731 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -45908,9 +46164,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2717 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O"
+    // Pos:2732 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -45924,9 +46180,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2718 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O"
+    // Pos:2733 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -45940,9 +46196,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2719 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O"
+    // Pos:2734 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -45956,9 +46212,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2720 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O"
+    // Pos:2735 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -45972,9 +46228,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2721 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O"
+    // Pos:2736 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -45988,9 +46244,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2722 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O"
+    // Pos:2737 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -46004,9 +46260,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2723 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O"
+    // Pos:2738 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -46020,9 +46276,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2724 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O"
+    // Pos:2739 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1705, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -46036,9 +46292,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2725 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
+    // Pos:2740 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
     {
-        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1706, 
+        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1721, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46051,9 +46307,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2726 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
+    // Pos:2741 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
     {
-        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1707, 
+        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1722, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46066,9 +46322,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2727 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
+    // Pos:2742 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
     {
-        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1708, 
+        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1723, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46081,9 +46337,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2728 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
+    // Pos:2743 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
     {
-        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1709, 
+        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1724, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46096,9 +46352,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2729 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
+    // Pos:2744 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
     {
-        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1710, 
+        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1725, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46111,9 +46367,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2730 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
+    // Pos:2745 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
     {
-        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1711, 
+        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1726, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
@@ -46126,9 +46382,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2731 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
+    // Pos:2746 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
     {
-        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1712, 
+        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1727, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46144,9 +46400,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2732 Instruction:"XLATB" Encoding:"0xD7"/""
+    // Pos:2747 Instruction:"XLATB" Encoding:"0xD7"/""
     {
-        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1713, 
+        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1728, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -46160,9 +46416,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2733 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
+    // Pos:2748 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46177,9 +46433,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2734 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
+    // Pos:2749 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46194,9 +46450,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2735 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
+    // Pos:2750 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46211,9 +46467,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2736 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
+    // Pos:2751 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46228,9 +46484,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2737 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
+    // Pos:2752 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -46245,9 +46501,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2738 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
+    // Pos:2753 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -46262,9 +46518,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2739 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
+    // Pos:2754 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46279,9 +46535,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2740 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
+    // Pos:2755 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46296,9 +46552,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2741 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
+    // Pos:2756 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
@@ -46313,9 +46569,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2742 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
+    // Pos:2757 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1714, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 
         ND_PREF_HLE|ND_PREF_LOCK, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46330,9 +46586,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2743 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
+    // Pos:2758 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1715, 
+        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1730, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
@@ -46346,9 +46602,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2744 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
+    // Pos:2759 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1716, 
+        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1731, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
@@ -46362,9 +46618,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2745 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
+    // Pos:2760 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
     {
-        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1717, 
+        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1732, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
@@ -46377,9 +46633,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2746 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2761 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1718, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1733, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46396,9 +46652,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2747 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2762 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1719, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1734, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46415,9 +46671,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2748 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2763 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1720, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1735, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -46434,9 +46690,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2749 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2764 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1721, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1736, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -46453,9 +46709,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2750 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2765 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1722, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1737, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46472,9 +46728,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2751 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2766 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1723, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1738, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46491,9 +46747,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2752 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2767 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1724, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1739, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
@@ -46510,9 +46766,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2753 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2768 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1725, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1740, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
@@ -46529,9 +46785,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2754 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2769 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1726, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1741, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46548,9 +46804,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2755 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2770 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1727, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1742, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46567,9 +46823,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2756 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2771 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1728, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1743, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -46586,9 +46842,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2757 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2772 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1729, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1744, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
@@ -46605,9 +46861,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2758 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
+    // Pos:2773 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
     {
-        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1730, 
+        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1745, 
         0, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 
         0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
@@ -46623,9 +46879,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2759 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
+    // Pos:2774 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
     {
-        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1731, 
+        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1746, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46638,9 +46894,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2760 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
+    // Pos:2775 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
     {
-        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1732, 
+        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1747, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46653,9 +46909,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2761 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
+    // Pos:2776 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
     {
-        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1733, 
+        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1748, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46668,9 +46924,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2762 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/""
+    // Pos:2777 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/""
     {
-        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1733, 
+        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1748, 
         ND_PREF_REP, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
@@ -46683,9 +46939,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2763 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
+    // Pos:2778 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1734, 
+        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1749, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
@@ -46698,9 +46954,9 @@ const ND_INSTRUCTION gInstructions[2765] =
         },
     }, 
 
-    // Pos:2764 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
+    // Pos:2779 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
     {
-        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1735, 
+        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1750, 
         0, 
         ND_MOD_ANY, 
         0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h
index 7bd203a..6e24ed3 100644
--- a/bddisasm/include/mnemonics.h
+++ b/bddisasm/include/mnemonics.h
@@ -10,7 +10,7 @@
 #ifndef MNEMONICS_H
 #define MNEMONICS_H
 
-const char *gMnemonics[1736] = 
+const char *gMnemonics[1751] = 
 {
     "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD", 
     "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", 
@@ -90,130 +90,130 @@ const char *gMnemonics[1736] =
     "OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", 
     "PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", 
     "PADDUSW", "PADDW", "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", 
-    "PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", 
-    "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", 
-    "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCONFIG", 
-    "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", 
-    "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", 
-    "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2", 
-    "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", 
-    "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", 
-    "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", 
-    "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", 
-    "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", 
-    "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", 
-    "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", 
-    "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", 
-    "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", 
-    "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", 
-    "PREFETCHIT0", "PREFETCHIT1", "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", 
-    "PREFETCHT1", "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", 
-    "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", 
-    "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", 
-    "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", 
-    "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", 
-    "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", 
-    "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", 
-    "PUSH", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", 
-    "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", 
-    "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", 
-    "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", 
-    "RETN", "RMPADJUST", "RMPQUERY", "RMPUPDATE", "ROL", "ROR", "RORX", 
-    "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", 
-    "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", 
-    "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", 
-    "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI", 
-    "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC", 
-    "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO", 
-    "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1", 
-    "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", 
-    "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX", 
-    "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMINT", 
-    "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", 
-    "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", 
-    "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", 
-    "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", 
-    "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS", 
-    "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", 
-    "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", 
-    "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", 
-    "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", 
-    "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", 
-    "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH", 
-    "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS", 
-    "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", 
-    "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", 
-    "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", "VBLENDMPD", 
-    "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS", 
-    "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8", 
-    "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2", 
-    "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4", 
-    "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", "VCMPPH", "VCMPPS", 
-    "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", 
-    "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", 
-    "VCVTNE2PS2BF16", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS", 
-    "VCVTNEOPH2PS", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", 
-    "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", 
-    "VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", 
-    "VCVTPH2UW", "VCVTPH2W", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", 
-    "VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", 
-    "VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", 
-    "VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", 
-    "VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", 
-    "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", 
-    "VCVTTPD2UQQ", "VCVTTPH2DQ", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", 
-    "VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", 
-    "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", 
-    "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", 
-    "VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", 
-    "VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVPD", 
-    "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS", 
-    "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", 
-    "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", 
-    "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", 
-    "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", 
-    "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", "VFCMULCSH", "VFIXUPIMMPD", 
-    "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", "VFMADD132PH", 
-    "VFMADD132PS", "VFMADD132SD", "VFMADD132SH", "VFMADD132SS", "VFMADD213PD", 
-    "VFMADD213PH", "VFMADD213PS", "VFMADD213SD", "VFMADD213SH", "VFMADD213SS", 
-    "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", "VFMADD231SD", "VFMADD231SH", 
-    "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", "VFMADDPD", "VFMADDPS", 
-    "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", "VFMADDSUB132PH", "VFMADDSUB132PS", 
-    "VFMADDSUB213PD", "VFMADDSUB213PH", "VFMADDSUB213PS", "VFMADDSUB231PD", 
-    "VFMADDSUB231PH", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", 
-    "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SH", 
-    "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH", "VFMSUB213PS", "VFMSUB213SD", 
-    "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PH", "VFMSUB231PS", 
-    "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", "VFMSUBADD132PD", 
-    "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", "VFMSUBADD213PH", 
-    "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", "VFMSUBADD231PS", 
-    "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", 
-    "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD", "VFNMADD132PH", 
-    "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH", "VFNMADD132SS", 
-    "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS", "VFNMADD213SD", 
-    "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD", "VFNMADD231PH", 
-    "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH", "VFNMADD231SS", 
-    "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD", 
-    "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SH", 
-    "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH", "VFNMSUB213PS", 
-    "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS", "VFNMSUB231PD", 
-    "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD", "VFNMSUB231SH", 
-    "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", 
-    "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", "VFPCLASSSH", 
-    "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", "VFRCZSS", "VGATHERDPD", 
-    "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", 
-    "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", 
-    "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", "VGETEXPPD", "VGETEXPPH", 
-    "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", "VGETEXPSS", "VGETMANTPD", 
-    "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", "VGETMANTSH", "VGETMANTSS", 
-    "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", "VGF2P8MULB", "VHADDPD", 
-    "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", "VINSERTF32X4", 
-    "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", "VINSERTI128", 
-    "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", "VINSERTI64X4", 
-    "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", "VMASKMOVPD", 
-    "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", "VMAXSH", 
-    "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", "VMINPD", 
-    "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", 
+    "PAVGUSB", "PAVGW", "PBLENDVB", "PBLENDW", "PBNDKB", "PCLMULQDQ", 
+    "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", "PCMPESTRI", "PCMPESTRM", 
+    "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", "PCMPISTRI", "PCMPISTRM", 
+    "PCONFIG", "PDEP", "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", 
+    "PF2ID", "PF2IW", "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", 
+    "PFMAX", "PFMIN", "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", 
+    "PFRCPIT2", "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", 
+    "PFSUBR", "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", 
+    "PHSUBSW", "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", 
+    "PINSRW", "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", 
+    "PMAXUB", "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", 
+    "PMINUD", "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", 
+    "PMOVSXDQ", "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", 
+    "PMOVZXDQ", "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", 
+    "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", 
+    "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", 
+    "PREFETCHE", "PREFETCHIT0", "PREFETCHIT1", "PREFETCHM", "PREFETCHNTA", 
+    "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", 
+    "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", 
+    "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", 
+    "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", 
+    "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", 
+    "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", 
+    "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", 
+    "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", 
+    "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", 
+    "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", 
+    "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", 
+    "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPQUERY", "RMPUPDATE", 
+    "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", 
+    "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", 
+    "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", 
+    "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", 
+    "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", 
+    "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", 
+    "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", 
+    "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", 
+    "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", 
+    "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", 
+    "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", 
+    "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", 
+    "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", 
+    "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", 
+    "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", 
+    "TCMMRLFP16PS", "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", 
+    "TDPBUSD", "TDPBUUD", "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", 
+    "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", 
+    "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", 
+    "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", 
+    "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", 
+    "V4FNMADDSS", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", 
+    "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", 
+    "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", 
+    "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", 
+    "VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", 
+    "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", 
+    "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", 
+    "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", 
+    "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", 
+    "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", 
+    "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", 
+    "VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS", 
+    "VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16", 
+    "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", 
+    "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", 
+    "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", 
+    "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", 
+    "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", 
+    "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", 
+    "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", 
+    "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", 
+    "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ", 
+    "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W", 
+    "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI", 
+    "VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI", 
+    "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH", 
+    "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH", 
+    "VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", 
+    "VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", 
+    "VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", 
+    "VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4", 
+    "VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2", 
+    "VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", 
+    "VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", 
+    "VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH", 
+    "VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD", 
+    "VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", 
+    "VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", 
+    "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", 
+    "VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH", 
+    "VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS", 
+    "VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", 
+    "VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH", 
+    "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD", 
+    "VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", 
+    "VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", 
+    "VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", 
+    "VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", 
+    "VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD", 
+    "VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH", 
+    "VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS", 
+    "VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD", 
+    "VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH", 
+    "VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", 
+    "VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", 
+    "VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH", 
+    "VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS", 
+    "VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD", 
+    "VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD", 
+    "VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", 
+    "VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", 
+    "VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", 
+    "VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", 
+    "VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", 
+    "VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", 
+    "VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", 
+    "VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", 
+    "VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", 
+    "VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", 
+    "VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", 
+    "VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", 
+    "VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", 
+    "VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", 
+    "VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", 
     "VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", 
     "VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16", 
     "VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", 
@@ -239,77 +239,80 @@ const char *gMnemonics[1736] =
     "VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW", 
     "VPCONFLICTD", "VPCONFLICTQ", "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD", 
     "VPDPBSUDS", "VPDPBUSD", "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS", 
-    "VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", 
-    "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q", 
-    "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS", 
-    "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD", 
-    "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD", 
-    "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW", 
-    "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", "VPGATHERQQ", "VPHADDBD", 
-    "VPHADDBQ", "VPHADDBW", "VPHADDD", "VPHADDDQ", "VPHADDSW", "VPHADDUBD", 
-    "VPHADDUBQ", "VPHADDUBW", "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", 
-    "VPHADDW", "VPHADDWD", "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", 
-    "VPHSUBD", "VPHSUBDQ", "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", 
-    "VPINSRD", "VPINSRQ", "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", 
-    "VPMACSDQH", "VPMACSDQL", "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", 
-    "VPMACSSWD", "VPMACSSWW", "VPMACSWD", "VPMACSWW", "VPMADCSSWD", 
-    "VPMADCSWD", "VPMADD52HUQ", "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", 
-    "VPMASKMOVD", "VPMASKMOVQ", "VPMAXSB", "VPMAXSD", "VPMAXSQ", 
-    "VPMAXSW", "VPMAXUB", "VPMAXUD", "VPMAXUQ", "VPMAXUW", "VPMINSB", 
-    "VPMINSD", "VPMINSQ", "VPMINSW", "VPMINUB", "VPMINUD", "VPMINUQ", 
-    "VPMINUW", "VPMOVB2M", "VPMOVD2M", "VPMOVDB", "VPMOVDW", "VPMOVM2B", 
-    "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", "VPMOVMSKB", "VPMOVQ2M", 
-    "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", "VPMOVSDW", "VPMOVSQB", 
-    "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", "VPMOVSXBQ", 
-    "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVUSDB", 
-    "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB", 
-    "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXBW", 
-    "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", "VPMULHRSW", 
-    "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", "VPMULTISHIFTQB", 
-    "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", "VPOPCNTW", "VPOR", 
-    "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ", 
-    "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD", 
-    "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ", 
-    "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW", 
-    "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ", 
-    "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ", 
-    "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB", 
-    "VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW", 
-    "VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW", 
-    "VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW", 
-    "VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ", 
-    "VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", 
-    "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", 
-    "VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB", 
-    "VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", 
-    "VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", 
-    "VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", 
-    "VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", 
-    "VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS", 
-    "VRCPSH", "VRCPSS", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD", 
-    "VREDUCESH", "VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS", 
-    "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", 
-    "VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", 
-    "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", 
-    "VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD", 
-    "VSCALEFPH", "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", 
-    "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", 
-    "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", 
-    "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", 
-    "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD", 
-    "VSHUFPS", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH", 
-    "VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD", 
-    "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", "VUCOMISH", 
-    "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", 
-    "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD", 
-    "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS", 
-    "WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", 
-    "XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR", 
-    "XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", 
-    "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", 
-    "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", 
-    "XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", "XSTORE", 
-    "XSUSLDTRK", "XTEST", 
+    "VPDPWSSD", "VPDPWSSDS", "VPDPWSUD", "VPDPWSUDS", "VPDPWUSD", 
+    "VPDPWUSDS", "VPDPWUUD", "VPDPWUUDS", "VPERM2F128", "VPERM2I128", 
+    "VPERMB", "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", 
+    "VPERMI2Q", "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", 
+    "VPERMILPS", "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", 
+    "VPERMT2PD", "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", 
+    "VPEXPANDD", "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", 
+    "VPEXTRQ", "VPEXTRW", "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", 
+    "VPGATHERQQ", "VPHADDBD", "VPHADDBQ", "VPHADDBW", "VPHADDD", 
+    "VPHADDDQ", "VPHADDSW", "VPHADDUBD", "VPHADDUBQ", "VPHADDUBW", 
+    "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", "VPHADDW", "VPHADDWD", 
+    "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", "VPHSUBD", "VPHSUBDQ", 
+    "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", "VPINSRD", "VPINSRQ", 
+    "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", "VPMACSDQH", "VPMACSDQL", 
+    "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", "VPMACSSWD", "VPMACSSWW", 
+    "VPMACSWD", "VPMACSWW", "VPMADCSSWD", "VPMADCSWD", "VPMADD52HUQ", 
+    "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", "VPMASKMOVD", "VPMASKMOVQ", 
+    "VPMAXSB", "VPMAXSD", "VPMAXSQ", "VPMAXSW", "VPMAXUB", "VPMAXUD", 
+    "VPMAXUQ", "VPMAXUW", "VPMINSB", "VPMINSD", "VPMINSQ", "VPMINSW", 
+    "VPMINUB", "VPMINUD", "VPMINUQ", "VPMINUW", "VPMOVB2M", "VPMOVD2M", 
+    "VPMOVDB", "VPMOVDW", "VPMOVM2B", "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", 
+    "VPMOVMSKB", "VPMOVQ2M", "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", 
+    "VPMOVSDW", "VPMOVSQB", "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", 
+    "VPMOVSXBQ", "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", 
+    "VPMOVUSDB", "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", 
+    "VPMOVUSWB", "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", 
+    "VPMOVZXBW", "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", 
+    "VPMULHRSW", "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", 
+    "VPMULTISHIFTQB", "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", 
+    "VPOPCNTW", "VPOR", "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", 
+    "VPROLVD", "VPROLVQ", "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", 
+    "VPROTB", "VPROTD", "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", 
+    "VPSCATTERDQ", "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", 
+    "VPSHAQ", "VPSHAW", "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", 
+    "VPSHLDVD", "VPSHLDVQ", "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", 
+    "VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", 
+    "VPSHUFB", "VPSHUFBITQMB", "VPSHUFD", "VPSHUFHW", "VPSHUFLW", 
+    "VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD", "VPSLLDQ", "VPSLLQ", 
+    "VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW", "VPSRAD", "VPSRAQ", 
+    "VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW", "VPSRLD", "VPSRLDQ", 
+    "VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW", "VPSRLW", "VPSUBB", 
+    "VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", "VPSUBUSB", "VPSUBUSW", 
+    "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", "VPTEST", "VPTESTMB", "VPTESTMD", 
+    "VPTESTMQ", "VPTESTMW", "VPTESTNMB", "VPTESTNMD", "VPTESTNMQ", 
+    "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", "VPUNPCKHQDQ", "VPUNPCKHWD", 
+    "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", "VPUNPCKLWD", "VPXOR", 
+    "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", "VRANGESD", "VRANGESS", 
+    "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", "VRCP28PD", "VRCP28PS", 
+    "VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS", 
+    "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH", 
+    "VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD", 
+    "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", "VROUNDSD", 
+    "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS", 
+    "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", "VRSQRTPH", 
+    "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD", "VSCALEFPH", 
+    "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD", 
+    "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD", 
+    "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD", 
+    "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", "VSHA512MSG1", 
+    "VSHA512MSG2", "VSHA512RNDS2", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", 
+    "VSHUFI64X2", "VSHUFPD", "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2", 
+    "VSM4KEY4", "VSM4RNDS4", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", 
+    "VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS", 
+    "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", 
+    "VUCOMISH", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", 
+    "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", 
+    "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", 
+    "WRMSRNS", "WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", 
+    "XABORT", "XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", 
+    "XCRYPTCTR", "XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", 
+    "XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", 
+    "XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", 
+    "XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", 
+    "XSTORE", "XSUSLDTRK", "XTEST", 
 };
 
 
diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h
index 333c3c6..e9ffc31 100644
--- a/bddisasm/include/table_evex.h
+++ b/bddisasm/include/table_evex.h
@@ -13,7 +13,7 @@
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1399]
+    (const void *)&gInstructions[1400]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = 
@@ -48,13 +48,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1683]
+    (const void *)&gInstructions[1684]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1686]
+    (const void *)&gInstructions[1687]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = 
@@ -80,7 +80,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1400]
+    (const void *)&gInstructions[1401]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = 
@@ -104,13 +104,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1688]
+    (const void *)&gInstructions[1689]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1691]
+    (const void *)&gInstructions[1692]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = 
@@ -136,7 +136,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1401]
+    (const void *)&gInstructions[1402]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = 
@@ -171,13 +171,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1693]
+    (const void *)&gInstructions[1694]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1696]
+    (const void *)&gInstructions[1697]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = 
@@ -203,7 +203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1402]
+    (const void *)&gInstructions[1403]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = 
@@ -227,13 +227,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1698]
+    (const void *)&gInstructions[1699]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1701]
+    (const void *)&gInstructions[1702]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = 
@@ -259,7 +259,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1415]
+    (const void *)&gInstructions[1416]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = 
@@ -276,7 +276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1417]
+    (const void *)&gInstructions[1418]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = 
@@ -293,7 +293,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1419]
+    (const void *)&gInstructions[1420]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = 
@@ -310,7 +310,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1421]
+    (const void *)&gInstructions[1422]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = 
@@ -327,13 +327,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1437]
+    (const void *)&gInstructions[1438]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1438]
+    (const void *)&gInstructions[1439]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = 
@@ -359,13 +359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1444]
+    (const void *)&gInstructions[1445]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1455]
+    (const void *)&gInstructions[1456]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = 
@@ -391,13 +391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1445]
+    (const void *)&gInstructions[1446]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1447]
+    (const void *)&gInstructions[1448]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = 
@@ -432,13 +432,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1446]
+    (const void *)&gInstructions[1447]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1448]
+    (const void *)&gInstructions[1449]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = 
@@ -484,13 +484,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1450]
+    (const void *)&gInstructions[1451]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2109]
+    (const void *)&gInstructions[2110]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = 
@@ -516,13 +516,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1451]
+    (const void *)&gInstructions[1452]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1453]
+    (const void *)&gInstructions[1454]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = 
@@ -557,13 +557,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1452]
+    (const void *)&gInstructions[1453]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1454]
+    (const void *)&gInstructions[1455]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = 
@@ -609,7 +609,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1457]
+    (const void *)&gInstructions[1458]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = 
@@ -635,13 +635,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1474]
+    (const void *)&gInstructions[1475]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1475]
+    (const void *)&gInstructions[1476]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = 
@@ -667,7 +667,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1482]
+    (const void *)&gInstructions[1483]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = 
@@ -682,7 +682,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1487]
+    (const void *)&gInstructions[1488]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = 
@@ -697,7 +697,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2473]
+    (const void *)&gInstructions[2480]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = 
@@ -723,7 +723,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1500]
+    (const void *)&gInstructions[1501]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = 
@@ -738,7 +738,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2371]
+    (const void *)&gInstructions[2378]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = 
@@ -764,7 +764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1593]
+    (const void *)&gInstructions[1594]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = 
@@ -779,7 +779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2049]
+    (const void *)&gInstructions[2050]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = 
@@ -814,7 +814,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2171]
+    (const void *)&gInstructions[2172]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = 
@@ -840,13 +840,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1598]
+    (const void *)&gInstructions[1599]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1599]
+    (const void *)&gInstructions[1600]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = 
@@ -883,13 +883,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1600]
+    (const void *)&gInstructions[1601]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1601]
+    (const void *)&gInstructions[1602]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = 
@@ -915,13 +915,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1624]
+    (const void *)&gInstructions[1625]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1627]
+    (const void *)&gInstructions[1628]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = 
@@ -947,13 +947,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1629]
+    (const void *)&gInstructions[1630]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1632]
+    (const void *)&gInstructions[1633]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = 
@@ -979,13 +979,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1634]
+    (const void *)&gInstructions[1635]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1637]
+    (const void *)&gInstructions[1638]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = 
@@ -1011,13 +1011,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1639]
+    (const void *)&gInstructions[1640]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1642]
+    (const void *)&gInstructions[1643]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = 
@@ -1043,13 +1043,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1644]
+    (const void *)&gInstructions[1645]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1647]
+    (const void *)&gInstructions[1648]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = 
@@ -1075,13 +1075,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1649]
+    (const void *)&gInstructions[1650]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1652]
+    (const void *)&gInstructions[1653]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = 
@@ -1107,13 +1107,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1664]
+    (const void *)&gInstructions[1665]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1667]
+    (const void *)&gInstructions[1668]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = 
@@ -1139,13 +1139,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1669]
+    (const void *)&gInstructions[1670]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1672]
+    (const void *)&gInstructions[1673]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = 
@@ -1171,13 +1171,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1674]
+    (const void *)&gInstructions[1675]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1677]
+    (const void *)&gInstructions[1678]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = 
@@ -1203,13 +1203,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1703]
+    (const void *)&gInstructions[1704]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1706]
+    (const void *)&gInstructions[1707]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = 
@@ -1235,13 +1235,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1708]
+    (const void *)&gInstructions[1709]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1711]
+    (const void *)&gInstructions[1712]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = 
@@ -1267,13 +1267,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1713]
+    (const void *)&gInstructions[1714]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1716]
+    (const void *)&gInstructions[1717]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = 
@@ -1299,13 +1299,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1718]
+    (const void *)&gInstructions[1719]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1721]
+    (const void *)&gInstructions[1722]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = 
@@ -1331,13 +1331,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1723]
+    (const void *)&gInstructions[1724]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1726]
+    (const void *)&gInstructions[1727]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = 
@@ -1363,13 +1363,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1742]
+    (const void *)&gInstructions[1743]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1745]
+    (const void *)&gInstructions[1746]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = 
@@ -1395,13 +1395,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1747]
+    (const void *)&gInstructions[1748]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1750]
+    (const void *)&gInstructions[1751]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = 
@@ -1427,13 +1427,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1752]
+    (const void *)&gInstructions[1753]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1755]
+    (const void *)&gInstructions[1756]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = 
@@ -1459,13 +1459,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1757]
+    (const void *)&gInstructions[1758]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1760]
+    (const void *)&gInstructions[1761]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = 
@@ -1491,13 +1491,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1762]
+    (const void *)&gInstructions[1763]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1765]
+    (const void *)&gInstructions[1766]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = 
@@ -1523,13 +1523,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1767]
+    (const void *)&gInstructions[1768]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1770]
+    (const void *)&gInstructions[1771]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = 
@@ -1555,13 +1555,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1780]
+    (const void *)&gInstructions[1781]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1783]
+    (const void *)&gInstructions[1784]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = 
@@ -1587,13 +1587,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1785]
+    (const void *)&gInstructions[1786]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1788]
+    (const void *)&gInstructions[1789]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = 
@@ -1619,13 +1619,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1790]
+    (const void *)&gInstructions[1791]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1793]
+    (const void *)&gInstructions[1794]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = 
@@ -1651,13 +1651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1795]
+    (const void *)&gInstructions[1796]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1798]
+    (const void *)&gInstructions[1799]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = 
@@ -1683,13 +1683,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1800]
+    (const void *)&gInstructions[1801]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1803]
+    (const void *)&gInstructions[1804]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = 
@@ -1715,13 +1715,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1805]
+    (const void *)&gInstructions[1806]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1808]
+    (const void *)&gInstructions[1809]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = 
@@ -1747,13 +1747,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1828]
+    (const void *)&gInstructions[1829]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1830]
+    (const void *)&gInstructions[1831]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = 
@@ -1788,13 +1788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1832]
+    (const void *)&gInstructions[1833]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1833]
+    (const void *)&gInstructions[1834]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = 
@@ -1820,13 +1820,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1836]
+    (const void *)&gInstructions[1837]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1837]
+    (const void *)&gInstructions[1838]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = 
@@ -1852,13 +1852,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2637]
+    (const void *)&gInstructions[2644]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2638]
+    (const void *)&gInstructions[2645]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = 
@@ -1884,13 +1884,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2641]
+    (const void *)&gInstructions[2648]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2642]
+    (const void *)&gInstructions[2649]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = 
@@ -1951,13 +1951,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1834]
+    (const void *)&gInstructions[1835]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1835]
+    (const void *)&gInstructions[1836]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = 
@@ -1983,13 +1983,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1838]
+    (const void *)&gInstructions[1839]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1839]
+    (const void *)&gInstructions[1840]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = 
@@ -2015,13 +2015,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2639]
+    (const void *)&gInstructions[2646]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2640]
+    (const void *)&gInstructions[2647]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = 
@@ -2047,13 +2047,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2643]
+    (const void *)&gInstructions[2650]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2644]
+    (const void *)&gInstructions[2651]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = 
@@ -2114,13 +2114,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1840]
+    (const void *)&gInstructions[1841]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1842]
+    (const void *)&gInstructions[1843]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = 
@@ -2155,13 +2155,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1844]
+    (const void *)&gInstructions[1845]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1846]
+    (const void *)&gInstructions[1847]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = 
@@ -2187,13 +2187,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1847]
+    (const void *)&gInstructions[1848]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1849]
+    (const void *)&gInstructions[1850]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = 
@@ -2219,7 +2219,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1860]
+    (const void *)&gInstructions[1861]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = 
@@ -2245,7 +2245,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1973]
+    (const void *)&gInstructions[1974]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = 
@@ -2269,7 +2269,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2107]
+    (const void *)&gInstructions[2108]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = 
@@ -2304,13 +2304,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2047]
+    (const void *)&gInstructions[2048]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2048]
+    (const void *)&gInstructions[2049]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = 
@@ -2336,7 +2336,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2050]
+    (const void *)&gInstructions[2051]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = 
@@ -2371,7 +2371,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2173]
+    (const void *)&gInstructions[2174]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = 
@@ -2397,7 +2397,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2051]
+    (const void *)&gInstructions[2052]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = 
@@ -2414,7 +2414,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2053]
+    (const void *)&gInstructions[2054]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = 
@@ -2440,7 +2440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2055]
+    (const void *)&gInstructions[2056]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = 
@@ -2466,7 +2466,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2056]
+    (const void *)&gInstructions[2057]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = 
@@ -2483,7 +2483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2062]
+    (const void *)&gInstructions[2063]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = 
@@ -2509,13 +2509,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2095]
+    (const void *)&gInstructions[2096]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2098]
+    (const void *)&gInstructions[2099]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = 
@@ -2541,13 +2541,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2096]
+    (const void *)&gInstructions[2097]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2097]
+    (const void *)&gInstructions[2098]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = 
@@ -2573,7 +2573,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2101]
+    (const void *)&gInstructions[2102]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = 
@@ -2599,7 +2599,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2102]
+    (const void *)&gInstructions[2103]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = 
@@ -2634,7 +2634,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2104]
+    (const void *)&gInstructions[2105]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = 
@@ -2660,13 +2660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2105]
+    (const void *)&gInstructions[2106]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2110]
+    (const void *)&gInstructions[2111]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_wi = 
@@ -2701,7 +2701,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2108]
+    (const void *)&gInstructions[2109]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = 
@@ -2725,7 +2725,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2331]
+    (const void *)&gInstructions[2338]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = 
@@ -2742,7 +2742,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2112]
+    (const void *)&gInstructions[2113]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = 
@@ -2768,7 +2768,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2113]
+    (const void *)&gInstructions[2114]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = 
@@ -2803,7 +2803,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2125]
+    (const void *)&gInstructions[2126]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = 
@@ -2818,13 +2818,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2333]
+    (const void *)&gInstructions[2340]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2376]
+    (const void *)&gInstructions[2383]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = 
@@ -2859,7 +2859,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2135]
+    (const void *)&gInstructions[2136]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = 
@@ -2885,13 +2885,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2149]
+    (const void *)&gInstructions[2150]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2152]
+    (const void *)&gInstructions[2153]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = 
@@ -2917,13 +2917,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2150]
+    (const void *)&gInstructions[2151]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2151]
+    (const void *)&gInstructions[2152]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = 
@@ -2949,13 +2949,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2159]
+    (const void *)&gInstructions[2160]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2160]
+    (const void *)&gInstructions[2161]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = 
@@ -2981,7 +2981,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2165]
+    (const void *)&gInstructions[2166]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = 
@@ -3007,7 +3007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2167]
+    (const void *)&gInstructions[2168]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = 
@@ -3033,13 +3033,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2177]
+    (const void *)&gInstructions[2184]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2214]
+    (const void *)&gInstructions[2221]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = 
@@ -3065,13 +3065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2178]
+    (const void *)&gInstructions[2185]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2205]
+    (const void *)&gInstructions[2212]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = 
@@ -3097,13 +3097,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2180]
+    (const void *)&gInstructions[2187]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2185]
+    (const void *)&gInstructions[2192]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = 
@@ -3129,13 +3129,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2181]
+    (const void *)&gInstructions[2188]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2184]
+    (const void *)&gInstructions[2191]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = 
@@ -3161,13 +3161,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2182]
+    (const void *)&gInstructions[2189]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2183]
+    (const void *)&gInstructions[2190]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = 
@@ -3193,7 +3193,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2190]
+    (const void *)&gInstructions[2197]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = 
@@ -3219,7 +3219,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2194]
+    (const void *)&gInstructions[2201]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = 
@@ -3245,13 +3245,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2198]
+    (const void *)&gInstructions[2205]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2202]
+    (const void *)&gInstructions[2209]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = 
@@ -3266,13 +3266,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2199]
+    (const void *)&gInstructions[2206]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2203]
+    (const void *)&gInstructions[2210]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = 
@@ -3309,13 +3309,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2208]
+    (const void *)&gInstructions[2215]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2213]
+    (const void *)&gInstructions[2220]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = 
@@ -3341,13 +3341,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2209]
+    (const void *)&gInstructions[2216]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2212]
+    (const void *)&gInstructions[2219]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = 
@@ -3373,13 +3373,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2210]
+    (const void *)&gInstructions[2217]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2211]
+    (const void *)&gInstructions[2218]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = 
@@ -3405,13 +3405,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2215]
+    (const void *)&gInstructions[2222]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2218]
+    (const void *)&gInstructions[2225]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = 
@@ -3437,13 +3437,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2216]
+    (const void *)&gInstructions[2223]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2217]
+    (const void *)&gInstructions[2224]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = 
@@ -3469,13 +3469,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2237]
+    (const void *)&gInstructions[2244]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2239]
+    (const void *)&gInstructions[2246]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = 
@@ -3510,13 +3510,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2241]
+    (const void *)&gInstructions[2248]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2243]
+    (const void *)&gInstructions[2250]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = 
@@ -3551,13 +3551,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2279]
+    (const void *)&gInstructions[2286]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2280]
+    (const void *)&gInstructions[2287]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = 
@@ -3583,7 +3583,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2293]
+    (const void *)&gInstructions[2300]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = 
@@ -3609,7 +3609,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2295]
+    (const void *)&gInstructions[2302]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = 
@@ -3635,7 +3635,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2297]
+    (const void *)&gInstructions[2304]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = 
@@ -3652,7 +3652,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2305]
+    (const void *)&gInstructions[2312]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = 
@@ -3669,13 +3669,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2307]
+    (const void *)&gInstructions[2314]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2309]
+    (const void *)&gInstructions[2316]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = 
@@ -3701,13 +3701,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2314]
+    (const void *)&gInstructions[2321]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2316]
+    (const void *)&gInstructions[2323]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = 
@@ -3733,7 +3733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2317]
+    (const void *)&gInstructions[2324]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = 
@@ -3750,19 +3750,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2319]
+    (const void *)&gInstructions[2326]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2338]
+    (const void *)&gInstructions[2345]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2339]
+    (const void *)&gInstructions[2346]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = 
@@ -3797,13 +3797,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2321]
+    (const void *)&gInstructions[2328]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2323]
+    (const void *)&gInstructions[2330]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = 
@@ -3818,13 +3818,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2334]
+    (const void *)&gInstructions[2341]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2342]
+    (const void *)&gInstructions[2349]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = 
@@ -3859,13 +3859,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2328]
+    (const void *)&gInstructions[2335]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2330]
+    (const void *)&gInstructions[2337]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = 
@@ -3891,7 +3891,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2335]
+    (const void *)&gInstructions[2342]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = 
@@ -3906,7 +3906,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2378]
+    (const void *)&gInstructions[2385]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = 
@@ -3923,7 +3923,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2336]
+    (const void *)&gInstructions[2343]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = 
@@ -3938,7 +3938,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2390]
+    (const void *)&gInstructions[2397]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = 
@@ -3955,13 +3955,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2337]
+    (const void *)&gInstructions[2344]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2340]
+    (const void *)&gInstructions[2347]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = 
@@ -3985,7 +3985,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2396]
+    (const void *)&gInstructions[2403]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = 
@@ -4011,7 +4011,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2343]
+    (const void *)&gInstructions[2350]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = 
@@ -4026,7 +4026,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2381]
+    (const void *)&gInstructions[2388]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = 
@@ -4043,7 +4043,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2344]
+    (const void *)&gInstructions[2351]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = 
@@ -4058,7 +4058,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2387]
+    (const void *)&gInstructions[2394]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = 
@@ -4084,7 +4084,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2345]
+    (const void *)&gInstructions[2352]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = 
@@ -4099,7 +4099,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2393]
+    (const void *)&gInstructions[2400]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = 
@@ -4116,7 +4116,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2346]
+    (const void *)&gInstructions[2353]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = 
@@ -4131,7 +4131,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2352]
+    (const void *)&gInstructions[2359]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = 
@@ -4148,7 +4148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2347]
+    (const void *)&gInstructions[2354]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = 
@@ -4163,7 +4163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2364]
+    (const void *)&gInstructions[2371]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = 
@@ -4180,7 +4180,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2348]
+    (const void *)&gInstructions[2355]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = 
@@ -4195,7 +4195,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2355]
+    (const void *)&gInstructions[2362]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = 
@@ -4212,7 +4212,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2349]
+    (const void *)&gInstructions[2356]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = 
@@ -4227,7 +4227,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2361]
+    (const void *)&gInstructions[2368]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = 
@@ -4253,7 +4253,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2350]
+    (const void *)&gInstructions[2357]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = 
@@ -4268,7 +4268,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2367]
+    (const void *)&gInstructions[2374]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = 
@@ -4285,7 +4285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2351]
+    (const void *)&gInstructions[2358]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = 
@@ -4300,7 +4300,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2358]
+    (const void *)&gInstructions[2365]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = 
@@ -4317,7 +4317,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2370]
+    (const void *)&gInstructions[2377]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = 
@@ -4332,7 +4332,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2515]
+    (const void *)&gInstructions[2522]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = 
@@ -4358,7 +4358,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2372]
+    (const void *)&gInstructions[2379]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = 
@@ -4373,7 +4373,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2501]
+    (const void *)&gInstructions[2508]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = 
@@ -4399,7 +4399,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2373]
+    (const void *)&gInstructions[2380]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = 
@@ -4414,13 +4414,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2423]
+    (const void *)&gInstructions[2430]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2424]
+    (const void *)&gInstructions[2431]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = 
@@ -4446,7 +4446,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2374]
+    (const void *)&gInstructions[2381]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = 
@@ -4461,13 +4461,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2427]
+    (const void *)&gInstructions[2434]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2428]
+    (const void *)&gInstructions[2435]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = 
@@ -4493,7 +4493,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2375]
+    (const void *)&gInstructions[2382]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = 
@@ -4508,7 +4508,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2534]
+    (const void *)&gInstructions[2541]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = 
@@ -4534,7 +4534,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2377]
+    (const void *)&gInstructions[2384]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = 
@@ -4549,7 +4549,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2384]
+    (const void *)&gInstructions[2391]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = 
@@ -4566,7 +4566,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2398]
+    (const void *)&gInstructions[2405]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = 
@@ -4583,13 +4583,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2404]
+    (const void *)&gInstructions[2411]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2406]
+    (const void *)&gInstructions[2413]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = 
@@ -4615,7 +4615,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2409]
+    (const void *)&gInstructions[2416]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = 
@@ -4641,13 +4641,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2412]
+    (const void *)&gInstructions[2419]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2415]
+    (const void *)&gInstructions[2422]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = 
@@ -4673,13 +4673,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2413]
+    (const void *)&gInstructions[2420]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2414]
+    (const void *)&gInstructions[2421]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = 
@@ -4705,13 +4705,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2443]
+    (const void *)&gInstructions[2450]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2444]
+    (const void *)&gInstructions[2451]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = 
@@ -4746,13 +4746,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2445]
+    (const void *)&gInstructions[2452]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2446]
+    (const void *)&gInstructions[2453]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = 
@@ -4787,13 +4787,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2462]
+    (const void *)&gInstructions[2469]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2463]
+    (const void *)&gInstructions[2470]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = 
@@ -4819,7 +4819,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2464]
+    (const void *)&gInstructions[2471]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = 
@@ -4845,13 +4845,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2471]
+    (const void *)&gInstructions[2478]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2472]
+    (const void *)&gInstructions[2479]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = 
@@ -4877,7 +4877,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2475]
+    (const void *)&gInstructions[2482]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = 
@@ -4894,7 +4894,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2477]
+    (const void *)&gInstructions[2484]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = 
@@ -4920,13 +4920,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2497]
+    (const void *)&gInstructions[2504]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2499]
+    (const void *)&gInstructions[2506]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = 
@@ -4952,13 +4952,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2512]
+    (const void *)&gInstructions[2519]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2514]
+    (const void *)&gInstructions[2521]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = 
@@ -4984,13 +4984,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2530]
+    (const void *)&gInstructions[2537]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2532]
+    (const void *)&gInstructions[2539]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = 
@@ -5016,13 +5016,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2558]
+    (const void *)&gInstructions[2565]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2561]
+    (const void *)&gInstructions[2568]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = 
@@ -5037,13 +5037,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2562]
+    (const void *)&gInstructions[2569]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2565]
+    (const void *)&gInstructions[2572]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = 
@@ -5069,13 +5069,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2559]
+    (const void *)&gInstructions[2566]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2560]
+    (const void *)&gInstructions[2567]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = 
@@ -5090,13 +5090,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2563]
+    (const void *)&gInstructions[2570]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2564]
+    (const void *)&gInstructions[2571]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = 
@@ -5122,13 +5122,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2589]
+    (const void *)&gInstructions[2596]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2590]
+    (const void *)&gInstructions[2597]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = 
@@ -5154,13 +5154,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2591]
+    (const void *)&gInstructions[2598]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2592]
+    (const void *)&gInstructions[2599]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = 
@@ -5186,13 +5186,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2593]
+    (const void *)&gInstructions[2600]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2594]
+    (const void *)&gInstructions[2601]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = 
@@ -5229,13 +5229,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2595]
+    (const void *)&gInstructions[2602]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2596]
+    (const void *)&gInstructions[2603]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = 
@@ -5261,13 +5261,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2617]
+    (const void *)&gInstructions[2624]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2618]
+    (const void *)&gInstructions[2625]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = 
@@ -5293,13 +5293,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2619]
+    (const void *)&gInstructions[2626]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2620]
+    (const void *)&gInstructions[2627]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = 
@@ -5325,13 +5325,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2621]
+    (const void *)&gInstructions[2628]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2622]
+    (const void *)&gInstructions[2629]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = 
@@ -5368,13 +5368,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2623]
+    (const void *)&gInstructions[2630]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2624]
+    (const void *)&gInstructions[2631]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = 
@@ -5400,13 +5400,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2629]
+    (const void *)&gInstructions[2636]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2631]
+    (const void *)&gInstructions[2638]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = 
@@ -5432,13 +5432,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2632]
+    (const void *)&gInstructions[2639]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2634]
+    (const void *)&gInstructions[2641]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = 
@@ -5464,13 +5464,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2635]
+    (const void *)&gInstructions[2642]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2636]
+    (const void *)&gInstructions[2643]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = 
@@ -5505,13 +5505,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2645]
+    (const void *)&gInstructions[2652]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2646]
+    (const void *)&gInstructions[2653]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = 
@@ -5809,7 +5809,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1403]
+    (const void *)&gInstructions[1404]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = 
@@ -5824,7 +5824,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1406]
+    (const void *)&gInstructions[1407]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = 
@@ -5839,7 +5839,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1408]
+    (const void *)&gInstructions[1409]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = 
@@ -5854,7 +5854,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1411]
+    (const void *)&gInstructions[1412]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = 
@@ -5880,7 +5880,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1427]
+    (const void *)&gInstructions[1428]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = 
@@ -5895,7 +5895,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1429]
+    (const void *)&gInstructions[1430]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = 
@@ -5921,7 +5921,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1431]
+    (const void *)&gInstructions[1432]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = 
@@ -5936,7 +5936,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1433]
+    (const void *)&gInstructions[1434]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = 
@@ -5962,7 +5962,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1459]
+    (const void *)&gInstructions[1460]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = 
@@ -5977,7 +5977,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1462]
+    (const void *)&gInstructions[1463]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = 
@@ -5992,7 +5992,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1464]
+    (const void *)&gInstructions[1465]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = 
@@ -6007,7 +6007,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1467]
+    (const void *)&gInstructions[1468]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = 
@@ -6033,7 +6033,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1469]
+    (const void *)&gInstructions[1470]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = 
@@ -6048,7 +6048,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1472]
+    (const void *)&gInstructions[1473]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = 
@@ -6074,13 +6074,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1476]
+    (const void *)&gInstructions[1477]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1521]
+    (const void *)&gInstructions[1522]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = 
@@ -6095,7 +6095,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1489]
+    (const void *)&gInstructions[1490]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = 
@@ -6110,7 +6110,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1546]
+    (const void *)&gInstructions[1547]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = 
@@ -6136,13 +6136,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1480]
+    (const void *)&gInstructions[1481]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1523]
+    (const void *)&gInstructions[1524]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = 
@@ -6157,7 +6157,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1509]
+    (const void *)&gInstructions[1510]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = 
@@ -6172,7 +6172,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1557]
+    (const void *)&gInstructions[1558]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = 
@@ -6198,7 +6198,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1492]
+    (const void *)&gInstructions[1493]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = 
@@ -6213,7 +6213,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1511]
+    (const void *)&gInstructions[1512]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = 
@@ -6228,7 +6228,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1527]
+    (const void *)&gInstructions[1528]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = 
@@ -6243,7 +6243,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1540]
+    (const void *)&gInstructions[1541]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = 
@@ -6269,13 +6269,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1495]
+    (const void *)&gInstructions[1496]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1518]
+    (const void *)&gInstructions[1519]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = 
@@ -6290,13 +6290,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1576]
+    (const void *)&gInstructions[1577]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1577]
+    (const void *)&gInstructions[1578]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi = 
@@ -6311,7 +6311,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1579]
+    (const void *)&gInstructions[1580]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = 
@@ -6328,13 +6328,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1496]
+    (const void *)&gInstructions[1497]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1519]
+    (const void *)&gInstructions[1520]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = 
@@ -6349,13 +6349,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1497]
+    (const void *)&gInstructions[1498]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1520]
+    (const void *)&gInstructions[1521]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = 
@@ -6370,13 +6370,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1529]
+    (const void *)&gInstructions[1530]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1545]
+    (const void *)&gInstructions[1546]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = 
@@ -6393,13 +6393,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1525]
+    (const void *)&gInstructions[1526]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1543]
+    (const void *)&gInstructions[1544]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = 
@@ -6416,13 +6416,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1534]
+    (const void *)&gInstructions[1535]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1535]
+    (const void *)&gInstructions[1536]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi = 
@@ -6437,7 +6437,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1538]
+    (const void *)&gInstructions[1539]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = 
@@ -6454,13 +6454,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1548]
+    (const void *)&gInstructions[1549]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1559]
+    (const void *)&gInstructions[1560]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = 
@@ -6475,13 +6475,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1570]
+    (const void *)&gInstructions[1571]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1573]
+    (const void *)&gInstructions[1574]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = 
@@ -6496,13 +6496,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1572]
+    (const void *)&gInstructions[1573]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1575]
+    (const void *)&gInstructions[1576]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = 
@@ -6528,13 +6528,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1549]
+    (const void *)&gInstructions[1550]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1560]
+    (const void *)&gInstructions[1561]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = 
@@ -6549,13 +6549,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1550]
+    (const void *)&gInstructions[1551]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1561]
+    (const void *)&gInstructions[1562]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = 
@@ -6570,13 +6570,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1564]
+    (const void *)&gInstructions[1565]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1569]
+    (const void *)&gInstructions[1570]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = 
@@ -6593,13 +6593,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1562]
+    (const void *)&gInstructions[1563]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1567]
+    (const void *)&gInstructions[1568]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = 
@@ -6616,7 +6616,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1583]
+    (const void *)&gInstructions[1584]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = 
@@ -6631,7 +6631,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1586]
+    (const void *)&gInstructions[1587]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = 
@@ -6646,7 +6646,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1588]
+    (const void *)&gInstructions[1589]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = 
@@ -6661,7 +6661,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1591]
+    (const void *)&gInstructions[1592]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = 
@@ -6687,7 +6687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1887]
+    (const void *)&gInstructions[1888]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = 
@@ -6702,7 +6702,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1890]
+    (const void *)&gInstructions[1891]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = 
@@ -6717,7 +6717,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1892]
+    (const void *)&gInstructions[1893]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = 
@@ -6732,7 +6732,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1895]
+    (const void *)&gInstructions[1896]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = 
@@ -6758,7 +6758,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1902]
+    (const void *)&gInstructions[1903]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = 
@@ -6773,7 +6773,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1905]
+    (const void *)&gInstructions[1906]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = 
@@ -6788,7 +6788,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1907]
+    (const void *)&gInstructions[1908]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = 
@@ -6803,7 +6803,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1910]
+    (const void *)&gInstructions[1911]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = 
@@ -6829,7 +6829,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1916]
+    (const void *)&gInstructions[1917]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = 
@@ -6844,7 +6844,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1920]
+    (const void *)&gInstructions[1921]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = 
@@ -6870,7 +6870,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1917]
+    (const void *)&gInstructions[1918]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = 
@@ -6885,7 +6885,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1921]
+    (const void *)&gInstructions[1922]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = 
@@ -6911,13 +6911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1924]
+    (const void *)&gInstructions[1925]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1979]
+    (const void *)&gInstructions[1980]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_wi = 
@@ -6954,13 +6954,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1925]
+    (const void *)&gInstructions[1926]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1980]
+    (const void *)&gInstructions[1981]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_wi = 
@@ -6986,7 +6986,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1981]
+    (const void *)&gInstructions[1982]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = 
@@ -7023,7 +7023,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1928]
+    (const void *)&gInstructions[1929]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = 
@@ -7038,7 +7038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1929]
+    (const void *)&gInstructions[1930]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = 
@@ -7053,7 +7053,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1930]
+    (const void *)&gInstructions[1931]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = 
@@ -7079,7 +7079,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1949]
+    (const void *)&gInstructions[1950]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = 
@@ -7105,7 +7105,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1965]
+    (const void *)&gInstructions[1966]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = 
@@ -7140,7 +7140,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1961]
+    (const void *)&gInstructions[1962]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = 
@@ -7175,7 +7175,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2001]
+    (const void *)&gInstructions[2002]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = 
@@ -7201,13 +7201,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1935]
+    (const void *)&gInstructions[1936]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1937]
+    (const void *)&gInstructions[1938]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = 
@@ -7222,13 +7222,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1941]
+    (const void *)&gInstructions[1942]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1947]
+    (const void *)&gInstructions[1948]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = 
@@ -7243,13 +7243,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1943]
+    (const void *)&gInstructions[1944]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1945]
+    (const void *)&gInstructions[1946]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = 
@@ -7275,13 +7275,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1936]
+    (const void *)&gInstructions[1937]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1938]
+    (const void *)&gInstructions[1939]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = 
@@ -7296,13 +7296,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1942]
+    (const void *)&gInstructions[1943]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1948]
+    (const void *)&gInstructions[1949]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = 
@@ -7317,13 +7317,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1944]
+    (const void *)&gInstructions[1945]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1946]
+    (const void *)&gInstructions[1947]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = 
@@ -7349,7 +7349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1951]
+    (const void *)&gInstructions[1952]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = 
@@ -7384,7 +7384,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1955]
+    (const void *)&gInstructions[1956]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = 
@@ -7410,7 +7410,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1959]
+    (const void *)&gInstructions[1960]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = 
@@ -7445,7 +7445,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1999]
+    (const void *)&gInstructions[2000]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = 
@@ -7471,7 +7471,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1952]
+    (const void *)&gInstructions[1953]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = 
@@ -7506,7 +7506,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1956]
+    (const void *)&gInstructions[1957]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = 
@@ -7552,7 +7552,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1962]
+    (const void *)&gInstructions[1963]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = 
@@ -7587,7 +7587,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1966]
+    (const void *)&gInstructions[1967]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = 
@@ -7633,7 +7633,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1971]
+    (const void *)&gInstructions[1972]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = 
@@ -7668,7 +7668,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1975]
+    (const void *)&gInstructions[1976]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = 
@@ -7692,7 +7692,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1977]
+    (const void *)&gInstructions[1978]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = 
@@ -7727,7 +7727,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1982]
+    (const void *)&gInstructions[1983]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = 
@@ -7764,7 +7764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1987]
+    (const void *)&gInstructions[1988]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = 
@@ -7779,7 +7779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1988]
+    (const void *)&gInstructions[1989]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = 
@@ -7803,7 +7803,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2003]
+    (const void *)&gInstructions[2004]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = 
@@ -7818,7 +7818,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2004]
+    (const void *)&gInstructions[2005]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = 
@@ -7842,7 +7842,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2011]
+    (const void *)&gInstructions[2012]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = 
@@ -7857,7 +7857,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2015]
+    (const void *)&gInstructions[2016]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = 
@@ -7883,7 +7883,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1989]
+    (const void *)&gInstructions[1990]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = 
@@ -7898,7 +7898,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1990]
+    (const void *)&gInstructions[1991]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = 
@@ -7922,7 +7922,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2005]
+    (const void *)&gInstructions[2006]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = 
@@ -7937,7 +7937,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2006]
+    (const void *)&gInstructions[2007]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = 
@@ -7961,7 +7961,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2012]
+    (const void *)&gInstructions[2013]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = 
@@ -7976,7 +7976,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2016]
+    (const void *)&gInstructions[2017]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = 
@@ -8002,7 +8002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2030]
+    (const void *)&gInstructions[2031]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = 
@@ -8017,7 +8017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2033]
+    (const void *)&gInstructions[2034]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = 
@@ -8032,7 +8032,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2035]
+    (const void *)&gInstructions[2036]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = 
@@ -8047,7 +8047,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2038]
+    (const void *)&gInstructions[2039]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = 
@@ -8073,7 +8073,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2043]
+    (const void *)&gInstructions[2044]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = 
@@ -8088,7 +8088,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2045]
+    (const void *)&gInstructions[2046]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = 
@@ -8114,7 +8114,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2058]
+    (const void *)&gInstructions[2059]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = 
@@ -8140,7 +8140,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2060]
+    (const void *)&gInstructions[2061]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = 
@@ -8157,7 +8157,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2064]
+    (const void *)&gInstructions[2065]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = 
@@ -8174,7 +8174,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2066]
+    (const void *)&gInstructions[2067]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = 
@@ -8191,7 +8191,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2068]
+    (const void *)&gInstructions[2069]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = 
@@ -8217,7 +8217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2070]
+    (const void *)&gInstructions[2071]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = 
@@ -8243,7 +8243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2072]
+    (const void *)&gInstructions[2073]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = 
@@ -8260,7 +8260,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2074]
+    (const void *)&gInstructions[2075]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = 
@@ -8277,7 +8277,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2076]
+    (const void *)&gInstructions[2077]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = 
@@ -8294,7 +8294,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2078]
+    (const void *)&gInstructions[2079]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = 
@@ -8311,7 +8311,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2080]
+    (const void *)&gInstructions[2081]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = 
@@ -8328,13 +8328,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2085]
+    (const void *)&gInstructions[2086]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2089]
+    (const void *)&gInstructions[2090]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = 
@@ -8360,13 +8360,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2087]
+    (const void *)&gInstructions[2088]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2088]
+    (const void *)&gInstructions[2089]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = 
@@ -8392,7 +8392,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2090]
+    (const void *)&gInstructions[2091]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = 
@@ -8409,7 +8409,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2092]
+    (const void *)&gInstructions[2093]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = 
@@ -8426,7 +8426,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2121]
+    (const void *)&gInstructions[2122]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = 
@@ -8443,7 +8443,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2123]
+    (const void *)&gInstructions[2124]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = 
@@ -8460,7 +8460,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2127]
+    (const void *)&gInstructions[2128]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = 
@@ -8477,7 +8477,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2131]
+    (const void *)&gInstructions[2132]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = 
@@ -8494,7 +8494,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2133]
+    (const void *)&gInstructions[2134]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = 
@@ -8520,7 +8520,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2137]
+    (const void *)&gInstructions[2138]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = 
@@ -8537,7 +8537,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2231]
+    (const void *)&gInstructions[2238]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = 
@@ -8574,7 +8574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2275]
+    (const void *)&gInstructions[2282]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = 
@@ -8591,7 +8591,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2276]
+    (const void *)&gInstructions[2283]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = 
@@ -8628,7 +8628,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2299]
+    (const void *)&gInstructions[2306]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = 
@@ -8645,7 +8645,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2310]
+    (const void *)&gInstructions[2317]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = 
@@ -8662,7 +8662,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2312]
+    (const void *)&gInstructions[2319]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = 
@@ -8679,7 +8679,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2324]
+    (const void *)&gInstructions[2331]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = 
@@ -8696,7 +8696,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2326]
+    (const void *)&gInstructions[2333]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = 
@@ -8713,7 +8713,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2400]
+    (const void *)&gInstructions[2407]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = 
@@ -8730,7 +8730,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2402]
+    (const void *)&gInstructions[2409]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = 
@@ -8747,7 +8747,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2407]
+    (const void *)&gInstructions[2414]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = 
@@ -8764,7 +8764,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2410]
+    (const void *)&gInstructions[2417]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = 
@@ -8790,13 +8790,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2417]
+    (const void *)&gInstructions[2424]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2418]
+    (const void *)&gInstructions[2425]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = 
@@ -8822,13 +8822,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2421]
+    (const void *)&gInstructions[2428]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2422]
+    (const void *)&gInstructions[2429]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = 
@@ -8843,13 +8843,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2425]
+    (const void *)&gInstructions[2432]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2426]
+    (const void *)&gInstructions[2433]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = 
@@ -8864,7 +8864,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2487]
+    (const void *)&gInstructions[2494]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = 
@@ -8879,13 +8879,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2506]
+    (const void *)&gInstructions[2513]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2510]
+    (const void *)&gInstructions[2517]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = 
@@ -8900,7 +8900,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2520]
+    (const void *)&gInstructions[2527]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = 
@@ -8941,7 +8941,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2441]
+    (const void *)&gInstructions[2448]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = 
@@ -8958,7 +8958,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2478]
+    (const void *)&gInstructions[2485]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = 
@@ -8973,13 +8973,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2480]
+    (const void *)&gInstructions[2487]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2482]
+    (const void *)&gInstructions[2489]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = 
@@ -8996,7 +8996,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2488]
+    (const void *)&gInstructions[2495]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = 
@@ -9022,13 +9022,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2491]
+    (const void *)&gInstructions[2498]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2493]
+    (const void *)&gInstructions[2500]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = 
@@ -9043,13 +9043,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2524]
+    (const void *)&gInstructions[2531]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2526]
+    (const void *)&gInstructions[2533]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = 
@@ -9090,7 +9090,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2494]
+    (const void *)&gInstructions[2501]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = 
@@ -9116,19 +9116,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2502]
+    (const void *)&gInstructions[2509]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2516]
+    (const void *)&gInstructions[2523]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2535]
+    (const void *)&gInstructions[2542]
 };
 
 const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = 
@@ -9160,7 +9160,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2503]
+    (const void *)&gInstructions[2510]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = 
@@ -9177,13 +9177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2507]
+    (const void *)&gInstructions[2514]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2511]
+    (const void *)&gInstructions[2518]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = 
@@ -9209,7 +9209,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2517]
+    (const void *)&gInstructions[2524]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = 
@@ -9226,7 +9226,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2521]
+    (const void *)&gInstructions[2528]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = 
@@ -9252,7 +9252,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2527]
+    (const void *)&gInstructions[2534]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = 
@@ -9278,7 +9278,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2536]
+    (const void *)&gInstructions[2543]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = 
@@ -9295,7 +9295,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2539]
+    (const void *)&gInstructions[2546]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = 
@@ -9312,7 +9312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2541]
+    (const void *)&gInstructions[2548]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = 
@@ -9338,7 +9338,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2543]
+    (const void *)&gInstructions[2550]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = 
@@ -9364,7 +9364,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2545]
+    (const void *)&gInstructions[2552]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = 
@@ -9381,7 +9381,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2547]
+    (const void *)&gInstructions[2554]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = 
@@ -9398,7 +9398,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2549]
+    (const void *)&gInstructions[2556]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = 
@@ -9415,7 +9415,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2551]
+    (const void *)&gInstructions[2558]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = 
@@ -9432,7 +9432,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2553]
+    (const void *)&gInstructions[2560]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = 
@@ -9449,7 +9449,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2566]
+    (const void *)&gInstructions[2573]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = 
@@ -9466,7 +9466,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2568]
+    (const void *)&gInstructions[2575]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = 
@@ -9492,7 +9492,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2570]
+    (const void *)&gInstructions[2577]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = 
@@ -9518,7 +9518,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2572]
+    (const void *)&gInstructions[2579]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = 
@@ -9535,7 +9535,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2574]
+    (const void *)&gInstructions[2581]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = 
@@ -9552,7 +9552,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2576]
+    (const void *)&gInstructions[2583]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = 
@@ -9578,7 +9578,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2578]
+    (const void *)&gInstructions[2585]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = 
@@ -9604,7 +9604,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2580]
+    (const void *)&gInstructions[2587]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = 
@@ -9621,13 +9621,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2583]
+    (const void *)&gInstructions[2590]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2584]
+    (const void *)&gInstructions[2591]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = 
@@ -9653,7 +9653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2651]
+    (const void *)&gInstructions[2661]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = 
@@ -9668,7 +9668,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2653]
+    (const void *)&gInstructions[2663]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = 
@@ -9694,7 +9694,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2655]
+    (const void *)&gInstructions[2670]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = 
@@ -9709,7 +9709,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2658]
+    (const void *)&gInstructions[2673]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = 
@@ -9724,7 +9724,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2660]
+    (const void *)&gInstructions[2675]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = 
@@ -9739,7 +9739,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2663]
+    (const void *)&gInstructions[2678]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = 
@@ -9765,7 +9765,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2666]
+    (const void *)&gInstructions[2681]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = 
@@ -9780,7 +9780,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2669]
+    (const void *)&gInstructions[2684]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = 
@@ -9795,7 +9795,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2671]
+    (const void *)&gInstructions[2686]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = 
@@ -9810,7 +9810,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2674]
+    (const void *)&gInstructions[2689]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = 
@@ -9836,7 +9836,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2678]
+    (const void *)&gInstructions[2693]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = 
@@ -9851,7 +9851,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2681]
+    (const void *)&gInstructions[2696]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = 
@@ -9877,7 +9877,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2683]
+    (const void *)&gInstructions[2698]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = 
@@ -9892,7 +9892,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2685]
+    (const void *)&gInstructions[2700]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = 
@@ -9918,7 +9918,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2687]
+    (const void *)&gInstructions[2702]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = 
@@ -9933,7 +9933,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2689]
+    (const void *)&gInstructions[2704]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = 
@@ -9959,7 +9959,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2691]
+    (const void *)&gInstructions[2706]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = 
@@ -9974,7 +9974,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2693]
+    (const void *)&gInstructions[2708]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = 
@@ -10263,7 +10263,7 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1405]
+    (const void *)&gInstructions[1406]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w = 
@@ -10278,7 +10278,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1410]
+    (const void *)&gInstructions[1411]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_58_02_w = 
@@ -10304,7 +10304,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_2f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1471]
+    (const void *)&gInstructions[1472]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_2f_00_w = 
@@ -10330,13 +10330,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1479]
+    (const void *)&gInstructions[1480]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1522]
+    (const void *)&gInstructions[1523]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w = 
@@ -10351,7 +10351,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1498]
+    (const void *)&gInstructions[1499]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w = 
@@ -10366,7 +10366,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1551]
+    (const void *)&gInstructions[1552]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5b_02_w = 
@@ -10392,7 +10392,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1491]
+    (const void *)&gInstructions[1492]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w = 
@@ -10407,7 +10407,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1499]
+    (const void *)&gInstructions[1500]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w = 
@@ -10422,7 +10422,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1524]
+    (const void *)&gInstructions[1525]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w = 
@@ -10437,7 +10437,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1530]
+    (const void *)&gInstructions[1531]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5a_02_w = 
@@ -10463,7 +10463,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1504]
+    (const void *)&gInstructions[1505]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w = 
@@ -10478,7 +10478,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1578]
+    (const void *)&gInstructions[1579]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp = 
@@ -10495,7 +10495,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1505]
+    (const void *)&gInstructions[1506]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w = 
@@ -10510,7 +10510,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1506]
+    (const void *)&gInstructions[1507]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w = 
@@ -10525,7 +10525,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1533]
+    (const void *)&gInstructions[1534]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp = 
@@ -10542,7 +10542,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1507]
+    (const void *)&gInstructions[1508]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w = 
@@ -10557,7 +10557,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1508]
+    (const void *)&gInstructions[1509]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w = 
@@ -10572,7 +10572,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1580]
+    (const void *)&gInstructions[1581]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w = 
@@ -10587,7 +10587,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1581]
+    (const void *)&gInstructions[1582]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7d_02_w = 
@@ -10613,7 +10613,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1517]
+    (const void *)&gInstructions[1518]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w = 
@@ -10628,7 +10628,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1542]
+    (const void *)&gInstructions[1543]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_1d_00_w = 
@@ -10654,7 +10654,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1531]
+    (const void *)&gInstructions[1532]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp = 
@@ -10671,7 +10671,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1537]
+    (const void *)&gInstructions[1538]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp = 
@@ -10688,7 +10688,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1552]
+    (const void *)&gInstructions[1553]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w = 
@@ -10703,13 +10703,13 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1571]
+    (const void *)&gInstructions[1572]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1574]
+    (const void *)&gInstructions[1575]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7a_03_w = 
@@ -10735,7 +10735,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1553]
+    (const void *)&gInstructions[1554]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w = 
@@ -10750,7 +10750,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1554]
+    (const void *)&gInstructions[1555]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w = 
@@ -10765,7 +10765,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1566]
+    (const void *)&gInstructions[1567]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_78_02_wi = 
@@ -10791,7 +10791,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1555]
+    (const void *)&gInstructions[1556]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w = 
@@ -10806,7 +10806,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1556]
+    (const void *)&gInstructions[1557]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_7c_01_w = 
@@ -10832,7 +10832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1565]
+    (const void *)&gInstructions[1566]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp = 
@@ -10849,7 +10849,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1585]
+    (const void *)&gInstructions[1586]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w = 
@@ -10864,7 +10864,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1590]
+    (const void *)&gInstructions[1591]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5e_02_w = 
@@ -10890,7 +10890,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1889]
+    (const void *)&gInstructions[1890]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w = 
@@ -10905,7 +10905,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1894]
+    (const void *)&gInstructions[1895]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5f_02_w = 
@@ -10931,7 +10931,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1904]
+    (const void *)&gInstructions[1905]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w = 
@@ -10946,7 +10946,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1909]
+    (const void *)&gInstructions[1910]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5d_02_w = 
@@ -10972,7 +10972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1995]
+    (const void *)&gInstructions[1996]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w = 
@@ -10987,7 +10987,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1996]
+    (const void *)&gInstructions[1997]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_10_02_reg_w = 
@@ -11022,7 +11022,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1997]
+    (const void *)&gInstructions[1998]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w = 
@@ -11037,7 +11037,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1998]
+    (const void *)&gInstructions[1999]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_11_02_reg_w = 
@@ -11072,7 +11072,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2019]
+    (const void *)&gInstructions[2020]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l = 
@@ -11089,7 +11089,7 @@ const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2020]
+    (const void *)&gInstructions[2021]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_reg_l = 
@@ -11126,7 +11126,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_6e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2021]
+    (const void *)&gInstructions[2022]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l = 
@@ -11143,7 +11143,7 @@ const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2022]
+    (const void *)&gInstructions[2023]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_reg_l = 
@@ -11180,7 +11180,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2032]
+    (const void *)&gInstructions[2033]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w = 
@@ -11195,7 +11195,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2037]
+    (const void *)&gInstructions[2038]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_59_02_w = 
@@ -11221,7 +11221,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2657]
+    (const void *)&gInstructions[2672]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w = 
@@ -11236,7 +11236,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2662]
+    (const void *)&gInstructions[2677]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_51_02_w = 
@@ -11262,7 +11262,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2668]
+    (const void *)&gInstructions[2683]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w = 
@@ -11277,7 +11277,7 @@ const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2673]
+    (const void *)&gInstructions[2688]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_5c_02_w = 
@@ -11303,7 +11303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_05_5c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_05_2e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2680]
+    (const void *)&gInstructions[2695]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_05_2e_00_w = 
@@ -11592,13 +11592,13 @@ const ND_TABLE_OPCODE gEvexTable_root_05_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1425]
+    (const void *)&gInstructions[1426]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1426]
+    (const void *)&gInstructions[1427]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = 
@@ -11624,7 +11624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1461]
+    (const void *)&gInstructions[1462]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w = 
@@ -11639,7 +11639,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1466]
+    (const void *)&gInstructions[1467]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_c2_02_w = 
@@ -11665,7 +11665,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_c2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1514]
+    (const void *)&gInstructions[1515]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = 
@@ -11691,7 +11691,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1582]
+    (const void *)&gInstructions[1583]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = 
@@ -11717,13 +11717,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1603]
+    (const void *)&gInstructions[1604]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1605]
+    (const void *)&gInstructions[1606]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = 
@@ -11749,13 +11749,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1604]
+    (const void *)&gInstructions[1605]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1606]
+    (const void *)&gInstructions[1607]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = 
@@ -11792,13 +11792,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1608]
+    (const void *)&gInstructions[1609]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1610]
+    (const void *)&gInstructions[1611]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = 
@@ -11824,13 +11824,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1609]
+    (const void *)&gInstructions[1610]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1611]
+    (const void *)&gInstructions[1612]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = 
@@ -11867,7 +11867,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1612]
+    (const void *)&gInstructions[1613]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = 
@@ -11884,7 +11884,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1613]
+    (const void *)&gInstructions[1614]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = 
@@ -11921,13 +11921,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1620]
+    (const void *)&gInstructions[1621]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1621]
+    (const void *)&gInstructions[1622]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = 
@@ -11953,13 +11953,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1622]
+    (const void *)&gInstructions[1623]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1623]
+    (const void *)&gInstructions[1624]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = 
@@ -11985,13 +11985,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1818]
+    (const void *)&gInstructions[1819]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1820]
+    (const void *)&gInstructions[1821]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = 
@@ -12006,7 +12006,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1819]
+    (const void *)&gInstructions[1820]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_66_00_w = 
@@ -12032,13 +12032,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1821]
+    (const void *)&gInstructions[1822]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1823]
+    (const void *)&gInstructions[1824]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = 
@@ -12053,7 +12053,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1822]
+    (const void *)&gInstructions[1823]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_67_00_w = 
@@ -12079,13 +12079,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1850]
+    (const void *)&gInstructions[1851]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1852]
+    (const void *)&gInstructions[1853]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = 
@@ -12100,7 +12100,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1851]
+    (const void *)&gInstructions[1852]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_26_00_w = 
@@ -12126,13 +12126,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1853]
+    (const void *)&gInstructions[1854]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1855]
+    (const void *)&gInstructions[1856]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = 
@@ -12147,7 +12147,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1854]
+    (const void *)&gInstructions[1855]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_27_00_w = 
@@ -12173,7 +12173,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1856]
+    (const void *)&gInstructions[1857]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = 
@@ -12199,7 +12199,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1858]
+    (const void *)&gInstructions[1859]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = 
@@ -12225,13 +12225,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1867]
+    (const void *)&gInstructions[1868]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1869]
+    (const void *)&gInstructions[1870]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = 
@@ -12257,13 +12257,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1868]
+    (const void *)&gInstructions[1869]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1870]
+    (const void *)&gInstructions[1871]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = 
@@ -12300,13 +12300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1872]
+    (const void *)&gInstructions[1873]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1874]
+    (const void *)&gInstructions[1875]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = 
@@ -12332,13 +12332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1873]
+    (const void *)&gInstructions[1874]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1875]
+    (const void *)&gInstructions[1876]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = 
@@ -12375,7 +12375,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1876]
+    (const void *)&gInstructions[1877]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = 
@@ -12392,7 +12392,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1877]
+    (const void *)&gInstructions[1878]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = 
@@ -12429,7 +12429,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2082]
+    (const void *)&gInstructions[2083]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = 
@@ -12446,7 +12446,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2115]
+    (const void *)&gInstructions[2116]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = 
@@ -12463,13 +12463,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2119]
+    (const void *)&gInstructions[2120]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2146]
+    (const void *)&gInstructions[2147]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = 
@@ -12495,13 +12495,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2120]
+    (const void *)&gInstructions[2121]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2141]
+    (const void *)&gInstructions[2142]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = 
@@ -12527,13 +12527,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2142]
+    (const void *)&gInstructions[2143]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2145]
+    (const void *)&gInstructions[2146]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = 
@@ -12559,13 +12559,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2143]
+    (const void *)&gInstructions[2144]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2144]
+    (const void *)&gInstructions[2145]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = 
@@ -12591,7 +12591,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2191]
+    (const void *)&gInstructions[2198]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = 
@@ -12617,7 +12617,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2195]
+    (const void *)&gInstructions[2202]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = 
@@ -12643,7 +12643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2200]
+    (const void *)&gInstructions[2207]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = 
@@ -12669,7 +12669,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2206]
+    (const void *)&gInstructions[2213]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = 
@@ -12695,7 +12695,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2219]
+    (const void *)&gInstructions[2226]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = 
@@ -12712,7 +12712,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2220]
+    (const void *)&gInstructions[2227]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = 
@@ -12749,13 +12749,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2223]
+    (const void *)&gInstructions[2230]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2227]
+    (const void *)&gInstructions[2234]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_16_01_mem_00_wi = 
@@ -12781,13 +12781,13 @@ const ND_TABLE_VEX_L gEvexTable_root_03_16_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2224]
+    (const void *)&gInstructions[2231]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2228]
+    (const void *)&gInstructions[2235]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_16_01_reg_00_wi = 
@@ -12833,7 +12833,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2232]
+    (const void *)&gInstructions[2239]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = 
@@ -12850,7 +12850,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2233]
+    (const void *)&gInstructions[2240]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = 
@@ -12887,7 +12887,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2267]
+    (const void *)&gInstructions[2274]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = 
@@ -12904,7 +12904,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2268]
+    (const void *)&gInstructions[2275]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = 
@@ -12941,13 +12941,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2271]
+    (const void *)&gInstructions[2278]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2273]
+    (const void *)&gInstructions[2280]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_wi = 
@@ -12984,13 +12984,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2460]
+    (const void *)&gInstructions[2467]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2461]
+    (const void *)&gInstructions[2468]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = 
@@ -13016,7 +13016,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2465]
+    (const void *)&gInstructions[2472]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = 
@@ -13042,13 +13042,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2469]
+    (const void *)&gInstructions[2476]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2470]
+    (const void *)&gInstructions[2477]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = 
@@ -13074,7 +13074,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2474]
+    (const void *)&gInstructions[2481]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = 
@@ -13100,13 +13100,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2555]
+    (const void *)&gInstructions[2562]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2556]
+    (const void *)&gInstructions[2563]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = 
@@ -13132,13 +13132,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2585]
+    (const void *)&gInstructions[2592]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2586]
+    (const void *)&gInstructions[2593]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = 
@@ -13164,13 +13164,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2587]
+    (const void *)&gInstructions[2594]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2588]
+    (const void *)&gInstructions[2595]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = 
@@ -13196,13 +13196,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2601]
+    (const void *)&gInstructions[2608]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2603]
+    (const void *)&gInstructions[2610]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = 
@@ -13217,7 +13217,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2602]
+    (const void *)&gInstructions[2609]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_56_00_w = 
@@ -13243,13 +13243,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2604]
+    (const void *)&gInstructions[2611]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2606]
+    (const void *)&gInstructions[2613]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = 
@@ -13264,7 +13264,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2605]
+    (const void *)&gInstructions[2612]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_57_00_w = 
@@ -13290,7 +13290,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2607]
+    (const void *)&gInstructions[2614]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = 
@@ -13316,7 +13316,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2608]
+    (const void *)&gInstructions[2615]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w = 
@@ -13331,7 +13331,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2609]
+    (const void *)&gInstructions[2616]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = 
@@ -13357,7 +13357,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2610]
+    (const void *)&gInstructions[2617]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = 
@@ -13383,7 +13383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2611]
+    (const void *)&gInstructions[2618]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w = 
@@ -13398,7 +13398,7 @@ const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2612]
+    (const void *)&gInstructions[2619]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = 
@@ -13424,13 +13424,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2647]
+    (const void *)&gInstructions[2657]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2648]
+    (const void *)&gInstructions[2658]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = 
@@ -13456,13 +13456,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2649]
+    (const void *)&gInstructions[2659]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2650]
+    (const void *)&gInstructions[2660]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = 
@@ -13751,7 +13751,7 @@ const ND_TABLE_OPCODE gEvexTable_root_03_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1503]
+    (const void *)&gInstructions[1504]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w = 
@@ -13766,7 +13766,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1532]
+    (const void *)&gInstructions[1533]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_13_00_w = 
@@ -13792,7 +13792,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1616]
+    (const void *)&gInstructions[1617]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w = 
@@ -13807,7 +13807,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1654]
+    (const void *)&gInstructions[1655]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_56_02_w = 
@@ -13833,7 +13833,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1617]
+    (const void *)&gInstructions[1618]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w = 
@@ -13848,7 +13848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1655]
+    (const void *)&gInstructions[1656]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_57_02_w = 
@@ -13874,7 +13874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_57_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1618]
+    (const void *)&gInstructions[1619]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w = 
@@ -13889,7 +13889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1740]
+    (const void *)&gInstructions[1741]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_d6_02_w = 
@@ -13915,7 +13915,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1619]
+    (const void *)&gInstructions[1620]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w = 
@@ -13930,7 +13930,7 @@ const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1741]
+    (const void *)&gInstructions[1742]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_d7_02_w = 
@@ -13956,7 +13956,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_d7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1626]
+    (const void *)&gInstructions[1627]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_98_01_w = 
@@ -13982,7 +13982,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_98_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1631]
+    (const void *)&gInstructions[1632]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_99_01_w = 
@@ -14008,7 +14008,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_99_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1636]
+    (const void *)&gInstructions[1637]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_a8_01_w = 
@@ -14034,7 +14034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1641]
+    (const void *)&gInstructions[1642]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_a9_01_w = 
@@ -14060,7 +14060,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1646]
+    (const void *)&gInstructions[1647]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_b8_01_w = 
@@ -14086,7 +14086,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1651]
+    (const void *)&gInstructions[1652]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_b9_01_w = 
@@ -14112,7 +14112,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1666]
+    (const void *)&gInstructions[1667]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_96_01_w = 
@@ -14138,7 +14138,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_96_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1671]
+    (const void *)&gInstructions[1672]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_a6_01_w = 
@@ -14164,7 +14164,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1676]
+    (const void *)&gInstructions[1677]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_b6_01_w = 
@@ -14190,7 +14190,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1685]
+    (const void *)&gInstructions[1686]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_9a_01_w = 
@@ -14216,7 +14216,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1690]
+    (const void *)&gInstructions[1691]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_9b_01_w = 
@@ -14242,7 +14242,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1695]
+    (const void *)&gInstructions[1696]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_aa_01_w = 
@@ -14268,7 +14268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_aa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1700]
+    (const void *)&gInstructions[1701]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_ab_01_w = 
@@ -14294,7 +14294,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ab_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1705]
+    (const void *)&gInstructions[1706]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_ba_01_w = 
@@ -14320,7 +14320,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ba_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1710]
+    (const void *)&gInstructions[1711]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_bb_01_w = 
@@ -14346,7 +14346,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1715]
+    (const void *)&gInstructions[1716]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_97_01_w = 
@@ -14372,7 +14372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_97_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1720]
+    (const void *)&gInstructions[1721]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_a7_01_w = 
@@ -14398,7 +14398,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_a7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1725]
+    (const void *)&gInstructions[1726]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_b7_01_w = 
@@ -14424,7 +14424,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_b7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1744]
+    (const void *)&gInstructions[1745]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_9c_01_w = 
@@ -14450,7 +14450,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1749]
+    (const void *)&gInstructions[1750]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_9d_01_w = 
@@ -14476,7 +14476,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1754]
+    (const void *)&gInstructions[1755]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_ac_01_w = 
@@ -14502,7 +14502,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ac_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1759]
+    (const void *)&gInstructions[1760]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_ad_01_w = 
@@ -14528,7 +14528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ad_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1764]
+    (const void *)&gInstructions[1765]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_bc_01_w = 
@@ -14554,7 +14554,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1769]
+    (const void *)&gInstructions[1770]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_bd_01_w = 
@@ -14580,7 +14580,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1782]
+    (const void *)&gInstructions[1783]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_9e_01_w = 
@@ -14606,7 +14606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1787]
+    (const void *)&gInstructions[1788]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_9f_01_w = 
@@ -14632,7 +14632,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_9f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1792]
+    (const void *)&gInstructions[1793]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_ae_01_w = 
@@ -14658,7 +14658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_ae_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1797]
+    (const void *)&gInstructions[1798]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_af_01_w = 
@@ -14684,7 +14684,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_af_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1802]
+    (const void *)&gInstructions[1803]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_be_01_w = 
@@ -14710,7 +14710,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_be_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1807]
+    (const void *)&gInstructions[1808]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_bf_01_w = 
@@ -14736,7 +14736,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_bf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1845]
+    (const void *)&gInstructions[1846]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_42_01_w = 
@@ -14762,7 +14762,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1848]
+    (const void *)&gInstructions[1849]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_43_01_w = 
@@ -14788,7 +14788,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_43_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2597]
+    (const void *)&gInstructions[2604]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_4c_01_w = 
@@ -14814,7 +14814,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_4d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2599]
+    (const void *)&gInstructions[2606]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_4d_01_w = 
@@ -14840,7 +14840,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_4e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2625]
+    (const void *)&gInstructions[2632]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_4e_01_w = 
@@ -14866,7 +14866,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_4f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2627]
+    (const void *)&gInstructions[2634]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_4f_01_w = 
@@ -14892,7 +14892,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_4f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_2c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2630]
+    (const void *)&gInstructions[2637]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_2c_01_w = 
@@ -14918,7 +14918,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_06_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_06_2d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2633]
+    (const void *)&gInstructions[2640]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_06_2d_01_w = 
diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h
index 395422d..2043b28 100644
--- a/bddisasm/include/table_root.h
+++ b/bddisasm/include/table_root.h
@@ -81,13 +81,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2707]
+    (const void *)&gInstructions[2722]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2708]
+    (const void *)&gInstructions[2723]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = 
@@ -1014,7 +1014,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[894]
+    (const void *)&gInstructions[895]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = 
@@ -1031,7 +1031,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[903]
+    (const void *)&gInstructions[904]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = 
@@ -1048,13 +1048,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[942]
+    (const void *)&gInstructions[943]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[943]
+    (const void *)&gInstructions[944]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = 
@@ -1071,13 +1071,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[944]
+    (const void *)&gInstructions[945]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[945]
+    (const void *)&gInstructions[946]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = 
@@ -1094,13 +1094,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[946]
+    (const void *)&gInstructions[947]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[947]
+    (const void *)&gInstructions[948]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = 
@@ -1117,7 +1117,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[948]
+    (const void *)&gInstructions[949]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = 
@@ -1134,13 +1134,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[949]
+    (const void *)&gInstructions[950]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[950]
+    (const void *)&gInstructions[951]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = 
@@ -1157,13 +1157,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[951]
+    (const void *)&gInstructions[952]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[952]
+    (const void *)&gInstructions[953]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = 
@@ -1180,13 +1180,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[953]
+    (const void *)&gInstructions[954]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[954]
+    (const void *)&gInstructions[955]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = 
@@ -1203,13 +1203,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[965]
+    (const void *)&gInstructions[966]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[966]
+    (const void *)&gInstructions[967]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = 
@@ -1226,7 +1226,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[969]
+    (const void *)&gInstructions[970]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = 
@@ -1243,7 +1243,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[970]
+    (const void *)&gInstructions[971]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = 
@@ -1260,7 +1260,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[975]
+    (const void *)&gInstructions[976]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = 
@@ -1277,7 +1277,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[976]
+    (const void *)&gInstructions[977]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = 
@@ -1294,7 +1294,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[977]
+    (const void *)&gInstructions[978]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = 
@@ -1311,7 +1311,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[978]
+    (const void *)&gInstructions[979]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = 
@@ -1328,7 +1328,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[983]
+    (const void *)&gInstructions[984]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = 
@@ -1345,7 +1345,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[984]
+    (const void *)&gInstructions[985]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = 
@@ -1362,7 +1362,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[987]
+    (const void *)&gInstructions[988]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = 
@@ -1379,7 +1379,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[988]
+    (const void *)&gInstructions[989]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = 
@@ -1396,7 +1396,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[989]
+    (const void *)&gInstructions[990]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = 
@@ -1413,7 +1413,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[990]
+    (const void *)&gInstructions[991]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = 
@@ -1430,7 +1430,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[991]
+    (const void *)&gInstructions[992]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = 
@@ -1447,7 +1447,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[992]
+    (const void *)&gInstructions[993]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = 
@@ -1464,7 +1464,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[993]
+    (const void *)&gInstructions[994]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = 
@@ -1481,7 +1481,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[994]
+    (const void *)&gInstructions[995]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = 
@@ -1498,7 +1498,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[995]
+    (const void *)&gInstructions[996]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = 
@@ -1515,7 +1515,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[996]
+    (const void *)&gInstructions[997]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = 
@@ -1532,7 +1532,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[997]
+    (const void *)&gInstructions[998]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = 
@@ -1549,7 +1549,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[998]
+    (const void *)&gInstructions[999]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = 
@@ -1566,7 +1566,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[999]
+    (const void *)&gInstructions[1000]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = 
@@ -1583,13 +1583,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1000]
+    (const void *)&gInstructions[1001]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1001]
+    (const void *)&gInstructions[1002]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = 
@@ -1606,7 +1606,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1007]
+    (const void *)&gInstructions[1008]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = 
@@ -1623,13 +1623,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1054]
+    (const void *)&gInstructions[1055]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1055]
+    (const void *)&gInstructions[1056]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = 
@@ -1646,13 +1646,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1060]
+    (const void *)&gInstructions[1061]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1061]
+    (const void *)&gInstructions[1062]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = 
@@ -1669,13 +1669,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1062]
+    (const void *)&gInstructions[1063]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1063]
+    (const void *)&gInstructions[1064]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = 
@@ -1692,13 +1692,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1064]
+    (const void *)&gInstructions[1065]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1065]
+    (const void *)&gInstructions[1066]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = 
@@ -1715,7 +1715,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1118]
+    (const void *)&gInstructions[1119]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = 
@@ -1732,7 +1732,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1279]
+    (const void *)&gInstructions[1280]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = 
@@ -1749,7 +1749,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1280]
+    (const void *)&gInstructions[1281]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = 
@@ -1766,7 +1766,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1281]
+    (const void *)&gInstructions[1282]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = 
@@ -1783,7 +1783,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1283]
+    (const void *)&gInstructions[1284]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = 
@@ -1800,7 +1800,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1284]
+    (const void *)&gInstructions[1285]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = 
@@ -1817,7 +1817,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1285]
+    (const void *)&gInstructions[1286]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = 
@@ -1834,13 +1834,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2709]
+    (const void *)&gInstructions[2724]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2710]
+    (const void *)&gInstructions[2725]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = 
@@ -2494,7 +2494,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[889]
+    (const void *)&gInstructions[890]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = 
@@ -2511,7 +2511,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[897]
+    (const void *)&gInstructions[898]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = 
@@ -2528,7 +2528,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[898]
+    (const void *)&gInstructions[899]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = 
@@ -2545,7 +2545,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[906]
+    (const void *)&gInstructions[907]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = 
@@ -2562,7 +2562,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[907]
+    (const void *)&gInstructions[908]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = 
@@ -2579,7 +2579,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[911]
+    (const void *)&gInstructions[912]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = 
@@ -2596,7 +2596,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[912]
+    (const void *)&gInstructions[913]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = 
@@ -2622,13 +2622,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_mem_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[913]
+    (const void *)&gInstructions[914]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_mem_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[915]
+    (const void *)&gInstructions[916]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_mem_66_auxiliary = 
@@ -2660,13 +2660,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_reg_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[914]
+    (const void *)&gInstructions[915]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_reg_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[916]
+    (const void *)&gInstructions[917]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_reg_66_auxiliary = 
@@ -2707,7 +2707,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_16_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[919]
+    (const void *)&gInstructions[920]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = 
@@ -2724,7 +2724,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[920]
+    (const void *)&gInstructions[921]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = 
@@ -2750,7 +2750,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[957]
+    (const void *)&gInstructions[958]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = 
@@ -2767,7 +2767,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[958]
+    (const void *)&gInstructions[959]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = 
@@ -2793,13 +2793,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[959]
+    (const void *)&gInstructions[960]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[960]
+    (const void *)&gInstructions[961]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = 
@@ -2831,7 +2831,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1210]
+    (const void *)&gInstructions[1211]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = 
@@ -2848,7 +2848,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1211]
+    (const void *)&gInstructions[1212]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = 
@@ -2865,7 +2865,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1212]
+    (const void *)&gInstructions[1213]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = 
@@ -2882,7 +2882,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1213]
+    (const void *)&gInstructions[1214]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = 
@@ -2899,7 +2899,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1282]
+    (const void *)&gInstructions[1283]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = 
@@ -3437,7 +3437,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1385]
+    (const void *)&gInstructions[1386]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = 
@@ -3631,7 +3631,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1255]
+    (const void *)&gInstructions[1256]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = 
@@ -3682,7 +3682,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1256]
+    (const void *)&gInstructions[1257]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = 
@@ -3699,7 +3699,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1257]
+    (const void *)&gInstructions[1258]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = 
@@ -3716,7 +3716,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1319]
+    (const void *)&gInstructions[1320]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = 
@@ -3733,7 +3733,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1362]
+    (const void *)&gInstructions[1363]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = 
@@ -3777,37 +3777,37 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1307]
+    (const void *)&gInstructions[1308]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1322]
+    (const void *)&gInstructions[1323]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1900]
+    (const void *)&gInstructions[1901]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1901]
+    (const void *)&gInstructions[1902]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1914]
+    (const void *)&gInstructions[1915]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1915]
+    (const void *)&gInstructions[1916]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = 
@@ -3824,19 +3824,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1913]
+    (const void *)&gInstructions[1914]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2028]
+    (const void *)&gInstructions[2029]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2029]
+    (const void *)&gInstructions[2030]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = 
@@ -3863,7 +3863,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1178]
+    (const void *)&gInstructions[1179]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = 
@@ -3880,7 +3880,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1236]
+    (const void *)&gInstructions[1237]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = 
@@ -3897,19 +3897,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1259]
+    (const void *)&gInstructions[1260]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1275]
+    (const void *)&gInstructions[1276]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2763]
+    (const void *)&gInstructions[2778]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = 
@@ -3926,13 +3926,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1336]
+    (const void *)&gInstructions[1337]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2705]
+    (const void *)&gInstructions[2720]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = 
@@ -3949,7 +3949,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1377]
+    (const void *)&gInstructions[1378]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = 
@@ -3966,7 +3966,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1392]
+    (const void *)&gInstructions[1393]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = 
@@ -3983,7 +3983,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2745]
+    (const void *)&gInstructions[2760]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = 
@@ -4027,13 +4027,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1194]
+    (const void *)&gInstructions[1195]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1196]
+    (const void *)&gInstructions[1197]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = 
@@ -4090,19 +4090,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1079]
+    (const void *)&gInstructions[1080]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1156]
+    (const void *)&gInstructions[1157]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1383]
+    (const void *)&gInstructions[1384]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = 
@@ -4119,13 +4119,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1180]
+    (const void *)&gInstructions[1181]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1195]
+    (const void *)&gInstructions[1196]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_05_mprefix = 
@@ -4142,13 +4142,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1189]
+    (const void *)&gInstructions[1190]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1354]
+    (const void *)&gInstructions[1355]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = 
@@ -4186,7 +4186,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1899]
+    (const void *)&gInstructions[1900]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = 
@@ -4203,7 +4203,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2730]
+    (const void *)&gInstructions[2745]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = 
@@ -4220,7 +4220,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2731]
+    (const void *)&gInstructions[2746]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = 
@@ -4237,7 +4237,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2758]
+    (const void *)&gInstructions[2773]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = 
@@ -4254,7 +4254,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2764]
+    (const void *)&gInstructions[2779]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = 
@@ -4300,10 +4300,27 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix =
     }
 };
 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_07_NP_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[889]
+};
+
+const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_07_mprefix = 
+{
+    ND_ILUT_MAN_PREFIX,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_07_NP_leaf,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[908]
+    (const void *)&gInstructions[909]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = 
@@ -4320,19 +4337,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1176]
+    (const void *)&gInstructions[1177]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2703]
+    (const void *)&gInstructions[2718]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2704]
+    (const void *)&gInstructions[2719]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix = 
@@ -4349,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1897]
+    (const void *)&gInstructions[1898]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix = 
@@ -4366,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1912]
+    (const void *)&gInstructions[1913]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix = 
@@ -4383,7 +4400,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2027]
+    (const void *)&gInstructions[2028]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix = 
@@ -4400,7 +4417,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2041]
+    (const void *)&gInstructions[2042]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix = 
@@ -4425,7 +4442,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm =
         /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_mprefix,
         /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix,
         /* 06 */ (const void *)&gRootTable_root_0f_01_reg_00_06_mprefix,
-        /* 07 */ ND_NULL,
+        /* 07 */ (const void *)&gRootTable_root_0f_01_reg_00_07_mprefix,
     }
 };
 
@@ -4438,7 +4455,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1313]
+    (const void *)&gInstructions[1314]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = 
@@ -4483,7 +4500,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1219]
+    (const void *)&gInstructions[1220]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = 
@@ -4500,19 +4517,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1278]
+    (const void *)&gInstructions[1279]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1306]
+    (const void *)&gInstructions[1307]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1312]
+    (const void *)&gInstructions[1313]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = 
@@ -4762,13 +4779,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2754]
+    (const void *)&gInstructions[2769]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2755]
+    (const void *)&gInstructions[2770]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = 
@@ -4893,19 +4910,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1119]
+    (const void *)&gInstructions[1120]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2750]
+    (const void *)&gInstructions[2765]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2751]
+    (const void *)&gInstructions[2766]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = 
@@ -4937,7 +4954,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1324]
+    (const void *)&gInstructions[1325]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = 
@@ -4954,13 +4971,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2746]
+    (const void *)&gInstructions[2761]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2747]
+    (const void *)&gInstructions[2762]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = 
@@ -5057,19 +5074,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1384]
+    (const void *)&gInstructions[1385]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1393]
+    (const void *)&gInstructions[1394]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1394]
+    (const void *)&gInstructions[1395]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = 
@@ -5086,7 +5103,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1119]
+    (const void *)&gInstructions[1120]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = 
@@ -5103,7 +5120,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1173]
+    (const void *)&gInstructions[1174]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = 
@@ -5135,7 +5152,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1174]
+    (const void *)&gInstructions[1175]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = 
@@ -5167,7 +5184,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1277]
+    (const void *)&gInstructions[1278]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = 
@@ -5184,7 +5201,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2700]
+    (const void *)&gInstructions[2715]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = 
@@ -5216,7 +5233,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2701]
+    (const void *)&gInstructions[2716]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = 
@@ -5448,19 +5465,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1898]
+    (const void *)&gInstructions[1899]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2024]
+    (const void *)&gInstructions[2025]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2042]
+    (const void *)&gInstructions[2043]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = 
@@ -5477,7 +5494,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2025]
+    (const void *)&gInstructions[2026]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = 
@@ -5494,13 +5511,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2748]
+    (const void *)&gInstructions[2763]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2749]
+    (const void *)&gInstructions[2764]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = 
@@ -5532,13 +5549,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2752]
+    (const void *)&gInstructions[2767]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2753]
+    (const void *)&gInstructions[2768]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = 
@@ -5570,13 +5587,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2756]
+    (const void *)&gInstructions[2771]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2757]
+    (const void *)&gInstructions[2772]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = 
@@ -5623,19 +5640,19 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1177]
+    (const void *)&gInstructions[1178]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1183]
+    (const void *)&gInstructions[1184]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1184]
+    (const void *)&gInstructions[1185]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = 
@@ -5652,19 +5669,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1181]
+    (const void *)&gInstructions[1182]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1182]
+    (const void *)&gInstructions[1183]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1258]
+    (const void *)&gInstructions[1259]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = 
@@ -6125,7 +6142,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1187]
+    (const void *)&gInstructions[1188]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = 
@@ -6146,7 +6163,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1186]
+    (const void *)&gInstructions[1187]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = 
@@ -6275,7 +6292,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2026]
+    (const void *)&gInstructions[2027]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = 
@@ -6292,7 +6309,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1351]
+    (const void *)&gInstructions[1352]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = 
@@ -6332,7 +6349,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2040]
+    (const void *)&gInstructions[2041]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = 
@@ -6349,7 +6366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2040]
+    (const void *)&gInstructions[2041]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = 
@@ -6375,7 +6392,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1214]
+    (const void *)&gInstructions[1215]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = 
@@ -6426,7 +6443,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2706]
+    (const void *)&gInstructions[2721]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = 
@@ -6468,7 +6485,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1353]
+    (const void *)&gInstructions[1354]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = 
@@ -6519,7 +6536,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1220]
+    (const void *)&gInstructions[1221]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = 
@@ -6618,25 +6635,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1308]
+    (const void *)&gInstructions[1309]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1333]
+    (const void *)&gInstructions[1334]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1596]
+    (const void *)&gInstructions[1597]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1597]
+    (const void *)&gInstructions[1598]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = 
@@ -6692,25 +6709,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1309]
+    (const void *)&gInstructions[1310]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1334]
+    (const void *)&gInstructions[1335]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1596]
+    (const void *)&gInstructions[1597]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1597]
+    (const void *)&gInstructions[1598]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = 
@@ -6746,7 +6763,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1028]
+    (const void *)&gInstructions[1029]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = 
@@ -7086,7 +7103,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2759]
+    (const void *)&gInstructions[2774]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = 
@@ -7118,7 +7135,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2760]
+    (const void *)&gInstructions[2775]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = 
@@ -7392,7 +7409,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1311]
+    (const void *)&gInstructions[1312]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = 
@@ -8048,49 +8065,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1034]
+    (const void *)&gInstructions[1035]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1035]
+    (const void *)&gInstructions[1036]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1036]
+    (const void *)&gInstructions[1037]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1037]
+    (const void *)&gInstructions[1038]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1038]
+    (const void *)&gInstructions[1039]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1041]
+    (const void *)&gInstructions[1042]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1050]
+    (const void *)&gInstructions[1051]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1051]
+    (const void *)&gInstructions[1052]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = 
@@ -8207,25 +8224,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1042]
+    (const void *)&gInstructions[1043]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1044]
+    (const void *)&gInstructions[1045]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1046]
+    (const void *)&gInstructions[1047]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1048]
+    (const void *)&gInstructions[1049]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_None_mem_modrmreg = 
@@ -8336,7 +8353,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_06_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_06_riprel_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1040]
+    (const void *)&gInstructions[1041]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_06_auxiliary = 
@@ -8363,7 +8380,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_07_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_07_riprel_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1039]
+    (const void *)&gInstructions[1040]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_07_auxiliary = 
@@ -8384,25 +8401,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_07_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1043]
+    (const void *)&gInstructions[1044]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1045]
+    (const void *)&gInstructions[1046]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1047]
+    (const void *)&gInstructions[1048]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1049]
+    (const void *)&gInstructions[1050]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_piti_mem_modrmreg = 
@@ -8816,151 +8833,151 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[921]
+    (const void *)&gInstructions[922]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[922]
+    (const void *)&gInstructions[923]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[923]
+    (const void *)&gInstructions[924]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[924]
+    (const void *)&gInstructions[925]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[925]
+    (const void *)&gInstructions[926]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[926]
+    (const void *)&gInstructions[927]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[927]
+    (const void *)&gInstructions[928]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[928]
+    (const void *)&gInstructions[929]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[929]
+    (const void *)&gInstructions[930]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[930]
+    (const void *)&gInstructions[931]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[931]
+    (const void *)&gInstructions[932]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[932]
+    (const void *)&gInstructions[933]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[933]
+    (const void *)&gInstructions[934]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[934]
+    (const void *)&gInstructions[935]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[935]
+    (const void *)&gInstructions[936]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[936]
+    (const void *)&gInstructions[937]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[937]
+    (const void *)&gInstructions[938]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[938]
+    (const void *)&gInstructions[939]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[939]
+    (const void *)&gInstructions[940]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[940]
+    (const void *)&gInstructions[941]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[941]
+    (const void *)&gInstructions[942]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[955]
+    (const void *)&gInstructions[956]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[956]
+    (const void *)&gInstructions[957]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1002]
+    (const void *)&gInstructions[1003]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1117]
+    (const void *)&gInstructions[1118]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = 
@@ -9252,13 +9269,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[890]
+    (const void *)&gInstructions[891]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[891]
+    (const void *)&gInstructions[892]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = 
@@ -9275,13 +9292,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[892]
+    (const void *)&gInstructions[893]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[893]
+    (const void *)&gInstructions[894]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = 
@@ -9298,13 +9315,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[895]
+    (const void *)&gInstructions[896]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[896]
+    (const void *)&gInstructions[897]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = 
@@ -9321,13 +9338,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[899]
+    (const void *)&gInstructions[900]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[900]
+    (const void *)&gInstructions[901]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = 
@@ -9344,13 +9361,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[901]
+    (const void *)&gInstructions[902]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[902]
+    (const void *)&gInstructions[903]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = 
@@ -9367,13 +9384,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[904]
+    (const void *)&gInstructions[905]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[905]
+    (const void *)&gInstructions[906]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = 
@@ -9390,13 +9407,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[917]
+    (const void *)&gInstructions[918]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[918]
+    (const void *)&gInstructions[919]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = 
@@ -9422,13 +9439,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[961]
+    (const void *)&gInstructions[962]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[963]
+    (const void *)&gInstructions[964]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = 
@@ -9445,13 +9462,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[962]
+    (const void *)&gInstructions[963]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[964]
+    (const void *)&gInstructions[965]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = 
@@ -9477,13 +9494,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[967]
+    (const void *)&gInstructions[968]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[968]
+    (const void *)&gInstructions[969]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = 
@@ -9500,13 +9517,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[971]
+    (const void *)&gInstructions[972]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[972]
+    (const void *)&gInstructions[973]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = 
@@ -9523,13 +9540,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[973]
+    (const void *)&gInstructions[974]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[974]
+    (const void *)&gInstructions[975]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = 
@@ -9546,13 +9563,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[979]
+    (const void *)&gInstructions[980]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[980]
+    (const void *)&gInstructions[981]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = 
@@ -9569,13 +9586,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[981]
+    (const void *)&gInstructions[982]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[982]
+    (const void *)&gInstructions[983]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = 
@@ -9592,13 +9609,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[985]
+    (const void *)&gInstructions[986]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[986]
+    (const void *)&gInstructions[987]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = 
@@ -9624,13 +9641,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1003]
+    (const void *)&gInstructions[1004]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1004]
+    (const void *)&gInstructions[1005]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = 
@@ -9647,13 +9664,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1005]
+    (const void *)&gInstructions[1006]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1006]
+    (const void *)&gInstructions[1007]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = 
@@ -9670,13 +9687,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1008]
+    (const void *)&gInstructions[1009]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1009]
+    (const void *)&gInstructions[1010]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = 
@@ -9693,13 +9710,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1010]
+    (const void *)&gInstructions[1011]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1011]
+    (const void *)&gInstructions[1012]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = 
@@ -9716,25 +9733,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1012]
+    (const void *)&gInstructions[1013]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1013]
+    (const void *)&gInstructions[1014]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1032]
+    (const void *)&gInstructions[1033]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1033]
+    (const void *)&gInstructions[1034]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = 
@@ -9751,13 +9768,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1052]
+    (const void *)&gInstructions[1053]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1053]
+    (const void *)&gInstructions[1054]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = 
@@ -9774,25 +9791,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1056]
+    (const void *)&gInstructions[1057]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1057]
+    (const void *)&gInstructions[1058]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1058]
+    (const void *)&gInstructions[1059]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1059]
+    (const void *)&gInstructions[1060]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = 
@@ -9809,13 +9826,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1066]
+    (const void *)&gInstructions[1067]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1067]
+    (const void *)&gInstructions[1068]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = 
@@ -9832,13 +9849,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1080]
+    (const void *)&gInstructions[1081]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1081]
+    (const void *)&gInstructions[1082]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = 
@@ -9855,13 +9872,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1088]
+    (const void *)&gInstructions[1089]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1089]
+    (const void *)&gInstructions[1090]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = 
@@ -9902,13 +9919,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1068]
+    (const void *)&gInstructions[1069]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1069]
+    (const void *)&gInstructions[1070]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = 
@@ -9925,7 +9942,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1070]
+    (const void *)&gInstructions[1071]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = 
@@ -9942,13 +9959,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1071]
+    (const void *)&gInstructions[1072]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1072]
+    (const void *)&gInstructions[1073]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = 
@@ -9965,7 +9982,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1092]
+    (const void *)&gInstructions[1093]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = 
@@ -9982,13 +9999,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1093]
+    (const void *)&gInstructions[1094]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1094]
+    (const void *)&gInstructions[1095]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = 
@@ -10029,13 +10046,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1073]
+    (const void *)&gInstructions[1074]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1074]
+    (const void *)&gInstructions[1075]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = 
@@ -10052,13 +10069,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1075]
+    (const void *)&gInstructions[1076]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1076]
+    (const void *)&gInstructions[1077]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = 
@@ -10075,13 +10092,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1084]
+    (const void *)&gInstructions[1085]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1085]
+    (const void *)&gInstructions[1086]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = 
@@ -10098,13 +10115,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1097]
+    (const void *)&gInstructions[1098]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1098]
+    (const void *)&gInstructions[1099]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = 
@@ -10145,13 +10162,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1077]
+    (const void *)&gInstructions[1078]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1078]
+    (const void *)&gInstructions[1079]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = 
@@ -10168,13 +10185,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1082]
+    (const void *)&gInstructions[1083]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1083]
+    (const void *)&gInstructions[1084]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = 
@@ -10191,13 +10208,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1086]
+    (const void *)&gInstructions[1087]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1087]
+    (const void *)&gInstructions[1088]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = 
@@ -10214,13 +10231,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1090]
+    (const void *)&gInstructions[1091]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1091]
+    (const void *)&gInstructions[1092]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = 
@@ -10237,13 +10254,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1095]
+    (const void *)&gInstructions[1096]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1096]
+    (const void *)&gInstructions[1097]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = 
@@ -10260,13 +10277,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1099]
+    (const void *)&gInstructions[1100]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1100]
+    (const void *)&gInstructions[1101]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = 
@@ -10283,13 +10300,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1101]
+    (const void *)&gInstructions[1102]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1102]
+    (const void *)&gInstructions[1103]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = 
@@ -10306,13 +10323,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1103]
+    (const void *)&gInstructions[1104]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1104]
+    (const void *)&gInstructions[1105]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = 
@@ -10329,13 +10346,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1105]
+    (const void *)&gInstructions[1106]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1106]
+    (const void *)&gInstructions[1107]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = 
@@ -10352,13 +10369,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1107]
+    (const void *)&gInstructions[1108]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1108]
+    (const void *)&gInstructions[1109]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = 
@@ -10375,13 +10392,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1109]
+    (const void *)&gInstructions[1110]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1110]
+    (const void *)&gInstructions[1111]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = 
@@ -10398,13 +10415,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1111]
+    (const void *)&gInstructions[1112]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1112]
+    (const void *)&gInstructions[1113]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = 
@@ -10421,13 +10438,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1113]
+    (const void *)&gInstructions[1114]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1114]
+    (const void *)&gInstructions[1115]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = 
@@ -10444,13 +10461,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1115]
+    (const void *)&gInstructions[1116]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1116]
+    (const void *)&gInstructions[1117]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = 
@@ -10467,13 +10484,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1120]
+    (const void *)&gInstructions[1121]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1121]
+    (const void *)&gInstructions[1122]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = 
@@ -10490,13 +10507,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1122]
+    (const void *)&gInstructions[1123]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1123]
+    (const void *)&gInstructions[1124]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = 
@@ -10513,7 +10530,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1124]
+    (const void *)&gInstructions[1125]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = 
@@ -10530,13 +10547,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1125]
+    (const void *)&gInstructions[1126]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1126]
+    (const void *)&gInstructions[1127]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = 
@@ -10553,13 +10570,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1127]
+    (const void *)&gInstructions[1128]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1128]
+    (const void *)&gInstructions[1129]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = 
@@ -10576,13 +10593,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1129]
+    (const void *)&gInstructions[1130]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1130]
+    (const void *)&gInstructions[1131]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = 
@@ -10599,7 +10616,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1131]
+    (const void *)&gInstructions[1132]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = 
@@ -10616,13 +10633,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1132]
+    (const void *)&gInstructions[1133]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1133]
+    (const void *)&gInstructions[1134]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = 
@@ -10639,25 +10656,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1134]
+    (const void *)&gInstructions[1135]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1135]
+    (const void *)&gInstructions[1136]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1157]
+    (const void *)&gInstructions[1158]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1158]
+    (const void *)&gInstructions[1159]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = 
@@ -10674,13 +10691,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1165]
+    (const void *)&gInstructions[1166]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1166]
+    (const void *)&gInstructions[1167]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = 
@@ -10697,19 +10714,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1175]
+    (const void *)&gInstructions[1176]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1179]
+    (const void *)&gInstructions[1180]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1185]
+    (const void *)&gInstructions[1186]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = 
@@ -10728,13 +10745,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1188]
+    (const void *)&gInstructions[1189]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1215]
+    (const void *)&gInstructions[1216]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = 
@@ -10762,19 +10779,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1216]
+    (const void *)&gInstructions[1217]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1217]
+    (const void *)&gInstructions[1218]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1218]
+    (const void *)&gInstructions[1219]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = 
@@ -10791,133 +10808,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1260]
+    (const void *)&gInstructions[1261]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1261]
+    (const void *)&gInstructions[1262]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1262]
+    (const void *)&gInstructions[1263]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1263]
+    (const void *)&gInstructions[1264]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1264]
+    (const void *)&gInstructions[1265]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1265]
+    (const void *)&gInstructions[1266]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1266]
+    (const void *)&gInstructions[1267]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1267]
+    (const void *)&gInstructions[1268]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1268]
+    (const void *)&gInstructions[1269]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1269]
+    (const void *)&gInstructions[1270]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1270]
+    (const void *)&gInstructions[1271]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1271]
+    (const void *)&gInstructions[1272]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1272]
+    (const void *)&gInstructions[1273]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1273]
+    (const void *)&gInstructions[1274]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1274]
+    (const void *)&gInstructions[1275]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1276]
+    (const void *)&gInstructions[1277]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1292]
+    (const void *)&gInstructions[1293]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1293]
+    (const void *)&gInstructions[1294]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1301]
+    (const void *)&gInstructions[1302]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1302]
+    (const void *)&gInstructions[1303]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1304]
+    (const void *)&gInstructions[1305]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1305]
+    (const void *)&gInstructions[1306]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = 
@@ -10934,25 +10951,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1315]
+    (const void *)&gInstructions[1316]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1316]
+    (const void *)&gInstructions[1317]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1317]
+    (const void *)&gInstructions[1318]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1318]
+    (const void *)&gInstructions[1319]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = 
@@ -10969,25 +10986,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1347]
+    (const void *)&gInstructions[1348]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1348]
+    (const void *)&gInstructions[1349]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1349]
+    (const void *)&gInstructions[1350]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1350]
+    (const void *)&gInstructions[1351]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = 
@@ -11004,7 +11021,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1352]
+    (const void *)&gInstructions[1353]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = 
@@ -11032,37 +11049,37 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1355]
+    (const void *)&gInstructions[1356]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1356]
+    (const void *)&gInstructions[1357]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1357]
+    (const void *)&gInstructions[1358]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1358]
+    (const void *)&gInstructions[1359]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1387]
+    (const void *)&gInstructions[1388]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1388]
+    (const void *)&gInstructions[1389]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = 
@@ -11079,31 +11096,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1389]
+    (const void *)&gInstructions[1390]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1390]
+    (const void *)&gInstructions[1391]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1391]
+    (const void *)&gInstructions[1392]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1395]
+    (const void *)&gInstructions[1396]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1396]
+    (const void *)&gInstructions[1397]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = 
@@ -11120,13 +11137,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1397]
+    (const void *)&gInstructions[1398]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1398]
+    (const void *)&gInstructions[1399]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = 
@@ -11143,13 +11160,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2698]
+    (const void *)&gInstructions[2713]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2699]
+    (const void *)&gInstructions[2714]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = 
@@ -11170,25 +11187,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2702]
+    (const void *)&gInstructions[2717]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2712]
+    (const void *)&gInstructions[2727]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2713]
+    (const void *)&gInstructions[2728]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2725]
+    (const void *)&gInstructions[2740]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = 
@@ -11220,7 +11237,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2726]
+    (const void *)&gInstructions[2741]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = 
@@ -11252,7 +11269,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2727]
+    (const void *)&gInstructions[2742]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = 
@@ -11284,7 +11301,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2728]
+    (const void *)&gInstructions[2743]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = 
@@ -11316,7 +11333,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2729]
+    (const void *)&gInstructions[2744]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = 
@@ -11348,13 +11365,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2761]
+    (const void *)&gInstructions[2776]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2762]
+    (const void *)&gInstructions[2777]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix = 
@@ -11410,13 +11427,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2743]
+    (const void *)&gInstructions[2758]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2744]
+    (const void *)&gInstructions[2759]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = 
@@ -11774,19 +11791,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1243]
+    (const void *)&gInstructions[1244]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1343]
+    (const void *)&gInstructions[1344]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2739]
+    (const void *)&gInstructions[2754]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = 
@@ -11837,19 +11854,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1244]
+    (const void *)&gInstructions[1245]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1344]
+    (const void *)&gInstructions[1345]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2740]
+    (const void *)&gInstructions[2755]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = 
@@ -11900,19 +11917,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1245]
+    (const void *)&gInstructions[1246]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1345]
+    (const void *)&gInstructions[1346]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2741]
+    (const void *)&gInstructions[2756]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = 
@@ -11963,19 +11980,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1246]
+    (const void *)&gInstructions[1247]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1346]
+    (const void *)&gInstructions[1347]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2742]
+    (const void *)&gInstructions[2757]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = 
@@ -12152,7 +12169,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1150]
+    (const void *)&gInstructions[1151]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = 
@@ -12197,7 +12214,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1150]
+    (const void *)&gInstructions[1151]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = 
@@ -12599,13 +12616,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1373]
+    (const void *)&gInstructions[1374]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1374]
+    (const void *)&gInstructions[1375]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = 
@@ -12662,13 +12679,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1375]
+    (const void *)&gInstructions[1376]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1376]
+    (const void *)&gInstructions[1377]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = 
@@ -14830,7 +14847,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2711]
+    (const void *)&gInstructions[2726]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = 
@@ -14902,7 +14919,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2714]
+    (const void *)&gInstructions[2729]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = 
@@ -15080,7 +15097,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2717]
+    (const void *)&gInstructions[2732]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = 
@@ -15255,73 +15272,73 @@ const ND_TABLE_DSIZE gRootTable_root_6f_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1014]
+    (const void *)&gInstructions[1015]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1015]
+    (const void *)&gInstructions[1016]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1016]
+    (const void *)&gInstructions[1017]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1017]
+    (const void *)&gInstructions[1018]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1018]
+    (const void *)&gInstructions[1019]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1019]
+    (const void *)&gInstructions[1020]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1020]
+    (const void *)&gInstructions[1021]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1021]
+    (const void *)&gInstructions[1022]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1022]
+    (const void *)&gInstructions[1023]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1023]
+    (const void *)&gInstructions[1024]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1024]
+    (const void *)&gInstructions[1025]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1025]
+    (const void *)&gInstructions[1026]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = 
@@ -15342,13 +15359,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1026]
+    (const void *)&gInstructions[1027]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1027]
+    (const void *)&gInstructions[1028]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_61_dsize = 
@@ -15367,19 +15384,19 @@ const ND_TABLE_DSIZE gRootTable_root_61_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1029]
+    (const void *)&gInstructions[1030]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1030]
+    (const void *)&gInstructions[1031]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1031]
+    (const void *)&gInstructions[1032]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9d_dsize = 
@@ -15398,97 +15415,97 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1136]
+    (const void *)&gInstructions[1137]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1137]
+    (const void *)&gInstructions[1138]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1138]
+    (const void *)&gInstructions[1139]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1139]
+    (const void *)&gInstructions[1140]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1140]
+    (const void *)&gInstructions[1141]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1141]
+    (const void *)&gInstructions[1142]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1142]
+    (const void *)&gInstructions[1143]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1143]
+    (const void *)&gInstructions[1144]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1144]
+    (const void *)&gInstructions[1145]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1145]
+    (const void *)&gInstructions[1146]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1146]
+    (const void *)&gInstructions[1147]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1147]
+    (const void *)&gInstructions[1148]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1148]
+    (const void *)&gInstructions[1149]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1149]
+    (const void *)&gInstructions[1150]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1151]
+    (const void *)&gInstructions[1152]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1152]
+    (const void *)&gInstructions[1153]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_60_dsize = 
@@ -15507,19 +15524,19 @@ const ND_TABLE_DSIZE gRootTable_root_60_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1153]
+    (const void *)&gInstructions[1154]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1154]
+    (const void *)&gInstructions[1155]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1155]
+    (const void *)&gInstructions[1156]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9c_dsize = 
@@ -15538,49 +15555,49 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1159]
+    (const void *)&gInstructions[1160]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1167]
+    (const void *)&gInstructions[1168]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1197]
+    (const void *)&gInstructions[1198]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1203]
+    (const void *)&gInstructions[1204]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1222]
+    (const void *)&gInstructions[1223]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1229]
+    (const void *)&gInstructions[1230]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1286]
+    (const void *)&gInstructions[1287]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1295]
+    (const void *)&gInstructions[1296]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = 
@@ -15601,49 +15618,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1160]
+    (const void *)&gInstructions[1161]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1168]
+    (const void *)&gInstructions[1169]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1198]
+    (const void *)&gInstructions[1199]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1204]
+    (const void *)&gInstructions[1205]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1223]
+    (const void *)&gInstructions[1224]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1230]
+    (const void *)&gInstructions[1231]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1287]
+    (const void *)&gInstructions[1288]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1296]
+    (const void *)&gInstructions[1297]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = 
@@ -15664,49 +15681,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1161]
+    (const void *)&gInstructions[1162]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1169]
+    (const void *)&gInstructions[1170]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1199]
+    (const void *)&gInstructions[1200]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1205]
+    (const void *)&gInstructions[1206]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1224]
+    (const void *)&gInstructions[1225]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1231]
+    (const void *)&gInstructions[1232]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1288]
+    (const void *)&gInstructions[1289]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1297]
+    (const void *)&gInstructions[1298]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = 
@@ -15727,49 +15744,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1162]
+    (const void *)&gInstructions[1163]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1170]
+    (const void *)&gInstructions[1171]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1200]
+    (const void *)&gInstructions[1201]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1206]
+    (const void *)&gInstructions[1207]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1225]
+    (const void *)&gInstructions[1226]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1232]
+    (const void *)&gInstructions[1233]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1289]
+    (const void *)&gInstructions[1290]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1298]
+    (const void *)&gInstructions[1299]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = 
@@ -15790,49 +15807,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1163]
+    (const void *)&gInstructions[1164]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1171]
+    (const void *)&gInstructions[1172]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1201]
+    (const void *)&gInstructions[1202]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1207]
+    (const void *)&gInstructions[1208]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1226]
+    (const void *)&gInstructions[1227]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1233]
+    (const void *)&gInstructions[1234]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1290]
+    (const void *)&gInstructions[1291]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1299]
+    (const void *)&gInstructions[1300]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = 
@@ -15853,49 +15870,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1164]
+    (const void *)&gInstructions[1165]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1172]
+    (const void *)&gInstructions[1173]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1202]
+    (const void *)&gInstructions[1203]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1208]
+    (const void *)&gInstructions[1209]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1227]
+    (const void *)&gInstructions[1228]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1234]
+    (const void *)&gInstructions[1235]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1291]
+    (const void *)&gInstructions[1292]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1300]
+    (const void *)&gInstructions[1301]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = 
@@ -15916,85 +15933,85 @@ const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1190]
+    (const void *)&gInstructions[1191]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1191]
+    (const void *)&gInstructions[1192]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1192]
+    (const void *)&gInstructions[1193]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1193]
+    (const void *)&gInstructions[1194]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1221]
+    (const void *)&gInstructions[1222]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1228]
+    (const void *)&gInstructions[1229]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1237]
+    (const void *)&gInstructions[1238]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1238]
+    (const void *)&gInstructions[1239]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1239]
+    (const void *)&gInstructions[1240]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1240]
+    (const void *)&gInstructions[1241]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1241]
+    (const void *)&gInstructions[1242]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1242]
+    (const void *)&gInstructions[1243]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1247]
+    (const void *)&gInstructions[1248]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1248]
+    (const void *)&gInstructions[1249]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = 
@@ -16015,13 +16032,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1249]
+    (const void *)&gInstructions[1250]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1250]
+    (const void *)&gInstructions[1251]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = 
@@ -16042,13 +16059,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1251]
+    (const void *)&gInstructions[1252]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1252]
+    (const void *)&gInstructions[1253]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = 
@@ -16069,13 +16086,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1253]
+    (const void *)&gInstructions[1254]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1254]
+    (const void *)&gInstructions[1255]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = 
@@ -16109,31 +16126,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1320]
+    (const void *)&gInstructions[1321]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1321]
+    (const void *)&gInstructions[1322]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1323]
+    (const void *)&gInstructions[1324]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1325]
+    (const void *)&gInstructions[1326]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1326]
+    (const void *)&gInstructions[1327]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = 
@@ -16154,13 +16171,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1327]
+    (const void *)&gInstructions[1328]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1328]
+    (const void *)&gInstructions[1329]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = 
@@ -16181,13 +16198,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1329]
+    (const void *)&gInstructions[1330]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1330]
+    (const void *)&gInstructions[1331]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = 
@@ -16208,13 +16225,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1331]
+    (const void *)&gInstructions[1332]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1332]
+    (const void *)&gInstructions[1333]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = 
@@ -16248,163 +16265,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1337]
+    (const void *)&gInstructions[1338]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1338]
+    (const void *)&gInstructions[1339]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1339]
+    (const void *)&gInstructions[1340]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1340]
+    (const void *)&gInstructions[1341]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1341]
+    (const void *)&gInstructions[1342]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1342]
+    (const void *)&gInstructions[1343]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1369]
+    (const void *)&gInstructions[1370]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1370]
+    (const void *)&gInstructions[1371]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1371]
+    (const void *)&gInstructions[1372]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1372]
+    (const void *)&gInstructions[1373]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2697]
+    (const void *)&gInstructions[2712]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2715]
+    (const void *)&gInstructions[2730]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2716]
+    (const void *)&gInstructions[2731]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2718]
+    (const void *)&gInstructions[2733]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2719]
+    (const void *)&gInstructions[2734]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2720]
+    (const void *)&gInstructions[2735]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2721]
+    (const void *)&gInstructions[2736]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2722]
+    (const void *)&gInstructions[2737]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2723]
+    (const void *)&gInstructions[2738]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2724]
+    (const void *)&gInstructions[2739]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2732]
+    (const void *)&gInstructions[2747]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2733]
+    (const void *)&gInstructions[2748]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2734]
+    (const void *)&gInstructions[2749]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2735]
+    (const void *)&gInstructions[2750]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2736]
+    (const void *)&gInstructions[2751]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2737]
+    (const void *)&gInstructions[2752]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2738]
+    (const void *)&gInstructions[2753]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_opcode = 
diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h
index 2e71717..900d9e5 100644
--- a/bddisasm/include/table_vex.h
+++ b/bddisasm/include/table_vex.h
@@ -58,7 +58,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1235]
+    (const void *)&gInstructions[1236]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = 
@@ -75,7 +75,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1294]
+    (const void *)&gInstructions[1295]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = 
@@ -92,7 +92,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1303]
+    (const void *)&gInstructions[1304]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = 
@@ -214,7 +214,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[909]
+    (const void *)&gInstructions[910]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = 
@@ -231,7 +231,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[910]
+    (const void *)&gInstructions[911]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = 
@@ -892,7 +892,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1380]
+    (const void *)&gInstructions[1381]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = 
@@ -957,7 +957,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1335]
+    (const void *)&gInstructions[1336]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = 
@@ -1007,7 +1007,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1382]
+    (const void *)&gInstructions[1383]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = 
@@ -1096,7 +1096,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_6c_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1360]
+    (const void *)&gInstructions[1361]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_6c_01_reg_00_w = 
@@ -1131,7 +1131,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_6c_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_6c_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1361]
+    (const void *)&gInstructions[1362]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_6c_00_reg_00_w = 
@@ -1177,7 +1177,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1363]
+    (const void *)&gInstructions[1364]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = 
@@ -1212,7 +1212,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1368]
+    (const void *)&gInstructions[1369]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5c_03_reg_00_w = 
@@ -1258,7 +1258,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1364]
+    (const void *)&gInstructions[1365]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = 
@@ -1293,7 +1293,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1365]
+    (const void *)&gInstructions[1366]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = 
@@ -1328,7 +1328,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1366]
+    (const void *)&gInstructions[1367]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = 
@@ -1363,7 +1363,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1367]
+    (const void *)&gInstructions[1368]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = 
@@ -1409,7 +1409,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1378]
+    (const void *)&gInstructions[1379]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = 
@@ -1444,7 +1444,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1379]
+    (const void *)&gInstructions[1380]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = 
@@ -1479,7 +1479,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1381]
+    (const void *)&gInstructions[1382]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = 
@@ -1525,7 +1525,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1416]
+    (const void *)&gInstructions[1417]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = 
@@ -1542,7 +1542,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1418]
+    (const void *)&gInstructions[1419]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = 
@@ -1559,7 +1559,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1420]
+    (const void *)&gInstructions[1421]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = 
@@ -1576,7 +1576,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1422]
+    (const void *)&gInstructions[1423]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = 
@@ -1593,7 +1593,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1423]
+    (const void *)&gInstructions[1424]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = 
@@ -1621,7 +1621,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1435]
+    (const void *)&gInstructions[1436]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b1_02_mem_w = 
@@ -1645,7 +1645,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b1_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1436]
+    (const void *)&gInstructions[1437]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b1_01_mem_w = 
@@ -1680,7 +1680,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1443]
+    (const void *)&gInstructions[1444]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = 
@@ -1726,7 +1726,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1449]
+    (const void *)&gInstructions[1450]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = 
@@ -1772,7 +1772,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1456]
+    (const void *)&gInstructions[1457]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = 
@@ -1798,7 +1798,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1458]
+    (const void *)&gInstructions[1459]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = 
@@ -1824,7 +1824,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1483]
+    (const void *)&gInstructions[1484]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b0_02_mem_w = 
@@ -1848,7 +1848,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1484]
+    (const void *)&gInstructions[1485]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b0_01_mem_w = 
@@ -1872,7 +1872,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1485]
+    (const void *)&gInstructions[1486]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b0_03_mem_w = 
@@ -1896,7 +1896,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1486]
+    (const void *)&gInstructions[1487]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b0_00_mem_w = 
@@ -1931,7 +1931,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_72_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1488]
+    (const void *)&gInstructions[1489]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_72_02_w = 
@@ -1957,7 +1957,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_72_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1501]
+    (const void *)&gInstructions[1502]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = 
@@ -1972,7 +1972,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1502]
+    (const void *)&gInstructions[1503]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = 
@@ -2009,13 +2009,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1625]
+    (const void *)&gInstructions[1626]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1628]
+    (const void *)&gInstructions[1629]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = 
@@ -2041,13 +2041,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1630]
+    (const void *)&gInstructions[1631]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1633]
+    (const void *)&gInstructions[1634]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = 
@@ -2073,13 +2073,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1635]
+    (const void *)&gInstructions[1636]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1638]
+    (const void *)&gInstructions[1639]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = 
@@ -2105,13 +2105,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1640]
+    (const void *)&gInstructions[1641]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1643]
+    (const void *)&gInstructions[1644]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = 
@@ -2137,13 +2137,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1645]
+    (const void *)&gInstructions[1646]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1648]
+    (const void *)&gInstructions[1649]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = 
@@ -2169,13 +2169,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1650]
+    (const void *)&gInstructions[1651]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1653]
+    (const void *)&gInstructions[1654]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = 
@@ -2201,13 +2201,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1665]
+    (const void *)&gInstructions[1666]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1668]
+    (const void *)&gInstructions[1669]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = 
@@ -2233,13 +2233,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1670]
+    (const void *)&gInstructions[1671]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1673]
+    (const void *)&gInstructions[1674]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = 
@@ -2265,13 +2265,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1675]
+    (const void *)&gInstructions[1676]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1678]
+    (const void *)&gInstructions[1679]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = 
@@ -2297,13 +2297,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1684]
+    (const void *)&gInstructions[1685]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1687]
+    (const void *)&gInstructions[1688]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = 
@@ -2329,13 +2329,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1689]
+    (const void *)&gInstructions[1690]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1692]
+    (const void *)&gInstructions[1693]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = 
@@ -2361,13 +2361,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1694]
+    (const void *)&gInstructions[1695]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1697]
+    (const void *)&gInstructions[1698]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = 
@@ -2393,13 +2393,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1699]
+    (const void *)&gInstructions[1700]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1702]
+    (const void *)&gInstructions[1703]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = 
@@ -2425,13 +2425,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1704]
+    (const void *)&gInstructions[1705]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1707]
+    (const void *)&gInstructions[1708]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = 
@@ -2457,13 +2457,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1709]
+    (const void *)&gInstructions[1710]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1712]
+    (const void *)&gInstructions[1713]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = 
@@ -2489,13 +2489,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1714]
+    (const void *)&gInstructions[1715]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1717]
+    (const void *)&gInstructions[1718]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = 
@@ -2521,13 +2521,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1719]
+    (const void *)&gInstructions[1720]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1722]
+    (const void *)&gInstructions[1723]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = 
@@ -2553,13 +2553,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1724]
+    (const void *)&gInstructions[1725]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1727]
+    (const void *)&gInstructions[1728]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = 
@@ -2585,13 +2585,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1743]
+    (const void *)&gInstructions[1744]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1746]
+    (const void *)&gInstructions[1747]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = 
@@ -2617,13 +2617,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1748]
+    (const void *)&gInstructions[1749]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1751]
+    (const void *)&gInstructions[1752]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = 
@@ -2649,13 +2649,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1753]
+    (const void *)&gInstructions[1754]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1756]
+    (const void *)&gInstructions[1757]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = 
@@ -2681,13 +2681,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1758]
+    (const void *)&gInstructions[1759]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1761]
+    (const void *)&gInstructions[1762]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = 
@@ -2713,13 +2713,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1763]
+    (const void *)&gInstructions[1764]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1766]
+    (const void *)&gInstructions[1767]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = 
@@ -2745,13 +2745,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1768]
+    (const void *)&gInstructions[1769]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1771]
+    (const void *)&gInstructions[1772]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = 
@@ -2777,13 +2777,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1781]
+    (const void *)&gInstructions[1782]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1784]
+    (const void *)&gInstructions[1785]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = 
@@ -2809,13 +2809,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1786]
+    (const void *)&gInstructions[1787]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1789]
+    (const void *)&gInstructions[1790]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = 
@@ -2841,13 +2841,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1791]
+    (const void *)&gInstructions[1792]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1794]
+    (const void *)&gInstructions[1795]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = 
@@ -2873,13 +2873,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1796]
+    (const void *)&gInstructions[1797]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1799]
+    (const void *)&gInstructions[1800]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = 
@@ -2905,13 +2905,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1801]
+    (const void *)&gInstructions[1802]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1804]
+    (const void *)&gInstructions[1805]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = 
@@ -2937,13 +2937,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1806]
+    (const void *)&gInstructions[1807]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1809]
+    (const void *)&gInstructions[1810]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = 
@@ -2969,13 +2969,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1829]
+    (const void *)&gInstructions[1830]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1831]
+    (const void *)&gInstructions[1832]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = 
@@ -3010,13 +3010,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1841]
+    (const void *)&gInstructions[1842]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1843]
+    (const void *)&gInstructions[1844]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = 
@@ -3051,7 +3051,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1861]
+    (const void *)&gInstructions[1862]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = 
@@ -3077,7 +3077,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1883]
+    (const void *)&gInstructions[1884]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = 
@@ -3112,7 +3112,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1884]
+    (const void *)&gInstructions[1885]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = 
@@ -3147,7 +3147,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1885]
+    (const void *)&gInstructions[1886]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = 
@@ -3182,7 +3182,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1886]
+    (const void *)&gInstructions[1887]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = 
@@ -3217,7 +3217,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1974]
+    (const void *)&gInstructions[1975]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = 
@@ -3243,7 +3243,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2052]
+    (const void *)&gInstructions[2053]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = 
@@ -3260,7 +3260,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2054]
+    (const void *)&gInstructions[2055]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = 
@@ -3277,7 +3277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2057]
+    (const void *)&gInstructions[2058]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = 
@@ -3294,7 +3294,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2063]
+    (const void *)&gInstructions[2064]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = 
@@ -3311,7 +3311,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2103]
+    (const void *)&gInstructions[2104]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = 
@@ -3337,7 +3337,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2106]
+    (const void *)&gInstructions[2107]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = 
@@ -3363,7 +3363,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2111]
+    (const void *)&gInstructions[2112]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = 
@@ -3389,7 +3389,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2114]
+    (const void *)&gInstructions[2115]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = 
@@ -3415,7 +3415,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2126]
+    (const void *)&gInstructions[2127]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = 
@@ -3432,7 +3432,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2136]
+    (const void *)&gInstructions[2137]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = 
@@ -3449,7 +3449,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_50_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2161]
+    (const void *)&gInstructions[2162]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_50_03_w = 
@@ -3464,7 +3464,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_03_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_50_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2163]
+    (const void *)&gInstructions[2164]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_50_02_w = 
@@ -3479,7 +3479,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_02_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2166]
+    (const void *)&gInstructions[2167]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = 
@@ -3494,7 +3494,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_50_01_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_50_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2169]
+    (const void *)&gInstructions[2170]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_50_00_w = 
@@ -3520,7 +3520,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_50_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_51_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2162]
+    (const void *)&gInstructions[2163]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_51_03_w = 
@@ -3535,7 +3535,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_03_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_51_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2164]
+    (const void *)&gInstructions[2165]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_51_02_w = 
@@ -3550,7 +3550,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_02_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2168]
+    (const void *)&gInstructions[2169]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = 
@@ -3565,7 +3565,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_51_01_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_51_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2170]
+    (const void *)&gInstructions[2171]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_51_00_w = 
@@ -3591,7 +3591,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_51_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_52_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2172]
+    (const void *)&gInstructions[2173]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_52_01_w = 
@@ -3617,7 +3617,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_52_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_53_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2174]
+    (const void *)&gInstructions[2175]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_53_01_w = 
@@ -3640,12 +3640,124 @@ const ND_TABLE_VEX_PP gVexTable_root_02_53_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_d2_02_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2176]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_d2_02_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d2_02_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_d2_01_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2178]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_d2_01_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d2_01_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_d2_00_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2180]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_d2_00_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d2_00_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_02_d2_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d2_00_w,
+        /* 01 */ (const void *)&gVexTable_root_02_d2_01_w,
+        /* 02 */ (const void *)&gVexTable_root_02_d2_02_w,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_d3_02_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2177]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_d3_02_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d3_02_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_d3_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[2179]
 };
 
+const ND_TABLE_VEX_W gVexTable_root_02_d3_01_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d3_01_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_d3_00_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2181]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_d3_00_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d3_00_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_02_d3_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_d3_00_w,
+        /* 01 */ (const void *)&gVexTable_root_02_d3_01_w,
+        /* 02 */ (const void *)&gVexTable_root_02_d3_02_w,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2186]
+};
+
 const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = 
 {
     ND_ILUT_VEX_W,
@@ -3680,7 +3792,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2192]
+    (const void *)&gInstructions[2199]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = 
@@ -3706,7 +3818,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2196]
+    (const void *)&gInstructions[2203]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = 
@@ -3732,7 +3844,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2204]
+    (const void *)&gInstructions[2211]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = 
@@ -3769,13 +3881,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2238]
+    (const void *)&gInstructions[2245]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2240]
+    (const void *)&gInstructions[2247]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = 
@@ -3810,13 +3922,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2242]
+    (const void *)&gInstructions[2249]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2244]
+    (const void *)&gInstructions[2251]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = 
@@ -3851,7 +3963,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2248]
+    (const void *)&gInstructions[2255]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = 
@@ -3868,7 +3980,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2250]
+    (const void *)&gInstructions[2257]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = 
@@ -3885,7 +3997,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2257]
+    (const void *)&gInstructions[2264]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = 
@@ -3902,7 +4014,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2260]
+    (const void *)&gInstructions[2267]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = 
@@ -3930,7 +4042,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2262]
+    (const void *)&gInstructions[2269]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = 
@@ -3947,7 +4059,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2264]
+    (const void *)&gInstructions[2271]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = 
@@ -3964,7 +4076,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2265]
+    (const void *)&gInstructions[2272]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = 
@@ -3981,7 +4093,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b5_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2294]
+    (const void *)&gInstructions[2301]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b5_01_w = 
@@ -4007,7 +4119,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2296]
+    (const void *)&gInstructions[2303]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b4_01_w = 
@@ -4033,7 +4145,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2298]
+    (const void *)&gInstructions[2305]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = 
@@ -4050,13 +4162,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2301]
+    (const void *)&gInstructions[2308]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2303]
+    (const void *)&gInstructions[2310]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = 
@@ -4091,13 +4203,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2302]
+    (const void *)&gInstructions[2309]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2304]
+    (const void *)&gInstructions[2311]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = 
@@ -4132,7 +4244,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2306]
+    (const void *)&gInstructions[2313]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = 
@@ -4149,7 +4261,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2308]
+    (const void *)&gInstructions[2315]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = 
@@ -4166,7 +4278,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2315]
+    (const void *)&gInstructions[2322]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = 
@@ -4183,7 +4295,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2318]
+    (const void *)&gInstructions[2325]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = 
@@ -4200,7 +4312,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2320]
+    (const void *)&gInstructions[2327]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = 
@@ -4217,7 +4329,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2322]
+    (const void *)&gInstructions[2329]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = 
@@ -4234,7 +4346,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2329]
+    (const void *)&gInstructions[2336]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = 
@@ -4251,7 +4363,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2332]
+    (const void *)&gInstructions[2339]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = 
@@ -4268,13 +4380,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2353]
+    (const void *)&gInstructions[2360]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2354]
+    (const void *)&gInstructions[2361]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = 
@@ -4302,13 +4414,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2356]
+    (const void *)&gInstructions[2363]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2357]
+    (const void *)&gInstructions[2364]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = 
@@ -4336,13 +4448,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2359]
+    (const void *)&gInstructions[2366]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2360]
+    (const void *)&gInstructions[2367]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = 
@@ -4370,13 +4482,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2362]
+    (const void *)&gInstructions[2369]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2363]
+    (const void *)&gInstructions[2370]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = 
@@ -4404,13 +4516,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2365]
+    (const void *)&gInstructions[2372]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2366]
+    (const void *)&gInstructions[2373]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = 
@@ -4438,13 +4550,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2368]
+    (const void *)&gInstructions[2375]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2369]
+    (const void *)&gInstructions[2376]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = 
@@ -4472,13 +4584,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2379]
+    (const void *)&gInstructions[2386]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2380]
+    (const void *)&gInstructions[2387]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = 
@@ -4506,13 +4618,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2382]
+    (const void *)&gInstructions[2389]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2383]
+    (const void *)&gInstructions[2390]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = 
@@ -4540,13 +4652,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2385]
+    (const void *)&gInstructions[2392]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2386]
+    (const void *)&gInstructions[2393]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = 
@@ -4574,13 +4686,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2388]
+    (const void *)&gInstructions[2395]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2389]
+    (const void *)&gInstructions[2396]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = 
@@ -4608,13 +4720,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2391]
+    (const void *)&gInstructions[2398]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2392]
+    (const void *)&gInstructions[2399]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = 
@@ -4642,13 +4754,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2394]
+    (const void *)&gInstructions[2401]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2395]
+    (const void *)&gInstructions[2402]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = 
@@ -4676,7 +4788,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2397]
+    (const void *)&gInstructions[2404]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = 
@@ -4693,7 +4805,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2399]
+    (const void *)&gInstructions[2406]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = 
@@ -4710,7 +4822,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2405]
+    (const void *)&gInstructions[2412]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = 
@@ -4727,7 +4839,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2476]
+    (const void *)&gInstructions[2483]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = 
@@ -4744,7 +4856,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2484]
+    (const void *)&gInstructions[2491]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = 
@@ -4761,7 +4873,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2485]
+    (const void *)&gInstructions[2492]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = 
@@ -4778,7 +4890,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2486]
+    (const void *)&gInstructions[2493]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = 
@@ -4795,13 +4907,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2498]
+    (const void *)&gInstructions[2505]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2500]
+    (const void *)&gInstructions[2507]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = 
@@ -4827,7 +4939,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2513]
+    (const void *)&gInstructions[2520]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = 
@@ -4853,13 +4965,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2531]
+    (const void *)&gInstructions[2538]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2533]
+    (const void *)&gInstructions[2540]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = 
@@ -4885,7 +4997,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2557]
+    (const void *)&gInstructions[2564]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = 
@@ -4899,10 +5011,241 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp =
     }
 };
 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_cc_03_reg_01_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2654]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_cc_03_reg_01_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_cc_03_reg_01_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_L gVexTable_root_02_cc_03_reg_l = 
+{
+    ND_ILUT_VEX_L,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_02_cc_03_reg_01_w,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gVexTable_root_02_cc_03_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_02_cc_03_reg_l,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_02_cc_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ (const void *)&gVexTable_root_02_cc_03_modrmmod,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_cd_03_reg_01_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2655]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_cd_03_reg_01_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_cd_03_reg_01_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_L gVexTable_root_02_cd_03_reg_l = 
+{
+    ND_ILUT_VEX_L,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_02_cd_03_reg_01_w,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gVexTable_root_02_cd_03_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_02_cd_03_reg_l,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_02_cd_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ (const void *)&gVexTable_root_02_cd_03_modrmmod,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_cb_03_reg_01_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2656]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_cb_03_reg_01_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_cb_03_reg_01_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_L gVexTable_root_02_cb_03_reg_l = 
+{
+    ND_ILUT_VEX_L,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_02_cb_03_reg_01_w,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_MODRM_MOD gVexTable_root_02_cb_03_modrmmod = 
+{
+    ND_ILUT_MODRM_MOD,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_02_cb_03_reg_l,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_02_cb_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ (const void *)&gVexTable_root_02_cb_03_modrmmod,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_da_00_00_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2665]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_da_00_00_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_00_00_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_L gVexTable_root_02_da_00_l = 
+{
+    ND_ILUT_VEX_L,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_00_00_w,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_da_01_00_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2666]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_da_01_00_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_01_00_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_L gVexTable_root_02_da_01_l = 
+{
+    ND_ILUT_VEX_L,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_01_00_w,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_da_02_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2668]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_da_02_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_02_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_INSTRUCTION gVexTable_root_02_da_03_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2669]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_02_da_03_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_03_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_02_da_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_02_da_00_l,
+        /* 01 */ (const void *)&gVexTable_root_02_da_01_l,
+        /* 02 */ (const void *)&gVexTable_root_02_da_02_w,
+        /* 03 */ (const void *)&gVexTable_root_02_da_03_w,
+    }
+};
+
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2676]
+    (const void *)&gInstructions[2691]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = 
@@ -4928,7 +5271,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2677]
+    (const void *)&gInstructions[2692]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = 
@@ -5158,22 +5501,22 @@ const ND_TABLE_OPCODE gVexTable_root_02_opcode =
         /* c8 */ ND_NULL,
         /* c9 */ ND_NULL,
         /* ca */ ND_NULL,
-        /* cb */ ND_NULL,
-        /* cc */ ND_NULL,
-        /* cd */ ND_NULL,
+        /* cb */ (const void *)&gVexTable_root_02_cb_pp,
+        /* cc */ (const void *)&gVexTable_root_02_cc_pp,
+        /* cd */ (const void *)&gVexTable_root_02_cd_pp,
         /* ce */ ND_NULL,
         /* cf */ (const void *)&gVexTable_root_02_cf_pp,
         /* d0 */ ND_NULL,
         /* d1 */ ND_NULL,
-        /* d2 */ ND_NULL,
-        /* d3 */ ND_NULL,
+        /* d2 */ (const void *)&gVexTable_root_02_d2_pp,
+        /* d3 */ (const void *)&gVexTable_root_02_d3_pp,
         /* d4 */ ND_NULL,
         /* d5 */ ND_NULL,
         /* d6 */ ND_NULL,
         /* d7 */ ND_NULL,
         /* d8 */ ND_NULL,
         /* d9 */ ND_NULL,
-        /* da */ ND_NULL,
+        /* da */ (const void *)&gVexTable_root_02_da_pp,
         /* db */ (const void *)&gVexTable_root_02_db_pp,
         /* dc */ (const void *)&gVexTable_root_02_dc_pp,
         /* dd */ (const void *)&gVexTable_root_02_dd_pp,
@@ -5238,7 +5581,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1314]
+    (const void *)&gInstructions[1315]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = 
@@ -5319,13 +5662,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1881]
+    (const void *)&gInstructions[1882]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2665]
+    (const void *)&gInstructions[2680]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = 
@@ -6876,25 +7219,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1404]
+    (const void *)&gInstructions[1405]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1407]
+    (const void *)&gInstructions[1408]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1409]
+    (const void *)&gInstructions[1410]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1412]
+    (const void *)&gInstructions[1413]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = 
@@ -6911,13 +7254,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1413]
+    (const void *)&gInstructions[1414]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1414]
+    (const void *)&gInstructions[1415]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = 
@@ -6934,13 +7277,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1428]
+    (const void *)&gInstructions[1429]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1430]
+    (const void *)&gInstructions[1431]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = 
@@ -6957,13 +7300,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1432]
+    (const void *)&gInstructions[1433]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1434]
+    (const void *)&gInstructions[1435]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = 
@@ -6980,25 +7323,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1460]
+    (const void *)&gInstructions[1461]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1463]
+    (const void *)&gInstructions[1464]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1465]
+    (const void *)&gInstructions[1466]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1468]
+    (const void *)&gInstructions[1469]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = 
@@ -7015,13 +7358,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1470]
+    (const void *)&gInstructions[1471]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1473]
+    (const void *)&gInstructions[1474]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = 
@@ -7038,13 +7381,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1477]
+    (const void *)&gInstructions[1478]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1478]
+    (const void *)&gInstructions[1479]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = 
@@ -7061,13 +7404,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1490]
+    (const void *)&gInstructions[1491]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1547]
+    (const void *)&gInstructions[1548]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = 
@@ -7084,19 +7427,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1481]
+    (const void *)&gInstructions[1482]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1510]
+    (const void *)&gInstructions[1511]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1558]
+    (const void *)&gInstructions[1559]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = 
@@ -7113,13 +7456,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1493]
+    (const void *)&gInstructions[1494]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1494]
+    (const void *)&gInstructions[1495]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = 
@@ -7136,13 +7479,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1512]
+    (const void *)&gInstructions[1513]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1513]
+    (const void *)&gInstructions[1514]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = 
@@ -7159,13 +7502,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1528]
+    (const void *)&gInstructions[1529]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1541]
+    (const void *)&gInstructions[1542]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = 
@@ -7182,13 +7525,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1526]
+    (const void *)&gInstructions[1527]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1544]
+    (const void *)&gInstructions[1545]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = 
@@ -7205,13 +7548,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1536]
+    (const void *)&gInstructions[1537]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1539]
+    (const void *)&gInstructions[1540]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = 
@@ -7228,13 +7571,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1563]
+    (const void *)&gInstructions[1564]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1568]
+    (const void *)&gInstructions[1569]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = 
@@ -7251,25 +7594,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1584]
+    (const void *)&gInstructions[1585]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1587]
+    (const void *)&gInstructions[1588]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1589]
+    (const void *)&gInstructions[1590]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1592]
+    (const void *)&gInstructions[1593]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = 
@@ -7286,13 +7629,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1862]
+    (const void *)&gInstructions[1863]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1863]
+    (const void *)&gInstructions[1864]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = 
@@ -7309,13 +7652,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1864]
+    (const void *)&gInstructions[1865]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1865]
+    (const void *)&gInstructions[1866]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = 
@@ -7332,7 +7675,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1880]
+    (const void *)&gInstructions[1881]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = 
@@ -7358,7 +7701,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1882]
+    (const void *)&gInstructions[1883]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = 
@@ -7395,25 +7738,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1888]
+    (const void *)&gInstructions[1889]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1891]
+    (const void *)&gInstructions[1892]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1893]
+    (const void *)&gInstructions[1894]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1896]
+    (const void *)&gInstructions[1897]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = 
@@ -7430,25 +7773,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1903]
+    (const void *)&gInstructions[1904]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1906]
+    (const void *)&gInstructions[1907]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1908]
+    (const void *)&gInstructions[1909]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1911]
+    (const void *)&gInstructions[1912]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = 
@@ -7465,13 +7808,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1918]
+    (const void *)&gInstructions[1919]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1922]
+    (const void *)&gInstructions[1923]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = 
@@ -7488,13 +7831,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1919]
+    (const void *)&gInstructions[1920]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1923]
+    (const void *)&gInstructions[1924]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = 
@@ -7511,13 +7854,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1926]
+    (const void *)&gInstructions[1927]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1983]
+    (const void *)&gInstructions[1984]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_wi = 
@@ -7554,13 +7897,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1927]
+    (const void *)&gInstructions[1928]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1984]
+    (const void *)&gInstructions[1985]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_wi = 
@@ -7586,7 +7929,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1985]
+    (const void *)&gInstructions[1986]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = 
@@ -7614,13 +7957,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1931]
+    (const void *)&gInstructions[1932]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1932]
+    (const void *)&gInstructions[1933]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = 
@@ -7637,7 +7980,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1950]
+    (const void *)&gInstructions[1951]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = 
@@ -7654,7 +7997,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1967]
+    (const void *)&gInstructions[1968]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = 
@@ -7680,7 +8023,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1963]
+    (const void *)&gInstructions[1964]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = 
@@ -7706,7 +8049,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2002]
+    (const void *)&gInstructions[2003]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = 
@@ -7723,13 +8066,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1933]
+    (const void *)&gInstructions[1934]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1939]
+    (const void *)&gInstructions[1940]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = 
@@ -7746,13 +8089,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1934]
+    (const void *)&gInstructions[1935]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1940]
+    (const void *)&gInstructions[1941]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = 
@@ -7769,7 +8112,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1953]
+    (const void *)&gInstructions[1954]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = 
@@ -7795,7 +8138,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1957]
+    (const void *)&gInstructions[1958]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = 
@@ -7812,7 +8155,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1960]
+    (const void *)&gInstructions[1961]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = 
@@ -7838,7 +8181,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2000]
+    (const void *)&gInstructions[2001]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = 
@@ -7855,7 +8198,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1954]
+    (const void *)&gInstructions[1955]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = 
@@ -7881,7 +8224,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1958]
+    (const void *)&gInstructions[1959]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = 
@@ -7918,7 +8261,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1964]
+    (const void *)&gInstructions[1965]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = 
@@ -7944,7 +8287,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1968]
+    (const void *)&gInstructions[1969]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = 
@@ -7981,7 +8324,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1969]
+    (const void *)&gInstructions[1970]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = 
@@ -7996,7 +8339,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1970]
+    (const void *)&gInstructions[1971]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = 
@@ -8022,7 +8365,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1972]
+    (const void *)&gInstructions[1973]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = 
@@ -8048,7 +8391,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1976]
+    (const void *)&gInstructions[1977]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = 
@@ -8063,7 +8406,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1978]
+    (const void *)&gInstructions[1979]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = 
@@ -8089,7 +8432,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1986]
+    (const void *)&gInstructions[1987]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = 
@@ -8117,13 +8460,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1991]
+    (const void *)&gInstructions[1992]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1992]
+    (const void *)&gInstructions[1993]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = 
@@ -8138,13 +8481,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2007]
+    (const void *)&gInstructions[2008]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2008]
+    (const void *)&gInstructions[2009]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = 
@@ -8159,13 +8502,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2013]
+    (const void *)&gInstructions[2014]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2017]
+    (const void *)&gInstructions[2018]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = 
@@ -8182,13 +8525,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1993]
+    (const void *)&gInstructions[1994]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1994]
+    (const void *)&gInstructions[1995]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = 
@@ -8203,13 +8546,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2009]
+    (const void *)&gInstructions[2010]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2010]
+    (const void *)&gInstructions[2011]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = 
@@ -8224,13 +8567,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2014]
+    (const void *)&gInstructions[2015]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2018]
+    (const void *)&gInstructions[2019]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = 
@@ -8247,25 +8590,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2031]
+    (const void *)&gInstructions[2032]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2034]
+    (const void *)&gInstructions[2035]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2036]
+    (const void *)&gInstructions[2037]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2039]
+    (const void *)&gInstructions[2040]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = 
@@ -8282,13 +8625,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2044]
+    (const void *)&gInstructions[2045]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2046]
+    (const void *)&gInstructions[2047]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = 
@@ -8305,7 +8648,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2059]
+    (const void *)&gInstructions[2060]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = 
@@ -8322,7 +8665,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2061]
+    (const void *)&gInstructions[2062]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = 
@@ -8339,7 +8682,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2065]
+    (const void *)&gInstructions[2066]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = 
@@ -8356,7 +8699,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2067]
+    (const void *)&gInstructions[2068]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = 
@@ -8373,7 +8716,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2069]
+    (const void *)&gInstructions[2070]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = 
@@ -8390,7 +8733,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2071]
+    (const void *)&gInstructions[2072]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = 
@@ -8407,7 +8750,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2073]
+    (const void *)&gInstructions[2074]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = 
@@ -8424,7 +8767,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2075]
+    (const void *)&gInstructions[2076]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = 
@@ -8441,7 +8784,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2077]
+    (const void *)&gInstructions[2078]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = 
@@ -8458,7 +8801,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2079]
+    (const void *)&gInstructions[2080]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = 
@@ -8475,7 +8818,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2081]
+    (const void *)&gInstructions[2082]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = 
@@ -8492,7 +8835,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2084]
+    (const void *)&gInstructions[2085]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = 
@@ -8509,7 +8852,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2086]
+    (const void *)&gInstructions[2087]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = 
@@ -8526,7 +8869,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2091]
+    (const void *)&gInstructions[2092]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = 
@@ -8543,7 +8886,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2093]
+    (const void *)&gInstructions[2094]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = 
@@ -8560,7 +8903,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2122]
+    (const void *)&gInstructions[2123]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = 
@@ -8577,7 +8920,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2124]
+    (const void *)&gInstructions[2125]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = 
@@ -8594,7 +8937,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2128]
+    (const void *)&gInstructions[2129]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = 
@@ -8611,7 +8954,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2132]
+    (const void *)&gInstructions[2133]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = 
@@ -8628,7 +8971,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2134]
+    (const void *)&gInstructions[2135]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = 
@@ -8645,7 +8988,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2138]
+    (const void *)&gInstructions[2139]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = 
@@ -8662,7 +9005,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2234]
+    (const void *)&gInstructions[2241]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = 
@@ -8699,7 +9042,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2277]
+    (const void *)&gInstructions[2284]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = 
@@ -8716,7 +9059,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2278]
+    (const void *)&gInstructions[2285]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = 
@@ -8753,7 +9096,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2300]
+    (const void *)&gInstructions[2307]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = 
@@ -8770,7 +9113,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2311]
+    (const void *)&gInstructions[2318]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = 
@@ -8787,7 +9130,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2313]
+    (const void *)&gInstructions[2320]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = 
@@ -8804,7 +9147,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2325]
+    (const void *)&gInstructions[2332]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = 
@@ -8821,7 +9164,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2327]
+    (const void *)&gInstructions[2334]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = 
@@ -8838,7 +9181,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2341]
+    (const void *)&gInstructions[2348]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = 
@@ -8864,7 +9207,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2401]
+    (const void *)&gInstructions[2408]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = 
@@ -8881,7 +9224,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2403]
+    (const void *)&gInstructions[2410]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = 
@@ -8898,7 +9241,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2408]
+    (const void *)&gInstructions[2415]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = 
@@ -8915,7 +9258,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2411]
+    (const void *)&gInstructions[2418]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = 
@@ -8932,7 +9275,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2416]
+    (const void *)&gInstructions[2423]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = 
@@ -8949,7 +9292,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2442]
+    (const void *)&gInstructions[2449]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = 
@@ -8966,19 +9309,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2479]
+    (const void *)&gInstructions[2486]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2481]
+    (const void *)&gInstructions[2488]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2483]
+    (const void *)&gInstructions[2490]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = 
@@ -8995,19 +9338,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2489]
+    (const void *)&gInstructions[2496]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2508]
+    (const void *)&gInstructions[2515]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2522]
+    (const void *)&gInstructions[2529]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = 
@@ -9048,7 +9391,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2490]
+    (const void *)&gInstructions[2497]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = 
@@ -9065,25 +9408,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2492]
+    (const void *)&gInstructions[2499]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2495]
+    (const void *)&gInstructions[2502]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2525]
+    (const void *)&gInstructions[2532]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2528]
+    (const void *)&gInstructions[2535]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = 
@@ -9124,7 +9467,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2496]
+    (const void *)&gInstructions[2503]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = 
@@ -9141,19 +9484,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2504]
+    (const void *)&gInstructions[2511]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2518]
+    (const void *)&gInstructions[2525]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2537]
+    (const void *)&gInstructions[2544]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = 
@@ -9194,7 +9537,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2505]
+    (const void *)&gInstructions[2512]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = 
@@ -9211,7 +9554,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2509]
+    (const void *)&gInstructions[2516]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = 
@@ -9228,7 +9571,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2519]
+    (const void *)&gInstructions[2526]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = 
@@ -9245,7 +9588,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2523]
+    (const void *)&gInstructions[2530]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = 
@@ -9262,7 +9605,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2529]
+    (const void *)&gInstructions[2536]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = 
@@ -9279,7 +9622,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2538]
+    (const void *)&gInstructions[2545]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = 
@@ -9296,7 +9639,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2540]
+    (const void *)&gInstructions[2547]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = 
@@ -9313,7 +9656,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2542]
+    (const void *)&gInstructions[2549]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = 
@@ -9330,7 +9673,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2544]
+    (const void *)&gInstructions[2551]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = 
@@ -9347,7 +9690,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2546]
+    (const void *)&gInstructions[2553]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = 
@@ -9364,7 +9707,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2548]
+    (const void *)&gInstructions[2555]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = 
@@ -9381,7 +9724,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2550]
+    (const void *)&gInstructions[2557]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = 
@@ -9398,7 +9741,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2552]
+    (const void *)&gInstructions[2559]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = 
@@ -9415,7 +9758,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2554]
+    (const void *)&gInstructions[2561]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = 
@@ -9432,7 +9775,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2567]
+    (const void *)&gInstructions[2574]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = 
@@ -9449,7 +9792,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2569]
+    (const void *)&gInstructions[2576]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = 
@@ -9466,7 +9809,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2571]
+    (const void *)&gInstructions[2578]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = 
@@ -9483,7 +9826,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2573]
+    (const void *)&gInstructions[2580]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = 
@@ -9500,7 +9843,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2575]
+    (const void *)&gInstructions[2582]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = 
@@ -9517,7 +9860,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2577]
+    (const void *)&gInstructions[2584]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = 
@@ -9534,7 +9877,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2579]
+    (const void *)&gInstructions[2586]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = 
@@ -9551,7 +9894,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2581]
+    (const void *)&gInstructions[2588]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = 
@@ -9568,7 +9911,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2582]
+    (const void *)&gInstructions[2589]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = 
@@ -9585,13 +9928,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2598]
+    (const void *)&gInstructions[2605]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2600]
+    (const void *)&gInstructions[2607]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = 
@@ -9608,13 +9951,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2626]
+    (const void *)&gInstructions[2633]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2628]
+    (const void *)&gInstructions[2635]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = 
@@ -9631,13 +9974,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2652]
+    (const void *)&gInstructions[2662]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2654]
+    (const void *)&gInstructions[2664]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = 
@@ -9654,25 +9997,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2656]
+    (const void *)&gInstructions[2671]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2659]
+    (const void *)&gInstructions[2674]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2661]
+    (const void *)&gInstructions[2676]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2664]
+    (const void *)&gInstructions[2679]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = 
@@ -9689,25 +10032,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2667]
+    (const void *)&gInstructions[2682]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2670]
+    (const void *)&gInstructions[2685]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2672]
+    (const void *)&gInstructions[2687]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2675]
+    (const void *)&gInstructions[2690]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = 
@@ -9724,13 +10067,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2679]
+    (const void *)&gInstructions[2694]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2682]
+    (const void *)&gInstructions[2697]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = 
@@ -9747,13 +10090,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2684]
+    (const void *)&gInstructions[2699]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2686]
+    (const void *)&gInstructions[2701]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = 
@@ -9770,13 +10113,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2688]
+    (const void *)&gInstructions[2703]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2690]
+    (const void *)&gInstructions[2705]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = 
@@ -9793,13 +10136,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2692]
+    (const void *)&gInstructions[2707]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2694]
+    (const void *)&gInstructions[2709]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = 
@@ -9816,13 +10159,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2695]
+    (const void *)&gInstructions[2710]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2696]
+    (const void *)&gInstructions[2711]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = 
@@ -10321,7 +10664,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1209]
+    (const void *)&gInstructions[1210]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = 
@@ -10349,7 +10692,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1424]
+    (const void *)&gInstructions[1425]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = 
@@ -10377,7 +10720,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1439]
+    (const void *)&gInstructions[1440]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = 
@@ -10394,7 +10737,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1440]
+    (const void *)&gInstructions[1441]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = 
@@ -10411,7 +10754,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1441]
+    (const void *)&gInstructions[1442]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = 
@@ -10437,7 +10780,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1442]
+    (const void *)&gInstructions[1443]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = 
@@ -10463,7 +10806,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1515]
+    (const void *)&gInstructions[1516]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = 
@@ -10478,7 +10821,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1516]
+    (const void *)&gInstructions[1517]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = 
@@ -10515,7 +10858,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1594]
+    (const void *)&gInstructions[1595]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = 
@@ -10543,7 +10886,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1595]
+    (const void *)&gInstructions[1596]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = 
@@ -10560,7 +10903,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1602]
+    (const void *)&gInstructions[1603]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = 
@@ -10597,7 +10940,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1607]
+    (const void *)&gInstructions[1608]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = 
@@ -10634,7 +10977,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1614]
+    (const void *)&gInstructions[1615]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = 
@@ -10651,7 +10994,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1615]
+    (const void *)&gInstructions[1616]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = 
@@ -10688,13 +11031,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1656]
+    (const void *)&gInstructions[1657]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1657]
+    (const void *)&gInstructions[1658]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = 
@@ -10720,13 +11063,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1658]
+    (const void *)&gInstructions[1659]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1659]
+    (const void *)&gInstructions[1660]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = 
@@ -10752,13 +11095,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1660]
+    (const void *)&gInstructions[1661]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1661]
+    (const void *)&gInstructions[1662]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = 
@@ -10784,13 +11127,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1662]
+    (const void *)&gInstructions[1663]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1663]
+    (const void *)&gInstructions[1664]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = 
@@ -10816,13 +11159,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1679]
+    (const void *)&gInstructions[1680]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1680]
+    (const void *)&gInstructions[1681]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = 
@@ -10848,13 +11191,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1681]
+    (const void *)&gInstructions[1682]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1682]
+    (const void *)&gInstructions[1683]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = 
@@ -10880,13 +11223,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1728]
+    (const void *)&gInstructions[1729]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1729]
+    (const void *)&gInstructions[1730]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = 
@@ -10912,13 +11255,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1730]
+    (const void *)&gInstructions[1731]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1731]
+    (const void *)&gInstructions[1732]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = 
@@ -10944,13 +11287,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1732]
+    (const void *)&gInstructions[1733]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1733]
+    (const void *)&gInstructions[1734]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = 
@@ -10976,13 +11319,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1734]
+    (const void *)&gInstructions[1735]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1735]
+    (const void *)&gInstructions[1736]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = 
@@ -11008,13 +11351,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1736]
+    (const void *)&gInstructions[1737]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1737]
+    (const void *)&gInstructions[1738]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = 
@@ -11040,13 +11383,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1738]
+    (const void *)&gInstructions[1739]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1739]
+    (const void *)&gInstructions[1740]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = 
@@ -11072,13 +11415,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1772]
+    (const void *)&gInstructions[1773]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1773]
+    (const void *)&gInstructions[1774]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = 
@@ -11104,13 +11447,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1774]
+    (const void *)&gInstructions[1775]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1775]
+    (const void *)&gInstructions[1776]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = 
@@ -11136,13 +11479,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1776]
+    (const void *)&gInstructions[1777]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1777]
+    (const void *)&gInstructions[1778]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = 
@@ -11168,13 +11511,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1778]
+    (const void *)&gInstructions[1779]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1779]
+    (const void *)&gInstructions[1780]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = 
@@ -11200,13 +11543,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1810]
+    (const void *)&gInstructions[1811]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1811]
+    (const void *)&gInstructions[1812]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = 
@@ -11232,13 +11575,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1812]
+    (const void *)&gInstructions[1813]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1813]
+    (const void *)&gInstructions[1814]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = 
@@ -11264,13 +11607,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1814]
+    (const void *)&gInstructions[1815]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1815]
+    (const void *)&gInstructions[1816]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = 
@@ -11296,13 +11639,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1816]
+    (const void *)&gInstructions[1817]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1817]
+    (const void *)&gInstructions[1818]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = 
@@ -11328,7 +11671,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1857]
+    (const void *)&gInstructions[1858]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = 
@@ -11354,7 +11697,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1859]
+    (const void *)&gInstructions[1860]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = 
@@ -11380,7 +11723,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1866]
+    (const void *)&gInstructions[1867]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = 
@@ -11417,7 +11760,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1871]
+    (const void *)&gInstructions[1872]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = 
@@ -11454,7 +11797,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1878]
+    (const void *)&gInstructions[1879]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = 
@@ -11471,7 +11814,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1879]
+    (const void *)&gInstructions[1880]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = 
@@ -11508,7 +11851,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2023]
+    (const void *)&gInstructions[2024]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = 
@@ -11525,7 +11868,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2083]
+    (const void *)&gInstructions[2084]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = 
@@ -11542,7 +11885,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2094]
+    (const void *)&gInstructions[2095]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = 
@@ -11568,7 +11911,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2099]
+    (const void *)&gInstructions[2100]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = 
@@ -11594,7 +11937,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2100]
+    (const void *)&gInstructions[2101]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = 
@@ -11611,7 +11954,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2116]
+    (const void *)&gInstructions[2117]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = 
@@ -11628,7 +11971,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2129]
+    (const void *)&gInstructions[2130]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = 
@@ -11656,7 +11999,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2130]
+    (const void *)&gInstructions[2131]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = 
@@ -11684,7 +12027,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2139]
+    (const void *)&gInstructions[2140]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = 
@@ -11712,7 +12055,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2140]
+    (const void *)&gInstructions[2141]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = 
@@ -11740,7 +12083,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2175]
+    (const void *)&gInstructions[2182]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = 
@@ -11777,7 +12120,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2176]
+    (const void *)&gInstructions[2183]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = 
@@ -11814,13 +12157,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2186]
+    (const void *)&gInstructions[2193]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2187]
+    (const void *)&gInstructions[2194]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = 
@@ -11846,13 +12189,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2188]
+    (const void *)&gInstructions[2195]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2189]
+    (const void *)&gInstructions[2196]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = 
@@ -11878,7 +12221,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2193]
+    (const void *)&gInstructions[2200]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = 
@@ -11904,7 +12247,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2197]
+    (const void *)&gInstructions[2204]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = 
@@ -11930,7 +12273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2201]
+    (const void *)&gInstructions[2208]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = 
@@ -11967,7 +12310,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2207]
+    (const void *)&gInstructions[2214]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = 
@@ -12004,7 +12347,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2221]
+    (const void *)&gInstructions[2228]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = 
@@ -12021,7 +12364,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2222]
+    (const void *)&gInstructions[2229]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = 
@@ -12058,13 +12401,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2225]
+    (const void *)&gInstructions[2232]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2229]
+    (const void *)&gInstructions[2236]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_16_01_mem_00_wi = 
@@ -12090,13 +12433,13 @@ const ND_TABLE_VEX_L gVexTable_root_03_16_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2226]
+    (const void *)&gInstructions[2233]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2230]
+    (const void *)&gInstructions[2237]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_16_01_reg_00_wi = 
@@ -12142,7 +12485,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2235]
+    (const void *)&gInstructions[2242]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = 
@@ -12159,7 +12502,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2236]
+    (const void *)&gInstructions[2243]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = 
@@ -12196,7 +12539,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2269]
+    (const void *)&gInstructions[2276]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = 
@@ -12213,7 +12556,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2270]
+    (const void *)&gInstructions[2277]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = 
@@ -12250,13 +12593,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2272]
+    (const void *)&gInstructions[2279]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2274]
+    (const void *)&gInstructions[2281]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_wi = 
@@ -12293,7 +12636,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2613]
+    (const void *)&gInstructions[2620]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = 
@@ -12310,7 +12653,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2614]
+    (const void *)&gInstructions[2621]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = 
@@ -12327,7 +12670,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2615]
+    (const void *)&gInstructions[2622]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = 
@@ -12344,7 +12687,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2616]
+    (const void *)&gInstructions[2623]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = 
@@ -12358,6 +12701,43 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp =
     }
 };
 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_de_01_00_00_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2667]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_03_de_01_00_w = 
+{
+    ND_ILUT_VEX_W,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_03_de_01_00_00_leaf,
+        /* 01 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_L gVexTable_root_03_de_01_l = 
+{
+    ND_ILUT_VEX_L,
+    { 
+        /* 00 */ (const void *)&gVexTable_root_03_de_01_00_w,
+        /* 01 */ ND_NULL,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
+const ND_TABLE_VEX_PP gVexTable_root_03_de_pp = 
+{
+    ND_ILUT_VEX_PP,
+    { 
+        /* 00 */ ND_NULL,
+        /* 01 */ (const void *)&gVexTable_root_03_de_01_l,
+        /* 02 */ ND_NULL,
+        /* 03 */ ND_NULL,
+    }
+};
+
 const ND_TABLE_OPCODE gVexTable_root_03_opcode = 
 {
     ND_ILUT_OPCODE,
@@ -12584,7 +12964,7 @@ const ND_TABLE_OPCODE gVexTable_root_03_opcode =
         /* db */ ND_NULL,
         /* dc */ ND_NULL,
         /* dd */ ND_NULL,
-        /* de */ ND_NULL,
+        /* de */ (const void *)&gVexTable_root_03_de_pp,
         /* df */ (const void *)&gVexTable_root_03_df_pp,
         /* e0 */ ND_NULL,
         /* e1 */ ND_NULL,
diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h
index 30f31a5..c77115a 100644
--- a/bddisasm/include/table_xop.h
+++ b/bddisasm/include/table_xop.h
@@ -339,13 +339,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1359]
+    (const void *)&gInstructions[1360]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1386]
+    (const void *)&gInstructions[1387]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = 
@@ -399,7 +399,7 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1310]
+    (const void *)&gInstructions[1311]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = 
@@ -429,127 +429,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1824]
+    (const void *)&gInstructions[1825]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1825]
+    (const void *)&gInstructions[1826]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1826]
+    (const void *)&gInstructions[1827]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1827]
+    (const void *)&gInstructions[1828]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2245]
+    (const void *)&gInstructions[2252]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2246]
+    (const void *)&gInstructions[2253]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2247]
+    (const void *)&gInstructions[2254]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2249]
+    (const void *)&gInstructions[2256]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2251]
+    (const void *)&gInstructions[2258]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2252]
+    (const void *)&gInstructions[2259]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2253]
+    (const void *)&gInstructions[2260]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2254]
+    (const void *)&gInstructions[2261]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2255]
+    (const void *)&gInstructions[2262]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2256]
+    (const void *)&gInstructions[2263]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2258]
+    (const void *)&gInstructions[2265]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2259]
+    (const void *)&gInstructions[2266]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2261]
+    (const void *)&gInstructions[2268]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2263]
+    (const void *)&gInstructions[2270]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2266]
+    (const void *)&gInstructions[2273]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2430]
+    (const void *)&gInstructions[2437]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2431]
+    (const void *)&gInstructions[2438]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_90_w = 
@@ -564,13 +564,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2433]
+    (const void *)&gInstructions[2440]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2434]
+    (const void *)&gInstructions[2441]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_92_w = 
@@ -585,13 +585,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2436]
+    (const void *)&gInstructions[2443]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2437]
+    (const void *)&gInstructions[2444]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_93_w = 
@@ -606,13 +606,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2439]
+    (const void *)&gInstructions[2446]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2440]
+    (const void *)&gInstructions[2447]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_91_w = 
@@ -627,13 +627,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2447]
+    (const void *)&gInstructions[2454]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2448]
+    (const void *)&gInstructions[2455]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_98_w = 
@@ -648,13 +648,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2449]
+    (const void *)&gInstructions[2456]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2450]
+    (const void *)&gInstructions[2457]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9a_w = 
@@ -669,13 +669,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2451]
+    (const void *)&gInstructions[2458]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2452]
+    (const void *)&gInstructions[2459]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9b_w = 
@@ -690,13 +690,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2453]
+    (const void *)&gInstructions[2460]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2454]
+    (const void *)&gInstructions[2461]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_99_w = 
@@ -711,13 +711,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2455]
+    (const void *)&gInstructions[2462]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2456]
+    (const void *)&gInstructions[2463]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_94_w = 
@@ -732,13 +732,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2457]
+    (const void *)&gInstructions[2464]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2468]
+    (const void *)&gInstructions[2475]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_95_w = 
@@ -753,13 +753,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2458]
+    (const void *)&gInstructions[2465]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2459]
+    (const void *)&gInstructions[2466]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_96_w = 
@@ -774,13 +774,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2466]
+    (const void *)&gInstructions[2473]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2467]
+    (const void *)&gInstructions[2474]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_97_w = 
@@ -1058,13 +1058,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2117]
+    (const void *)&gInstructions[2118]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2118]
+    (const void *)&gInstructions[2119]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a2_w = 
@@ -1079,133 +1079,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2147]
+    (const void *)&gInstructions[2148]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2148]
+    (const void *)&gInstructions[2149]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2153]
+    (const void *)&gInstructions[2154]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2154]
+    (const void *)&gInstructions[2155]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2155]
+    (const void *)&gInstructions[2156]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2156]
+    (const void *)&gInstructions[2157]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2157]
+    (const void *)&gInstructions[2158]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2158]
+    (const void *)&gInstructions[2159]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2281]
+    (const void *)&gInstructions[2288]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2282]
+    (const void *)&gInstructions[2289]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2283]
+    (const void *)&gInstructions[2290]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2284]
+    (const void *)&gInstructions[2291]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2285]
+    (const void *)&gInstructions[2292]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2286]
+    (const void *)&gInstructions[2293]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2287]
+    (const void *)&gInstructions[2294]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2288]
+    (const void *)&gInstructions[2295]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2289]
+    (const void *)&gInstructions[2296]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2290]
+    (const void *)&gInstructions[2297]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2291]
+    (const void *)&gInstructions[2298]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2292]
+    (const void *)&gInstructions[2299]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2419]
+    (const void *)&gInstructions[2426]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2420]
+    (const void *)&gInstructions[2427]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a3_w = 
@@ -1220,25 +1220,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2429]
+    (const void *)&gInstructions[2436]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2432]
+    (const void *)&gInstructions[2439]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2435]
+    (const void *)&gInstructions[2442]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2438]
+    (const void *)&gInstructions[2445]
 };
 
 const ND_TABLE_OPCODE gXopTable_root_08_opcode = 
diff --git a/bddisasm_test/x86/avx/avxvnniint16_64.asm b/bddisasm_test/x86/avx/avxvnniint16_64.asm
new file mode 100644
index 0000000..e6a047c
--- /dev/null
+++ b/bddisasm_test/x86/avx/avxvnniint16_64.asm
@@ -0,0 +1,35 @@
+        bits 64
+        
+        db 0xc4, 0x62, 0x78, 0xd2, 0xc7         ; VPDPWUUD  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x78, 0xd2, 0x01         ; VPDPWUUD  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x78, 0xd3, 0xc7         ; VPDPWUUDS xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x78, 0xd3, 0x01         ; VPDPWUUDS xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x79, 0xd2, 0xc7         ; VPDPWUSD  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x79, 0xd2, 0x01         ; VPDPWUSD  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x79, 0xd3, 0xc7         ; VPDPWUSDS xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x79, 0xd3, 0x01         ; VPDPWUSDS xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7a, 0xd2, 0xc7         ; VPDPWSUD  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7a, 0xd2, 0x01         ; VPDPWSUD  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x7a, 0xd3, 0xc7         ; VPDPWSUDS xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7a, 0xd3, 0x01         ; VPDPWSUDS xmm8, xmm0, xmmword ptr [rcx]
+        
+        
+        db 0xc4, 0x62, 0x7c, 0xd2, 0xc7         ; VPDPWUUD  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7c, 0xd2, 0x01         ; VPDPWUUD  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7c, 0xd3, 0xc7         ; VPDPWUUDS ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7c, 0xd3, 0x01         ; VPDPWUUDS ymm8, ymm0, ymmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7d, 0xd2, 0xc7         ; VPDPWUSD  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7d, 0xd2, 0x01         ; VPDPWUSD  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7d, 0xd3, 0xc7         ; VPDPWUSDS ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7d, 0xd3, 0x01         ; VPDPWUSDS ymm8, ymm0, ymmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7e, 0xd2, 0xc7         ; VPDPWSUD  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7e, 0xd2, 0x01         ; VPDPWSUD  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7e, 0xd3, 0xc7         ; VPDPWSUDS ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7e, 0xd3, 0x01         ; VPDPWSUDS ymm8, ymm0, ymmword ptr [rcx]
+        
+        
+    
\ No newline at end of file
diff --git a/bddisasm_test/x86/avx/avxvnniint16_64.result b/bddisasm_test/x86/avx/avxvnniint16_64.result
new file mode 100644
index 0000000..2c3c1ed
--- /dev/null
+++ b/bddisasm_test/x86/avx/avxvnniint16_64.result
@@ -0,0 +1,444 @@
+0000000000000000 c46278d2c7                      VPDPWUUD  xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000005 c46278d201                      VPDPWUUD  xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000000A c46278d3c7                      VPDPWUUDS xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+000000000000000F c46278d301                      VPDPWUUDS xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000014 c46279d2c7                      VPDPWUSD  xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000019 c46279d201                      VPDPWUSD  xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000001E c46279d3c7                      VPDPWUSDS xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000023 c46279d301                      VPDPWUSDS xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000028 c4627ad2c7                      VPDPWSUD  xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+000000000000002D c4627ad201                      VPDPWSUD  xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000032 c4627ad3c7                      VPDPWSUDS xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000037 c4627ad301                      VPDPWSUDS xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000003C c4627cd2c7                      VPDPWUUD  ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+0000000000000041 c4627cd201                      VPDPWUUD  ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000046 c4627cd3c7                      VPDPWUUDS ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+000000000000004B c4627cd301                      VPDPWUUDS ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000050 c4627dd2c7                      VPDPWUSD  ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+0000000000000055 c4627dd201                      VPDPWUSD  ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000005A c4627dd3c7                      VPDPWUSDS ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+000000000000005F c4627dd301                      VPDPWUSDS ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000064 c4627ed2c7                      VPDPWSUD  ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+0000000000000069 c4627ed201                      VPDPWSUD  ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000006E c4627ed3c7                      VPDPWSUDS ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+0000000000000073 c4627ed301                      VPDPWSUDS ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: AVXVNNIINT16, Ins cat: AVXVNNIINT16, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 10
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
diff --git a/bddisasm_test/x86/avx/avxvnniint16_64.test b/bddisasm_test/x86/avx/avxvnniint16_64.test
new file mode 100644
index 0000000..8bde97b
--- /dev/null
+++ b/bddisasm_test/x86/avx/avxvnniint16_64.test
@@ -0,0 +1 @@
+ÄbxÒÇÄbxÒ
ÄbxÓÇÄbxÓ
ÄbyÒÇÄbyÒ
ÄbyÓÇÄbyÓ
ÄbzÒÇÄbzÒ
ÄbzÓÇÄbzÓ
Äb|ÒÇÄb|Ò
Äb|ÓÇÄb|Ó
Äb}ÒÇÄb}Ò
Äb}ÓÇÄb}Ó
Äb~ÒÇÄb~Ò
Äb~ÓÇÄb~Ó

\ No newline at end of file
diff --git a/bddisasm_test/x86/sha512/sha512_64.asm b/bddisasm_test/x86/sha512/sha512_64.asm
new file mode 100644
index 0000000..9826c9b
--- /dev/null
+++ b/bddisasm_test/x86/sha512/sha512_64.asm
@@ -0,0 +1,7 @@
+        bits 64
+        
+        db 0xc4, 0x62, 0x7f, 0xcb, 0xc7         ; VSHA512RNDS2 ymm8, ymm0, xmm7
+        db 0xc4, 0x62, 0x7f, 0xcc, 0xc7         ; VSHA512MSG1 ymm8, xmm7
+        db 0xc4, 0x62, 0x7f, 0xcd, 0xc7         ; VSHA512MSG2 ymm8, ymm7
+        db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
\ No newline at end of file
diff --git a/bddisasm_test/x86/sha512/sha512_64.result b/bddisasm_test/x86/sha512/sha512_64.result
new file mode 100644
index 0000000..0250a99
--- /dev/null
+++ b/bddisasm_test/x86/sha512/sha512_64.result
@@ -0,0 +1,91 @@
+0000000000000000 c4627fcbc7                      VSHA512RNDS2 ymm8, ymm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000005 c4627fccc7                      VSHA512MSG1 ymm8, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+000000000000000A c4627fcdc7                      VSHA512MSG2 ymm8, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SHA512, Ins cat: SHA512, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 0
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+000000000000000F c46379dec7ef                    VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+
+0000000000000015 c46379de01ef                    VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+        Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+
diff --git a/bddisasm_test/x86/sha512/sha512_64.test b/bddisasm_test/x86/sha512/sha512_64.test
new file mode 100644
index 0000000..6dc7f94
--- /dev/null
+++ b/bddisasm_test/x86/sha512/sha512_64.test
@@ -0,0 +1 @@
+ÄbËÇÄbÌÇÄbÍÇÄcyÞÇïÄcyÞ
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\ No newline at end of file
diff --git a/bddisasm_test/x86/sm/sm_64.asm b/bddisasm_test/x86/sm/sm_64.asm
new file mode 100644
index 0000000..fc52ba5
--- /dev/null
+++ b/bddisasm_test/x86/sm/sm_64.asm
@@ -0,0 +1,19 @@
+        bits 64
+        
+        db 0xc4, 0x62, 0x78, 0xda, 0xc7         ; VSM3MSG1  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x78, 0xda, 0x01         ; VSM3MSG1  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x79, 0xda, 0xc7         ; VSM3MSG2  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x79, 0xda, 0x01         ; VSM3MSG2  xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7a, 0xda, 0xc7         ; VSM4KEY4  xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7a, 0xda, 0x01         ; VSM4KEY4  xmm8, xmm0, xmmword ptr [rcx]
+        db 0xc4, 0x62, 0x7b, 0xda, 0xc7         ; VSM4RNDS4 xmm8, xmm0, xmm7
+        db 0xc4, 0x62, 0x7b, 0xda, 0x01         ; VSM4RNDS4 xmm8, xmm0, xmmword ptr [rcx]
+        
+        db 0xc4, 0x62, 0x7e, 0xda, 0xc7         ; VSM4KEY4  ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7e, 0xda, 0x01         ; VSM4KEY4  ymm8, ymm0, ymmword ptr [rcx]
+        db 0xc4, 0x62, 0x7f, 0xda, 0xc7         ; VSM4RNDS4 ymm8, ymm0, ymm7
+        db 0xc4, 0x62, 0x7f, 0xda, 0x01         ; VSM4RNDS4 ymm8, ymm0, ymmword ptr [rcx]
+        
+        db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef   ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
\ No newline at end of file
diff --git a/bddisasm_test/x86/sm/sm_64.result b/bddisasm_test/x86/sm/sm_64.result
new file mode 100644
index 0000000..8730d8c
--- /dev/null
+++ b/bddisasm_test/x86/sm/sm_64.result
@@ -0,0 +1,261 @@
+0000000000000000 c46278dac7                      VSM3MSG1  xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000005 c46278da01                      VSM3MSG1  xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000000A c46279dac7                      VSM3MSG2  xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+000000000000000F c46279da01                      VSM3MSG2  xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000014 c4627adac7                      VSM4KEY4  xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000019 c4627ada01                      VSM4KEY4  xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000001E c4627bdac7                      VSM4RNDS4 xmm8, xmm0, xmm7
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+
+0000000000000023 c4627bda01                      VSM4RNDS4 xmm8, xmm0, xmmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000028 c4627edac7                      VSM4KEY4  ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+000000000000002D c4627eda01                      VSM4KEY4  ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+0000000000000032 c4627fdac7                      VSM4RNDS4 ymm8, ymm0, ymm7
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: M, RegType:           Vector, RegSize: 32, RegId: 7, RegCount: 1
+
+0000000000000037 c4627fda01                      VSM4RNDS4 ymm8, ymm0, ymmword ptr [rcx]
+        DSIZE: 32, ASIZE: 64, VLEN: 256
+        ISA Set: SM4, Ins cat: SM4, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
+        Exception class: SSE/VEX, exception type: 6
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: V, RegType:           Vector, RegSize: 32, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, 
+                Segment: 3, Base: 1, 
+
+000000000000003C c46379dec7ef                    VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+
+0000000000000042 c46379de01ef                    VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: SM3, Ins cat: SM3, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 1
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 8, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+                Segment: 3, Base: 1, 
+        Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+
diff --git a/bddisasm_test/x86/sm/sm_64.test b/bddisasm_test/x86/sm/sm_64.test
new file mode 100644
index 0000000..2e0c1bb
--- /dev/null
+++ b/bddisasm_test/x86/sm/sm_64.test
@@ -0,0 +1 @@
+ÄbxÚÇÄbxÚ
ÄbyÚÇÄbyÚ
ÄbzÚÇÄbzÚ
Äb{ÚÇÄb{Ú
Äb~ÚÇÄb~Ú
ÄbÚÇÄbÚ
ÄcyÞÇïÄcyÞ
ï
\ No newline at end of file
diff --git a/bddisasm_test/x86/tse/tse_64.asm b/bddisasm_test/x86/tse/tse_64.asm
new file mode 100644
index 0000000..80f6169
--- /dev/null
+++ b/bddisasm_test/x86/tse/tse_64.asm
@@ -0,0 +1,3 @@
+    bits 64
+    
+    db 0x0f, 0x01, 0xc7         ; PBNDKB
\ No newline at end of file
diff --git a/bddisasm_test/x86/tse/tse_64.result b/bddisasm_test/x86/tse/tse_64.result
new file mode 100644
index 0000000..416a99c
--- /dev/null
+++ b/bddisasm_test/x86/tse/tse_64.result
@@ -0,0 +1,20 @@
+0000000000000000 0f01c7                          PBNDKB
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: TSE, Ins cat: SYSTEM, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ebx, bit: 1
+        FLAGS access
+                CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, 
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
+                SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
+                VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 3, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 1, RegCount: 1
+        Operand: 3, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
diff --git a/bddisasm_test/x86/tse/tse_64.test b/bddisasm_test/x86/tse/tse_64.test
new file mode 100644
index 0000000..3393771
--- /dev/null
+++ b/bddisasm_test/x86/tse/tse_64.test
@@ -0,0 +1 @@
+
Ç
\ No newline at end of file
diff --git a/bindings/pybddisasm/setup.py b/bindings/pybddisasm/setup.py
index 2ceede3..2e7ef9e 100644
--- a/bindings/pybddisasm/setup.py
+++ b/bindings/pybddisasm/setup.py
@@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
 from codecs import open
 
 VERSION = (0, 3, 0)
-LIBRARY_VERSION = (1, 37, 0)
+LIBRARY_VERSION = (1, 38, 0)
 DIR_INCLUDE = '../../inc'
 
 here = os.path.abspath(os.path.dirname(__file__))
diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c
index 5a9e3e3..5073c42 100644
--- a/disasmtool/disasmtool.c
+++ b/disasmtool/disasmtool.c
@@ -136,6 +136,7 @@ set_to_string(
     case ND_SET_AVXNECONVERT:          return "AVXNECONVERT";
     case ND_SET_AVXVNNI:               return "AVXVNNI";
     case ND_SET_AVXVNNIINT8:           return "AVXVNNIINT8";
+    case ND_SET_AVXVNNIINT16:          return "AVXVNNIINT16";
     case ND_SET_BMI1:                  return "BMI1";
     case ND_SET_BMI2:                  return "BMI2";
     case ND_SET_CET_SS:                return "CET_SS";
@@ -201,6 +202,9 @@ set_to_string(
     case ND_SET_SERIALIZE:             return "SERIALIZE";
     case ND_SET_SGX:                   return "SGX";
     case ND_SET_SHA:                   return "SHA";
+    case ND_SET_SHA512:                return "SHA512";
+    case ND_SET_SM3:                   return "SM3";
+    case ND_SET_SM4:                   return "SM4";
     case ND_SET_SMAP:                  return "SMAP";
     case ND_SET_SMX:                   return "SMX";
     case ND_SET_SNP:                   return "SNP";
@@ -214,6 +218,7 @@ set_to_string(
     case ND_SET_SVM:                   return "SVM";
     case ND_SET_TBM:                   return "TBM";
     case ND_SET_TDX:                   return "TDX";
+    case ND_SET_TSE:                   return "TSE";
     case ND_SET_TSX:                   return "TSX";
     case ND_SET_TSXLDTRK:              return "TSXLDTRK";
     case ND_SET_UD:                    return "UD";
@@ -258,6 +263,7 @@ category_to_string(
     case ND_CAT_AVXIFMA:              return "AVXIFMA";
     case ND_CAT_AVXVNNI:              return "AVXVNNI";
     case ND_CAT_AVXVNNIINT8:          return "AVXVNNIINT8";
+    case ND_CAT_AVXVNNIINT16:         return "AVXVNNIINT16";
     case ND_CAT_AVXNECONVERT:         return "AVXNECONVERT";
     case ND_CAT_BITBYTE:              return "BITBYTE";
     case ND_CAT_BLEND:                return "BLEND";
@@ -321,7 +327,10 @@ category_to_string(
     case ND_CAT_SEMAPHORE:            return "SEMAPHORE";
     case ND_CAT_SGX:                  return "SGX";
     case ND_CAT_SHA:                  return "SHA";
+    case ND_CAT_SHA512:               return "SHA512";
     case ND_CAT_SHIFT:                return "SHIFT";
+    case ND_CAT_SM3:                  return "SM3";
+    case ND_CAT_SM4:                  return "SM4";
     case ND_CAT_SMAP:                 return "SMAP";
     case ND_CAT_SSE:                  return "SSE";
     case ND_CAT_SSE2:                 return "SSE2";
diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp
index de94d45..abf94b6 100644
--- a/disasmtool_lix/dumpers.cpp
+++ b/disasmtool_lix/dumpers.cpp
@@ -70,7 +70,9 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_INVALID: return "invalid";
     case ND_INS_AAA: return "aaa";
     case ND_INS_AAD: return "aad";
+    case ND_INS_AADD: return "aadd";
     case ND_INS_AAM: return "aam";
+    case ND_INS_AAND: return "aand";
     case ND_INS_AAS: return "aas";
     case ND_INS_ADC: return "adc";
     case ND_INS_ADCX: return "adcx";
@@ -85,15 +87,15 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_AESDEC: return "aesdec";
     case ND_INS_AESDEC128KL: return "aesdec128kl";
     case ND_INS_AESDEC256KL: return "aesdec256kl";
+    case ND_INS_AESDECLAST: return "aesdeclast";
     case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl";
     case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl";
-    case ND_INS_AESDECLAST: return "aesdeclast";
     case ND_INS_AESENC: return "aesenc";
     case ND_INS_AESENC128KL: return "aesenc128kl";
     case ND_INS_AESENC256KL: return "aesenc256kl";
+    case ND_INS_AESENCLAST: return "aesenclast";
     case ND_INS_AESENCWIDE128KL: return "aesencwide128kl";
     case ND_INS_AESENCWIDE256KL: return "aesencwide256kl";
-    case ND_INS_AESENCLAST: return "aesenclast";
     case ND_INS_AESIMC: return "aesimc";
     case ND_INS_AESKEYGENASSIST: return "aeskeygenassist";
     case ND_INS_ALTINST: return "altinst";
@@ -103,7 +105,9 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_ANDNPS: return "andnps";
     case ND_INS_ANDPD: return "andpd";
     case ND_INS_ANDPS: return "andps";
+    case ND_INS_AOR: return "aor";
     case ND_INS_ARPL: return "arpl";
+    case ND_INS_AXOR: return "axor";
     case ND_INS_BEXTR: return "bextr";
     case ND_INS_BLCFILL: return "blcfill";
     case ND_INS_BLCI: return "blci";
@@ -154,19 +158,36 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_CLI: return "cli";
     case ND_INS_CLRSSBSY: return "clrssbsy";
     case ND_INS_CLTS: return "clts";
+    case ND_INS_CLUI: return "clui";
     case ND_INS_CLWB: return "clwb";
     case ND_INS_CLZERO: return "clzero";
     case ND_INS_CMC: return "cmc";
     case ND_INS_CMOVcc: return "cmovcc";
     case ND_INS_CMP: return "cmp";
+    case ND_INS_CMPBEXADD: return "cmpbexadd";
+    case ND_INS_CMPCXADD: return "cmpcxadd";
+    case ND_INS_CMPLEXADD: return "cmplexadd";
+    case ND_INS_CMPLXADD: return "cmplxadd";
+    case ND_INS_CMPNBEXADD: return "cmpnbexadd";
+    case ND_INS_CMPNCXADD: return "cmpncxadd";
+    case ND_INS_CMPNLEXADD: return "cmpnlexadd";
+    case ND_INS_CMPNLXADD: return "cmpnlxadd";
+    case ND_INS_CMPNOXADD: return "cmpnoxadd";
+    case ND_INS_CMPNPXADD: return "cmpnpxadd";
+    case ND_INS_CMPNSXADD: return "cmpnsxadd";
+    case ND_INS_CMPNZXADD: return "cmpnzxadd";
+    case ND_INS_CMPOXADD: return "cmpoxadd";
     case ND_INS_CMPPD: return "cmppd";
     case ND_INS_CMPPS: return "cmpps";
+    case ND_INS_CMPPXADD: return "cmppxadd";
     case ND_INS_CMPS: return "cmps";
     case ND_INS_CMPSD: return "cmpsd";
     case ND_INS_CMPSS: return "cmpss";
+    case ND_INS_CMPSXADD: return "cmpsxadd";
     case ND_INS_CMPXCHG: return "cmpxchg";
     case ND_INS_CMPXCHG16B: return "cmpxchg16b";
     case ND_INS_CMPXCHG8B: return "cmpxchg8b";
+    case ND_INS_CMPZXADD: return "cmpzxadd";
     case ND_INS_COMISD: return "comisd";
     case ND_INS_COMISS: return "comiss";
     case ND_INS_CPUID: return "cpuid";
@@ -328,6 +349,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_HADDPD: return "haddpd";
     case ND_INS_HADDPS: return "haddps";
     case ND_INS_HLT: return "hlt";
+    case ND_INS_HRESET: return "hreset";
     case ND_INS_HSUBPD: return "hsubpd";
     case ND_INS_HSUBPS: return "hsubps";
     case ND_INS_IDIV: return "idiv";
@@ -501,6 +523,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_PAVGW: return "pavgw";
     case ND_INS_PBLENDVB: return "pblendvb";
     case ND_INS_PBLENDW: return "pblendw";
+    case ND_INS_PBNDKB: return "pbndkb";
     case ND_INS_PCLMULQDQ: return "pclmulqdq";
     case ND_INS_PCMPEQB: return "pcmpeqb";
     case ND_INS_PCMPEQD: return "pcmpeqd";
@@ -598,6 +621,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_POR: return "por";
     case ND_INS_PREFETCH: return "prefetch";
     case ND_INS_PREFETCHE: return "prefetche";
+    case ND_INS_PREFETCHIT0: return "prefetchit0";
+    case ND_INS_PREFETCHIT1: return "prefetchit1";
     case ND_INS_PREFETCHM: return "prefetchm";
     case ND_INS_PREFETCHNTA: return "prefetchnta";
     case ND_INS_PREFETCHT0: return "prefetcht0";
@@ -657,6 +682,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_RDFSBASE: return "rdfsbase";
     case ND_INS_RDGSBASE: return "rdgsbase";
     case ND_INS_RDMSR: return "rdmsr";
+    case ND_INS_RDMSRLIST: return "rdmsrlist";
     case ND_INS_RDPID: return "rdpid";
     case ND_INS_RDPKRU: return "rdpkru";
     case ND_INS_RDPMC: return "rdpmc";
@@ -669,6 +695,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_RETF: return "retf";
     case ND_INS_RETN: return "retn";
     case ND_INS_RMPADJUST: return "rmpadjust";
+    case ND_INS_RMPQUERY: return "rmpquery";
     case ND_INS_RMPUPDATE: return "rmpupdate";
     case ND_INS_ROL: return "rol";
     case ND_INS_ROR: return "ror";
@@ -696,6 +723,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_SEAMOPS: return "seamops";
     case ND_INS_SEAMCALL: return "seamcall";
     case ND_INS_SEAMRET: return "seamret";
+    case ND_INS_SENDUIPI: return "senduipi";
     case ND_INS_SERIALIZE: return "serialize";
     case ND_INS_SETSSBSY: return "setssbsy";
     case ND_INS_SETcc: return "setcc";
@@ -736,6 +764,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_STOS: return "stos";
     case ND_INS_STR: return "str";
     case ND_INS_STTILECFG: return "sttilecfg";
+    case ND_INS_STUI: return "stui";
     case ND_INS_SUB: return "sub";
     case ND_INS_SUBPD: return "subpd";
     case ND_INS_SUBPS: return "subps";
@@ -750,13 +779,17 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_SYSEXIT: return "sysexit";
     case ND_INS_SYSRET: return "sysret";
     case ND_INS_T1MSKC: return "t1mskc";
+    case ND_INS_TCMMIMFP16PS: return "tcmmimfp16ps";
+    case ND_INS_TCMMRLFP16PS: return "tcmmrlfp16ps";
     case ND_INS_TDCALL: return "tdcall";
     case ND_INS_TDPBF16PS: return "tdpbf16ps";
     case ND_INS_TDPBSSD: return "tdpbssd";
     case ND_INS_TDPBSUD: return "tdpbsud";
     case ND_INS_TDPBUSD: return "tdpbusd";
     case ND_INS_TDPBUUD: return "tdpbuud";
+    case ND_INS_TDPFP16PS: return "tdpfp16ps";
     case ND_INS_TEST: return "test";
+    case ND_INS_TESTUI: return "testui";
     case ND_INS_TILELOADD: return "tileloadd";
     case ND_INS_TILELOADDT1: return "tileloaddt1";
     case ND_INS_TILERELEASE: return "tilerelease";
@@ -771,6 +804,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_UD0: return "ud0";
     case ND_INS_UD1: return "ud1";
     case ND_INS_UD2: return "ud2";
+    case ND_INS_UIRET: return "uiret";
     case ND_INS_UMONITOR: return "umonitor";
     case ND_INS_UMWAIT: return "umwait";
     case ND_INS_UNPCKHPD: return "unpckhpd";
@@ -782,8 +816,10 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_V4FNMADDPS: return "v4fnmaddps";
     case ND_INS_V4FNMADDSS: return "v4fnmaddss";
     case ND_INS_VADDPD: return "vaddpd";
+    case ND_INS_VADDPH: return "vaddph";
     case ND_INS_VADDPS: return "vaddps";
     case ND_INS_VADDSD: return "vaddsd";
+    case ND_INS_VADDSH: return "vaddsh";
     case ND_INS_VADDSS: return "vaddss";
     case ND_INS_VADDSUBPD: return "vaddsubpd";
     case ND_INS_VADDSUBPS: return "vaddsubps";
@@ -799,6 +835,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VANDNPS: return "vandnps";
     case ND_INS_VANDPD: return "vandpd";
     case ND_INS_VANDPS: return "vandps";
+    case ND_INS_VBCSTNEBF162PS: return "vbcstnebf162ps";
+    case ND_INS_VBCSTNESH2PS: return "vbcstnesh2ps";
     case ND_INS_VBLENDMPD: return "vblendmpd";
     case ND_INS_VBLENDMPS: return "vblendmps";
     case ND_INS_VBLENDPD: return "vblendpd";
@@ -820,61 +858,102 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VBROADCASTSD: return "vbroadcastsd";
     case ND_INS_VBROADCASTSS: return "vbroadcastss";
     case ND_INS_VCMPPD: return "vcmppd";
+    case ND_INS_VCMPPH: return "vcmpph";
     case ND_INS_VCMPPS: return "vcmpps";
     case ND_INS_VCMPSD: return "vcmpsd";
+    case ND_INS_VCMPSH: return "vcmpsh";
     case ND_INS_VCMPSS: return "vcmpss";
     case ND_INS_VCOMISD: return "vcomisd";
+    case ND_INS_VCOMISH: return "vcomish";
     case ND_INS_VCOMISS: return "vcomiss";
     case ND_INS_VCOMPRESSPD: return "vcompresspd";
     case ND_INS_VCOMPRESSPS: return "vcompressps";
     case ND_INS_VCVTDQ2PD: return "vcvtdq2pd";
+    case ND_INS_VCVTDQ2PH: return "vcvtdq2ph";
     case ND_INS_VCVTDQ2PS: return "vcvtdq2ps";
     case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16";
+    case ND_INS_VCVTNEEBF162PS: return "vcvtneebf162ps";
+    case ND_INS_VCVTNEEPH2PS: return "vcvtneeph2ps";
+    case ND_INS_VCVTNEOBF162PS: return "vcvtneobf162ps";
+    case ND_INS_VCVTNEOPH2PS: return "vcvtneoph2ps";
     case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16";
     case ND_INS_VCVTPD2DQ: return "vcvtpd2dq";
+    case ND_INS_VCVTPD2PH: return "vcvtpd2ph";
     case ND_INS_VCVTPD2PS: return "vcvtpd2ps";
     case ND_INS_VCVTPD2QQ: return "vcvtpd2qq";
     case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq";
     case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq";
+    case ND_INS_VCVTPH2DQ: return "vcvtph2dq";
+    case ND_INS_VCVTPH2PD: return "vcvtph2pd";
     case ND_INS_VCVTPH2PS: return "vcvtph2ps";
+    case ND_INS_VCVTPH2PSX: return "vcvtph2psx";
+    case ND_INS_VCVTPH2QQ: return "vcvtph2qq";
+    case ND_INS_VCVTPH2UDQ: return "vcvtph2udq";
+    case ND_INS_VCVTPH2UQQ: return "vcvtph2uqq";
+    case ND_INS_VCVTPH2UW: return "vcvtph2uw";
+    case ND_INS_VCVTPH2W: return "vcvtph2w";
     case ND_INS_VCVTPS2DQ: return "vcvtps2dq";
     case ND_INS_VCVTPS2PD: return "vcvtps2pd";
     case ND_INS_VCVTPS2PH: return "vcvtps2ph";
+    case ND_INS_VCVTPS2PHX: return "vcvtps2phx";
     case ND_INS_VCVTPS2QQ: return "vcvtps2qq";
     case ND_INS_VCVTPS2UDQ: return "vcvtps2udq";
     case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq";
     case ND_INS_VCVTQQ2PD: return "vcvtqq2pd";
+    case ND_INS_VCVTQQ2PH: return "vcvtqq2ph";
     case ND_INS_VCVTQQ2PS: return "vcvtqq2ps";
+    case ND_INS_VCVTSD2SH: return "vcvtsd2sh";
     case ND_INS_VCVTSD2SI: return "vcvtsd2si";
     case ND_INS_VCVTSD2SS: return "vcvtsd2ss";
     case ND_INS_VCVTSD2USI: return "vcvtsd2usi";
+    case ND_INS_VCVTSH2SD: return "vcvtsh2sd";
+    case ND_INS_VCVTSH2SI: return "vcvtsh2si";
+    case ND_INS_VCVTSH2SS: return "vcvtsh2ss";
+    case ND_INS_VCVTSH2USI: return "vcvtsh2usi";
     case ND_INS_VCVTSI2SD: return "vcvtsi2sd";
+    case ND_INS_VCVTSI2SH: return "vcvtsi2sh";
     case ND_INS_VCVTSI2SS: return "vcvtsi2ss";
     case ND_INS_VCVTSS2SD: return "vcvtss2sd";
+    case ND_INS_VCVTSS2SH: return "vcvtss2sh";
     case ND_INS_VCVTSS2SI: return "vcvtss2si";
     case ND_INS_VCVTSS2USI: return "vcvtss2usi";
     case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq";
     case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq";
     case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq";
     case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq";
+    case ND_INS_VCVTTPH2DQ: return "vcvttph2dq";
+    case ND_INS_VCVTTPH2QQ: return "vcvttph2qq";
+    case ND_INS_VCVTTPH2UDQ: return "vcvttph2udq";
+    case ND_INS_VCVTTPH2UQQ: return "vcvttph2uqq";
+    case ND_INS_VCVTTPH2UW: return "vcvttph2uw";
+    case ND_INS_VCVTTPH2W: return "vcvttph2w";
     case ND_INS_VCVTTPS2DQ: return "vcvttps2dq";
     case ND_INS_VCVTTPS2QQ: return "vcvttps2qq";
     case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq";
     case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq";
     case ND_INS_VCVTTSD2SI: return "vcvttsd2si";
     case ND_INS_VCVTTSD2USI: return "vcvttsd2usi";
+    case ND_INS_VCVTTSH2SI: return "vcvttsh2si";
+    case ND_INS_VCVTTSH2USI: return "vcvttsh2usi";
     case ND_INS_VCVTTSS2SI: return "vcvttss2si";
     case ND_INS_VCVTTSS2USI: return "vcvttss2usi";
     case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd";
+    case ND_INS_VCVTUDQ2PH: return "vcvtudq2ph";
     case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps";
     case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd";
+    case ND_INS_VCVTUQQ2PH: return "vcvtuqq2ph";
     case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps";
     case ND_INS_VCVTUSI2SD: return "vcvtusi2sd";
+    case ND_INS_VCVTUSI2SH: return "vcvtusi2sh";
     case ND_INS_VCVTUSI2SS: return "vcvtusi2ss";
+    case ND_INS_VCVTUW2PH: return "vcvtuw2ph";
+    case ND_INS_VCVTW2PH: return "vcvtw2ph";
     case ND_INS_VDBPSADBW: return "vdbpsadbw";
     case ND_INS_VDIVPD: return "vdivpd";
+    case ND_INS_VDIVPH: return "vdivph";
     case ND_INS_VDIVPS: return "vdivps";
     case ND_INS_VDIVSD: return "vdivsd";
+    case ND_INS_VDIVSH: return "vdivsh";
     case ND_INS_VDIVSS: return "vdivss";
     case ND_INS_VDPBF16PS: return "vdpbf16ps";
     case ND_INS_VDPPD: return "vdppd";
@@ -896,51 +975,75 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VEXTRACTI64X2: return "vextracti64x2";
     case ND_INS_VEXTRACTI64X4: return "vextracti64x4";
     case ND_INS_VEXTRACTPS: return "vextractps";
+    case ND_INS_VFCMADDCPH: return "vfcmaddcph";
+    case ND_INS_VFCMADDCSH: return "vfcmaddcsh";
+    case ND_INS_VFCMULCPH: return "vfcmulcph";
+    case ND_INS_VFCMULCSH: return "vfcmulcsh";
     case ND_INS_VFIXUPIMMPD: return "vfixupimmpd";
     case ND_INS_VFIXUPIMMPS: return "vfixupimmps";
     case ND_INS_VFIXUPIMMSD: return "vfixupimmsd";
     case ND_INS_VFIXUPIMMSS: return "vfixupimmss";
     case ND_INS_VFMADD132PD: return "vfmadd132pd";
+    case ND_INS_VFMADD132PH: return "vfmadd132ph";
     case ND_INS_VFMADD132PS: return "vfmadd132ps";
     case ND_INS_VFMADD132SD: return "vfmadd132sd";
+    case ND_INS_VFMADD132SH: return "vfmadd132sh";
     case ND_INS_VFMADD132SS: return "vfmadd132ss";
     case ND_INS_VFMADD213PD: return "vfmadd213pd";
+    case ND_INS_VFMADD213PH: return "vfmadd213ph";
     case ND_INS_VFMADD213PS: return "vfmadd213ps";
     case ND_INS_VFMADD213SD: return "vfmadd213sd";
+    case ND_INS_VFMADD213SH: return "vfmadd213sh";
     case ND_INS_VFMADD213SS: return "vfmadd213ss";
     case ND_INS_VFMADD231PD: return "vfmadd231pd";
+    case ND_INS_VFMADD231PH: return "vfmadd231ph";
     case ND_INS_VFMADD231PS: return "vfmadd231ps";
     case ND_INS_VFMADD231SD: return "vfmadd231sd";
+    case ND_INS_VFMADD231SH: return "vfmadd231sh";
     case ND_INS_VFMADD231SS: return "vfmadd231ss";
+    case ND_INS_VFMADDCPH: return "vfmaddcph";
+    case ND_INS_VFMADDCSH: return "vfmaddcsh";
     case ND_INS_VFMADDPD: return "vfmaddpd";
     case ND_INS_VFMADDPS: return "vfmaddps";
     case ND_INS_VFMADDSD: return "vfmaddsd";
     case ND_INS_VFMADDSS: return "vfmaddss";
     case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd";
+    case ND_INS_VFMADDSUB132PH: return "vfmaddsub132ph";
     case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps";
     case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd";
+    case ND_INS_VFMADDSUB213PH: return "vfmaddsub213ph";
     case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps";
     case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd";
+    case ND_INS_VFMADDSUB231PH: return "vfmaddsub231ph";
     case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps";
     case ND_INS_VFMADDSUBPD: return "vfmaddsubpd";
     case ND_INS_VFMADDSUBPS: return "vfmaddsubps";
     case ND_INS_VFMSUB132PD: return "vfmsub132pd";
+    case ND_INS_VFMSUB132PH: return "vfmsub132ph";
     case ND_INS_VFMSUB132PS: return "vfmsub132ps";
     case ND_INS_VFMSUB132SD: return "vfmsub132sd";
+    case ND_INS_VFMSUB132SH: return "vfmsub132sh";
     case ND_INS_VFMSUB132SS: return "vfmsub132ss";
     case ND_INS_VFMSUB213PD: return "vfmsub213pd";
+    case ND_INS_VFMSUB213PH: return "vfmsub213ph";
     case ND_INS_VFMSUB213PS: return "vfmsub213ps";
     case ND_INS_VFMSUB213SD: return "vfmsub213sd";
+    case ND_INS_VFMSUB213SH: return "vfmsub213sh";
     case ND_INS_VFMSUB213SS: return "vfmsub213ss";
     case ND_INS_VFMSUB231PD: return "vfmsub231pd";
+    case ND_INS_VFMSUB231PH: return "vfmsub231ph";
     case ND_INS_VFMSUB231PS: return "vfmsub231ps";
     case ND_INS_VFMSUB231SD: return "vfmsub231sd";
+    case ND_INS_VFMSUB231SH: return "vfmsub231sh";
     case ND_INS_VFMSUB231SS: return "vfmsub231ss";
     case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd";
+    case ND_INS_VFMSUBADD132PH: return "vfmsubadd132ph";
     case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps";
     case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd";
+    case ND_INS_VFMSUBADD213PH: return "vfmsubadd213ph";
     case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps";
     case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd";
+    case ND_INS_VFMSUBADD231PH: return "vfmsubadd231ph";
     case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps";
     case ND_INS_VFMSUBADDPD: return "vfmsubaddpd";
     case ND_INS_VFMSUBADDPS: return "vfmsubaddps";
@@ -948,41 +1051,57 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VFMSUBPS: return "vfmsubps";
     case ND_INS_VFMSUBSD: return "vfmsubsd";
     case ND_INS_VFMSUBSS: return "vfmsubss";
+    case ND_INS_VFMULCPH: return "vfmulcph";
+    case ND_INS_VFMULCSH: return "vfmulcsh";
     case ND_INS_VFNMADD132PD: return "vfnmadd132pd";
+    case ND_INS_VFNMADD132PH: return "vfnmadd132ph";
     case ND_INS_VFNMADD132PS: return "vfnmadd132ps";
     case ND_INS_VFNMADD132SD: return "vfnmadd132sd";
+    case ND_INS_VFNMADD132SH: return "vfnmadd132sh";
     case ND_INS_VFNMADD132SS: return "vfnmadd132ss";
     case ND_INS_VFNMADD213PD: return "vfnmadd213pd";
+    case ND_INS_VFNMADD213PH: return "vfnmadd213ph";
     case ND_INS_VFNMADD213PS: return "vfnmadd213ps";
     case ND_INS_VFNMADD213SD: return "vfnmadd213sd";
+    case ND_INS_VFNMADD213SH: return "vfnmadd213sh";
     case ND_INS_VFNMADD213SS: return "vfnmadd213ss";
     case ND_INS_VFNMADD231PD: return "vfnmadd231pd";
+    case ND_INS_VFNMADD231PH: return "vfnmadd231ph";
     case ND_INS_VFNMADD231PS: return "vfnmadd231ps";
     case ND_INS_VFNMADD231SD: return "vfnmadd231sd";
+    case ND_INS_VFNMADD231SH: return "vfnmadd231sh";
     case ND_INS_VFNMADD231SS: return "vfnmadd231ss";
     case ND_INS_VFNMADDPD: return "vfnmaddpd";
     case ND_INS_VFNMADDPS: return "vfnmaddps";
     case ND_INS_VFNMADDSD: return "vfnmaddsd";
     case ND_INS_VFNMADDSS: return "vfnmaddss";
     case ND_INS_VFNMSUB132PD: return "vfnmsub132pd";
+    case ND_INS_VFNMSUB132PH: return "vfnmsub132ph";
     case ND_INS_VFNMSUB132PS: return "vfnmsub132ps";
     case ND_INS_VFNMSUB132SD: return "vfnmsub132sd";
+    case ND_INS_VFNMSUB132SH: return "vfnmsub132sh";
     case ND_INS_VFNMSUB132SS: return "vfnmsub132ss";
     case ND_INS_VFNMSUB213PD: return "vfnmsub213pd";
+    case ND_INS_VFNMSUB213PH: return "vfnmsub213ph";
     case ND_INS_VFNMSUB213PS: return "vfnmsub213ps";
     case ND_INS_VFNMSUB213SD: return "vfnmsub213sd";
+    case ND_INS_VFNMSUB213SH: return "vfnmsub213sh";
     case ND_INS_VFNMSUB213SS: return "vfnmsub213ss";
     case ND_INS_VFNMSUB231PD: return "vfnmsub231pd";
+    case ND_INS_VFNMSUB231PH: return "vfnmsub231ph";
     case ND_INS_VFNMSUB231PS: return "vfnmsub231ps";
     case ND_INS_VFNMSUB231SD: return "vfnmsub231sd";
+    case ND_INS_VFNMSUB231SH: return "vfnmsub231sh";
     case ND_INS_VFNMSUB231SS: return "vfnmsub231ss";
     case ND_INS_VFNMSUBPD: return "vfnmsubpd";
     case ND_INS_VFNMSUBPS: return "vfnmsubps";
     case ND_INS_VFNMSUBSD: return "vfnmsubsd";
     case ND_INS_VFNMSUBSS: return "vfnmsubss";
     case ND_INS_VFPCLASSPD: return "vfpclasspd";
+    case ND_INS_VFPCLASSPH: return "vfpclassph";
     case ND_INS_VFPCLASSPS: return "vfpclassps";
     case ND_INS_VFPCLASSSD: return "vfpclasssd";
+    case ND_INS_VFPCLASSSH: return "vfpclasssh";
     case ND_INS_VFPCLASSSS: return "vfpclassss";
     case ND_INS_VFRCZPD: return "vfrczpd";
     case ND_INS_VFRCZPS: return "vfrczps";
@@ -1001,12 +1120,16 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VGATHERQPD: return "vgatherqpd";
     case ND_INS_VGATHERQPS: return "vgatherqps";
     case ND_INS_VGETEXPPD: return "vgetexppd";
+    case ND_INS_VGETEXPPH: return "vgetexpph";
     case ND_INS_VGETEXPPS: return "vgetexpps";
     case ND_INS_VGETEXPSD: return "vgetexpsd";
+    case ND_INS_VGETEXPSH: return "vgetexpsh";
     case ND_INS_VGETEXPSS: return "vgetexpss";
     case ND_INS_VGETMANTPD: return "vgetmantpd";
+    case ND_INS_VGETMANTPH: return "vgetmantph";
     case ND_INS_VGETMANTPS: return "vgetmantps";
     case ND_INS_VGETMANTSD: return "vgetmantsd";
+    case ND_INS_VGETMANTSH: return "vgetmantsh";
     case ND_INS_VGETMANTSS: return "vgetmantss";
     case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb";
     case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb";
@@ -1032,16 +1155,20 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VMASKMOVPD: return "vmaskmovpd";
     case ND_INS_VMASKMOVPS: return "vmaskmovps";
     case ND_INS_VMAXPD: return "vmaxpd";
+    case ND_INS_VMAXPH: return "vmaxph";
     case ND_INS_VMAXPS: return "vmaxps";
     case ND_INS_VMAXSD: return "vmaxsd";
+    case ND_INS_VMAXSH: return "vmaxsh";
     case ND_INS_VMAXSS: return "vmaxss";
     case ND_INS_VMCALL: return "vmcall";
     case ND_INS_VMCLEAR: return "vmclear";
     case ND_INS_VMFUNC: return "vmfunc";
     case ND_INS_VMGEXIT: return "vmgexit";
     case ND_INS_VMINPD: return "vminpd";
+    case ND_INS_VMINPH: return "vminph";
     case ND_INS_VMINPS: return "vminps";
     case ND_INS_VMINSD: return "vminsd";
+    case ND_INS_VMINSH: return "vminsh";
     case ND_INS_VMINSS: return "vminss";
     case ND_INS_VMLAUNCH: return "vmlaunch";
     case ND_INS_VMLOAD: return "vmload";
@@ -1072,11 +1199,13 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VMOVNTPS: return "vmovntps";
     case ND_INS_VMOVQ: return "vmovq";
     case ND_INS_VMOVSD: return "vmovsd";
+    case ND_INS_VMOVSH: return "vmovsh";
     case ND_INS_VMOVSHDUP: return "vmovshdup";
     case ND_INS_VMOVSLDUP: return "vmovsldup";
     case ND_INS_VMOVSS: return "vmovss";
     case ND_INS_VMOVUPD: return "vmovupd";
     case ND_INS_VMOVUPS: return "vmovups";
+    case ND_INS_VMOVW: return "vmovw";
     case ND_INS_VMPSADBW: return "vmpsadbw";
     case ND_INS_VMPTRLD: return "vmptrld";
     case ND_INS_VMPTRST: return "vmptrst";
@@ -1085,8 +1214,10 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VMRUN: return "vmrun";
     case ND_INS_VMSAVE: return "vmsave";
     case ND_INS_VMULPD: return "vmulpd";
+    case ND_INS_VMULPH: return "vmulph";
     case ND_INS_VMULPS: return "vmulps";
     case ND_INS_VMULSD: return "vmulsd";
+    case ND_INS_VMULSH: return "vmulsh";
     case ND_INS_VMULSS: return "vmulss";
     case ND_INS_VMWRITE: return "vmwrite";
     case ND_INS_VMXOFF: return "vmxoff";
@@ -1171,10 +1302,22 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VPCOMW: return "vpcomw";
     case ND_INS_VPCONFLICTD: return "vpconflictd";
     case ND_INS_VPCONFLICTQ: return "vpconflictq";
+    case ND_INS_VPDPBSSD: return "vpdpbssd";
+    case ND_INS_VPDPBSSDS: return "vpdpbssds";
+    case ND_INS_VPDPBSUD: return "vpdpbsud";
+    case ND_INS_VPDPBSUDS: return "vpdpbsuds";
     case ND_INS_VPDPBUSD: return "vpdpbusd";
     case ND_INS_VPDPBUSDS: return "vpdpbusds";
+    case ND_INS_VPDPBUUD: return "vpdpbuud";
+    case ND_INS_VPDPBUUDS: return "vpdpbuuds";
     case ND_INS_VPDPWSSD: return "vpdpwssd";
     case ND_INS_VPDPWSSDS: return "vpdpwssds";
+    case ND_INS_VPDPWSUD: return "vpdpwsud";
+    case ND_INS_VPDPWSUDS: return "vpdpwsuds";
+    case ND_INS_VPDPWUSD: return "vpdpwusd";
+    case ND_INS_VPDPWUSDS: return "vpdpwusds";
+    case ND_INS_VPDPWUUD: return "vpdpwuud";
+    case ND_INS_VPDPWUUDS: return "vpdpwuuds";
     case ND_INS_VPERM2F128: return "vperm2f128";
     case ND_INS_VPERM2I128: return "vperm2i128";
     case ND_INS_VPERMB: return "vpermb";
@@ -1436,15 +1579,21 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VRCP28PS: return "vrcp28ps";
     case ND_INS_VRCP28SD: return "vrcp28sd";
     case ND_INS_VRCP28SS: return "vrcp28ss";
+    case ND_INS_VRCPPH: return "vrcpph";
     case ND_INS_VRCPPS: return "vrcpps";
+    case ND_INS_VRCPSH: return "vrcpsh";
     case ND_INS_VRCPSS: return "vrcpss";
     case ND_INS_VREDUCEPD: return "vreducepd";
+    case ND_INS_VREDUCEPH: return "vreduceph";
     case ND_INS_VREDUCEPS: return "vreduceps";
     case ND_INS_VREDUCESD: return "vreducesd";
+    case ND_INS_VREDUCESH: return "vreducesh";
     case ND_INS_VREDUCESS: return "vreducess";
     case ND_INS_VRNDSCALEPD: return "vrndscalepd";
+    case ND_INS_VRNDSCALEPH: return "vrndscaleph";
     case ND_INS_VRNDSCALEPS: return "vrndscaleps";
     case ND_INS_VRNDSCALESD: return "vrndscalesd";
+    case ND_INS_VRNDSCALESH: return "vrndscalesh";
     case ND_INS_VRNDSCALESS: return "vrndscaless";
     case ND_INS_VROUNDPD: return "vroundpd";
     case ND_INS_VROUNDPS: return "vroundps";
@@ -1458,11 +1607,15 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VRSQRT28PS: return "vrsqrt28ps";
     case ND_INS_VRSQRT28SD: return "vrsqrt28sd";
     case ND_INS_VRSQRT28SS: return "vrsqrt28ss";
+    case ND_INS_VRSQRTPH: return "vrsqrtph";
     case ND_INS_VRSQRTPS: return "vrsqrtps";
+    case ND_INS_VRSQRTSH: return "vrsqrtsh";
     case ND_INS_VRSQRTSS: return "vrsqrtss";
     case ND_INS_VSCALEFPD: return "vscalefpd";
+    case ND_INS_VSCALEFPH: return "vscalefph";
     case ND_INS_VSCALEFPS: return "vscalefps";
     case ND_INS_VSCALEFSD: return "vscalefsd";
+    case ND_INS_VSCALEFSH: return "vscalefsh";
     case ND_INS_VSCALEFSS: return "vscalefss";
     case ND_INS_VSCATTERDPD: return "vscatterdpd";
     case ND_INS_VSCATTERDPS: return "vscatterdps";
@@ -1476,24 +1629,37 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps";
     case ND_INS_VSCATTERQPD: return "vscatterqpd";
     case ND_INS_VSCATTERQPS: return "vscatterqps";
+    case ND_INS_VSHA512MSG1: return "vsha512msg1";
+    case ND_INS_VSHA512MSG2: return "vsha512msg2";
+    case ND_INS_VSHA512RNDS2: return "vsha512rnds2";
     case ND_INS_VSHUFF32X4: return "vshuff32x4";
     case ND_INS_VSHUFF64X2: return "vshuff64x2";
     case ND_INS_VSHUFI32X4: return "vshufi32x4";
     case ND_INS_VSHUFI64X2: return "vshufi64x2";
     case ND_INS_VSHUFPD: return "vshufpd";
     case ND_INS_VSHUFPS: return "vshufps";
+    case ND_INS_VSM3MSG1: return "vsm3msg1";
+    case ND_INS_VSM3MSG2: return "vsm3msg2";
+    case ND_INS_VSM3RNDS2: return "vsm3rnds2";
+    case ND_INS_VSM4KEY4: return "vsm4key4";
+    case ND_INS_VSM4RNDS4: return "vsm4rnds4";
     case ND_INS_VSQRTPD: return "vsqrtpd";
+    case ND_INS_VSQRTPH: return "vsqrtph";
     case ND_INS_VSQRTPS: return "vsqrtps";
     case ND_INS_VSQRTSD: return "vsqrtsd";
+    case ND_INS_VSQRTSH: return "vsqrtsh";
     case ND_INS_VSQRTSS: return "vsqrtss";
     case ND_INS_VSTMXCSR: return "vstmxcsr";
     case ND_INS_VSUBPD: return "vsubpd";
+    case ND_INS_VSUBPH: return "vsubph";
     case ND_INS_VSUBPS: return "vsubps";
     case ND_INS_VSUBSD: return "vsubsd";
+    case ND_INS_VSUBSH: return "vsubsh";
     case ND_INS_VSUBSS: return "vsubss";
     case ND_INS_VTESTPD: return "vtestpd";
     case ND_INS_VTESTPS: return "vtestps";
     case ND_INS_VUCOMISD: return "vucomisd";
+    case ND_INS_VUCOMISH: return "vucomish";
     case ND_INS_VUCOMISS: return "vucomiss";
     case ND_INS_VUNPCKHPD: return "vunpckhpd";
     case ND_INS_VUNPCKHPS: return "vunpckhps";
@@ -1509,6 +1675,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_WRFSBASE: return "wrfsbase";
     case ND_INS_WRGSBASE: return "wrgsbase";
     case ND_INS_WRMSR: return "wrmsr";
+    case ND_INS_WRMSRLIST: return "wrmsrlist";
+    case ND_INS_WRMSRNS: return "wrmsrns";
     case ND_INS_WRPKRU: return "wrpkru";
     case ND_INS_WRSHR: return "wrshr";
     case ND_INS_WRSS: return "wrss";
@@ -1528,7 +1696,7 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_XOR: return "xor";
     case ND_INS_XORPD: return "xorpd";
     case ND_INS_XORPS: return "xorps";
-    case ND_INS_XRESLDTRK: return "xresldtrik";
+    case ND_INS_XRESLDTRK: return "xresldtrk";
     case ND_INS_XRSTOR: return "xrstor";
     case ND_INS_XRSTORS: return "xrstors";
     case ND_INS_XSAVE: return "xsave";
@@ -1538,56 +1706,9 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_XSETBV: return "xsetbv";
     case ND_INS_XSHA1: return "xsha1";
     case ND_INS_XSHA256: return "xsha256";
-    case ND_INS_XSUSLDTRK: return "xsusldtrk";
     case ND_INS_XSTORE: return "xstore";
+    case ND_INS_XSUSLDTRK: return "xsusldtrk";
     case ND_INS_XTEST: return "xtest";
-    case ND_INS_HRESET: return "hreset";
-    case ND_INS_CLUI: return "clui";
-    case ND_INS_STUI: return "stui";
-    case ND_INS_TESTUI: return "testui";
-    case ND_INS_UIRET: return "uiret";
-    case ND_INS_SENDUIPI: return "senduipi";
-    case ND_INS_AADD: return "aadd";
-    case ND_INS_AAND: return "aand";
-    case ND_INS_AOR: return "aor";
-    case ND_INS_AXOR: return "axor";
-    case ND_INS_CMPBEXADD: return "cmpbexadd";
-    case ND_INS_CMPCXADD: return "cmpcxadd";
-    case ND_INS_CMPLEXADD: return "cmplexadd";
-    case ND_INS_CMPLXADD: return "cmplxadd";
-    case ND_INS_CMPNBEXADD: return "cmpnbexadd";
-    case ND_INS_CMPNCXADD: return "cmpncxadd";
-    case ND_INS_CMPNLEXADD: return "cmpnlexadd";
-    case ND_INS_CMPNLXADD: return "cmpnlxadd";
-    case ND_INS_CMPNOXADD: return "cmpnoxadd";
-    case ND_INS_CMPNPXADD: return "cmpnpxadd";
-    case ND_INS_CMPNSXADD: return "cmpnsxadd";
-    case ND_INS_CMPNZXADD: return "cmpnzxadd";
-    case ND_INS_CMPOXADD: return  "cmpoxadd";
-    case ND_INS_CMPPXADD: return "cmppxadd";
-    case ND_INS_CMPSXADD: return "cmpsxadd";
-    case ND_INS_CMPZXADD: return "cmpzxadd";
-    case ND_INS_PREFETCHIT0: return "prefetchit0";
-    case ND_INS_PREFETCHIT1: return "prefetchit1";
-    case ND_INS_RDMSRLIST: return "rdmsrlist";
-    case ND_INS_TDPFP16PS: return "tdpfp16ps";
-    case ND_INS_VBCSTNEBF162PS: return "vbcstnebf162ps";
-    case ND_INS_VBCSTNESH2PS: return "vbcstnesh2ps";
-    case ND_INS_VCVTNEEBF162PS: return "vcvtneebf162ps";
-    case ND_INS_VCVTNEEPH2PS: return "vcvtneeph2ps";
-    case ND_INS_VCVTNEOBF162PS: return "vcvtneobf162ps";
-    case ND_INS_VCVTNEOPH2PS: return "vcvtneoph2ps";
-    case ND_INS_VPDPBSSD:  return "vpdpbssd";
-    case ND_INS_VPDPBSSDS: return "vpdpbssds";
-    case ND_INS_VPDPBSUD:  return "vpdpbsud";
-    case ND_INS_VPDPBSUDS: return "vpdpbsuds";
-    case ND_INS_VPDPBUUD:  return "vpdpbuud";
-    case ND_INS_VPDPBUUDS: return "vpdpbuuds";
-    case ND_INS_WRMSRLIST: return "wrmsrlist";
-    case ND_INS_WRMSRNS: return "wrmsrns";
-    case ND_INS_RMPQUERY: return "rmpquery";
-    case ND_INS_TCMMRLFP16PS: return "tcmmrlfp16ps";
-    case ND_INS_TCMMIMFP16PS: return "tcmmimfp16ps";
     default: return "unhandled!";
     }
 
@@ -1609,10 +1730,14 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_AVX2GATHER: return "avx2gather";
     case ND_CAT_AVX512: return "avx512";
     case ND_CAT_AVX512BF16: return "avx512bf16";
+    case ND_CAT_AVX512FP16: return "avx512fp16";
     case ND_CAT_AVX512VBMI: return "avx512vbmi";
     case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect";
-    case ND_CAT_AVX512FP16: return "avx512fp16";
+    case ND_CAT_AVXIFMA: return "avxifma";
+    case ND_CAT_AVXNECONVERT: return "avxneconvert";
     case ND_CAT_AVXVNNI: return "avxvnni";
+    case ND_CAT_AVXVNNIINT16: return "avxvnniint16";
+    case ND_CAT_AVXVNNIINT8: return "avxvnniint8";
     case ND_CAT_BITBYTE: return "bitbyte";
     case ND_CAT_BLEND: return "blend";
     case ND_CAT_BMI1: return "bmi1";
@@ -1622,6 +1747,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_CET: return "cet";
     case ND_CAT_CLDEMOTE: return "cldemote";
     case ND_CAT_CMOV: return "cmov";
+    case ND_CAT_CMPCCXADD: return "cmpccxadd";
     case ND_CAT_COMPRESS: return "compress";
     case ND_CAT_COND_BR: return "cond_br";
     case ND_CAT_CONFLICT: return "conflict";
@@ -1662,6 +1788,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_PREFETCH: return "prefetch";
     case ND_CAT_PTWRITE: return "ptwrite";
     case ND_CAT_PUSH: return "push";
+    case ND_CAT_RAOINT: return "raoint";
     case ND_CAT_RDPID: return "rdpid";
     case ND_CAT_RDRAND: return "rdrand";
     case ND_CAT_RDSEED: return "rdseed";
@@ -1673,7 +1800,10 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_SEMAPHORE: return "semaphore";
     case ND_CAT_SGX: return "sgx";
     case ND_CAT_SHA: return "sha";
+    case ND_CAT_SHA512: return "sha512";
     case ND_CAT_SHIFT: return "shift";
+    case ND_CAT_SM3: return "sm3";
+    case ND_CAT_SM4: return "sm4";
     case ND_CAT_SMAP: return "smap";
     case ND_CAT_SSE: return "sse";
     case ND_CAT_SSE2: return "sse2";
@@ -1702,11 +1832,6 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_X87_ALU: return "x87_alu";
     case ND_CAT_XOP: return "xop";
     case ND_CAT_XSAVE: return "xsave";
-    case ND_CAT_AVXIFMA: return "avxifma";
-    case ND_CAT_AVXVNNIINT8: return "avxvnniint8";
-    case ND_CAT_AVXNECONVERT: return "avxneconvert";
-    case ND_CAT_CMPCCXADD: return "cmpccxass";
-    case ND_CAT_RAOINT: return "rao-int";
     }
 
     return "<unknown>";
@@ -1722,9 +1847,10 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_AES: return "aes";
     case ND_SET_AMD: return "amd";
     case ND_SET_AMXBF16: return "amxbf16";
+    case ND_SET_AMXCOMPLEX: return "amxcomplex";
+    case ND_SET_AMXFP16: return "amxfp16";
     case ND_SET_AMXINT8: return "amxint8";
     case ND_SET_AMXTILE: return "amxtile";
-    case ND_SET_AMXCOMPLEX: return "amxcomplex";
     case ND_SET_AVX: return "avx";
     case ND_SET_AVX2: return "avx2";
     case ND_SET_AVX2GATHER: return "avx2gather";
@@ -1737,6 +1863,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_AVX512DQ: return "avx512dq";
     case ND_SET_AVX512ER: return "avx512er";
     case ND_SET_AVX512F: return "avx512f";
+    case ND_SET_AVX512FP16: return "avx512fp16";
     case ND_SET_AVX512IFMA: return "avx512ifma";
     case ND_SET_AVX512PF: return "avx512pf";
     case ND_SET_AVX512VBMI: return "avx512vbmi";
@@ -1744,8 +1871,11 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_AVX512VNNI: return "avx512vnni";
     case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect";
     case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq";
-    case ND_SET_AVX512FP16: return "avx512fp16";
+    case ND_SET_AVXIFMA: return "avxifma";
+    case ND_SET_AVXNECONVERT: return "avxneconvert";
     case ND_SET_AVXVNNI: return "avxvnni";
+    case ND_SET_AVXVNNIINT16: return "avxvnniint16";
+    case ND_SET_AVXVNNIINT8: return "avxvnniint8";
     case ND_SET_BMI1: return "bmi1";
     case ND_SET_BMI2: return "bmi2";
     case ND_SET_CET_SS: return "cet_ss";
@@ -1755,6 +1885,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_CLFSHOPT: return "clfshopt";
     case ND_SET_CLWB: return "clwb";
     case ND_SET_CLZERO: return "clzero";
+    case ND_SET_CMPCCXADD: return "cmpccxadd";
     case ND_SET_CMPXCHG16B: return "cmpxchg16b";
     case ND_SET_CYRIX: return "cyrix";
     case ND_SET_CYRIX_SMM: return "cyrix_smm";
@@ -1767,7 +1898,6 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_GFNI: return "gfni";
     case ND_SET_HRESET: return "hreset";
     case ND_SET_I186: return "i186";
-    case ND_SET_INVLPGB: return "invlpgb";
     case ND_SET_I286PROT: return "i286prot";
     case ND_SET_I286REAL: return "i286real";
     case ND_SET_I386: return "i386";
@@ -1775,6 +1905,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_I486REAL: return "i486real";
     case ND_SET_I64: return "i64";
     case ND_SET_I86: return "i86";
+    case ND_SET_INVLPGB: return "invlpgb";
     case ND_SET_INVPCID: return "invpcid";
     case ND_SET_KL: return "kl";
     case ND_SET_LKGS: return "lkgs";
@@ -1787,6 +1918,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_MOVDIR64B: return "movdir64b";
     case ND_SET_MOVDIRI: return "movdiri";
     case ND_SET_MPX: return "mpx";
+    case ND_SET_MSRLIST: return "msrlist";
     case ND_SET_MWAITT: return "mwaitt";
     case ND_SET_PAUSE: return "pause";
     case ND_SET_PCLMULQDQ: return "pclmulqdq";
@@ -1795,8 +1927,10 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_PKU: return "pku";
     case ND_SET_POPCNT: return "popcnt";
     case ND_SET_PPRO: return "ppro";
+    case ND_SET_PREFETCHITI: return "prefetchiti";
     case ND_SET_PREFETCH_NOP: return "prefetch_nop";
     case ND_SET_PTWRITE: return "ptwrite";
+    case ND_SET_RAOINT: return "raoint";
     case ND_SET_RDPID: return "rdpid";
     case ND_SET_RDPMC: return "rdpmc";
     case ND_SET_RDPRU: return "rdpru";
@@ -1807,6 +1941,9 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_SERIALIZE: return "serialize";
     case ND_SET_SGX: return "sgx";
     case ND_SET_SHA: return "sha";
+    case ND_SET_SHA512: return "sha512";
+    case ND_SET_SM3: return "sm3";
+    case ND_SET_SM4: return "sm4";
     case ND_SET_SMAP: return "smap";
     case ND_SET_SMX: return "smx";
     case ND_SET_SNP: return "snp";
@@ -1820,6 +1957,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_SVM: return "svm";
     case ND_SET_TBM: return "tbm";
     case ND_SET_TDX: return "tdx";
+    case ND_SET_TSE: return "tse";
     case ND_SET_TSX: return "tsx";
     case ND_SET_TSXLDTRK: return "tsxldtrk";
     case ND_SET_UD: return "ud";
@@ -1830,20 +1968,12 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
     case ND_SET_VTX: return "vtx";
     case ND_SET_WAITPKG: return "waitpkg";
     case ND_SET_WBNOINVD: return "wbnoinvd";
+    case ND_SET_WRMSRNS: return "wrmsrns";
     case ND_SET_X87: return "x87";
     case ND_SET_XOP: return "xop";
     case ND_SET_XSAVE: return "xsave";
     case ND_SET_XSAVEC: return "xsavec";
     case ND_SET_XSAVES: return "xsaves";
-    case ND_SET_AMXFP16: return "AMX-FP16";
-    case ND_SET_AVXIFMA: return "avxifma";
-    case ND_SET_AVXNECONVERT: return "avxneconvert";
-    case ND_SET_AVXVNNIINT8: return "avxvnniint8";
-    case ND_SET_CMPCCXADD: return "cmpccxadd";
-    case ND_SET_MSRLIST: return "msrlist";
-    case ND_SET_PREFETCHITI: return "prefetchiti";
-    case ND_SET_RAOINT: return "raoint";
-    case ND_SET_WRMSRNS: return "wrmsrns";
     }
 
     return "<unknown>";
diff --git a/inc/constants.h b/inc/constants.h
index d6a36cc..9bf6400 100644
--- a/inc/constants.h
+++ b/inc/constants.h
@@ -469,6 +469,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_PAVGW,
     ND_INS_PBLENDVB,
     ND_INS_PBLENDW,
+    ND_INS_PBNDKB,
     ND_INS_PCLMULQDQ,
     ND_INS_PCMPEQB,
     ND_INS_PCMPEQD,
@@ -1257,6 +1258,12 @@ typedef enum _ND_INS_CLASS
     ND_INS_VPDPBUUDS,
     ND_INS_VPDPWSSD,
     ND_INS_VPDPWSSDS,
+    ND_INS_VPDPWSUD,
+    ND_INS_VPDPWSUDS,
+    ND_INS_VPDPWUSD,
+    ND_INS_VPDPWUSDS,
+    ND_INS_VPDPWUUD,
+    ND_INS_VPDPWUUDS,
     ND_INS_VPERM2F128,
     ND_INS_VPERM2I128,
     ND_INS_VPERMB,
@@ -1568,12 +1575,20 @@ typedef enum _ND_INS_CLASS
     ND_INS_VSCATTERPF1QPS,
     ND_INS_VSCATTERQPD,
     ND_INS_VSCATTERQPS,
+    ND_INS_VSHA512MSG1,
+    ND_INS_VSHA512MSG2,
+    ND_INS_VSHA512RNDS2,
     ND_INS_VSHUFF32X4,
     ND_INS_VSHUFF64X2,
     ND_INS_VSHUFI32X4,
     ND_INS_VSHUFI64X2,
     ND_INS_VSHUFPD,
     ND_INS_VSHUFPS,
+    ND_INS_VSM3MSG1,
+    ND_INS_VSM3MSG2,
+    ND_INS_VSM3RNDS2,
+    ND_INS_VSM4KEY4,
+    ND_INS_VSM4RNDS4,
     ND_INS_VSQRTPD,
     ND_INS_VSQRTPH,
     ND_INS_VSQRTPS,
@@ -1679,6 +1694,7 @@ typedef enum _ND_INS_SET
     ND_SET_AVXIFMA,
     ND_SET_AVXNECONVERT,
     ND_SET_AVXVNNI,
+    ND_SET_AVXVNNIINT16,
     ND_SET_AVXVNNIINT8,
     ND_SET_BMI1,
     ND_SET_BMI2,
@@ -1745,6 +1761,9 @@ typedef enum _ND_INS_SET
     ND_SET_SERIALIZE,
     ND_SET_SGX,
     ND_SET_SHA,
+    ND_SET_SHA512,
+    ND_SET_SM3,
+    ND_SET_SM4,
     ND_SET_SMAP,
     ND_SET_SMX,
     ND_SET_SNP,
@@ -1758,6 +1777,7 @@ typedef enum _ND_INS_SET
     ND_SET_SVM,
     ND_SET_TBM,
     ND_SET_TDX,
+    ND_SET_TSE,
     ND_SET_TSX,
     ND_SET_TSXLDTRK,
     ND_SET_UD,
@@ -1797,6 +1817,7 @@ typedef enum _ND_INS_TYPE
     ND_CAT_AVXIFMA,
     ND_CAT_AVXNECONVERT,
     ND_CAT_AVXVNNI,
+    ND_CAT_AVXVNNIINT16,
     ND_CAT_AVXVNNIINT8,
     ND_CAT_BITBYTE,
     ND_CAT_BLEND,
@@ -1860,7 +1881,10 @@ typedef enum _ND_INS_TYPE
     ND_CAT_SEMAPHORE,
     ND_CAT_SGX,
     ND_CAT_SHA,
+    ND_CAT_SHA512,
     ND_CAT_SHIFT,
+    ND_CAT_SM3,
+    ND_CAT_SM4,
     ND_CAT_SMAP,
     ND_CAT_SSE,
     ND_CAT_SSE2,
diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h
index 730f8e2..570c1df 100644
--- a/inc/cpuidflags.h
+++ b/inc/cpuidflags.h
@@ -94,6 +94,9 @@
 #define ND_CFF_AVX512FP16               ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23)
 #define ND_CFF_AMXTILE                  ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24)
 #define ND_CFF_AMXINT8                  ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25)
+#define ND_CFF_SHA512                   ND_CFF(0x00000007, 0x00000001, NDR_EAX, 0)
+#define ND_CFF_SM3                      ND_CFF(0x00000007, 0x00000001, NDR_EAX, 1)
+#define ND_CFF_SM4                      ND_CFF(0x00000007, 0x00000001, NDR_EAX, 2)
 #define ND_CFF_RAOINT                   ND_CFF(0x00000007, 0x00000001, NDR_EAX, 3)
 #define ND_CFF_AVXVNNI                  ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4)
 #define ND_CFF_AVX512BF16               ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5)
@@ -105,9 +108,11 @@
 #define ND_CFF_HRESET                   ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
 #define ND_CFF_AVXIFMA                  ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23)
 #define ND_CFF_MSRLIST                  ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
+#define ND_CFF_TSE                      ND_CFF(0x00000007, 0x00000001, NDR_EBX, 1)
 #define ND_CFF_AVXVNNIINT8              ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
 #define ND_CFF_AVXNECONVERT             ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
 #define ND_CFF_AMXCOMPLEX               ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
+#define ND_CFF_AVXVNNIINT16             ND_CFF(0x00000007, 0x00000001, NDR_EDX, 10)
 #define ND_CFF_PREFETCHITI              ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14)
 #define ND_CFF_XSAVEOPT                 ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
 #define ND_CFF_XSAVEC                   ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
diff --git a/inc/version.h b/inc/version.h
index cfa4575..d6ade4c 100644
--- a/inc/version.h
+++ b/inc/version.h
@@ -6,7 +6,7 @@
 #define DISASM_VER_H
 
 #define DISASM_VERSION_MAJOR        1
-#define DISASM_VERSION_MINOR        37
+#define DISASM_VERSION_MINOR        38
 #define DISASM_VERSION_REVISION     0
 
 // bdshemu depends on bddisasm. It cannot be used without it.
diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat
index 10d4734..3e08584 100644
--- a/isagenerator/instructions/cpuid.dat
+++ b/isagenerator/instructions/cpuid.dat
@@ -95,6 +95,9 @@ AMXTILE                 : 0x00000007, 0x00000000, EDX, 24
 AMXINT8                 : 0x00000007, 0x00000000, EDX, 25
 
 
+SHA512                  : 0x00000007, 0x00000001, EAX, 0
+SM3                     : 0x00000007, 0x00000001, EAX, 1
+SM4                     : 0x00000007, 0x00000001, EAX, 2
 RAOINT                  : 0x00000007, 0x00000001, EAX, 3
 AVXVNNI                 : 0x00000007, 0x00000001, EAX, 4
 AVX512BF16              : 0x00000007, 0x00000001, EAX, 5
@@ -107,9 +110,12 @@ HRESET                  : 0x00000007, 0x00000001, EAX, 22
 AVXIFMA                 : 0x00000007, 0x00000001, EAX, 23
 MSRLIST                 : 0x00000007, 0x00000001, EAX, 27
 
+TSE                     : 0x00000007, 0x00000001, EBX, 1
+
 AVXVNNIINT8             : 0x00000007, 0x00000001, EDX, 4
 AVXNECONVERT            : 0x00000007, 0x00000001, EDX, 5
 AMXCOMPLEX              : 0x00000007, 0x00000001, EDX, 8
+AVXVNNIINT16            : 0x00000007, 0x00000001, EDX, 10
 PREFETCHITI             : 0x00000007, 0x00000001, EDX, 14
 
 
diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat
index 3d0630f..de25e91 100644
--- a/isagenerator/instructions/table_0F.dat
+++ b/isagenerator/instructions/table_0F.dat
@@ -29,10 +29,11 @@ VMCALL       ; n/a         ; n/a                     ;         NP 0x0F 0x01 /0xC
 VMLAUNCH     ; n/a         ; Fv                      ;         NP 0x0F 0x01 /0xC2         ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
 VMRESUME     ; n/a         ; Fv                      ;         NP 0x0F 0x01 /0xC3         ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
 VMXOFF       ; n/a         ; Fv                      ;         NP 0x0F 0x01 /0xC4         ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT
-PCONFIG      ; n/a         ; EAX,RBX,RCX,RDX         ;         NP 0x0F 0x01 /0xC5         ; s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW, m:NOV86
+PCONFIG      ; n/a         ; EAX,RBX,RCX,RDX,Fv      ;         NP 0x0F 0x01 /0xC5         ; s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW|W, m:KERNEL, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0
 WRMSRNS      ; n/a         ; EAX,EDX,ECX,MSR         ;         NP 0x0F 0x01 /0xC6         ; s:WRMSRNS, t:SYSTEM, w:R|R|R|W, m:KERNEL
 WRMSRLIST    ; n/a         ; SMT,DMT,ECX             ;       0xF3 0x0F 0x01 /0xC6         ; s:MSRLIST, t:SYSTEM, w:R|R|RW, m:KERNEL|O64
 RDMSRLIST    ; n/a         ; SMT,DMT,ECX             ;       0xF2 0x0F 0x01 /0xC6         ; s:MSRLIST, t:SYSTEM, w:R|W|RW, m:KERNEL|O64
+PBNDKB       ; n/a         ; EAX,RBX,RCX,Fv          ;         NP 0x0F 0x01 /0xC7         ; s:TSE, t:SYSTEM, w:W|R|R|W, m:KERNEL|O64, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0
 MONITOR      ; n/a         ; pAXb,ECX,EDX            ;         NP 0x0F 0x01 /0xC8         ; s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86
 MWAIT        ; n/a         ; EAX,ECX                 ;         NP 0x0F 0x01 /0xC9         ; s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86
 CLAC         ; n/a         ; Fv                      ;         NP 0x0F 0x01 /0xCA         ; s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86
diff --git a/isagenerator/instructions/table_vex2.dat b/isagenerator/instructions/table_vex2.dat
index fa173e3..3bf4071 100644
--- a/isagenerator/instructions/table_vex2.dat
+++ b/isagenerator/instructions/table_vex2.dat
@@ -218,7 +218,23 @@ VFNMSUB231PS      ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:0
 VFNMSUB231PD      ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:1 0xBE /r          ; s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMSUB231SS      ; Vdq,Hdq,Wss         ; n/a             ;  vex m:2 p:1 l:i w:0 0xBF /r          ; s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMSUB231SD      ; Vdq,Hdq,Wsd         ; n/a             ;  vex m:2 p:1 l:i w:1 0xBF /r          ; s:FMA, t:VFMA, w:RW|R|R, e:3
+
+VSHA512RNDS2      ; Vqq,Hqq,Udq         ; n/a             ;  vex m:2 p:3 l:1 w:0 0xCB /r:reg      ; s:SHA512, t:SHA512, w:RW|R|R, e:6
+VSHA512MSG1       ; Vqq,Udq             ; n/a             ;  vex m:2 p:3 l:1 w:0 0xCC /r:reg      ; s:SHA512, t:SHA512, w:RW|R, e:6
+VSHA512MSG2       ; Vqq,Uqq             ; n/a             ;  vex m:2 p:3 l:1 w:0 0xCD /r:reg      ; s:SHA512, t:SHA512, w:RW|R, e:6
 VGF2P8MULB        ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:0 0xCF /r          ; s:GFNI, t:GFNI, w:W|R|R
+
+VPDPWUUD          ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:0 l:x w:0 0xD2 /r          ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
+VPDPWUSD          ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:0 0xD2 /r          ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
+VPDPWSUD          ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:2 l:x w:0 0xD2 /r          ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
+VPDPWUUDS         ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:0 l:x w:0 0xD3 /r          ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
+VPDPWUSDS         ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:0 0xD3 /r          ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
+VPDPWSUDS         ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:2 l:x w:0 0xD3 /r          ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4
+
+VSM3MSG1          ; Vdq,Hdq,Wdq         ; n/a             ;  vex m:2 p:0 l:0 w:0 0xDA /r          ; s:SM3, t:SM3, w:RW|R|R, e:4
+VSM3MSG2          ; Vdq,Hdq,Wdq         ; n/a             ;  vex m:2 p:1 l:0 w:0 0xDA /r          ; s:SM3, t:SM3, w:RW|R|R, e:4
+VSM4KEY4          ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:2 l:x w:0 0xDA /r          ; s:SM4, t:SM4, w:W|R|R, e:6
+VSM4RNDS4         ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:3 l:x w:0 0xDA /r          ; s:SM4, t:SM4, w:W|R|R, e:6
 VAESIMC           ; Vdq,Wdq             ; n/a             ;  vex m:2 p:1 l:0 w:i 0xDB /r          ; s:AES, t:AES, w:W|R, e:4
 VAESENC           ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:i 0xDC /r          ; s:AES, t:AES, w:W|R|R, e:4
 VAESENCLAST       ; Vx,Hx,Wx            ; n/a             ;  vex m:2 p:1 l:x w:i 0xDD /r          ; s:AES, t:AES, w:W|R|R, e:4
diff --git a/isagenerator/instructions/table_vex3.dat b/isagenerator/instructions/table_vex3.dat
index cf46257..8cb6b5d 100644
--- a/isagenerator/instructions/table_vex3.dat
+++ b/isagenerator/instructions/table_vex3.dat
@@ -124,6 +124,7 @@ VGF2P8AFFINEQB    ; Vx,Hx,Wx,Ib         ; n/a             ;  vex m:3 p:1 l:x w:1
 VGF2P8AFFINEINVQB ; Vx,Hx,Wx,Ib         ; n/a             ;  vex m:3 p:1 l:x w:1 0xCF /r ib       ; s:GFNI, t:GFNI, w:W|R|R|R, e:4
 
 # 0xD0 - 0xDF
+VSM3RNDS2         ; Vdq,Hdq,Wdq,Ib      ; n/a             ;  vex m:3 p:1 l:0 w:0 0xDE /r ib       ; s:SM3, t:SM3, w:RW|R|R|R, e:4
 VAESKEYGENASSIST  ; Vdq,Wdq,Ib          ; n/a             ;  vex m:3 p:1 l:0 w:i 0xDF /r ib       ; s:AES, t:AES, w:W|R|R, e:4
 
 # 0xF0 - 0xFF