From 767bf2e5c0f32928026e942b03b2b2aba2bdebf0 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Mon, 16 Sep 2024 12:23:54 +0300 Subject: [PATCH] Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands. --- bddisasm/bdx86_decoder.c | 229 +- bddisasm/include/bdx86_instructions.h | 28635 +++++++++-------- bddisasm/include/bdx86_mnemonics.h | 236 +- bddisasm/include/bdx86_table_evex.h | 6444 ++-- bddisasm/include/bdx86_table_root.h | 2652 +- bddisasm/include/bdx86_table_vex.h | 1218 +- bddisasm/include/bdx86_table_xop.h | 170 +- bddisasm/include/bdx86_tabledefs.h | 1 + bdshemu/bdshemu.c | 20 +- bdshemu/bdshemu_x86.c | 20 +- bindings/pybddisasm/setup.py | 2 +- disasmtool/disasmtool.c | 8 + inc/bddisasm_status.h | 1 + inc/bddisasm_version.h | 4 +- inc/bdx86_constants.h | 90 + inc/bdx86_core.h | 44 +- inc/bdx86_cpuidflags.h | 1 + isagenerator/disasmlib.py | 1 + isagenerator/instructions/cpuid.dat | 1 + isagenerator/instructions/flags.dat | 3 + isagenerator/instructions/table_evex_1.dat | 8 + isagenerator/instructions/table_evex_2.dat | 15 + isagenerator/instructions/table_evex_3.dat | 13 + isagenerator/instructions/table_evex_4.dat | 38 +- isagenerator/instructions/table_evex_5.dat | 50 + isagenerator/instructions/table_evex_6.dat | 15 + isagenerator/instructions/table_legacy_0.dat | 4 +- isagenerator/instructions/table_legacy_1.dat | 1 + 28 files changed, 21696 insertions(+), 18228 deletions(-) diff --git a/bddisasm/bdx86_decoder.c b/bddisasm/bdx86_decoder.c index 6e43f24..0cbdaab 100644 --- a/bddisasm/bdx86_decoder.c +++ b/bddisasm/bdx86_decoder.c @@ -151,11 +151,11 @@ NdFetchXop( Instrux->Xop.Xop[2] = Code[Offset + 2]; Instrux->Exs.w = Instrux->Xop.w; - Instrux->Exs.r = ~Instrux->Xop.r; - Instrux->Exs.x = ~Instrux->Xop.x; - Instrux->Exs.b = ~Instrux->Xop.b; + Instrux->Exs.r = (ND_UINT32)~Instrux->Xop.r; + Instrux->Exs.x = (ND_UINT32)~Instrux->Xop.x; + Instrux->Exs.b = (ND_UINT32)~Instrux->Xop.b; Instrux->Exs.l = Instrux->Xop.l; - Instrux->Exs.v = ~Instrux->Xop.v; + Instrux->Exs.v = (ND_UINT32)~Instrux->Xop.v; Instrux->Exs.m = Instrux->Xop.m; Instrux->Exs.p = Instrux->Xop.p; @@ -226,8 +226,8 @@ NdFetchVex2( Instrux->Vex2.Vex[1] = Code[Offset + 1]; Instrux->Exs.m = 1; // For VEX2 instructions, always use the second table. - Instrux->Exs.r = ~Instrux->Vex2.r; - Instrux->Exs.v = ~Instrux->Vex2.v; + Instrux->Exs.r = (ND_UINT32)~Instrux->Vex2.r; + Instrux->Exs.v = (ND_UINT32)~Instrux->Vex2.v; Instrux->Exs.l = Instrux->Vex2.l; Instrux->Exs.p = Instrux->Vex2.p; @@ -282,12 +282,12 @@ NdFetchVex3( Instrux->Vex3.Vex[1] = Code[Offset + 1]; Instrux->Vex3.Vex[2] = Code[Offset + 2]; - Instrux->Exs.r = ~Instrux->Vex3.r; - Instrux->Exs.x = ~Instrux->Vex3.x; - Instrux->Exs.b = ~Instrux->Vex3.b; + Instrux->Exs.r = (ND_UINT32)~Instrux->Vex3.r; + Instrux->Exs.x = (ND_UINT32)~Instrux->Vex3.x; + Instrux->Exs.b = (ND_UINT32)~Instrux->Vex3.b; Instrux->Exs.m = Instrux->Vex3.m; Instrux->Exs.w = Instrux->Vex3.w; - Instrux->Exs.v = ~Instrux->Vex3.v; + Instrux->Exs.v = (ND_UINT32)~Instrux->Vex3.v; Instrux->Exs.l = Instrux->Vex3.l; Instrux->Exs.p = Instrux->Vex3.p; @@ -363,29 +363,29 @@ NdFetchEvex( return ND_STATUS_INVALID_ENCODING; } - // APX not enabled, legacy EVEX prefix. - if (!(Instrux->FeatMode & ND_FEAT_APX)) + // Check map. Maps 4 & 7 are allowed only if APX is enabled. + if (Instrux->Evex.m == 4 || Instrux->Evex.m == 7) { - // Map > 3 is for APX instructions. B4 must be 0, and X4 must be 1 if APX is not enabled. - if (Instrux->Evex.m > 3 || Instrux->Evex.b4 != 0 || Instrux->Evex.x4 != 1) + if (!(Instrux->FeatMode & ND_FEAT_APX)) { return ND_STATUS_INVALID_ENCODING; } } + // Fill in the generic extension bits. We initially optimistically fill in all possible values. // Once we determine the opcode and, subsequently, the EVEX extension mode, we will do further // validations, and reset unused fields to 0. - Instrux->Exs.r = ~Instrux->Evex.r; - Instrux->Exs.x = ~Instrux->Evex.x; - Instrux->Exs.b = ~Instrux->Evex.b; - Instrux->Exs.rp = ~Instrux->Evex.rp; + Instrux->Exs.r = (ND_UINT32)~Instrux->Evex.r; + Instrux->Exs.x = (ND_UINT32)~Instrux->Evex.x; + Instrux->Exs.b = (ND_UINT32)~Instrux->Evex.b; + Instrux->Exs.rp = (ND_UINT32)~Instrux->Evex.rp; + Instrux->Exs.x4 = (ND_UINT32)~Instrux->Evex.u; Instrux->Exs.b4 = Instrux->Evex.b4; - Instrux->Exs.x4 = ~Instrux->Evex.x4; Instrux->Exs.m = Instrux->Evex.m; Instrux->Exs.w = Instrux->Evex.w; - Instrux->Exs.v = ~Instrux->Evex.v; - Instrux->Exs.vp = ~Instrux->Evex.vp; + Instrux->Exs.v = (ND_UINT32)~Instrux->Evex.v; + Instrux->Exs.vp = (ND_UINT32)~Instrux->Evex.vp; Instrux->Exs.p = Instrux->Evex.p; Instrux->Exs.z = Instrux->Evex.z; @@ -393,7 +393,7 @@ NdFetchEvex( Instrux->Exs.bm = Instrux->Evex.bm; Instrux->Exs.k = Instrux->Evex.a; - // EVEX extensions. + // EVEX extensions. The fields are undefined if the encoding does not use them. Instrux->Exs.nf = (Instrux->Evex.Evex[3] >> 2) & 1; Instrux->Exs.nd = (Instrux->Evex.Evex[3] >> 4) & 1; Instrux->Exs.sc = (Instrux->Evex.Evex[3] & 0xF); @@ -1333,10 +1333,17 @@ NdParseMemoryOperand3264( Operand->Info.Memory.BaseSize = defsize; Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->Sib.base; - // If APX is present, extend the base. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.b4 != 0) { - Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + // If APX is present, extend the base. + if (Instrux->FeatMode & ND_FEAT_APX) + { + Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP)) @@ -1361,10 +1368,17 @@ NdParseMemoryOperand3264( // Regular SIB, index RSP is ignored. Bit 4 of the 32-bit index register is given by the X4 field. Operand->Info.Memory.Index = (ND_UINT8)(Instrux->Exs.x << 3) | Instrux->Sib.index; - // If APX is present, extend the index. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.x4 != 0) { - Operand->Info.Memory.Index |= Instrux->Exs.x4 << 4; + // If APX is present, extend the index. + if (Instrux->FeatMode & ND_FEAT_APX) + { + Operand->Info.Memory.Index |= Instrux->Exs.x4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } if (Operand->Info.Memory.Index != NDR_RSP) @@ -1401,10 +1415,17 @@ NdParseMemoryOperand3264( Operand->Info.Memory.BaseSize = defsize; Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm; - // If APX is present, extend the base register. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.b4 != 0) { - Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + // If APX is present, extend the base register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP)) @@ -2378,13 +2399,7 @@ NdParseOperand( operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_CR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg; - - // If APX is present, use R4 as well. - if (Instrux->FeatMode & ND_FEAT_APX) - { - operand->Info.Register.Reg |= Instrux->Exs.rp << 4; - } + operand->Info.Register.Reg = (Instrux->Exs.rp << 4) | (Instrux->Exs.r << 3) | Instrux->ModRm.reg; // On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing // higher 8 control registers. @@ -2411,13 +2426,7 @@ NdParseOperand( operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_DR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg; - - // If APX is present, use R4 as well. - if (Instrux->FeatMode & ND_FEAT_APX) - { - operand->Info.Register.Reg |= Instrux->Exs.rp << 4; - } + operand->Info.Register.Reg = (Instrux->Exs.rp << 4) | (Instrux->Exs.r << 3) | Instrux->ModRm.reg; // Only DR0-DR7 valid. if (operand->Info.Register.Reg >= 8) @@ -2481,9 +2490,16 @@ NdParseOperand( operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm; // If APX is present, use B4 as well. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.b4 != 0) { - operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && @@ -2560,10 +2576,17 @@ NdParseOperand( operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm; - // If APX is present, use B4 as well. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.b4 != 0) { - operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + // If APX is present, use B4 as well. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && @@ -2985,6 +3008,18 @@ memory: operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; + case ND_OPT_pBP: + // [sBP], used implicitly by ENTER, when nesting level is > 1. + // Operand size bytes accessed from memory. Base reg size determined by stack address size attribute. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Info.Memory.HasBase = ND_TRUE; + operand->Info.Memory.BaseSize = 2 << Instrux->DefStack; + operand->Info.Memory.Base = NDR_RBP; // Always rBP. + operand->Info.Memory.HasSeg = ND_TRUE; + operand->Info.Memory.Seg = NDR_SS; + break; + case ND_OPT_SHS: // Shadow stack access using the current SSP. Instrux->MemoryAccess |= operand->Access.Access; @@ -3037,10 +3072,17 @@ memory: operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7); - // If APX is present, extend the register. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.b4 != 0) { - operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + // If APX is present, extend the register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && @@ -3150,10 +3192,17 @@ memory: operand->Info.Memory.HasBase = ND_TRUE; operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); - // If APX is present, extend the base register. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.rp != 0) { - operand->Info.Memory.Base |= Instrux->Exs.rp << 4; + // If APX is present, extend the base register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Memory.Base |= Instrux->Exs.rp << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; @@ -3168,10 +3217,17 @@ memory: operand->Info.Memory.HasBase = ND_TRUE; operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - // If APX is present, extend the base register. - if (Instrux->FeatMode & ND_FEAT_APX) + if (Instrux->Exs.b4 != 0) { - operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + // If APX is present, extend the base register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; @@ -3188,20 +3244,11 @@ memory: operand->Info.Register.Reg = Instrux->ModRm.reg; // #UD if a tile register > 7 is encoded. - if (Instrux->Exs.r != 0) + if (Instrux->Exs.r != 0 || Instrux->Exs.rp != 0) { return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } - // #UD of R4 is not 0. - if (Instrux->FeatMode & ND_FEAT_APX) - { - if (Instrux->Exs.rp != 0) - { - return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; - } - } - break; case ND_OPT_mT: @@ -3213,20 +3260,11 @@ memory: operand->Info.Register.Reg = Instrux->ModRm.rm; // #UD if a tile register > 7 is encoded. - if (Instrux->Exs.b != 0) + if (Instrux->Exs.b != 0 || Instrux->Exs.b4 != 0) { return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } - // #UD of B4 is not 0. - if (Instrux->FeatMode & ND_FEAT_APX) - { - if (Instrux->Exs.b4 != 0) - { - return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; - } - } - break; case ND_OPT_vT: @@ -3238,20 +3276,11 @@ memory: operand->Info.Register.Reg = Instrux->Exs.v; // #UD if a tile register > 7 is encoded. - if (operand->Info.Register.Reg > 7) + if (operand->Info.Register.Reg > 7 || Instrux->Exs.vp != 0) { return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } - // #UD of V4 is not 0. - if (Instrux->FeatMode & ND_FEAT_APX) - { - if (Instrux->Exs.vp != 0) - { - return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; - } - } - break; case ND_OPT_dfv: @@ -3278,7 +3307,7 @@ memory: if (opb != 0) { operand->Info.Register.Count = opb; - operand->Info.Register.Reg &= ~(opb - 1); + operand->Info.Register.Reg &= (ND_UINT32)~(opb - 1); operand->Info.Register.IsBlock = ND_TRUE; } else @@ -3894,10 +3923,18 @@ NdGetVectorLength( (Instrux->TupleType == ND_TUPLE_T1S16) || (Instrux->TupleType == ND_TUPLE_T1F)) { + // Scalar instruction, vector length is 128 bits. Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128; } + else if (Instrux->Evex.u == 0) + { + // AVX 10 allows SAE/ER for 256-bit vector length, if EVEX.U is 0. + // It is unclear whether the EVEX.U bit is ignored or reserved for scalar instructions. + Instrux->VecMode = Instrux->EfVecMode = ND_VECM_256; + } else { + // Legacy or AVX 10 instruction with U bit set, vector length is 512 bits. Instrux->VecMode = Instrux->EfVecMode = ND_VECM_512; } @@ -4055,6 +4092,12 @@ NdGetEvexFields( // Validate the EVEX prefix, depending on the EVEX extension mode. if (Instrux->EvexMode == ND_EVEXM_EVEX) { + // EVEX.U field must be 1 if the Modrm.Mod is not reg-reg OR if EVEX.b is 0. + if (Instrux->Evex.u != 1 && (Instrux->ModRm.mod != 3 || Instrux->Exs.bm == 0)) + { + return ND_STATUS_BAD_EVEX_U; + } + // Handle embedded broadcast/rounding-control. if (Instrux->Exs.bm == 1) { @@ -4173,6 +4216,12 @@ NdGetEvexFields( return ND_STATUS_INVALID_EVEX_BYTE3; } + // EVEX.U field must be 1 if mod is reg-reg. + if (Instrux->Evex.u != 1 && Instrux->ModRm.mod == 3) + { + return ND_STATUS_BAD_EVEX_U; + } + if (Instrux->ValidDecorators.Nd) { Instrux->HasNd = (ND_BOOL)Instrux->Exs.nd; diff --git a/bddisasm/include/bdx86_instructions.h b/bddisasm/include/bdx86_instructions.h index 671b964..8bfcc43 100644 --- a/bddisasm/include/bdx86_instructions.h +++ b/bddisasm/include/bdx86_instructions.h @@ -10,7 +10,7 @@ #ifndef BDX86_INSTRUCTIONS_H #define BDX86_INSTRUCTIONS_H -const ND_IDBE gInstructions[4075] = +const ND_IDBE gInstructions[4157] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { @@ -3012,35 +3012,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:107 Instruction:"AESDEC128KL Vdq,M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem"/"RM" - { - .Instruction = ND_INS_AESDEC128KL, - .Category = ND_CAT_AESKL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 17, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:108 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" + // Pos:107 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" { .Instruction = ND_INS_AESDEC128KL, .Category = ND_CAT_AESKL, @@ -3068,35 +3040,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:109 Instruction:"AESDEC256KL Vdq,M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem"/"RM" - { - .Instruction = ND_INS_AESDEC256KL, - .Category = ND_CAT_AESKL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 18, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:110 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" + // Pos:108 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" { .Instruction = ND_INS_AESDEC256KL, .Category = ND_CAT_AESKL, @@ -3124,7 +3068,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:111 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" + // Pos:109 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" { .Instruction = ND_INS_AESDECLAST, .Category = ND_CAT_AES, @@ -3151,35 +3095,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:112 Instruction:"AESDECWIDE128KL M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem"/"M" - { - .Instruction = ND_INS_AESDECWIDE128KL, - .Category = ND_CAT_WIDE_KL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 20, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 2), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:113 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" + // Pos:110 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" { .Instruction = ND_INS_AESDECWIDE128KL, .Category = ND_CAT_WIDE_KL, @@ -3207,35 +3123,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:114 Instruction:"AESDECWIDE256KL M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem"/"M" - { - .Instruction = ND_INS_AESDECWIDE256KL, - .Category = ND_CAT_WIDE_KL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 21, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 2), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:115 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" + // Pos:111 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" { .Instruction = ND_INS_AESDECWIDE256KL, .Category = ND_CAT_WIDE_KL, @@ -3263,7 +3151,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:116 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" + // Pos:112 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" { .Instruction = ND_INS_AESENC, .Category = ND_CAT_AES, @@ -3290,35 +3178,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:117 Instruction:"AESENC128KL Vdq,M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem"/"RM" - { - .Instruction = ND_INS_AESENC128KL, - .Category = ND_CAT_AESKL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 23, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:118 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" + // Pos:113 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" { .Instruction = ND_INS_AESENC128KL, .Category = ND_CAT_AESKL, @@ -3346,35 +3206,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:119 Instruction:"AESENC256KL Vdq,M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem"/"RM" - { - .Instruction = ND_INS_AESENC256KL, - .Category = ND_CAT_AESKL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 24, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:120 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" + // Pos:114 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" { .Instruction = ND_INS_AESENC256KL, .Category = ND_CAT_AESKL, @@ -3402,7 +3234,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:121 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" + // Pos:115 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" { .Instruction = ND_INS_AESENCLAST, .Category = ND_CAT_AES, @@ -3429,35 +3261,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:122 Instruction:"AESENCWIDE128KL M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem"/"M" - { - .Instruction = ND_INS_AESENCWIDE128KL, - .Category = ND_CAT_WIDE_KL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 26, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 2), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:123 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" + // Pos:116 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" { .Instruction = ND_INS_AESENCWIDE128KL, .Category = ND_CAT_WIDE_KL, @@ -3485,35 +3289,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:124 Instruction:"AESENCWIDE256KL M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem"/"M" - { - .Instruction = ND_INS_AESENCWIDE256KL, - .Category = ND_CAT_WIDE_KL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 27, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 2), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_ZF, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:125 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" + // Pos:117 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" { .Instruction = ND_INS_AESENCWIDE256KL, .Category = ND_CAT_WIDE_KL, @@ -3541,7 +3317,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:126 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" + // Pos:118 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" { .Instruction = ND_INS_AESIMC, .Category = ND_CAT_AES, @@ -3568,7 +3344,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:127 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" + // Pos:119 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" { .Instruction = ND_INS_AESKEYGENASSIST, .Category = ND_CAT_AES, @@ -3596,7 +3372,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:128 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x20 /r"/"MR" + // Pos:120 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x20 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3624,7 +3400,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:129 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x21 /r"/"MR" + // Pos:121 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x21 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3652,7 +3428,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:130 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x21 /r"/"MR" + // Pos:122 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x21 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3680,7 +3456,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:131 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x22 /r"/"RM" + // Pos:123 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x22 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3708,7 +3484,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:132 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x23 /r"/"RM" + // Pos:124 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x23 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3736,7 +3512,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:133 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x23 /r"/"RM" + // Pos:125 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x23 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3764,7 +3540,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:134 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /4 ib"/"MI" + // Pos:126 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3792,7 +3568,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:135 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /4 iz"/"MI" + // Pos:127 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /4 iz"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3820,7 +3596,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:136 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /4 iz"/"MI" + // Pos:128 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /4 iz"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3848,7 +3624,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:137 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /4 ib"/"MI" + // Pos:129 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3876,7 +3652,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:138 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /4 ib"/"MI" + // Pos:130 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3904,7 +3680,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:139 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x20 /r"/"MR" + // Pos:131 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x20 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3931,7 +3707,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:140 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x21 /r"/"MR" + // Pos:132 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x21 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3958,7 +3734,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:141 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x21 /r"/"MR" + // Pos:133 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x21 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -3985,7 +3761,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:142 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x22 /r"/"RM" + // Pos:134 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x22 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4012,7 +3788,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:143 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x23 /r"/"RM" + // Pos:135 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x23 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4039,7 +3815,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:144 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x23 /r"/"RM" + // Pos:136 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x23 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4066,7 +3842,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:145 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /4 ib"/"MI" + // Pos:137 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4093,7 +3869,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:146 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /4 iz"/"MI" + // Pos:138 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /4 iz"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4120,7 +3896,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:147 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /4 iz"/"MI" + // Pos:139 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /4 iz"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4147,7 +3923,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:148 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /4 ib"/"MI" + // Pos:140 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4174,7 +3950,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:149 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /4 ib"/"MI" + // Pos:141 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4201,7 +3977,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:150 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x20 /r"/"VMR" + // Pos:142 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x20 /r"/"VMR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4230,7 +4006,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:151 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x21 /r"/"VMR" + // Pos:143 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x21 /r"/"VMR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4259,7 +4035,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:152 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x21 /r"/"VMR" + // Pos:144 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x21 /r"/"VMR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4288,7 +4064,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:153 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x22 /r"/"VRM" + // Pos:145 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x22 /r"/"VRM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4317,7 +4093,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:154 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x23 /r"/"VRM" + // Pos:146 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x23 /r"/"VRM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4346,7 +4122,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:155 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x23 /r"/"VRM" + // Pos:147 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x23 /r"/"VRM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4375,7 +4151,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:156 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /4 ib"/"VMI" + // Pos:148 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /4 ib"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4404,7 +4180,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:157 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /4 iz"/"VMI" + // Pos:149 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /4 iz"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4433,7 +4209,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:158 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /4 iz"/"VMI" + // Pos:150 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /4 iz"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4462,7 +4238,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:159 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /4 ib"/"VMI" + // Pos:151 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /4 ib"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4491,7 +4267,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:160 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /4 ib"/"VMI" + // Pos:152 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /4 ib"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4520,7 +4296,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:161 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x20 /r"/"VMR" + // Pos:153 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x20 /r"/"VMR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4548,7 +4324,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:162 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x21 /r"/"VMR" + // Pos:154 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x21 /r"/"VMR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4576,7 +4352,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:163 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x21 /r"/"VMR" + // Pos:155 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x21 /r"/"VMR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4604,7 +4380,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:164 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x22 /r"/"VRM" + // Pos:156 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x22 /r"/"VRM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4632,7 +4408,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:165 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x23 /r"/"VRM" + // Pos:157 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x23 /r"/"VRM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4660,7 +4436,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:166 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x23 /r"/"VRM" + // Pos:158 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x23 /r"/"VRM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4688,7 +4464,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:167 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /4 ib"/"VMI" + // Pos:159 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /4 ib"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4716,7 +4492,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:168 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /4 iz"/"VMI" + // Pos:160 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /4 iz"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4744,7 +4520,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:169 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /4 iz"/"VMI" + // Pos:161 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /4 iz"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4772,7 +4548,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:170 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /4 ib"/"VMI" + // Pos:162 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /4 ib"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4800,7 +4576,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:171 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /4 ib"/"VMI" + // Pos:163 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /4 ib"/"VMI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4828,7 +4604,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:172 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" + // Pos:164 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4856,7 +4632,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:173 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" + // Pos:165 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4884,7 +4660,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:174 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" + // Pos:166 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4912,7 +4688,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:175 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" + // Pos:167 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4940,7 +4716,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:176 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" + // Pos:168 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4968,7 +4744,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:177 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" + // Pos:169 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -4996,7 +4772,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:178 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" + // Pos:170 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -5024,7 +4800,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:179 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" + // Pos:171 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -5052,7 +4828,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:180 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" + // Pos:172 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -5080,7 +4856,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:181 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" + // Pos:173 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" { .Instruction = ND_INS_AND, .Category = ND_CAT_LOGIC, @@ -5108,7 +4884,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:182 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF2 /r"/"RVM" + // Pos:174 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF2 /r"/"RVM" { .Instruction = ND_INS_ANDN, .Category = ND_CAT_BMI1, @@ -5137,7 +4913,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:183 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF2 /r"/"RVM" + // Pos:175 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF2 /r"/"RVM" { .Instruction = ND_INS_ANDN, .Category = ND_CAT_BMI1, @@ -5165,7 +4941,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:184 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" + // Pos:176 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" { .Instruction = ND_INS_ANDN, .Category = ND_CAT_BMI1, @@ -5194,7 +4970,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:185 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" + // Pos:177 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" { .Instruction = ND_INS_ANDNPD, .Category = ND_CAT_LOGICAL_FP, @@ -5221,7 +4997,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:186 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" + // Pos:178 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" { .Instruction = ND_INS_ANDNPS, .Category = ND_CAT_LOGICAL_FP, @@ -5248,7 +5024,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:187 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" + // Pos:179 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" { .Instruction = ND_INS_ANDPD, .Category = ND_CAT_LOGICAL_FP, @@ -5275,7 +5051,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:188 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" + // Pos:180 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" { .Instruction = ND_INS_ANDPS, .Category = ND_CAT_LOGICAL_FP, @@ -5302,7 +5078,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:189 Instruction:"AOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 0xFC /r:mem"/"MR" + // Pos:181 Instruction:"AOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 0xFC /r:mem"/"MR" { .Instruction = ND_INS_AOR, .Category = ND_CAT_RAOINT, @@ -5329,7 +5105,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:190 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR" + // Pos:182 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR" { .Instruction = ND_INS_AOR, .Category = ND_CAT_RAOINT, @@ -5356,7 +5132,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:191 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" + // Pos:183 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" { .Instruction = ND_INS_ARPL, .Category = ND_CAT_SYSTEM, @@ -5384,7 +5160,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:192 Instruction:"AXOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0xFC /r:mem"/"MR" + // Pos:184 Instruction:"AXOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0xFC /r:mem"/"MR" { .Instruction = ND_INS_AXOR, .Category = ND_CAT_RAOINT, @@ -5411,7 +5187,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:193 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR" + // Pos:185 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR" { .Instruction = ND_INS_AXOR, .Category = ND_CAT_RAOINT, @@ -5438,7 +5214,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:194 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:186 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_BEXTR, .Category = ND_CAT_BMI1, @@ -5467,7 +5243,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:195 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF7 /r"/"RMV" + // Pos:187 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF7 /r"/"RMV" { .Instruction = ND_INS_BEXTR, .Category = ND_CAT_BMI1, @@ -5495,7 +5271,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:196 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" + // Pos:188 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_BEXTR, .Category = ND_CAT_BMI1, @@ -5524,7 +5300,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:197 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" + // Pos:189 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" { .Instruction = ND_INS_BEXTR, .Category = ND_CAT_BITBYTE, @@ -5552,7 +5328,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:198 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" + // Pos:190 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" { .Instruction = ND_INS_BLCFILL, .Category = ND_CAT_BITBYTE, @@ -5579,7 +5355,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:199 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" + // Pos:191 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" { .Instruction = ND_INS_BLCI, .Category = ND_CAT_BITBYTE, @@ -5606,7 +5382,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:200 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" + // Pos:192 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" { .Instruction = ND_INS_BLCIC, .Category = ND_CAT_BITBYTE, @@ -5633,7 +5409,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:201 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" + // Pos:193 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" { .Instruction = ND_INS_BLCMSK, .Category = ND_CAT_BITBYTE, @@ -5660,7 +5436,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:202 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" + // Pos:194 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" { .Instruction = ND_INS_BLCS, .Category = ND_CAT_BITBYTE, @@ -5687,7 +5463,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:203 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" + // Pos:195 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" { .Instruction = ND_INS_BLENDPD, .Category = ND_CAT_SSE, @@ -5715,7 +5491,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:204 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" + // Pos:196 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" { .Instruction = ND_INS_BLENDPS, .Category = ND_CAT_SSE, @@ -5743,7 +5519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:205 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" + // Pos:197 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" { .Instruction = ND_INS_BLENDVPD, .Category = ND_CAT_SSE, @@ -5771,7 +5547,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:206 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" + // Pos:198 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" { .Instruction = ND_INS_BLENDVPS, .Category = ND_CAT_SSE, @@ -5799,7 +5575,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:207 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" + // Pos:199 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" { .Instruction = ND_INS_BLSFILL, .Category = ND_CAT_BITBYTE, @@ -5826,7 +5602,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:208 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /3"/"VM" + // Pos:200 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /3"/"VM" { .Instruction = ND_INS_BLSI, .Category = ND_CAT_BMI1, @@ -5854,7 +5630,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:209 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /3"/"VM" + // Pos:201 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /3"/"VM" { .Instruction = ND_INS_BLSI, .Category = ND_CAT_BMI1, @@ -5881,7 +5657,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:210 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" + // Pos:202 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" { .Instruction = ND_INS_BLSI, .Category = ND_CAT_BMI1, @@ -5909,7 +5685,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:211 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" + // Pos:203 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" { .Instruction = ND_INS_BLSIC, .Category = ND_CAT_BITBYTE, @@ -5936,7 +5712,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:212 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /2"/"VM" + // Pos:204 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /2"/"VM" { .Instruction = ND_INS_BLSMSK, .Category = ND_CAT_BMI1, @@ -5964,7 +5740,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:213 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /2"/"VM" + // Pos:205 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /2"/"VM" { .Instruction = ND_INS_BLSMSK, .Category = ND_CAT_BMI1, @@ -5991,7 +5767,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:214 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" + // Pos:206 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" { .Instruction = ND_INS_BLSMSK, .Category = ND_CAT_BMI1, @@ -6019,7 +5795,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:215 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /1"/"VM" + // Pos:207 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /1"/"VM" { .Instruction = ND_INS_BLSR, .Category = ND_CAT_BMI1, @@ -6047,7 +5823,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:216 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /1"/"VM" + // Pos:208 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /1"/"VM" { .Instruction = ND_INS_BLSR, .Category = ND_CAT_BMI1, @@ -6074,7 +5850,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:217 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" + // Pos:209 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" { .Instruction = ND_INS_BLSR, .Category = ND_CAT_BMI1, @@ -6102,7 +5878,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:218 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" + // Pos:210 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" { .Instruction = ND_INS_BNDCL, .Category = ND_CAT_MPX, @@ -6129,7 +5905,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:219 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" + // Pos:211 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" { .Instruction = ND_INS_BNDCN, .Category = ND_CAT_MPX, @@ -6156,7 +5932,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:220 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" + // Pos:212 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" { .Instruction = ND_INS_BNDCU, .Category = ND_CAT_MPX, @@ -6183,7 +5959,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:221 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx NP 0x0F 0x1A /r:mem mib"/"RM" + // Pos:213 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx NP 0x0F 0x1A /r:mem mib"/"RM" { .Instruction = ND_INS_BNDLDX, .Category = ND_CAT_MPX, @@ -6210,7 +5986,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:222 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" + // Pos:214 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" { .Instruction = ND_INS_BNDMK, .Category = ND_CAT_MPX, @@ -6237,7 +6013,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:223 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" + // Pos:215 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" { .Instruction = ND_INS_BNDMOV, .Category = ND_CAT_MPX, @@ -6264,7 +6040,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:224 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" + // Pos:216 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" { .Instruction = ND_INS_BNDMOV, .Category = ND_CAT_MPX, @@ -6291,7 +6067,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:225 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx NP 0x0F 0x1B /r:mem mib"/"MR" + // Pos:217 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx NP 0x0F 0x1B /r:mem mib"/"MR" { .Instruction = ND_INS_BNDSTX, .Category = ND_CAT_MPX, @@ -6318,7 +6094,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:226 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" + // Pos:218 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" { .Instruction = ND_INS_BOUND, .Category = ND_CAT_INTERRUPT, @@ -6345,7 +6121,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:227 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" + // Pos:219 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" { .Instruction = ND_INS_BSF, .Category = ND_CAT_I386, @@ -6373,7 +6149,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:228 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" + // Pos:220 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" { .Instruction = ND_INS_BSR, .Category = ND_CAT_BITBYTE, @@ -6401,7 +6177,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:229 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" + // Pos:221 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6427,7 +6203,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:230 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" + // Pos:222 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6453,7 +6229,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:231 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" + // Pos:223 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6479,7 +6255,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:232 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" + // Pos:224 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6505,7 +6281,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:233 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" + // Pos:225 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6531,7 +6307,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:234 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" + // Pos:226 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6557,7 +6333,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:235 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" + // Pos:227 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6583,7 +6359,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:236 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" + // Pos:228 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" { .Instruction = ND_INS_BSWAP, .Category = ND_CAT_DATAXFER, @@ -6609,7 +6385,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:237 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" + // Pos:229 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" { .Instruction = ND_INS_BT, .Category = ND_CAT_BITBYTE, @@ -6637,7 +6413,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:238 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" + // Pos:230 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" { .Instruction = ND_INS_BT, .Category = ND_CAT_BITBYTE, @@ -6665,7 +6441,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:239 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" + // Pos:231 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" { .Instruction = ND_INS_BTC, .Category = ND_CAT_BITBYTE, @@ -6693,7 +6469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:240 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" + // Pos:232 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" { .Instruction = ND_INS_BTC, .Category = ND_CAT_I386, @@ -6721,7 +6497,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:241 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" + // Pos:233 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" { .Instruction = ND_INS_BTR, .Category = ND_CAT_BITBYTE, @@ -6749,7 +6525,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:242 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" + // Pos:234 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" { .Instruction = ND_INS_BTR, .Category = ND_CAT_BITBYTE, @@ -6777,7 +6553,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:243 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" + // Pos:235 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" { .Instruction = ND_INS_BTS, .Category = ND_CAT_BITBYTE, @@ -6805,7 +6581,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:244 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" + // Pos:236 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" { .Instruction = ND_INS_BTS, .Category = ND_CAT_BITBYTE, @@ -6833,7 +6609,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:245 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF5 /r"/"RMV" + // Pos:237 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF5 /r"/"RMV" { .Instruction = ND_INS_BZHI, .Category = ND_CAT_BMI2, @@ -6862,7 +6638,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:246 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF5 /r"/"RMV" + // Pos:238 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF5 /r"/"RMV" { .Instruction = ND_INS_BZHI, .Category = ND_CAT_BMI2, @@ -6890,7 +6666,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:247 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" + // Pos:239 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" { .Instruction = ND_INS_BZHI, .Category = ND_CAT_BMI2, @@ -6919,7 +6695,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:248 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" + // Pos:240 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" { .Instruction = ND_INS_CALLNR, .Category = ND_CAT_CALL, @@ -6948,7 +6724,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:249 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" + // Pos:241 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" { .Instruction = ND_INS_CALLNI, .Category = ND_CAT_CALL, @@ -6977,7 +6753,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:250 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" + // Pos:242 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" { .Instruction = ND_INS_CALLFD, .Category = ND_CAT_CALL, @@ -7007,7 +6783,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:251 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" + // Pos:243 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" { .Instruction = ND_INS_CALLFI, .Category = ND_CAT_CALL, @@ -7037,7 +6813,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:252 Instruction:"CBW" Encoding:"ds16 0x98"/"" + // Pos:244 Instruction:"CBW" Encoding:"ds16 0x98"/"" { .Instruction = ND_INS_CBW, .Category = ND_CAT_CONVERT, @@ -7064,7 +6840,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:253 Instruction:"CCMPBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x38 /r"/"MRV" + // Pos:245 Instruction:"CCMPBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7093,7 +6869,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:254 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x39 /r"/"MRV" + // Pos:246 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7122,7 +6898,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:255 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x39 /r"/"MRV" + // Pos:247 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7151,7 +6927,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:256 Instruction:"CCMPBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3A /r"/"RMV" + // Pos:248 Instruction:"CCMPBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7180,7 +6956,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:257 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3B /r"/"RMV" + // Pos:249 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7209,7 +6985,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:258 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x3B /r"/"RMV" + // Pos:250 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7238,7 +7014,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:259 Instruction:"CCMPBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x80 /7 ib"/"MIV" + // Pos:251 Instruction:"CCMPBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7267,7 +7043,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:260 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x81 /7 iz"/"MIV" + // Pos:252 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7296,7 +7072,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:261 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x81 /7 iz"/"MIV" + // Pos:253 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7325,7 +7101,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:262 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x83 /7 ib"/"MIV" + // Pos:254 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7354,7 +7130,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:263 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x83 /7 ib"/"MIV" + // Pos:255 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7383,7 +7159,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:264 Instruction:"CCMPC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x38 /r"/"MRV" + // Pos:256 Instruction:"CCMPC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7412,7 +7188,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:265 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x39 /r"/"MRV" + // Pos:257 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7441,7 +7217,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:266 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x39 /r"/"MRV" + // Pos:258 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7470,7 +7246,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:267 Instruction:"CCMPC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3A /r"/"RMV" + // Pos:259 Instruction:"CCMPC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7499,7 +7275,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:268 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3B /r"/"RMV" + // Pos:260 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7528,7 +7304,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:269 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x3B /r"/"RMV" + // Pos:261 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7557,7 +7333,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:270 Instruction:"CCMPC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x80 /7 ib"/"MIV" + // Pos:262 Instruction:"CCMPC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7586,7 +7362,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:271 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x81 /7 iz"/"MIV" + // Pos:263 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7615,7 +7391,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:272 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x81 /7 iz"/"MIV" + // Pos:264 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7644,7 +7420,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:273 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x83 /7 ib"/"MIV" + // Pos:265 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7673,7 +7449,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:274 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x83 /7 ib"/"MIV" + // Pos:266 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7702,7 +7478,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:275 Instruction:"CCMPF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x38 /r"/"MRV" + // Pos:267 Instruction:"CCMPF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7731,7 +7507,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:276 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x39 /r"/"MRV" + // Pos:268 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7760,7 +7536,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:277 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x39 /r"/"MRV" + // Pos:269 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7789,7 +7565,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:278 Instruction:"CCMPF Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3A /r"/"RMV" + // Pos:270 Instruction:"CCMPF Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7818,7 +7594,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:279 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3B /r"/"RMV" + // Pos:271 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7847,7 +7623,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:280 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x3B /r"/"RMV" + // Pos:272 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7876,7 +7652,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:281 Instruction:"CCMPF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x80 /7 ib"/"MIV" + // Pos:273 Instruction:"CCMPF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7905,7 +7681,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:282 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x81 /7 iz"/"MIV" + // Pos:274 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7934,7 +7710,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:283 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x81 /7 iz"/"MIV" + // Pos:275 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7963,7 +7739,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:284 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x83 /7 ib"/"MIV" + // Pos:276 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -7992,7 +7768,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:285 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x83 /7 ib"/"MIV" + // Pos:277 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8021,7 +7797,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:286 Instruction:"CCMPL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x38 /r"/"MRV" + // Pos:278 Instruction:"CCMPL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8050,7 +7826,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:287 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x39 /r"/"MRV" + // Pos:279 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8079,7 +7855,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:288 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x39 /r"/"MRV" + // Pos:280 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8108,7 +7884,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:289 Instruction:"CCMPL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3A /r"/"RMV" + // Pos:281 Instruction:"CCMPL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8137,7 +7913,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:290 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3B /r"/"RMV" + // Pos:282 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8166,7 +7942,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:291 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x3B /r"/"RMV" + // Pos:283 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8195,7 +7971,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:292 Instruction:"CCMPL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x80 /7 ib"/"MIV" + // Pos:284 Instruction:"CCMPL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8224,7 +8000,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:293 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x81 /7 iz"/"MIV" + // Pos:285 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8253,7 +8029,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:294 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x81 /7 iz"/"MIV" + // Pos:286 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8282,7 +8058,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:295 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x83 /7 ib"/"MIV" + // Pos:287 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8311,7 +8087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:296 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x83 /7 ib"/"MIV" + // Pos:288 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8340,7 +8116,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:297 Instruction:"CCMPLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x38 /r"/"MRV" + // Pos:289 Instruction:"CCMPLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8369,7 +8145,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:298 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x39 /r"/"MRV" + // Pos:290 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8398,7 +8174,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:299 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x39 /r"/"MRV" + // Pos:291 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8427,7 +8203,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:300 Instruction:"CCMPLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3A /r"/"RMV" + // Pos:292 Instruction:"CCMPLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8456,7 +8232,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:301 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3B /r"/"RMV" + // Pos:293 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8485,7 +8261,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:302 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x3B /r"/"RMV" + // Pos:294 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8514,7 +8290,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:303 Instruction:"CCMPLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x80 /7 ib"/"MIV" + // Pos:295 Instruction:"CCMPLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8543,7 +8319,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:304 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x81 /7 iz"/"MIV" + // Pos:296 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8572,7 +8348,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:305 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x81 /7 iz"/"MIV" + // Pos:297 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8601,7 +8377,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:306 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x83 /7 ib"/"MIV" + // Pos:298 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8630,7 +8406,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:307 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x83 /7 ib"/"MIV" + // Pos:299 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8659,7 +8435,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:308 Instruction:"CCMPNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x38 /r"/"MRV" + // Pos:300 Instruction:"CCMPNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8688,7 +8464,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:309 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x39 /r"/"MRV" + // Pos:301 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8717,7 +8493,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:310 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x39 /r"/"MRV" + // Pos:302 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8746,7 +8522,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:311 Instruction:"CCMPNBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3A /r"/"RMV" + // Pos:303 Instruction:"CCMPNBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8775,7 +8551,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:312 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3B /r"/"RMV" + // Pos:304 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8804,7 +8580,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:313 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x3B /r"/"RMV" + // Pos:305 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8833,7 +8609,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:314 Instruction:"CCMPNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x80 /7 ib"/"MIV" + // Pos:306 Instruction:"CCMPNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8862,7 +8638,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:315 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x81 /7 iz"/"MIV" + // Pos:307 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8891,7 +8667,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:316 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x81 /7 iz"/"MIV" + // Pos:308 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8920,7 +8696,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:317 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x83 /7 ib"/"MIV" + // Pos:309 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8949,7 +8725,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:318 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x83 /7 ib"/"MIV" + // Pos:310 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -8978,7 +8754,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:319 Instruction:"CCMPNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x38 /r"/"MRV" + // Pos:311 Instruction:"CCMPNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9007,7 +8783,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:320 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x39 /r"/"MRV" + // Pos:312 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9036,7 +8812,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:321 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x39 /r"/"MRV" + // Pos:313 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9065,7 +8841,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:322 Instruction:"CCMPNC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3A /r"/"RMV" + // Pos:314 Instruction:"CCMPNC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9094,7 +8870,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:323 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3B /r"/"RMV" + // Pos:315 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9123,7 +8899,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:324 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x3B /r"/"RMV" + // Pos:316 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9152,7 +8928,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:325 Instruction:"CCMPNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x80 /7 ib"/"MIV" + // Pos:317 Instruction:"CCMPNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9181,7 +8957,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:326 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x81 /7 iz"/"MIV" + // Pos:318 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9210,7 +8986,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:327 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x81 /7 iz"/"MIV" + // Pos:319 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9239,7 +9015,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:328 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x83 /7 ib"/"MIV" + // Pos:320 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9268,7 +9044,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:329 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x83 /7 ib"/"MIV" + // Pos:321 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9297,7 +9073,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:330 Instruction:"CCMPNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x38 /r"/"MRV" + // Pos:322 Instruction:"CCMPNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9326,7 +9102,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:331 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x39 /r"/"MRV" + // Pos:323 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9355,7 +9131,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:332 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x39 /r"/"MRV" + // Pos:324 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9384,7 +9160,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:333 Instruction:"CCMPNL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3A /r"/"RMV" + // Pos:325 Instruction:"CCMPNL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9413,7 +9189,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:334 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3B /r"/"RMV" + // Pos:326 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9442,7 +9218,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:335 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x3B /r"/"RMV" + // Pos:327 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9471,7 +9247,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:336 Instruction:"CCMPNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x80 /7 ib"/"MIV" + // Pos:328 Instruction:"CCMPNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9500,7 +9276,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:337 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x81 /7 iz"/"MIV" + // Pos:329 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9529,7 +9305,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:338 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x81 /7 iz"/"MIV" + // Pos:330 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9558,7 +9334,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:339 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x83 /7 ib"/"MIV" + // Pos:331 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9587,7 +9363,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:340 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x83 /7 ib"/"MIV" + // Pos:332 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9616,7 +9392,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:341 Instruction:"CCMPNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x38 /r"/"MRV" + // Pos:333 Instruction:"CCMPNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9645,7 +9421,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:342 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x39 /r"/"MRV" + // Pos:334 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9674,7 +9450,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:343 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x39 /r"/"MRV" + // Pos:335 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9703,7 +9479,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:344 Instruction:"CCMPNLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3A /r"/"RMV" + // Pos:336 Instruction:"CCMPNLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9732,7 +9508,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:345 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3B /r"/"RMV" + // Pos:337 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9761,7 +9537,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:346 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x3B /r"/"RMV" + // Pos:338 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9790,7 +9566,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:347 Instruction:"CCMPNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x80 /7 ib"/"MIV" + // Pos:339 Instruction:"CCMPNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9819,7 +9595,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:348 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x81 /7 iz"/"MIV" + // Pos:340 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9848,7 +9624,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:349 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x81 /7 iz"/"MIV" + // Pos:341 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9877,7 +9653,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:350 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x83 /7 ib"/"MIV" + // Pos:342 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9906,7 +9682,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:351 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x83 /7 ib"/"MIV" + // Pos:343 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9935,7 +9711,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:352 Instruction:"CCMPNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x38 /r"/"MRV" + // Pos:344 Instruction:"CCMPNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9964,7 +9740,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:353 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x39 /r"/"MRV" + // Pos:345 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -9993,7 +9769,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:354 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x39 /r"/"MRV" + // Pos:346 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10022,7 +9798,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:355 Instruction:"CCMPNO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3A /r"/"RMV" + // Pos:347 Instruction:"CCMPNO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10051,7 +9827,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:356 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3B /r"/"RMV" + // Pos:348 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10080,7 +9856,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:357 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x3B /r"/"RMV" + // Pos:349 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10109,7 +9885,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:358 Instruction:"CCMPNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x80 /7 ib"/"MIV" + // Pos:350 Instruction:"CCMPNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10138,7 +9914,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:359 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x81 /7 iz"/"MIV" + // Pos:351 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10167,7 +9943,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:360 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x81 /7 iz"/"MIV" + // Pos:352 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10196,7 +9972,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:361 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x83 /7 ib"/"MIV" + // Pos:353 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10225,7 +10001,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:362 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x83 /7 ib"/"MIV" + // Pos:354 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10254,7 +10030,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:363 Instruction:"CCMPNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x38 /r"/"MRV" + // Pos:355 Instruction:"CCMPNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10283,7 +10059,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:364 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x39 /r"/"MRV" + // Pos:356 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10312,7 +10088,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:365 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x39 /r"/"MRV" + // Pos:357 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10341,7 +10117,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:366 Instruction:"CCMPNS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3A /r"/"RMV" + // Pos:358 Instruction:"CCMPNS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10370,7 +10146,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:367 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3B /r"/"RMV" + // Pos:359 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10399,7 +10175,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:368 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x3B /r"/"RMV" + // Pos:360 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10428,7 +10204,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:369 Instruction:"CCMPNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x80 /7 ib"/"MIV" + // Pos:361 Instruction:"CCMPNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10457,7 +10233,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:370 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x81 /7 iz"/"MIV" + // Pos:362 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10486,7 +10262,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:371 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x81 /7 iz"/"MIV" + // Pos:363 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10515,7 +10291,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:372 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x83 /7 ib"/"MIV" + // Pos:364 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10544,7 +10320,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:373 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x83 /7 ib"/"MIV" + // Pos:365 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10573,7 +10349,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:374 Instruction:"CCMPNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x38 /r"/"MRV" + // Pos:366 Instruction:"CCMPNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10602,7 +10378,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:375 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x39 /r"/"MRV" + // Pos:367 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10631,7 +10407,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:376 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x39 /r"/"MRV" + // Pos:368 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10660,7 +10436,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:377 Instruction:"CCMPNZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3A /r"/"RMV" + // Pos:369 Instruction:"CCMPNZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10689,7 +10465,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:378 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3B /r"/"RMV" + // Pos:370 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10718,7 +10494,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:379 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x3B /r"/"RMV" + // Pos:371 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10747,7 +10523,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:380 Instruction:"CCMPNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x80 /7 ib"/"MIV" + // Pos:372 Instruction:"CCMPNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10776,7 +10552,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:381 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x81 /7 iz"/"MIV" + // Pos:373 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10805,7 +10581,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:382 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x81 /7 iz"/"MIV" + // Pos:374 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10834,7 +10610,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:383 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x83 /7 ib"/"MIV" + // Pos:375 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10863,7 +10639,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:384 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x83 /7 ib"/"MIV" + // Pos:376 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10892,7 +10668,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:385 Instruction:"CCMPO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x38 /r"/"MRV" + // Pos:377 Instruction:"CCMPO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10921,7 +10697,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:386 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x39 /r"/"MRV" + // Pos:378 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10950,7 +10726,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:387 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x39 /r"/"MRV" + // Pos:379 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -10979,7 +10755,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:388 Instruction:"CCMPO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3A /r"/"RMV" + // Pos:380 Instruction:"CCMPO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11008,7 +10784,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:389 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3B /r"/"RMV" + // Pos:381 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11037,7 +10813,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:390 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x3B /r"/"RMV" + // Pos:382 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11066,7 +10842,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:391 Instruction:"CCMPO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x80 /7 ib"/"MIV" + // Pos:383 Instruction:"CCMPO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11095,7 +10871,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:392 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x81 /7 iz"/"MIV" + // Pos:384 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11124,7 +10900,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:393 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x81 /7 iz"/"MIV" + // Pos:385 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11153,7 +10929,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:394 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x83 /7 ib"/"MIV" + // Pos:386 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11182,7 +10958,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:395 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x83 /7 ib"/"MIV" + // Pos:387 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11211,7 +10987,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:396 Instruction:"CCMPS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x38 /r"/"MRV" + // Pos:388 Instruction:"CCMPS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11240,7 +11016,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:397 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x39 /r"/"MRV" + // Pos:389 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11269,7 +11045,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:398 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x39 /r"/"MRV" + // Pos:390 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11298,7 +11074,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:399 Instruction:"CCMPS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3A /r"/"RMV" + // Pos:391 Instruction:"CCMPS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11327,7 +11103,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:400 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3B /r"/"RMV" + // Pos:392 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11356,7 +11132,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:401 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x3B /r"/"RMV" + // Pos:393 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11385,7 +11161,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:402 Instruction:"CCMPS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x80 /7 ib"/"MIV" + // Pos:394 Instruction:"CCMPS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11414,7 +11190,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:403 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x81 /7 iz"/"MIV" + // Pos:395 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11443,7 +11219,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:404 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x81 /7 iz"/"MIV" + // Pos:396 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11472,7 +11248,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:405 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x83 /7 ib"/"MIV" + // Pos:397 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11501,7 +11277,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:406 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x83 /7 ib"/"MIV" + // Pos:398 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11530,7 +11306,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:407 Instruction:"CCMPT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x38 /r"/"MRV" + // Pos:399 Instruction:"CCMPT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11559,7 +11335,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:408 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x39 /r"/"MRV" + // Pos:400 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11588,7 +11364,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:409 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x39 /r"/"MRV" + // Pos:401 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11617,7 +11393,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:410 Instruction:"CCMPT Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3A /r"/"RMV" + // Pos:402 Instruction:"CCMPT Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11646,7 +11422,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:411 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3B /r"/"RMV" + // Pos:403 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11675,7 +11451,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:412 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x3B /r"/"RMV" + // Pos:404 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11704,7 +11480,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:413 Instruction:"CCMPT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x80 /7 ib"/"MIV" + // Pos:405 Instruction:"CCMPT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11733,7 +11509,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:414 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x81 /7 iz"/"MIV" + // Pos:406 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11762,7 +11538,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:415 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x81 /7 iz"/"MIV" + // Pos:407 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11791,7 +11567,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:416 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x83 /7 ib"/"MIV" + // Pos:408 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11820,7 +11596,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:417 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x83 /7 ib"/"MIV" + // Pos:409 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11849,7 +11625,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:418 Instruction:"CCMPZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x38 /r"/"MRV" + // Pos:410 Instruction:"CCMPZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x38 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11878,7 +11654,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:419 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x39 /r"/"MRV" + // Pos:411 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11907,7 +11683,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:420 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x39 /r"/"MRV" + // Pos:412 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x39 /r"/"MRV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11936,7 +11712,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:421 Instruction:"CCMPZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3A /r"/"RMV" + // Pos:413 Instruction:"CCMPZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3A /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11965,7 +11741,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:422 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3B /r"/"RMV" + // Pos:414 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -11994,7 +11770,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:423 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x3B /r"/"RMV" + // Pos:415 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x3B /r"/"RMV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -12023,7 +11799,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:424 Instruction:"CCMPZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x80 /7 ib"/"MIV" + // Pos:416 Instruction:"CCMPZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x80 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -12052,7 +11828,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:425 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x81 /7 iz"/"MIV" + // Pos:417 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -12081,7 +11857,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:426 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x81 /7 iz"/"MIV" + // Pos:418 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x81 /7 iz"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -12110,7 +11886,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:427 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x83 /7 ib"/"MIV" + // Pos:419 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -12139,7 +11915,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:428 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x83 /7 ib"/"MIV" + // Pos:420 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x83 /7 ib"/"MIV" { .Instruction = ND_INS_CCMP, .Category = ND_CAT_APX, @@ -12168,7 +11944,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:429 Instruction:"CDQ" Encoding:"ds32 0x99"/"" + // Pos:421 Instruction:"CDQ" Encoding:"ds32 0x99"/"" { .Instruction = ND_INS_CDQ, .Category = ND_CAT_CONVERT, @@ -12195,7 +11971,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:430 Instruction:"CDQE" Encoding:"ds64 0x98"/"" + // Pos:422 Instruction:"CDQE" Encoding:"ds64 0x98"/"" { .Instruction = ND_INS_CDQE, .Category = ND_CAT_CONVERT, @@ -12222,7 +11998,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:431 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x46 /r"/"RM" + // Pos:423 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x46 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12250,7 +12026,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:432 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:reg"/"MR" + // Pos:424 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12278,7 +12054,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:433 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:mem"/"MR" + // Pos:425 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12306,7 +12082,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:434 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x46 /r"/"RM" + // Pos:426 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x46 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12334,7 +12110,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:435 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:reg"/"MR" + // Pos:427 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12362,7 +12138,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:436 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:mem"/"MR" + // Pos:428 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12390,7 +12166,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:437 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x46 /r"/"VRM" + // Pos:429 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x46 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12419,7 +12195,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:438 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x46 /r"/"VRM" + // Pos:430 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x46 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12448,7 +12224,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:439 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x42 /r"/"RM" + // Pos:431 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x42 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12476,7 +12252,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:440 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:reg"/"MR" + // Pos:432 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12504,7 +12280,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:441 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:mem"/"MR" + // Pos:433 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12532,7 +12308,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:442 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x42 /r"/"RM" + // Pos:434 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x42 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12560,7 +12336,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:443 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:reg"/"MR" + // Pos:435 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12588,7 +12364,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:444 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:mem"/"MR" + // Pos:436 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12616,7 +12392,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:445 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x42 /r"/"VRM" + // Pos:437 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x42 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12645,7 +12421,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:446 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x42 /r"/"VRM" + // Pos:438 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x42 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12674,7 +12450,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:447 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4C /r"/"RM" + // Pos:439 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4C /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12702,7 +12478,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:448 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:reg"/"MR" + // Pos:440 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12730,7 +12506,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:449 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:mem"/"MR" + // Pos:441 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12758,7 +12534,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:450 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4C /r"/"RM" + // Pos:442 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4C /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12786,7 +12562,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:451 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:reg"/"MR" + // Pos:443 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12814,7 +12590,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:452 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:mem"/"MR" + // Pos:444 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12842,7 +12618,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:453 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4C /r"/"VRM" + // Pos:445 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4C /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12871,7 +12647,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:454 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4C /r"/"VRM" + // Pos:446 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4C /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12900,7 +12676,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:455 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4E /r"/"RM" + // Pos:447 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4E /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12928,7 +12704,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:456 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:reg"/"MR" + // Pos:448 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12956,7 +12732,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:457 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:mem"/"MR" + // Pos:449 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -12984,7 +12760,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:458 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4E /r"/"RM" + // Pos:450 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4E /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13012,7 +12788,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:459 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:reg"/"MR" + // Pos:451 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13040,7 +12816,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:460 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:mem"/"MR" + // Pos:452 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13068,7 +12844,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:461 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4E /r"/"VRM" + // Pos:453 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4E /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13097,7 +12873,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:462 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4E /r"/"VRM" + // Pos:454 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4E /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13126,7 +12902,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:463 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x47 /r"/"RM" + // Pos:455 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x47 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13154,7 +12930,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:464 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:reg"/"MR" + // Pos:456 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13182,7 +12958,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:465 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:mem"/"MR" + // Pos:457 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13210,7 +12986,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:466 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x47 /r"/"RM" + // Pos:458 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x47 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13238,7 +13014,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:467 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:reg"/"MR" + // Pos:459 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13266,7 +13042,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:468 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:mem"/"MR" + // Pos:460 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13294,7 +13070,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:469 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x47 /r"/"VRM" + // Pos:461 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x47 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13323,7 +13099,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:470 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x47 /r"/"VRM" + // Pos:462 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x47 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13352,7 +13128,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:471 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x43 /r"/"RM" + // Pos:463 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x43 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13380,7 +13156,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:472 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:reg"/"MR" + // Pos:464 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13408,7 +13184,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:473 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:mem"/"MR" + // Pos:465 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13436,7 +13212,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:474 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x43 /r"/"RM" + // Pos:466 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x43 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13464,7 +13240,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:475 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:reg"/"MR" + // Pos:467 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13492,7 +13268,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:476 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:mem"/"MR" + // Pos:468 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13520,7 +13296,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:477 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x43 /r"/"VRM" + // Pos:469 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x43 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13549,7 +13325,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:478 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x43 /r"/"VRM" + // Pos:470 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x43 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13578,7 +13354,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:479 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4D /r"/"RM" + // Pos:471 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4D /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13606,7 +13382,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:480 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:reg"/"MR" + // Pos:472 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13634,7 +13410,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:481 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:mem"/"MR" + // Pos:473 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13662,7 +13438,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:482 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4D /r"/"RM" + // Pos:474 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4D /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13690,7 +13466,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:483 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:reg"/"MR" + // Pos:475 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13718,7 +13494,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:484 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:mem"/"MR" + // Pos:476 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13746,7 +13522,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:485 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4D /r"/"VRM" + // Pos:477 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4D /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13775,7 +13551,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:486 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4D /r"/"VRM" + // Pos:478 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4D /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13804,7 +13580,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:487 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4F /r"/"RM" + // Pos:479 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4F /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13832,7 +13608,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:488 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:reg"/"MR" + // Pos:480 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13860,7 +13636,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:489 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:mem"/"MR" + // Pos:481 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13888,7 +13664,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:490 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4F /r"/"RM" + // Pos:482 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4F /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13916,7 +13692,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:491 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:reg"/"MR" + // Pos:483 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13944,7 +13720,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:492 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:mem"/"MR" + // Pos:484 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -13972,7 +13748,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:493 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4F /r"/"VRM" + // Pos:485 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4F /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14001,7 +13777,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:494 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4F /r"/"VRM" + // Pos:486 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4F /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14030,7 +13806,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:495 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x41 /r"/"RM" + // Pos:487 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x41 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14058,7 +13834,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:496 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:reg"/"MR" + // Pos:488 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14086,7 +13862,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:497 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:mem"/"MR" + // Pos:489 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14114,7 +13890,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:498 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x41 /r"/"RM" + // Pos:490 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x41 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14142,7 +13918,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:499 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:reg"/"MR" + // Pos:491 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14170,7 +13946,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:500 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:mem"/"MR" + // Pos:492 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14198,7 +13974,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:501 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x41 /r"/"VRM" + // Pos:493 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x41 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14227,7 +14003,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:502 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x41 /r"/"VRM" + // Pos:494 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x41 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14256,7 +14032,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:503 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4B /r"/"RM" + // Pos:495 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4B /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14284,7 +14060,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:504 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:reg"/"MR" + // Pos:496 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14312,7 +14088,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:505 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:mem"/"MR" + // Pos:497 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14340,7 +14116,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:506 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4B /r"/"RM" + // Pos:498 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4B /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14368,7 +14144,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:507 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:reg"/"MR" + // Pos:499 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14396,7 +14172,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:508 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:mem"/"MR" + // Pos:500 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14424,7 +14200,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:509 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4B /r"/"VRM" + // Pos:501 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4B /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14453,7 +14229,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:510 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4B /r"/"VRM" + // Pos:502 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4B /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14482,7 +14258,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:511 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x49 /r"/"RM" + // Pos:503 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x49 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14510,7 +14286,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:512 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:reg"/"MR" + // Pos:504 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14538,7 +14314,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:513 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:mem"/"MR" + // Pos:505 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14566,7 +14342,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:514 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x49 /r"/"RM" + // Pos:506 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x49 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14594,7 +14370,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:515 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:reg"/"MR" + // Pos:507 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14622,7 +14398,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:516 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:mem"/"MR" + // Pos:508 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14650,7 +14426,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:517 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x49 /r"/"VRM" + // Pos:509 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x49 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14679,7 +14455,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:518 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x49 /r"/"VRM" + // Pos:510 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x49 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14708,7 +14484,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:519 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x45 /r"/"RM" + // Pos:511 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x45 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14736,7 +14512,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:520 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:reg"/"MR" + // Pos:512 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14764,7 +14540,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:521 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:mem"/"MR" + // Pos:513 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14792,7 +14568,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:522 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x45 /r"/"RM" + // Pos:514 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x45 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14820,7 +14596,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:523 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:reg"/"MR" + // Pos:515 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14848,7 +14624,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:524 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:mem"/"MR" + // Pos:516 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14876,7 +14652,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:525 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x45 /r"/"VRM" + // Pos:517 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x45 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14905,7 +14681,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:526 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x45 /r"/"VRM" + // Pos:518 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x45 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14934,7 +14710,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:527 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x40 /r"/"RM" + // Pos:519 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x40 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14962,7 +14738,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:528 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:reg"/"MR" + // Pos:520 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -14990,7 +14766,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:529 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:mem"/"MR" + // Pos:521 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15018,7 +14794,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:530 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x40 /r"/"RM" + // Pos:522 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x40 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15046,7 +14822,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:531 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:reg"/"MR" + // Pos:523 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15074,7 +14850,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:532 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:mem"/"MR" + // Pos:524 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15102,7 +14878,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:533 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x40 /r"/"VRM" + // Pos:525 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x40 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15131,7 +14907,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:534 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x40 /r"/"VRM" + // Pos:526 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x40 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15160,7 +14936,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:535 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4A /r"/"RM" + // Pos:527 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4A /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15188,7 +14964,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:536 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:reg"/"MR" + // Pos:528 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15216,7 +14992,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:537 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:mem"/"MR" + // Pos:529 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15244,7 +15020,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:538 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4A /r"/"RM" + // Pos:530 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4A /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15272,7 +15048,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:539 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:reg"/"MR" + // Pos:531 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15300,7 +15076,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:540 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:mem"/"MR" + // Pos:532 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15328,7 +15104,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:541 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4A /r"/"VRM" + // Pos:533 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4A /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15357,7 +15133,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:542 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4A /r"/"VRM" + // Pos:534 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4A /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15386,7 +15162,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:543 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x48 /r"/"RM" + // Pos:535 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x48 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15414,7 +15190,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:544 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:reg"/"MR" + // Pos:536 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15442,7 +15218,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:545 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:mem"/"MR" + // Pos:537 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15470,7 +15246,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:546 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x48 /r"/"RM" + // Pos:538 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x48 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15498,7 +15274,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:547 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:reg"/"MR" + // Pos:539 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15526,7 +15302,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:548 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:mem"/"MR" + // Pos:540 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15554,7 +15330,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:549 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x48 /r"/"VRM" + // Pos:541 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x48 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15583,7 +15359,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:550 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x48 /r"/"VRM" + // Pos:542 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x48 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15612,7 +15388,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:551 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x44 /r"/"RM" + // Pos:543 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x44 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15640,7 +15416,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:552 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:reg"/"MR" + // Pos:544 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15668,7 +15444,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:553 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:mem"/"MR" + // Pos:545 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15696,7 +15472,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:554 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x44 /r"/"RM" + // Pos:546 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x44 /r"/"RM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15724,7 +15500,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:555 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:reg"/"MR" + // Pos:547 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:reg"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15752,7 +15528,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:556 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:mem"/"MR" + // Pos:548 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:mem"/"MR" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15780,7 +15556,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:557 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x44 /r"/"VRM" + // Pos:549 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x44 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15809,7 +15585,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:558 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x44 /r"/"VRM" + // Pos:550 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x44 /r"/"VRM" { .Instruction = ND_INS_CFCMOV, .Category = ND_CAT_APX, @@ -15838,7 +15614,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:559 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" + // Pos:551 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" { .Instruction = ND_INS_CLAC, .Category = ND_CAT_SMAP, @@ -15864,7 +15640,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:560 Instruction:"CLC" Encoding:"0xF8"/"" + // Pos:552 Instruction:"CLC" Encoding:"0xF8"/"" { .Instruction = ND_INS_CLC, .Category = ND_CAT_FLAGOP, @@ -15890,7 +15666,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:561 Instruction:"CLD" Encoding:"0xFC"/"" + // Pos:553 Instruction:"CLD" Encoding:"0xFC"/"" { .Instruction = ND_INS_CLD, .Category = ND_CAT_FLAGOP, @@ -15916,7 +15692,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:562 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" + // Pos:554 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" { .Instruction = ND_INS_CLDEMOTE, .Category = ND_CAT_CLDEMOTE, @@ -15942,7 +15718,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:563 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" + // Pos:555 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" { .Instruction = ND_INS_CLEVICT0, .Category = ND_CAT_UNKNOWN, @@ -15968,7 +15744,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:564 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" + // Pos:556 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" { .Instruction = ND_INS_CLEVICT1, .Category = ND_CAT_UNKNOWN, @@ -15994,7 +15770,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:565 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" + // Pos:557 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" { .Instruction = ND_INS_CLFLUSH, .Category = ND_CAT_MISC, @@ -16020,7 +15796,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:566 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" + // Pos:558 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" { .Instruction = ND_INS_CLFLUSHOPT, .Category = ND_CAT_MISC, @@ -16046,7 +15822,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:567 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" + // Pos:559 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" { .Instruction = ND_INS_CLGI, .Category = ND_CAT_SYSTEM, @@ -16072,7 +15848,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:568 Instruction:"CLI" Encoding:"0xFA"/"" + // Pos:560 Instruction:"CLI" Encoding:"0xFA"/"" { .Instruction = ND_INS_CLI, .Category = ND_CAT_FLAGOP, @@ -16098,7 +15874,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:569 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" + // Pos:561 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" { .Instruction = ND_INS_CLRSSBSY, .Category = ND_CAT_CET, @@ -16125,7 +15901,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:570 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" + // Pos:562 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" { .Instruction = ND_INS_CLTS, .Category = ND_CAT_SYSTEM, @@ -16151,7 +15927,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:571 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" + // Pos:563 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" { .Instruction = ND_INS_CLUI, .Category = ND_CAT_UINTR, @@ -16177,7 +15953,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:572 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + // Pos:564 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" { .Instruction = ND_INS_CLWB, .Category = ND_CAT_MISC, @@ -16203,7 +15979,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:573 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" + // Pos:565 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" { .Instruction = ND_INS_CLZERO, .Category = ND_CAT_MISC, @@ -16229,7 +16005,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:574 Instruction:"CMC" Encoding:"0xF5"/"" + // Pos:566 Instruction:"CMC" Encoding:"0xF5"/"" { .Instruction = ND_INS_CMC, .Category = ND_CAT_FLAGOP, @@ -16255,7 +16031,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:575 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x46 /r"/"VRM" + // Pos:567 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x46 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16284,7 +16060,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:576 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x46 /r"/"VRM" + // Pos:568 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x46 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16313,7 +16089,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:577 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" + // Pos:569 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16341,7 +16117,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:578 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x42 /r"/"VRM" + // Pos:570 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x42 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16370,7 +16146,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:579 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x42 /r"/"VRM" + // Pos:571 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x42 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16399,7 +16175,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:580 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" + // Pos:572 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16427,7 +16203,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:581 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4C /r"/"VRM" + // Pos:573 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4C /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16456,7 +16232,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:582 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4C /r"/"VRM" + // Pos:574 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4C /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16485,7 +16261,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:583 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" + // Pos:575 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16513,7 +16289,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:584 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4E /r"/"VRM" + // Pos:576 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4E /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16542,7 +16318,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:585 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4E /r"/"VRM" + // Pos:577 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4E /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16571,7 +16347,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:586 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" + // Pos:578 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16599,7 +16375,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:587 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x47 /r"/"VRM" + // Pos:579 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x47 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16628,7 +16404,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:588 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x47 /r"/"VRM" + // Pos:580 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x47 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16657,7 +16433,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:589 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" + // Pos:581 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16685,7 +16461,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:590 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x43 /r"/"VRM" + // Pos:582 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x43 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16714,7 +16490,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:591 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x43 /r"/"VRM" + // Pos:583 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x43 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16743,7 +16519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:592 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" + // Pos:584 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16771,7 +16547,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:593 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4D /r"/"VRM" + // Pos:585 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4D /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16800,7 +16576,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:594 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4D /r"/"VRM" + // Pos:586 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4D /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16829,7 +16605,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:595 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" + // Pos:587 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16857,7 +16633,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:596 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4F /r"/"VRM" + // Pos:588 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4F /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16886,7 +16662,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:597 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4F /r"/"VRM" + // Pos:589 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4F /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16915,7 +16691,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:598 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" + // Pos:590 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -16943,7 +16719,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:599 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x41 /r"/"VRM" + // Pos:591 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x41 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -16972,7 +16748,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:600 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x41 /r"/"VRM" + // Pos:592 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x41 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17001,7 +16777,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:601 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" + // Pos:593 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17029,7 +16805,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:602 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4B /r"/"VRM" + // Pos:594 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4B /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17058,7 +16834,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:603 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4B /r"/"VRM" + // Pos:595 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4B /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17087,7 +16863,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:604 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" + // Pos:596 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17115,7 +16891,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:605 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x49 /r"/"VRM" + // Pos:597 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x49 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17144,7 +16920,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:606 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x49 /r"/"VRM" + // Pos:598 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x49 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17173,7 +16949,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:607 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" + // Pos:599 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17201,7 +16977,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:608 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x45 /r"/"VRM" + // Pos:600 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x45 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17230,7 +17006,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:609 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x45 /r"/"VRM" + // Pos:601 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x45 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17259,7 +17035,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:610 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" + // Pos:602 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17287,7 +17063,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:611 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x40 /r"/"VRM" + // Pos:603 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x40 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17316,7 +17092,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:612 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x40 /r"/"VRM" + // Pos:604 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x40 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17345,7 +17121,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:613 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" + // Pos:605 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17373,7 +17149,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:614 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4A /r"/"VRM" + // Pos:606 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4A /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17402,7 +17178,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:615 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4A /r"/"VRM" + // Pos:607 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4A /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17431,7 +17207,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:616 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" + // Pos:608 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17459,7 +17235,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:617 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x48 /r"/"VRM" + // Pos:609 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x48 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17488,7 +17264,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:618 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x48 /r"/"VRM" + // Pos:610 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x48 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17517,7 +17293,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:619 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" + // Pos:611 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17545,7 +17321,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:620 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x44 /r"/"VRM" + // Pos:612 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x44 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17574,7 +17350,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:621 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x44 /r"/"VRM" + // Pos:613 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x44 /r"/"VRM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_APX, @@ -17603,7 +17379,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:622 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" + // Pos:614 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" { .Instruction = ND_INS_CMOVcc, .Category = ND_CAT_CMOV, @@ -17631,7 +17407,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:623 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" + // Pos:615 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17659,7 +17435,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:624 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" + // Pos:616 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17687,7 +17463,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:625 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" + // Pos:617 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17715,7 +17491,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:626 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" + // Pos:618 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17743,7 +17519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:627 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" + // Pos:619 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17771,7 +17547,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:628 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" + // Pos:620 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17799,7 +17575,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:629 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" + // Pos:621 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17827,7 +17603,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:630 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" + // Pos:622 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17855,7 +17631,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:631 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" + // Pos:623 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17883,7 +17659,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:632 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" + // Pos:624 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" { .Instruction = ND_INS_CMP, .Category = ND_CAT_ARITH, @@ -17911,7 +17687,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:633 Instruction:"CMPBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE6 /r:mem"/"MRV" + // Pos:625 Instruction:"CMPBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE6 /r:mem"/"MRV" { .Instruction = ND_INS_CMPBEXADD, .Category = ND_CAT_CMPCCXADD, @@ -17940,7 +17716,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:634 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV" + // Pos:626 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV" { .Instruction = ND_INS_CMPBEXADD, .Category = ND_CAT_CMPCCXADD, @@ -17969,7 +17745,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:635 Instruction:"CMPCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE2 /r:mem"/"MRV" + // Pos:627 Instruction:"CMPCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE2 /r:mem"/"MRV" { .Instruction = ND_INS_CMPCXADD, .Category = ND_CAT_CMPCCXADD, @@ -17998,7 +17774,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:636 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV" + // Pos:628 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV" { .Instruction = ND_INS_CMPCXADD, .Category = ND_CAT_CMPCCXADD, @@ -18027,7 +17803,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:637 Instruction:"CMPLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEE /r:mem"/"MRV" + // Pos:629 Instruction:"CMPLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEE /r:mem"/"MRV" { .Instruction = ND_INS_CMPLEXADD, .Category = ND_CAT_CMPCCXADD, @@ -18056,7 +17832,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:638 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV" + // Pos:630 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV" { .Instruction = ND_INS_CMPLEXADD, .Category = ND_CAT_CMPCCXADD, @@ -18085,7 +17861,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:639 Instruction:"CMPLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEC /r:mem"/"MRV" + // Pos:631 Instruction:"CMPLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEC /r:mem"/"MRV" { .Instruction = ND_INS_CMPLXADD, .Category = ND_CAT_CMPCCXADD, @@ -18114,7 +17890,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:640 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV" + // Pos:632 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV" { .Instruction = ND_INS_CMPLXADD, .Category = ND_CAT_CMPCCXADD, @@ -18143,7 +17919,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:641 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE7 /r:mem"/"MRV" + // Pos:633 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE7 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNBEXADD, .Category = ND_CAT_CMPCCXADD, @@ -18172,7 +17948,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:642 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV" + // Pos:634 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNBEXADD, .Category = ND_CAT_CMPCCXADD, @@ -18201,7 +17977,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:643 Instruction:"CMPNCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE3 /r:mem"/"MRV" + // Pos:635 Instruction:"CMPNCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE3 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNCXADD, .Category = ND_CAT_CMPCCXADD, @@ -18230,7 +18006,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:644 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV" + // Pos:636 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNCXADD, .Category = ND_CAT_CMPCCXADD, @@ -18259,7 +18035,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:645 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEF /r:mem"/"MRV" + // Pos:637 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEF /r:mem"/"MRV" { .Instruction = ND_INS_CMPNLEXADD, .Category = ND_CAT_CMPCCXADD, @@ -18288,7 +18064,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:646 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV" + // Pos:638 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV" { .Instruction = ND_INS_CMPNLEXADD, .Category = ND_CAT_CMPCCXADD, @@ -18317,7 +18093,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:647 Instruction:"CMPNLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xED /r:mem"/"MRV" + // Pos:639 Instruction:"CMPNLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xED /r:mem"/"MRV" { .Instruction = ND_INS_CMPNLXADD, .Category = ND_CAT_CMPCCXADD, @@ -18346,7 +18122,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:648 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV" + // Pos:640 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV" { .Instruction = ND_INS_CMPNLXADD, .Category = ND_CAT_CMPCCXADD, @@ -18375,7 +18151,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:649 Instruction:"CMPNOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE1 /r:mem"/"MRV" + // Pos:641 Instruction:"CMPNOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE1 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNOXADD, .Category = ND_CAT_CMPCCXADD, @@ -18404,7 +18180,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:650 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV" + // Pos:642 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNOXADD, .Category = ND_CAT_CMPCCXADD, @@ -18433,7 +18209,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:651 Instruction:"CMPNPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEB /r:mem"/"MRV" + // Pos:643 Instruction:"CMPNPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEB /r:mem"/"MRV" { .Instruction = ND_INS_CMPNPXADD, .Category = ND_CAT_CMPCCXADD, @@ -18462,7 +18238,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:652 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV" + // Pos:644 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV" { .Instruction = ND_INS_CMPNPXADD, .Category = ND_CAT_CMPCCXADD, @@ -18491,7 +18267,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:653 Instruction:"CMPNSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE9 /r:mem"/"MRV" + // Pos:645 Instruction:"CMPNSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE9 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNSXADD, .Category = ND_CAT_CMPCCXADD, @@ -18520,7 +18296,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:654 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV" + // Pos:646 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNSXADD, .Category = ND_CAT_CMPCCXADD, @@ -18549,7 +18325,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:655 Instruction:"CMPNZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE5 /r:mem"/"MRV" + // Pos:647 Instruction:"CMPNZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE5 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNZXADD, .Category = ND_CAT_CMPCCXADD, @@ -18578,7 +18354,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:656 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV" + // Pos:648 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV" { .Instruction = ND_INS_CMPNZXADD, .Category = ND_CAT_CMPCCXADD, @@ -18607,7 +18383,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:657 Instruction:"CMPOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE0 /r:mem"/"MRV" + // Pos:649 Instruction:"CMPOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE0 /r:mem"/"MRV" { .Instruction = ND_INS_CMPOXADD, .Category = ND_CAT_CMPCCXADD, @@ -18636,7 +18412,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:658 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV" + // Pos:650 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV" { .Instruction = ND_INS_CMPOXADD, .Category = ND_CAT_CMPCCXADD, @@ -18665,7 +18441,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:659 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + // Pos:651 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" { .Instruction = ND_INS_CMPPD, .Category = ND_CAT_SSE, @@ -18693,7 +18469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:660 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" + // Pos:652 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" { .Instruction = ND_INS_CMPPS, .Category = ND_CAT_SSE, @@ -18721,7 +18497,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:661 Instruction:"CMPPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEA /r:mem"/"MRV" + // Pos:653 Instruction:"CMPPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEA /r:mem"/"MRV" { .Instruction = ND_INS_CMPPXADD, .Category = ND_CAT_CMPCCXADD, @@ -18750,7 +18526,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:662 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV" + // Pos:654 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV" { .Instruction = ND_INS_CMPPXADD, .Category = ND_CAT_CMPCCXADD, @@ -18779,7 +18555,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:663 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" + // Pos:655 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -18809,7 +18585,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:664 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" + // Pos:656 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -18840,7 +18616,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:665 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" + // Pos:657 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -18870,7 +18646,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:666 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" + // Pos:658 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -18901,7 +18677,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:667 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" + // Pos:659 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" { .Instruction = ND_INS_CMPSD, .Category = ND_CAT_SSE, @@ -18929,7 +18705,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:668 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" + // Pos:660 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -18959,7 +18735,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:669 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" + // Pos:661 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -18990,7 +18766,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:670 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" + // Pos:662 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" { .Instruction = ND_INS_CMPSS, .Category = ND_CAT_SSE, @@ -19018,7 +18794,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:671 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" + // Pos:663 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -19048,7 +18824,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:672 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" + // Pos:664 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" { .Instruction = ND_INS_CMPS, .Category = ND_CAT_STRINGOP, @@ -19079,7 +18855,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:673 Instruction:"CMPSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE8 /r:mem"/"MRV" + // Pos:665 Instruction:"CMPSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE8 /r:mem"/"MRV" { .Instruction = ND_INS_CMPSXADD, .Category = ND_CAT_CMPCCXADD, @@ -19108,7 +18884,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:674 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV" + // Pos:666 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV" { .Instruction = ND_INS_CMPSXADD, .Category = ND_CAT_CMPCCXADD, @@ -19137,7 +18913,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:675 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + // Pos:667 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" { .Instruction = ND_INS_CMPXCHG, .Category = ND_CAT_SEMAPHORE, @@ -19166,7 +18942,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:676 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" + // Pos:668 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" { .Instruction = ND_INS_CMPXCHG, .Category = ND_CAT_SEMAPHORE, @@ -19195,7 +18971,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:677 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" + // Pos:669 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" { .Instruction = ND_INS_CMPXCHG16B, .Category = ND_CAT_SEMAPHORE, @@ -19226,7 +19002,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:678 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" + // Pos:670 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" { .Instruction = ND_INS_CMPXCHG8B, .Category = ND_CAT_SEMAPHORE, @@ -19257,7 +19033,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:679 Instruction:"CMPZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE4 /r:mem"/"MRV" + // Pos:671 Instruction:"CMPZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE4 /r:mem"/"MRV" { .Instruction = ND_INS_CMPZXADD, .Category = ND_CAT_CMPCCXADD, @@ -19286,7 +19062,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:680 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV" + // Pos:672 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV" { .Instruction = ND_INS_CMPZXADD, .Category = ND_CAT_CMPCCXADD, @@ -19315,7 +19091,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:681 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" + // Pos:673 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" { .Instruction = ND_INS_COMISD, .Category = ND_CAT_SSE2, @@ -19343,7 +19119,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:682 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" + // Pos:674 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" { .Instruction = ND_INS_COMISS, .Category = ND_CAT_SSE, @@ -19371,7 +19147,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:683 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" + // Pos:675 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" { .Instruction = ND_INS_CPUID, .Category = ND_CAT_MISC, @@ -19400,7 +19176,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:684 Instruction:"CQO" Encoding:"ds64 0x99"/"" + // Pos:676 Instruction:"CQO" Encoding:"ds64 0x99"/"" { .Instruction = ND_INS_CQO, .Category = ND_CAT_CONVERT, @@ -19427,7 +19203,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:685 Instruction:"CRC32 Gy,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF0 /r"/"RM" + // Pos:677 Instruction:"CRC32 Gy,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF0 /r"/"RM" { .Instruction = ND_INS_CRC32, .Category = ND_CAT_APX, @@ -19454,7 +19230,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:686 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF1 /r"/"RM" + // Pos:678 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF1 /r"/"RM" { .Instruction = ND_INS_CRC32, .Category = ND_CAT_APX, @@ -19481,7 +19257,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:687 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF1 /r"/"RM" + // Pos:679 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF1 /r"/"RM" { .Instruction = ND_INS_CRC32, .Category = ND_CAT_APX, @@ -19508,7 +19284,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:688 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" + // Pos:680 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" { .Instruction = ND_INS_CRC32, .Category = ND_CAT_SSE, @@ -19535,7 +19311,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:689 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" + // Pos:681 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" { .Instruction = ND_INS_CRC32, .Category = ND_CAT_SSE, @@ -19562,7 +19338,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:690 Instruction:"CTESTBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x84 /r"/"MRV" + // Pos:682 Instruction:"CTESTBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19591,7 +19367,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:691 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x85 /r"/"MRV" + // Pos:683 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19620,7 +19396,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:692 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x85 /r"/"MRV" + // Pos:684 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19649,7 +19425,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:693 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /0 ib"/"MIV" + // Pos:685 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19678,7 +19454,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:694 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /1 ib"/"MIV" + // Pos:686 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19707,7 +19483,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:695 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /0 iz"/"MIV" + // Pos:687 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19736,7 +19512,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:696 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /0 iz"/"MIV" + // Pos:688 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19765,7 +19541,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:697 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /1 iz"/"MIV" + // Pos:689 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19794,7 +19570,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:698 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /1 iz"/"MIV" + // Pos:690 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19823,7 +19599,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:699 Instruction:"CTESTC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x84 /r"/"MRV" + // Pos:691 Instruction:"CTESTC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19852,7 +19628,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:700 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x85 /r"/"MRV" + // Pos:692 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19881,7 +19657,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:701 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x85 /r"/"MRV" + // Pos:693 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19910,7 +19686,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:702 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /0 ib"/"MIV" + // Pos:694 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19939,7 +19715,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:703 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /1 ib"/"MIV" + // Pos:695 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19968,7 +19744,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:704 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /0 iz"/"MIV" + // Pos:696 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -19997,7 +19773,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:705 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /0 iz"/"MIV" + // Pos:697 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20026,7 +19802,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:706 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /1 iz"/"MIV" + // Pos:698 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20055,7 +19831,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:707 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /1 iz"/"MIV" + // Pos:699 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20084,7 +19860,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:708 Instruction:"CTESTF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x84 /r"/"MRV" + // Pos:700 Instruction:"CTESTF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20113,7 +19889,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:709 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x85 /r"/"MRV" + // Pos:701 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20142,7 +19918,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:710 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x85 /r"/"MRV" + // Pos:702 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20171,7 +19947,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:711 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /0 ib"/"MIV" + // Pos:703 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20200,7 +19976,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:712 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /1 ib"/"MIV" + // Pos:704 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20229,7 +20005,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:713 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /0 iz"/"MIV" + // Pos:705 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20258,7 +20034,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:714 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /0 iz"/"MIV" + // Pos:706 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20287,7 +20063,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:715 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /1 iz"/"MIV" + // Pos:707 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20316,7 +20092,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:716 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /1 iz"/"MIV" + // Pos:708 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20345,7 +20121,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:717 Instruction:"CTESTL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x84 /r"/"MRV" + // Pos:709 Instruction:"CTESTL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20374,7 +20150,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:718 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x85 /r"/"MRV" + // Pos:710 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20403,7 +20179,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:719 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x85 /r"/"MRV" + // Pos:711 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20432,7 +20208,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:720 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /0 ib"/"MIV" + // Pos:712 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20461,7 +20237,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:721 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /1 ib"/"MIV" + // Pos:713 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20490,7 +20266,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:722 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /0 iz"/"MIV" + // Pos:714 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20519,7 +20295,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:723 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /0 iz"/"MIV" + // Pos:715 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20548,7 +20324,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:724 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /1 iz"/"MIV" + // Pos:716 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20577,7 +20353,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:725 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /1 iz"/"MIV" + // Pos:717 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20606,7 +20382,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:726 Instruction:"CTESTLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x84 /r"/"MRV" + // Pos:718 Instruction:"CTESTLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20635,7 +20411,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:727 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x85 /r"/"MRV" + // Pos:719 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20664,7 +20440,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:728 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x85 /r"/"MRV" + // Pos:720 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20693,7 +20469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:729 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /0 ib"/"MIV" + // Pos:721 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20722,7 +20498,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:730 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /1 ib"/"MIV" + // Pos:722 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20751,7 +20527,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:731 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /0 iz"/"MIV" + // Pos:723 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20780,7 +20556,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:732 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /0 iz"/"MIV" + // Pos:724 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20809,7 +20585,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:733 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /1 iz"/"MIV" + // Pos:725 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20838,7 +20614,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:734 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /1 iz"/"MIV" + // Pos:726 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20867,7 +20643,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:735 Instruction:"CTESTNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x84 /r"/"MRV" + // Pos:727 Instruction:"CTESTNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20896,7 +20672,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:736 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x85 /r"/"MRV" + // Pos:728 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20925,7 +20701,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:737 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x85 /r"/"MRV" + // Pos:729 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20954,7 +20730,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:738 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /0 ib"/"MIV" + // Pos:730 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -20983,7 +20759,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:739 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /1 ib"/"MIV" + // Pos:731 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21012,7 +20788,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:740 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /0 iz"/"MIV" + // Pos:732 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21041,7 +20817,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:741 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /0 iz"/"MIV" + // Pos:733 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21070,7 +20846,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:742 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /1 iz"/"MIV" + // Pos:734 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21099,7 +20875,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:743 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /1 iz"/"MIV" + // Pos:735 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21128,7 +20904,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:744 Instruction:"CTESTNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x84 /r"/"MRV" + // Pos:736 Instruction:"CTESTNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21157,7 +20933,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:745 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x85 /r"/"MRV" + // Pos:737 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21186,7 +20962,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:746 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x85 /r"/"MRV" + // Pos:738 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21215,7 +20991,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:747 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /0 ib"/"MIV" + // Pos:739 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21244,7 +21020,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:748 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /1 ib"/"MIV" + // Pos:740 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21273,7 +21049,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:749 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /0 iz"/"MIV" + // Pos:741 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21302,7 +21078,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:750 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /0 iz"/"MIV" + // Pos:742 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21331,7 +21107,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:751 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /1 iz"/"MIV" + // Pos:743 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21360,7 +21136,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:752 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /1 iz"/"MIV" + // Pos:744 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21389,7 +21165,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:753 Instruction:"CTESTNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x84 /r"/"MRV" + // Pos:745 Instruction:"CTESTNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21418,7 +21194,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:754 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x85 /r"/"MRV" + // Pos:746 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21447,7 +21223,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:755 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x85 /r"/"MRV" + // Pos:747 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21476,7 +21252,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:756 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /0 ib"/"MIV" + // Pos:748 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21505,7 +21281,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:757 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /1 ib"/"MIV" + // Pos:749 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21534,7 +21310,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:758 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /0 iz"/"MIV" + // Pos:750 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21563,7 +21339,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:759 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /0 iz"/"MIV" + // Pos:751 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21592,7 +21368,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:760 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /1 iz"/"MIV" + // Pos:752 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21621,7 +21397,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:761 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /1 iz"/"MIV" + // Pos:753 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21650,7 +21426,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:762 Instruction:"CTESTNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x84 /r"/"MRV" + // Pos:754 Instruction:"CTESTNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21679,7 +21455,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:763 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x85 /r"/"MRV" + // Pos:755 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21708,7 +21484,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:764 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x85 /r"/"MRV" + // Pos:756 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21737,7 +21513,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:765 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /0 ib"/"MIV" + // Pos:757 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21766,7 +21542,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:766 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /1 ib"/"MIV" + // Pos:758 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21795,7 +21571,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:767 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /0 iz"/"MIV" + // Pos:759 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21824,7 +21600,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:768 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /0 iz"/"MIV" + // Pos:760 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21853,7 +21629,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:769 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /1 iz"/"MIV" + // Pos:761 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21882,7 +21658,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:770 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /1 iz"/"MIV" + // Pos:762 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21911,7 +21687,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:771 Instruction:"CTESTNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x84 /r"/"MRV" + // Pos:763 Instruction:"CTESTNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21940,7 +21716,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:772 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x85 /r"/"MRV" + // Pos:764 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21969,7 +21745,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:773 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x85 /r"/"MRV" + // Pos:765 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -21998,7 +21774,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:774 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /0 ib"/"MIV" + // Pos:766 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22027,7 +21803,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:775 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /1 ib"/"MIV" + // Pos:767 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22056,7 +21832,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:776 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /0 iz"/"MIV" + // Pos:768 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22085,7 +21861,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:777 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /0 iz"/"MIV" + // Pos:769 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22114,7 +21890,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:778 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /1 iz"/"MIV" + // Pos:770 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22143,7 +21919,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:779 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /1 iz"/"MIV" + // Pos:771 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22172,7 +21948,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:780 Instruction:"CTESTNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x84 /r"/"MRV" + // Pos:772 Instruction:"CTESTNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22201,7 +21977,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:781 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x85 /r"/"MRV" + // Pos:773 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22230,7 +22006,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:782 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x85 /r"/"MRV" + // Pos:774 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22259,7 +22035,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:783 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /0 ib"/"MIV" + // Pos:775 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22288,7 +22064,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:784 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /1 ib"/"MIV" + // Pos:776 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22317,7 +22093,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:785 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /0 iz"/"MIV" + // Pos:777 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22346,7 +22122,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:786 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /0 iz"/"MIV" + // Pos:778 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22375,7 +22151,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:787 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /1 iz"/"MIV" + // Pos:779 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22404,7 +22180,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:788 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /1 iz"/"MIV" + // Pos:780 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22433,7 +22209,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:789 Instruction:"CTESTNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x84 /r"/"MRV" + // Pos:781 Instruction:"CTESTNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22462,7 +22238,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:790 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x85 /r"/"MRV" + // Pos:782 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22491,7 +22267,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:791 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x85 /r"/"MRV" + // Pos:783 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22520,7 +22296,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:792 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /0 ib"/"MIV" + // Pos:784 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22549,7 +22325,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:793 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /1 ib"/"MIV" + // Pos:785 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22578,7 +22354,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:794 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /0 iz"/"MIV" + // Pos:786 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22607,7 +22383,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:795 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /0 iz"/"MIV" + // Pos:787 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22636,7 +22412,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:796 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /1 iz"/"MIV" + // Pos:788 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22665,7 +22441,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:797 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /1 iz"/"MIV" + // Pos:789 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22694,7 +22470,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:798 Instruction:"CTESTO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x84 /r"/"MRV" + // Pos:790 Instruction:"CTESTO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22723,7 +22499,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:799 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x85 /r"/"MRV" + // Pos:791 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22752,7 +22528,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:800 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x85 /r"/"MRV" + // Pos:792 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22781,7 +22557,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:801 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /0 ib"/"MIV" + // Pos:793 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22810,7 +22586,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:802 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /1 ib"/"MIV" + // Pos:794 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22839,7 +22615,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:803 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /0 iz"/"MIV" + // Pos:795 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22868,7 +22644,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:804 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /0 iz"/"MIV" + // Pos:796 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22897,7 +22673,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:805 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /1 iz"/"MIV" + // Pos:797 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22926,7 +22702,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:806 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /1 iz"/"MIV" + // Pos:798 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22955,7 +22731,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:807 Instruction:"CTESTS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x84 /r"/"MRV" + // Pos:799 Instruction:"CTESTS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -22984,7 +22760,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:808 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x85 /r"/"MRV" + // Pos:800 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23013,7 +22789,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:809 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x85 /r"/"MRV" + // Pos:801 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23042,7 +22818,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:810 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /0 ib"/"MIV" + // Pos:802 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23071,7 +22847,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:811 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /1 ib"/"MIV" + // Pos:803 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23100,7 +22876,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:812 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /0 iz"/"MIV" + // Pos:804 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23129,7 +22905,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:813 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /0 iz"/"MIV" + // Pos:805 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23158,7 +22934,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:814 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /1 iz"/"MIV" + // Pos:806 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23187,7 +22963,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:815 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /1 iz"/"MIV" + // Pos:807 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23216,7 +22992,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:816 Instruction:"CTESTT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x84 /r"/"MRV" + // Pos:808 Instruction:"CTESTT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23245,7 +23021,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:817 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x85 /r"/"MRV" + // Pos:809 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23274,7 +23050,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:818 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x85 /r"/"MRV" + // Pos:810 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23303,7 +23079,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:819 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /0 ib"/"MIV" + // Pos:811 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23332,7 +23108,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:820 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /1 ib"/"MIV" + // Pos:812 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23361,7 +23137,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:821 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /0 iz"/"MIV" + // Pos:813 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23390,7 +23166,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:822 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /0 iz"/"MIV" + // Pos:814 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23419,7 +23195,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:823 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /1 iz"/"MIV" + // Pos:815 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23448,7 +23224,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:824 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /1 iz"/"MIV" + // Pos:816 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23477,7 +23253,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:825 Instruction:"CTESTZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x84 /r"/"MRV" + // Pos:817 Instruction:"CTESTZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x84 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23506,7 +23282,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:826 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x85 /r"/"MRV" + // Pos:818 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23535,7 +23311,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:827 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x85 /r"/"MRV" + // Pos:819 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x85 /r"/"MRV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23564,7 +23340,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:828 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /0 ib"/"MIV" + // Pos:820 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /0 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23593,7 +23369,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:829 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /1 ib"/"MIV" + // Pos:821 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /1 ib"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23622,7 +23398,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:830 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /0 iz"/"MIV" + // Pos:822 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23651,7 +23427,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:831 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /0 iz"/"MIV" + // Pos:823 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /0 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23680,7 +23456,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:832 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /1 iz"/"MIV" + // Pos:824 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23709,7 +23485,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:833 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /1 iz"/"MIV" + // Pos:825 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /1 iz"/"MIV" { .Instruction = ND_INS_CTEST, .Category = ND_CAT_APX, @@ -23738,7 +23514,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:834 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" + // Pos:826 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" { .Instruction = ND_INS_CVTDQ2PD, .Category = ND_CAT_CONVERT, @@ -23765,7 +23541,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:835 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" + // Pos:827 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" { .Instruction = ND_INS_CVTDQ2PS, .Category = ND_CAT_CONVERT, @@ -23792,7 +23568,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:836 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" + // Pos:828 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" { .Instruction = ND_INS_CVTPD2DQ, .Category = ND_CAT_CONVERT, @@ -23819,7 +23595,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:837 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" + // Pos:829 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" { .Instruction = ND_INS_CVTPD2PI, .Category = ND_CAT_CONVERT, @@ -23846,7 +23622,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:838 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" + // Pos:830 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" { .Instruction = ND_INS_CVTPD2PS, .Category = ND_CAT_CONVERT, @@ -23873,7 +23649,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:839 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" + // Pos:831 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" { .Instruction = ND_INS_CVTPI2PD, .Category = ND_CAT_CONVERT, @@ -23900,7 +23676,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:840 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" + // Pos:832 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" { .Instruction = ND_INS_CVTPI2PS, .Category = ND_CAT_CONVERT, @@ -23927,7 +23703,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:841 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" + // Pos:833 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" { .Instruction = ND_INS_CVTPS2DQ, .Category = ND_CAT_CONVERT, @@ -23954,7 +23730,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:842 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" + // Pos:834 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" { .Instruction = ND_INS_CVTPS2PD, .Category = ND_CAT_CONVERT, @@ -23981,7 +23757,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:843 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" + // Pos:835 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" { .Instruction = ND_INS_CVTPS2PI, .Category = ND_CAT_CONVERT, @@ -24008,7 +23784,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:844 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" + // Pos:836 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" { .Instruction = ND_INS_CVTSD2SI, .Category = ND_CAT_CONVERT, @@ -24035,7 +23811,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:845 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" + // Pos:837 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" { .Instruction = ND_INS_CVTSD2SS, .Category = ND_CAT_CONVERT, @@ -24062,7 +23838,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:846 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" + // Pos:838 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" { .Instruction = ND_INS_CVTSI2SD, .Category = ND_CAT_CONVERT, @@ -24089,7 +23865,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:847 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" + // Pos:839 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" { .Instruction = ND_INS_CVTSI2SS, .Category = ND_CAT_CONVERT, @@ -24116,7 +23892,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:848 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" + // Pos:840 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" { .Instruction = ND_INS_CVTSS2SD, .Category = ND_CAT_CONVERT, @@ -24143,7 +23919,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:849 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" + // Pos:841 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" { .Instruction = ND_INS_CVTSS2SI, .Category = ND_CAT_CONVERT, @@ -24170,7 +23946,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:850 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" + // Pos:842 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" { .Instruction = ND_INS_CVTTPD2DQ, .Category = ND_CAT_CONVERT, @@ -24197,7 +23973,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:851 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" + // Pos:843 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" { .Instruction = ND_INS_CVTTPD2PI, .Category = ND_CAT_CONVERT, @@ -24224,7 +24000,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:852 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" + // Pos:844 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" { .Instruction = ND_INS_CVTTPS2DQ, .Category = ND_CAT_CONVERT, @@ -24251,7 +24027,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:853 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" + // Pos:845 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" { .Instruction = ND_INS_CVTTPS2PI, .Category = ND_CAT_CONVERT, @@ -24278,7 +24054,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:854 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" + // Pos:846 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" { .Instruction = ND_INS_CVTTSD2SI, .Category = ND_CAT_CONVERT, @@ -24305,7 +24081,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:855 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" + // Pos:847 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" { .Instruction = ND_INS_CVTTSS2SI, .Category = ND_CAT_CONVERT, @@ -24332,7 +24108,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:856 Instruction:"CWD" Encoding:"ds16 0x99"/"" + // Pos:848 Instruction:"CWD" Encoding:"ds16 0x99"/"" { .Instruction = ND_INS_CWD, .Category = ND_CAT_CONVERT, @@ -24359,7 +24135,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:857 Instruction:"CWDE" Encoding:"ds32 0x98"/"" + // Pos:849 Instruction:"CWDE" Encoding:"ds32 0x98"/"" { .Instruction = ND_INS_CWDE, .Category = ND_CAT_CONVERT, @@ -24386,7 +24162,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:858 Instruction:"DAA" Encoding:"0x27"/"" + // Pos:850 Instruction:"DAA" Encoding:"0x27"/"" { .Instruction = ND_INS_DAA, .Category = ND_CAT_DECIMAL, @@ -24413,7 +24189,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:859 Instruction:"DAS" Encoding:"0x2F"/"" + // Pos:851 Instruction:"DAS" Encoding:"0x2F"/"" { .Instruction = ND_INS_DAS, .Category = ND_CAT_DECIMAL, @@ -24440,7 +24216,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:860 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /1"/"M" + // Pos:852 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24467,7 +24243,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:861 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /1"/"M" + // Pos:853 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24494,7 +24270,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:862 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /1"/"M" + // Pos:854 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24521,7 +24297,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:863 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /1"/"M" + // Pos:855 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24547,7 +24323,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:864 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /1"/"M" + // Pos:856 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24573,7 +24349,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:865 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /1"/"M" + // Pos:857 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24599,7 +24375,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:866 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /1"/"VM" + // Pos:858 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /1"/"VM" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24627,7 +24403,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:867 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /1"/"VM" + // Pos:859 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /1"/"VM" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24655,7 +24431,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:868 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /1"/"VM" + // Pos:860 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /1"/"VM" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24683,7 +24459,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:869 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /1"/"VM" + // Pos:861 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /1"/"VM" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24710,7 +24486,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:870 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /1"/"VM" + // Pos:862 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /1"/"VM" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24737,7 +24513,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:871 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /1"/"VM" + // Pos:863 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /1"/"VM" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24764,7 +24540,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:872 Instruction:"DEC Zv" Encoding:"0x48"/"O" + // Pos:864 Instruction:"DEC Zv" Encoding:"0x48"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24791,7 +24567,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:873 Instruction:"DEC Zv" Encoding:"0x49"/"O" + // Pos:865 Instruction:"DEC Zv" Encoding:"0x49"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24818,7 +24594,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:874 Instruction:"DEC Zv" Encoding:"0x4A"/"O" + // Pos:866 Instruction:"DEC Zv" Encoding:"0x4A"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24845,7 +24621,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:875 Instruction:"DEC Zv" Encoding:"0x4B"/"O" + // Pos:867 Instruction:"DEC Zv" Encoding:"0x4B"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24872,7 +24648,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:876 Instruction:"DEC Zv" Encoding:"0x4C"/"O" + // Pos:868 Instruction:"DEC Zv" Encoding:"0x4C"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24899,7 +24675,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:877 Instruction:"DEC Zv" Encoding:"0x4D"/"O" + // Pos:869 Instruction:"DEC Zv" Encoding:"0x4D"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24926,7 +24702,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:878 Instruction:"DEC Zv" Encoding:"0x4E"/"O" + // Pos:870 Instruction:"DEC Zv" Encoding:"0x4E"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24953,7 +24729,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:879 Instruction:"DEC Zv" Encoding:"0x4F"/"O" + // Pos:871 Instruction:"DEC Zv" Encoding:"0x4F"/"O" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -24980,7 +24756,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:880 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" + // Pos:872 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -25007,7 +24783,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:881 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" + // Pos:873 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" { .Instruction = ND_INS_DEC, .Category = ND_CAT_ARITH, @@ -25034,7 +24810,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:882 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" + // Pos:874 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" { .Instruction = ND_INS_DELAY, .Category = ND_CAT_UNKNOWN, @@ -25060,7 +24836,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:883 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /6"/"M" + // Pos:875 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25090,7 +24866,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:884 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /6"/"M" + // Pos:876 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25119,7 +24895,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:885 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /6"/"M" + // Pos:877 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25148,7 +24924,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:886 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /6"/"M" + // Pos:878 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25177,7 +24953,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:887 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /6"/"M" + // Pos:879 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25205,7 +24981,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:888 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /6"/"M" + // Pos:880 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25233,7 +25009,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:889 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" + // Pos:881 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25263,7 +25039,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:890 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" + // Pos:882 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" { .Instruction = ND_INS_DIV, .Category = ND_CAT_ARITH, @@ -25292,7 +25068,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:891 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" + // Pos:883 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" { .Instruction = ND_INS_DIVPD, .Category = ND_CAT_SSE, @@ -25319,7 +25095,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:892 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" + // Pos:884 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" { .Instruction = ND_INS_DIVPS, .Category = ND_CAT_SSE, @@ -25346,7 +25122,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:893 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" + // Pos:885 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" { .Instruction = ND_INS_DIVSD, .Category = ND_CAT_SSE, @@ -25373,7 +25149,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:894 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" + // Pos:886 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" { .Instruction = ND_INS_DIVSS, .Category = ND_CAT_SSE, @@ -25400,7 +25176,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:895 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" + // Pos:887 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" { .Instruction = ND_INS_DPPD, .Category = ND_CAT_SSE, @@ -25428,7 +25204,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:896 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" + // Pos:888 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" { .Instruction = ND_INS_DPPS, .Category = ND_CAT_SSE, @@ -25456,7 +25232,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:897 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" + // Pos:889 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" { .Instruction = ND_INS_EMMS, .Category = ND_CAT_MMX, @@ -25482,7 +25258,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:898 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" + // Pos:890 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" { .Instruction = ND_INS_ENCLS, .Category = ND_CAT_SGX, @@ -25511,7 +25287,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:899 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" + // Pos:891 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" { .Instruction = ND_INS_ENCLU, .Category = ND_CAT_SGX, @@ -25540,7 +25316,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:900 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" + // Pos:892 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" { .Instruction = ND_INS_ENCLV, .Category = ND_CAT_SGX, @@ -25569,38 +25345,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:901 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg"/"RM" - { - .Instruction = ND_INS_ENCODEKEY128, - .Category = ND_CAT_AESKL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 226, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 4), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3), - OP(ND_OPT_XMM4, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:902 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" + // Pos:893 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" { .Instruction = ND_INS_ENCODEKEY128, .Category = ND_CAT_AESKL, @@ -25631,37 +25376,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:903 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg"/"RM" - { - .Instruction = ND_INS_ENCODEKEY256, - .Category = ND_CAT_AESKL, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 227, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 3), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 2), - OP(ND_OPT_XMM2, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 5), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:904 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" + // Pos:894 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" { .Instruction = ND_INS_ENCODEKEY256, .Category = ND_CAT_AESKL, @@ -25691,7 +25406,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:905 Instruction:"ENDBR32" Encoding:"cet repz 0x0F 0x1E /0xFB"/"" + // Pos:895 Instruction:"ENDBR32" Encoding:"cet repz 0x0F 0x1E /0xFB"/"" { .Instruction = ND_INS_ENDBR, .Category = ND_CAT_CET, @@ -25717,7 +25432,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:906 Instruction:"ENDBR64" Encoding:"cet repz 0x0F 0x1E /0xFA"/"" + // Pos:896 Instruction:"ENDBR64" Encoding:"cet repz 0x0F 0x1E /0xFA"/"" { .Instruction = ND_INS_ENDBR, .Category = ND_CAT_CET, @@ -25743,7 +25458,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:907 Instruction:"ENQCMD rM?,Moq" Encoding:"evex m:4 l:0 p:3 nd:0 nf:0 0xF8 /r:mem"/"M" + // Pos:897 Instruction:"ENQCMD rM?,Moq" Encoding:"evex m:4 l:0 p:3 nd:0 nf:0 0xF8 /r:mem"/"M" { .Instruction = ND_INS_ENQCMD, .Category = ND_CAT_ENQCMD, @@ -25771,7 +25486,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:908 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:898 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" { .Instruction = ND_INS_ENQCMD, .Category = ND_CAT_ENQCMD, @@ -25799,7 +25514,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:909 Instruction:"ENQCMDS rM?,Moq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF8 /r:mem"/"M" + // Pos:899 Instruction:"ENQCMDS rM?,Moq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF8 /r:mem"/"M" { .Instruction = ND_INS_ENQCMDS, .Category = ND_CAT_ENQCMD, @@ -25827,7 +25542,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:910 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:900 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" { .Instruction = ND_INS_ENQCMDS, .Category = ND_CAT_ENQCMD, @@ -25855,7 +25570,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:911 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" + // Pos:901 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" { .Instruction = ND_INS_ENTER, .Category = ND_CAT_MISC, @@ -25864,7 +25579,7 @@ const ND_IDBE gInstructions[4075] = .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 3), + .OpsCount = ND_OPS_CNT(2, 5), .TupleType = 0, .ExcType = 0, .FpuFlags = 0, @@ -25880,12 +25595,14 @@ const ND_IDBE gInstructions[4075] = OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rBP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_pBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), }, }, - // Pos:912 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" + // Pos:902 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" { .Instruction = ND_INS_ERETS, .Category = ND_CAT_RET, @@ -25915,7 +25632,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:913 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" + // Pos:903 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" { .Instruction = ND_INS_ERETU, .Category = ND_CAT_RET, @@ -25949,7 +25666,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:914 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" + // Pos:904 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" { .Instruction = ND_INS_EXTRACTPS, .Category = ND_CAT_SSE, @@ -25977,7 +25694,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:915 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 ib ib"/"MII" + // Pos:905 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 ib ib"/"MII" { .Instruction = ND_INS_EXTRQ, .Category = ND_CAT_BITBYTE, @@ -26005,7 +25722,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:916 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" + // Pos:906 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" { .Instruction = ND_INS_EXTRQ, .Category = ND_CAT_BITBYTE, @@ -26032,7 +25749,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:917 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" + // Pos:907 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" { .Instruction = ND_INS_F2XM1, .Category = ND_CAT_X87_ALU, @@ -26058,7 +25775,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:918 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" + // Pos:908 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" { .Instruction = ND_INS_FABS, .Category = ND_CAT_X87_ALU, @@ -26084,7 +25801,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:919 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" + // Pos:909 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" { .Instruction = ND_INS_FADD, .Category = ND_CAT_X87_ALU, @@ -26112,7 +25829,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:920 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" + // Pos:910 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" { .Instruction = ND_INS_FADD, .Category = ND_CAT_X87_ALU, @@ -26140,7 +25857,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:921 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" + // Pos:911 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" { .Instruction = ND_INS_FADD, .Category = ND_CAT_X87_ALU, @@ -26168,7 +25885,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:922 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" + // Pos:912 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" { .Instruction = ND_INS_FADD, .Category = ND_CAT_X87_ALU, @@ -26196,7 +25913,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:923 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" + // Pos:913 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" { .Instruction = ND_INS_FADDP, .Category = ND_CAT_X87_ALU, @@ -26224,7 +25941,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:924 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" + // Pos:914 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" { .Instruction = ND_INS_FBLD, .Category = ND_CAT_X87_ALU, @@ -26252,7 +25969,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:925 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" + // Pos:915 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" { .Instruction = ND_INS_FBSTP, .Category = ND_CAT_X87_ALU, @@ -26280,7 +25997,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:926 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" + // Pos:916 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" { .Instruction = ND_INS_FCHS, .Category = ND_CAT_X87_ALU, @@ -26306,7 +26023,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:927 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" + // Pos:917 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" { .Instruction = ND_INS_FCMOVB, .Category = ND_CAT_X87_ALU, @@ -26335,7 +26052,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:928 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" + // Pos:918 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" { .Instruction = ND_INS_FCMOVBE, .Category = ND_CAT_X87_ALU, @@ -26364,7 +26081,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:929 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" + // Pos:919 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" { .Instruction = ND_INS_FCMOVE, .Category = ND_CAT_X87_ALU, @@ -26393,7 +26110,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:930 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" + // Pos:920 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" { .Instruction = ND_INS_FCMOVNB, .Category = ND_CAT_X87_ALU, @@ -26422,7 +26139,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:931 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" + // Pos:921 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" { .Instruction = ND_INS_FCMOVNBE, .Category = ND_CAT_X87_ALU, @@ -26451,7 +26168,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:932 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" + // Pos:922 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" { .Instruction = ND_INS_FCMOVNE, .Category = ND_CAT_X87_ALU, @@ -26480,7 +26197,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:933 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" + // Pos:923 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" { .Instruction = ND_INS_FCMOVNU, .Category = ND_CAT_X87_ALU, @@ -26509,7 +26226,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:934 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" + // Pos:924 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" { .Instruction = ND_INS_FCMOVU, .Category = ND_CAT_X87_ALU, @@ -26538,7 +26255,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:935 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" + // Pos:925 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" { .Instruction = ND_INS_FCOM, .Category = ND_CAT_X87_ALU, @@ -26566,7 +26283,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:936 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" + // Pos:926 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" { .Instruction = ND_INS_FCOM, .Category = ND_CAT_X87_ALU, @@ -26594,7 +26311,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:937 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" + // Pos:927 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" { .Instruction = ND_INS_FCOM, .Category = ND_CAT_X87_ALU, @@ -26622,7 +26339,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:938 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" + // Pos:928 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" { .Instruction = ND_INS_FCOM, .Category = ND_CAT_X87_ALU, @@ -26650,7 +26367,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:939 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" + // Pos:929 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" { .Instruction = ND_INS_FCOMI, .Category = ND_CAT_X87_ALU, @@ -26679,7 +26396,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:940 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" + // Pos:930 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" { .Instruction = ND_INS_FCOMIP, .Category = ND_CAT_X87_ALU, @@ -26708,7 +26425,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:941 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" + // Pos:931 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" { .Instruction = ND_INS_FCOMP, .Category = ND_CAT_X87_ALU, @@ -26736,7 +26453,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:942 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" + // Pos:932 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" { .Instruction = ND_INS_FCOMP, .Category = ND_CAT_X87_ALU, @@ -26764,7 +26481,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:943 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" + // Pos:933 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" { .Instruction = ND_INS_FCOMP, .Category = ND_CAT_X87_ALU, @@ -26792,7 +26509,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:944 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" + // Pos:934 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" { .Instruction = ND_INS_FCOMP, .Category = ND_CAT_X87_ALU, @@ -26820,7 +26537,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:945 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" + // Pos:935 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" { .Instruction = ND_INS_FCOMP, .Category = ND_CAT_X87_ALU, @@ -26848,7 +26565,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:946 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" + // Pos:936 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" { .Instruction = ND_INS_FCOMPP, .Category = ND_CAT_X87_ALU, @@ -26874,7 +26591,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:947 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" + // Pos:937 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" { .Instruction = ND_INS_FCOS, .Category = ND_CAT_X87_ALU, @@ -26900,7 +26617,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:948 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" + // Pos:938 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" { .Instruction = ND_INS_FDECSTP, .Category = ND_CAT_X87_ALU, @@ -26926,7 +26643,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:949 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" + // Pos:939 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" { .Instruction = ND_INS_FDIV, .Category = ND_CAT_X87_ALU, @@ -26954,7 +26671,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:950 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" + // Pos:940 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" { .Instruction = ND_INS_FDIV, .Category = ND_CAT_X87_ALU, @@ -26982,7 +26699,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:951 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" + // Pos:941 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" { .Instruction = ND_INS_FDIV, .Category = ND_CAT_X87_ALU, @@ -27010,7 +26727,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:952 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" + // Pos:942 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" { .Instruction = ND_INS_FDIV, .Category = ND_CAT_X87_ALU, @@ -27038,7 +26755,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:953 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" + // Pos:943 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" { .Instruction = ND_INS_FDIVP, .Category = ND_CAT_X87_ALU, @@ -27066,7 +26783,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:954 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" + // Pos:944 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" { .Instruction = ND_INS_FDIVR, .Category = ND_CAT_X87_ALU, @@ -27094,7 +26811,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:955 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" + // Pos:945 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" { .Instruction = ND_INS_FDIVR, .Category = ND_CAT_X87_ALU, @@ -27122,7 +26839,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:956 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" + // Pos:946 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" { .Instruction = ND_INS_FDIVR, .Category = ND_CAT_X87_ALU, @@ -27150,7 +26867,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:957 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" + // Pos:947 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" { .Instruction = ND_INS_FDIVR, .Category = ND_CAT_X87_ALU, @@ -27178,7 +26895,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:958 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" + // Pos:948 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" { .Instruction = ND_INS_FDIVRP, .Category = ND_CAT_X87_ALU, @@ -27206,7 +26923,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:959 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" + // Pos:949 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" { .Instruction = ND_INS_FEMMS, .Category = ND_CAT_MMX, @@ -27232,7 +26949,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:960 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" + // Pos:950 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" { .Instruction = ND_INS_FFREE, .Category = ND_CAT_X87_ALU, @@ -27259,7 +26976,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:961 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" + // Pos:951 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" { .Instruction = ND_INS_FFREEP, .Category = ND_CAT_X87_ALU, @@ -27286,7 +27003,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:962 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" + // Pos:952 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" { .Instruction = ND_INS_FIADD, .Category = ND_CAT_X87_ALU, @@ -27314,7 +27031,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:963 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" + // Pos:953 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" { .Instruction = ND_INS_FIADD, .Category = ND_CAT_X87_ALU, @@ -27342,7 +27059,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:964 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" + // Pos:954 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" { .Instruction = ND_INS_FICOM, .Category = ND_CAT_X87_ALU, @@ -27370,7 +27087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:965 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" + // Pos:955 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" { .Instruction = ND_INS_FICOM, .Category = ND_CAT_X87_ALU, @@ -27398,7 +27115,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:966 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" + // Pos:956 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" { .Instruction = ND_INS_FICOMP, .Category = ND_CAT_X87_ALU, @@ -27426,7 +27143,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:967 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" + // Pos:957 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" { .Instruction = ND_INS_FICOMP, .Category = ND_CAT_X87_ALU, @@ -27454,7 +27171,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:968 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" + // Pos:958 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" { .Instruction = ND_INS_FIDIV, .Category = ND_CAT_X87_ALU, @@ -27482,7 +27199,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:969 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" + // Pos:959 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" { .Instruction = ND_INS_FIDIV, .Category = ND_CAT_X87_ALU, @@ -27510,7 +27227,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:970 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" + // Pos:960 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" { .Instruction = ND_INS_FIDIVR, .Category = ND_CAT_X87_ALU, @@ -27538,7 +27255,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:971 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" + // Pos:961 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" { .Instruction = ND_INS_FIDIVR, .Category = ND_CAT_X87_ALU, @@ -27566,7 +27283,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:972 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" + // Pos:962 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" { .Instruction = ND_INS_FILD, .Category = ND_CAT_X87_ALU, @@ -27594,7 +27311,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:973 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" + // Pos:963 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" { .Instruction = ND_INS_FILD, .Category = ND_CAT_X87_ALU, @@ -27622,7 +27339,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:974 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" + // Pos:964 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" { .Instruction = ND_INS_FILD, .Category = ND_CAT_X87_ALU, @@ -27650,7 +27367,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:975 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" + // Pos:965 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" { .Instruction = ND_INS_FIMUL, .Category = ND_CAT_X87_ALU, @@ -27678,7 +27395,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:976 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" + // Pos:966 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" { .Instruction = ND_INS_FIMUL, .Category = ND_CAT_X87_ALU, @@ -27706,7 +27423,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:977 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" + // Pos:967 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" { .Instruction = ND_INS_FINCSTP, .Category = ND_CAT_X87_ALU, @@ -27732,7 +27449,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:978 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" + // Pos:968 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" { .Instruction = ND_INS_FIST, .Category = ND_CAT_X87_ALU, @@ -27760,7 +27477,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:979 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" + // Pos:969 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" { .Instruction = ND_INS_FIST, .Category = ND_CAT_X87_ALU, @@ -27788,7 +27505,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:980 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" + // Pos:970 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" { .Instruction = ND_INS_FISTP, .Category = ND_CAT_X87_ALU, @@ -27816,7 +27533,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:981 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" + // Pos:971 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" { .Instruction = ND_INS_FISTP, .Category = ND_CAT_X87_ALU, @@ -27844,7 +27561,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:982 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" + // Pos:972 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" { .Instruction = ND_INS_FISTP, .Category = ND_CAT_X87_ALU, @@ -27872,7 +27589,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:983 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" + // Pos:973 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" { .Instruction = ND_INS_FISTTP, .Category = ND_CAT_X87_ALU, @@ -27900,7 +27617,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:984 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" + // Pos:974 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" { .Instruction = ND_INS_FISTTP, .Category = ND_CAT_X87_ALU, @@ -27928,7 +27645,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:985 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" + // Pos:975 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" { .Instruction = ND_INS_FISTTP, .Category = ND_CAT_X87_ALU, @@ -27956,7 +27673,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:986 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" + // Pos:976 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" { .Instruction = ND_INS_FISUB, .Category = ND_CAT_X87_ALU, @@ -27984,7 +27701,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:987 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" + // Pos:977 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" { .Instruction = ND_INS_FISUB, .Category = ND_CAT_X87_ALU, @@ -28012,7 +27729,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:988 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" + // Pos:978 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" { .Instruction = ND_INS_FISUBR, .Category = ND_CAT_X87_ALU, @@ -28040,7 +27757,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:989 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" + // Pos:979 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" { .Instruction = ND_INS_FISUBR, .Category = ND_CAT_X87_ALU, @@ -28068,7 +27785,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:990 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" + // Pos:980 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" { .Instruction = ND_INS_FLD, .Category = ND_CAT_X87_ALU, @@ -28096,7 +27813,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:991 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" + // Pos:981 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" { .Instruction = ND_INS_FLD, .Category = ND_CAT_X87_ALU, @@ -28124,7 +27841,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:992 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" + // Pos:982 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" { .Instruction = ND_INS_FLD, .Category = ND_CAT_X87_ALU, @@ -28152,7 +27869,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:993 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" + // Pos:983 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" { .Instruction = ND_INS_FLD, .Category = ND_CAT_X87_ALU, @@ -28180,7 +27897,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:994 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" + // Pos:984 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" { .Instruction = ND_INS_FLD1, .Category = ND_CAT_X87_ALU, @@ -28206,7 +27923,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:995 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" + // Pos:985 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" { .Instruction = ND_INS_FLDCW, .Category = ND_CAT_X87_ALU, @@ -28234,7 +27951,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:996 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" + // Pos:986 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" { .Instruction = ND_INS_FLDENV, .Category = ND_CAT_X87_ALU, @@ -28261,7 +27978,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:997 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" + // Pos:987 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" { .Instruction = ND_INS_FLDL2E, .Category = ND_CAT_X87_ALU, @@ -28287,7 +28004,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:998 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" + // Pos:988 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" { .Instruction = ND_INS_FLDL2T, .Category = ND_CAT_X87_ALU, @@ -28313,7 +28030,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:999 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" + // Pos:989 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" { .Instruction = ND_INS_FLDLG2, .Category = ND_CAT_X87_ALU, @@ -28339,7 +28056,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1000 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" + // Pos:990 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" { .Instruction = ND_INS_FLDLN2, .Category = ND_CAT_X87_ALU, @@ -28365,7 +28082,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1001 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" + // Pos:991 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" { .Instruction = ND_INS_FLDPI, .Category = ND_CAT_X87_ALU, @@ -28391,7 +28108,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1002 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" + // Pos:992 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" { .Instruction = ND_INS_FLDZ, .Category = ND_CAT_X87_ALU, @@ -28417,7 +28134,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1003 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" + // Pos:993 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" { .Instruction = ND_INS_FMUL, .Category = ND_CAT_X87_ALU, @@ -28445,7 +28162,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1004 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" + // Pos:994 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" { .Instruction = ND_INS_FMUL, .Category = ND_CAT_X87_ALU, @@ -28473,7 +28190,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1005 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" + // Pos:995 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" { .Instruction = ND_INS_FMUL, .Category = ND_CAT_X87_ALU, @@ -28501,7 +28218,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1006 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" + // Pos:996 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" { .Instruction = ND_INS_FMUL, .Category = ND_CAT_X87_ALU, @@ -28529,7 +28246,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1007 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" + // Pos:997 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" { .Instruction = ND_INS_FMULP, .Category = ND_CAT_X87_ALU, @@ -28557,7 +28274,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1008 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" + // Pos:998 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" { .Instruction = ND_INS_FNCLEX, .Category = ND_CAT_X87_ALU, @@ -28583,7 +28300,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1009 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" + // Pos:999 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" { .Instruction = ND_INS_FNDISI, .Category = ND_CAT_X87_ALU, @@ -28609,7 +28326,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1010 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" + // Pos:1000 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" { .Instruction = ND_INS_FNINIT, .Category = ND_CAT_X87_ALU, @@ -28637,7 +28354,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1011 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" + // Pos:1001 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" { .Instruction = ND_INS_FNOP, .Category = ND_CAT_X87_ALU, @@ -28663,7 +28380,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1012 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" + // Pos:1002 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" { .Instruction = ND_INS_FNOP, .Category = ND_CAT_X87_ALU, @@ -28689,7 +28406,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1013 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" + // Pos:1003 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" { .Instruction = ND_INS_FNOP, .Category = ND_CAT_X87_ALU, @@ -28715,7 +28432,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1014 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" + // Pos:1004 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" { .Instruction = ND_INS_FNSAVE, .Category = ND_CAT_X87_ALU, @@ -28744,7 +28461,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1015 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" + // Pos:1005 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" { .Instruction = ND_INS_FNSTCW, .Category = ND_CAT_X87_ALU, @@ -28772,7 +28489,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1016 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" + // Pos:1006 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" { .Instruction = ND_INS_FNSTENV, .Category = ND_CAT_X87_ALU, @@ -28799,7 +28516,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1017 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" + // Pos:1007 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" { .Instruction = ND_INS_FNSTSW, .Category = ND_CAT_X87_ALU, @@ -28826,7 +28543,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1018 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" + // Pos:1008 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" { .Instruction = ND_INS_FNSTSW, .Category = ND_CAT_X87_ALU, @@ -28853,7 +28570,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1019 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" + // Pos:1009 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" { .Instruction = ND_INS_FPATAN, .Category = ND_CAT_X87_ALU, @@ -28879,7 +28596,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1020 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" + // Pos:1010 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" { .Instruction = ND_INS_FPREM, .Category = ND_CAT_X87_ALU, @@ -28905,7 +28622,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1021 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" + // Pos:1011 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" { .Instruction = ND_INS_FPREM1, .Category = ND_CAT_X87_ALU, @@ -28931,7 +28648,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1022 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" + // Pos:1012 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" { .Instruction = ND_INS_FPTAN, .Category = ND_CAT_X87_ALU, @@ -28957,7 +28674,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1023 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" + // Pos:1013 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" { .Instruction = ND_INS_FRINEAR, .Category = ND_CAT_X87_ALU, @@ -28983,7 +28700,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1024 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" + // Pos:1014 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" { .Instruction = ND_INS_FRNDINT, .Category = ND_CAT_X87_ALU, @@ -29009,7 +28726,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1025 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" + // Pos:1015 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" { .Instruction = ND_INS_FRSTOR, .Category = ND_CAT_X87_ALU, @@ -29036,7 +28753,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1026 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" + // Pos:1016 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" { .Instruction = ND_INS_FSCALE, .Category = ND_CAT_X87_ALU, @@ -29062,7 +28779,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1027 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" + // Pos:1017 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" { .Instruction = ND_INS_FSIN, .Category = ND_CAT_X87_ALU, @@ -29088,7 +28805,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1028 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" + // Pos:1018 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" { .Instruction = ND_INS_FSINCOS, .Category = ND_CAT_X87_ALU, @@ -29114,7 +28831,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1029 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" + // Pos:1019 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" { .Instruction = ND_INS_FSQRT, .Category = ND_CAT_X87_ALU, @@ -29140,7 +28857,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1030 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" + // Pos:1020 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" { .Instruction = ND_INS_FST, .Category = ND_CAT_X87_ALU, @@ -29168,7 +28885,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1031 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" + // Pos:1021 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" { .Instruction = ND_INS_FST, .Category = ND_CAT_X87_ALU, @@ -29196,7 +28913,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1032 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" + // Pos:1022 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" { .Instruction = ND_INS_FST, .Category = ND_CAT_X87_ALU, @@ -29224,7 +28941,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1033 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" + // Pos:1023 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" { .Instruction = ND_INS_FSTDW, .Category = ND_CAT_X87_ALU, @@ -29250,7 +28967,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1034 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" + // Pos:1024 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" { .Instruction = ND_INS_FSTP, .Category = ND_CAT_X87_ALU, @@ -29278,7 +28995,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1035 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" + // Pos:1025 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" { .Instruction = ND_INS_FSTP, .Category = ND_CAT_X87_ALU, @@ -29306,7 +29023,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1036 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" + // Pos:1026 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" { .Instruction = ND_INS_FSTP, .Category = ND_CAT_X87_ALU, @@ -29334,7 +29051,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1037 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" + // Pos:1027 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" { .Instruction = ND_INS_FSTP, .Category = ND_CAT_X87_ALU, @@ -29362,7 +29079,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1038 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" + // Pos:1028 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" { .Instruction = ND_INS_FSTP, .Category = ND_CAT_X87_ALU, @@ -29390,7 +29107,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1039 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" + // Pos:1029 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" { .Instruction = ND_INS_FSTP, .Category = ND_CAT_X87_ALU, @@ -29418,7 +29135,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1040 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" + // Pos:1030 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" { .Instruction = ND_INS_FSTPNCE, .Category = ND_CAT_X87_ALU, @@ -29446,7 +29163,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1041 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" + // Pos:1031 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" { .Instruction = ND_INS_FSTSG, .Category = ND_CAT_X87_ALU, @@ -29472,7 +29189,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1042 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" + // Pos:1032 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" { .Instruction = ND_INS_FSUB, .Category = ND_CAT_X87_ALU, @@ -29500,7 +29217,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1043 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" + // Pos:1033 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" { .Instruction = ND_INS_FSUB, .Category = ND_CAT_X87_ALU, @@ -29528,7 +29245,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1044 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" + // Pos:1034 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" { .Instruction = ND_INS_FSUB, .Category = ND_CAT_X87_ALU, @@ -29556,7 +29273,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1045 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" + // Pos:1035 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" { .Instruction = ND_INS_FSUB, .Category = ND_CAT_X87_ALU, @@ -29584,7 +29301,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1046 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" + // Pos:1036 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" { .Instruction = ND_INS_FSUBP, .Category = ND_CAT_X87_ALU, @@ -29612,7 +29329,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1047 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" + // Pos:1037 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" { .Instruction = ND_INS_FSUBR, .Category = ND_CAT_X87_ALU, @@ -29640,7 +29357,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1048 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" + // Pos:1038 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" { .Instruction = ND_INS_FSUBR, .Category = ND_CAT_X87_ALU, @@ -29668,7 +29385,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1049 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" + // Pos:1039 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" { .Instruction = ND_INS_FSUBR, .Category = ND_CAT_X87_ALU, @@ -29696,7 +29413,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1050 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" + // Pos:1040 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" { .Instruction = ND_INS_FSUBR, .Category = ND_CAT_X87_ALU, @@ -29724,7 +29441,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1051 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" + // Pos:1041 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" { .Instruction = ND_INS_FSUBRP, .Category = ND_CAT_X87_ALU, @@ -29752,7 +29469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1052 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" + // Pos:1042 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" { .Instruction = ND_INS_FTST, .Category = ND_CAT_X87_ALU, @@ -29778,7 +29495,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1053 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" + // Pos:1043 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" { .Instruction = ND_INS_FUCOM, .Category = ND_CAT_X87_ALU, @@ -29806,7 +29523,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1054 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" + // Pos:1044 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" { .Instruction = ND_INS_FUCOMI, .Category = ND_CAT_X87_ALU, @@ -29835,7 +29552,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1055 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" + // Pos:1045 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" { .Instruction = ND_INS_FUCOMIP, .Category = ND_CAT_X87_ALU, @@ -29864,7 +29581,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1056 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" + // Pos:1046 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" { .Instruction = ND_INS_FUCOMP, .Category = ND_CAT_X87_ALU, @@ -29892,7 +29609,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1057 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" + // Pos:1047 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" { .Instruction = ND_INS_FUCOMPP, .Category = ND_CAT_X87_ALU, @@ -29918,7 +29635,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1058 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" + // Pos:1048 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" { .Instruction = ND_INS_FXAM, .Category = ND_CAT_X87_ALU, @@ -29944,7 +29661,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1059 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" + // Pos:1049 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" { .Instruction = ND_INS_FXCH, .Category = ND_CAT_X87_ALU, @@ -29972,7 +29689,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1060 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" + // Pos:1050 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" { .Instruction = ND_INS_FXCH, .Category = ND_CAT_X87_ALU, @@ -30000,7 +29717,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1061 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" + // Pos:1051 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" { .Instruction = ND_INS_FXCH, .Category = ND_CAT_X87_ALU, @@ -30028,7 +29745,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1062 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" + // Pos:1052 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" { .Instruction = ND_INS_FXRSTOR, .Category = ND_CAT_SSE, @@ -30055,7 +29772,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1063 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" + // Pos:1053 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" { .Instruction = ND_INS_FXRSTOR64, .Category = ND_CAT_SSE, @@ -30082,7 +29799,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1064 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" + // Pos:1054 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" { .Instruction = ND_INS_FXSAVE, .Category = ND_CAT_SSE, @@ -30109,7 +29826,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1065 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" + // Pos:1055 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" { .Instruction = ND_INS_FXSAVE64, .Category = ND_CAT_SSE, @@ -30136,7 +29853,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1066 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" + // Pos:1056 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" { .Instruction = ND_INS_FXTRACT, .Category = ND_CAT_X87_ALU, @@ -30162,7 +29879,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1067 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" + // Pos:1057 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" { .Instruction = ND_INS_FYL2X, .Category = ND_CAT_X87_ALU, @@ -30188,7 +29905,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1068 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" + // Pos:1058 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" { .Instruction = ND_INS_FYL2XP1, .Category = ND_CAT_X87_ALU, @@ -30214,7 +29931,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1069 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" + // Pos:1059 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" { .Instruction = ND_INS_GETSEC, .Category = ND_CAT_SYSTEM, @@ -30241,7 +29958,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1070 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" + // Pos:1060 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" { .Instruction = ND_INS_GF2P8AFFINEINVQB, .Category = ND_CAT_GFNI, @@ -30269,7 +29986,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1071 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" + // Pos:1061 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" { .Instruction = ND_INS_GF2P8AFFINEQB, .Category = ND_CAT_GFNI, @@ -30297,7 +30014,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1072 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" + // Pos:1062 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" { .Instruction = ND_INS_GF2P8MULB, .Category = ND_CAT_GFNI, @@ -30324,7 +30041,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1073 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" + // Pos:1063 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" { .Instruction = ND_INS_HADDPD, .Category = ND_CAT_SSE, @@ -30351,7 +30068,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1074 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" + // Pos:1064 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" { .Instruction = ND_INS_HADDPS, .Category = ND_CAT_SSE, @@ -30378,7 +30095,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1075 Instruction:"HLT" Encoding:"0xF4"/"" + // Pos:1065 Instruction:"HLT" Encoding:"0xF4"/"" { .Instruction = ND_INS_HLT, .Category = ND_CAT_SYSTEM, @@ -30404,7 +30121,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1076 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" + // Pos:1066 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" { .Instruction = ND_INS_HRESET, .Category = ND_CAT_HRESET, @@ -30431,7 +30148,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1077 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" + // Pos:1067 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" { .Instruction = ND_INS_HSUBPD, .Category = ND_CAT_SSE, @@ -30458,7 +30175,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1078 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" + // Pos:1068 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" { .Instruction = ND_INS_HSUBPS, .Category = ND_CAT_SSE, @@ -30485,7 +30202,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1079 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /7"/"M" + // Pos:1069 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30515,7 +30232,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1080 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /7"/"M" + // Pos:1070 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30544,7 +30261,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1081 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /7"/"M" + // Pos:1071 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30573,7 +30290,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1082 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /7"/"M" + // Pos:1072 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30602,7 +30319,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1083 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /7"/"M" + // Pos:1073 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30630,7 +30347,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1084 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /7"/"M" + // Pos:1074 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30658,7 +30375,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1085 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" + // Pos:1075 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30688,7 +30405,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1086 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" + // Pos:1076 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" { .Instruction = ND_INS_IDIV, .Category = ND_CAT_ARITH, @@ -30717,7 +30434,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1087 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x69 /r iz"/"RMI" + // Pos:1077 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30746,7 +30463,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1088 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x69 /r iz"/"RMI" + // Pos:1078 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30775,7 +30492,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1089 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x6B /r ib"/"RMI" + // Pos:1079 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30804,7 +30521,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1090 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x6B /r ib"/"RMI" + // Pos:1080 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30833,7 +30550,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1091 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x69 /r iz"/"RMI" + // Pos:1081 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30861,7 +30578,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1092 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x69 /r iz"/"RMI" + // Pos:1082 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30889,7 +30606,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1093 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x6B /r ib"/"RMI" + // Pos:1083 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30917,7 +30634,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1094 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x6B /r ib"/"RMI" + // Pos:1084 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30945,7 +30662,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1095 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x69 /r iz"/"RMI" + // Pos:1085 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -30974,7 +30691,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1096 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x69 /r iz"/"RMI" + // Pos:1086 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31003,7 +30720,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1097 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x6B /r ib"/"RMI" + // Pos:1087 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31032,7 +30749,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1098 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x6B /r ib"/"RMI" + // Pos:1088 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31061,7 +30778,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1099 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x69 /r iz"/"RMI" + // Pos:1089 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31089,7 +30806,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1100 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x69 /r iz"/"RMI" + // Pos:1090 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31117,7 +30834,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1101 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x6B /r ib"/"RMI" + // Pos:1091 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31145,7 +30862,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1102 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x6B /r ib"/"RMI" + // Pos:1092 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31173,7 +30890,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1103 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAF /r"/"RM" + // Pos:1093 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAF /r"/"RM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31201,7 +30918,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1104 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAF /r"/"RM" + // Pos:1094 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAF /r"/"RM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31229,7 +30946,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1105 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /5"/"M" + // Pos:1095 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31258,7 +30975,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1106 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /5"/"M" + // Pos:1096 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31287,7 +31004,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1107 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /5"/"M" + // Pos:1097 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31316,7 +31033,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1108 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAF /r"/"RM" + // Pos:1098 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAF /r"/"RM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31343,7 +31060,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1109 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAF /r"/"RM" + // Pos:1099 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAF /r"/"RM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31370,7 +31087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1110 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /5"/"M" + // Pos:1100 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31398,7 +31115,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1111 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /5"/"M" + // Pos:1101 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31426,7 +31143,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1112 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /5"/"M" + // Pos:1102 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31454,7 +31171,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1113 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAF /r"/"VRM" + // Pos:1103 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAF /r"/"VRM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31483,7 +31200,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1114 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAF /r"/"VRM" + // Pos:1104 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAF /r"/"VRM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31512,7 +31229,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1115 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAF /r"/"VRM" + // Pos:1105 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAF /r"/"VRM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31540,7 +31257,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1116 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAF /r"/"VRM" + // Pos:1106 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAF /r"/"VRM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31568,7 +31285,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1117 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" + // Pos:1107 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31597,7 +31314,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1118 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" + // Pos:1108 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31626,7 +31343,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1119 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" + // Pos:1109 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31655,7 +31372,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1120 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" + // Pos:1110 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31684,7 +31401,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1121 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" + // Pos:1111 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" { .Instruction = ND_INS_IMUL, .Category = ND_CAT_ARITH, @@ -31712,7 +31429,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1122 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" + // Pos:1112 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" { .Instruction = ND_INS_IN, .Category = ND_CAT_IO, @@ -31740,7 +31457,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1123 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" + // Pos:1113 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" { .Instruction = ND_INS_IN, .Category = ND_CAT_IO, @@ -31768,7 +31485,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1124 Instruction:"IN AL,DX" Encoding:"0xEC"/"" + // Pos:1114 Instruction:"IN AL,DX" Encoding:"0xEC"/"" { .Instruction = ND_INS_IN, .Category = ND_CAT_IO, @@ -31796,7 +31513,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1125 Instruction:"IN eAX,DX" Encoding:"0xED"/"" + // Pos:1115 Instruction:"IN eAX,DX" Encoding:"0xED"/"" { .Instruction = ND_INS_IN, .Category = ND_CAT_IO, @@ -31824,7 +31541,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1126 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /0"/"M" + // Pos:1116 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -31851,7 +31568,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1127 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /0"/"M" + // Pos:1117 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -31878,7 +31595,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1128 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /0"/"M" + // Pos:1118 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -31905,7 +31622,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1129 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /0"/"M" + // Pos:1119 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -31931,7 +31648,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1130 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /0"/"M" + // Pos:1120 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -31957,7 +31674,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1131 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /0"/"M" + // Pos:1121 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -31983,7 +31700,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1132 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /0"/"VM" + // Pos:1122 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /0"/"VM" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32011,7 +31728,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1133 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /0"/"VM" + // Pos:1123 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /0"/"VM" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32039,7 +31756,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1134 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /0"/"VM" + // Pos:1124 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /0"/"VM" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32067,7 +31784,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1135 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /0"/"VM" + // Pos:1125 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /0"/"VM" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32094,7 +31811,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1136 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /0"/"VM" + // Pos:1126 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /0"/"VM" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32121,7 +31838,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1137 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /0"/"VM" + // Pos:1127 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /0"/"VM" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32148,7 +31865,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1138 Instruction:"INC Zv" Encoding:"0x40"/"O" + // Pos:1128 Instruction:"INC Zv" Encoding:"0x40"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32175,7 +31892,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1139 Instruction:"INC Zv" Encoding:"0x41"/"O" + // Pos:1129 Instruction:"INC Zv" Encoding:"0x41"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32202,7 +31919,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1140 Instruction:"INC Zv" Encoding:"0x42"/"O" + // Pos:1130 Instruction:"INC Zv" Encoding:"0x42"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32229,7 +31946,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1141 Instruction:"INC Zv" Encoding:"0x43"/"O" + // Pos:1131 Instruction:"INC Zv" Encoding:"0x43"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32256,7 +31973,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1142 Instruction:"INC Zv" Encoding:"0x44"/"O" + // Pos:1132 Instruction:"INC Zv" Encoding:"0x44"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32283,7 +32000,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1143 Instruction:"INC Zv" Encoding:"0x45"/"O" + // Pos:1133 Instruction:"INC Zv" Encoding:"0x45"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32310,7 +32027,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1144 Instruction:"INC Zv" Encoding:"0x46"/"O" + // Pos:1134 Instruction:"INC Zv" Encoding:"0x46"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32337,7 +32054,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1145 Instruction:"INC Zv" Encoding:"0x47"/"O" + // Pos:1135 Instruction:"INC Zv" Encoding:"0x47"/"O" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32364,7 +32081,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1146 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" + // Pos:1136 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32391,7 +32108,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1147 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" + // Pos:1137 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" { .Instruction = ND_INS_INC, .Category = ND_CAT_ARITH, @@ -32418,7 +32135,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1148 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" + // Pos:1138 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" { .Instruction = ND_INS_INCSSP, .Category = ND_CAT_CET, @@ -32446,7 +32163,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1149 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" + // Pos:1139 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" { .Instruction = ND_INS_INCSSP, .Category = ND_CAT_CET, @@ -32474,7 +32191,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1150 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" + // Pos:1140 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" { .Instruction = ND_INS_INS, .Category = ND_CAT_IOSTRINGOP, @@ -32503,7 +32220,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1151 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" + // Pos:1141 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" { .Instruction = ND_INS_INS, .Category = ND_CAT_IOSTRINGOP, @@ -32533,7 +32250,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1152 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" + // Pos:1142 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" { .Instruction = ND_INS_INS, .Category = ND_CAT_IOSTRINGOP, @@ -32562,7 +32279,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1153 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" + // Pos:1143 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" { .Instruction = ND_INS_INS, .Category = ND_CAT_IOSTRINGOP, @@ -32592,7 +32309,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1154 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" + // Pos:1144 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" { .Instruction = ND_INS_INSERTPS, .Category = ND_CAT_SSE, @@ -32620,7 +32337,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1155 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" + // Pos:1145 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" { .Instruction = ND_INS_INSERTPS, .Category = ND_CAT_SSE, @@ -32648,7 +32365,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1156 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" + // Pos:1146 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" { .Instruction = ND_INS_INSERTQ, .Category = ND_CAT_BITBYTE, @@ -32677,7 +32394,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1157 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" + // Pos:1147 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" { .Instruction = ND_INS_INSERTQ, .Category = ND_CAT_BITBYTE, @@ -32704,7 +32421,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1158 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" + // Pos:1148 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" { .Instruction = ND_INS_INS, .Category = ND_CAT_IOSTRINGOP, @@ -32733,7 +32450,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1159 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" + // Pos:1149 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" { .Instruction = ND_INS_INS, .Category = ND_CAT_IOSTRINGOP, @@ -32763,7 +32480,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1160 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" + // Pos:1150 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" { .Instruction = ND_INS_INT, .Category = ND_CAT_INTERRUPT, @@ -32794,7 +32511,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1161 Instruction:"INT1" Encoding:"0xF1"/"" + // Pos:1151 Instruction:"INT1" Encoding:"0xF1"/"" { .Instruction = ND_INS_INT1, .Category = ND_CAT_INTERRUPT, @@ -32823,7 +32540,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1162 Instruction:"INT3" Encoding:"0xCC"/"" + // Pos:1152 Instruction:"INT3" Encoding:"0xCC"/"" { .Instruction = ND_INS_INT3, .Category = ND_CAT_INTERRUPT, @@ -32853,7 +32570,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1163 Instruction:"INTO" Encoding:"0xCE"/"" + // Pos:1153 Instruction:"INTO" Encoding:"0xCE"/"" { .Instruction = ND_INS_INTO, .Category = ND_CAT_INTERRUPT, @@ -32883,7 +32600,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1164 Instruction:"INVD" Encoding:"0x0F 0x08"/"" + // Pos:1154 Instruction:"INVD" Encoding:"0x0F 0x08"/"" { .Instruction = ND_INS_INVD, .Category = ND_CAT_SYSTEM, @@ -32909,7 +32626,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1165 Instruction:"INVEPT Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF0 /r:mem"/"RM" + // Pos:1155 Instruction:"INVEPT Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF0 /r:mem"/"RM" { .Instruction = ND_INS_INVEPT, .Category = ND_CAT_VTX, @@ -32937,7 +32654,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1166 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" + // Pos:1156 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" { .Instruction = ND_INS_INVEPT, .Category = ND_CAT_VTX, @@ -32965,7 +32682,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1167 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" + // Pos:1157 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" { .Instruction = ND_INS_INVLPG, .Category = ND_CAT_SYSTEM, @@ -32991,7 +32708,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1168 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" + // Pos:1158 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" { .Instruction = ND_INS_INVLPGA, .Category = ND_CAT_SYSTEM, @@ -33018,7 +32735,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1169 Instruction:"INVLPGB" Encoding:"NP 0x0F 0x01 /0xFE"/"" + // Pos:1159 Instruction:"INVLPGB" Encoding:"NP 0x0F 0x01 /0xFE"/"" { .Instruction = ND_INS_INVLPGB, .Category = ND_CAT_SYSTEM, @@ -33046,7 +32763,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1170 Instruction:"INVPCID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF2 /r:mem"/"RM" + // Pos:1160 Instruction:"INVPCID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF2 /r:mem"/"RM" { .Instruction = ND_INS_INVPCID, .Category = ND_CAT_MISC, @@ -33073,7 +32790,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1171 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" + // Pos:1161 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" { .Instruction = ND_INS_INVPCID, .Category = ND_CAT_MISC, @@ -33100,7 +32817,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1172 Instruction:"INVVPID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF1 /r:mem"/"RM" + // Pos:1162 Instruction:"INVVPID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF1 /r:mem"/"RM" { .Instruction = ND_INS_INVVPID, .Category = ND_CAT_VTX, @@ -33128,7 +32845,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1173 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" + // Pos:1163 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" { .Instruction = ND_INS_INVVPID, .Category = ND_CAT_VTX, @@ -33156,7 +32873,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1174 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" + // Pos:1164 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" { .Instruction = ND_INS_IRET, .Category = ND_CAT_RET, @@ -33186,7 +32903,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1175 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" + // Pos:1165 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" { .Instruction = ND_INS_IRET, .Category = ND_CAT_RET, @@ -33216,7 +32933,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1176 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" + // Pos:1166 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" { .Instruction = ND_INS_IRET, .Category = ND_CAT_RET, @@ -33246,7 +32963,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1177 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" + // Pos:1167 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33274,7 +32991,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1178 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" + // Pos:1168 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33302,7 +33019,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1179 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" + // Pos:1169 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33330,7 +33047,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1180 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" + // Pos:1170 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33358,7 +33075,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1181 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" + // Pos:1171 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" { .Instruction = ND_INS_JrCXZ, .Category = ND_CAT_COND_BR, @@ -33386,7 +33103,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1182 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" + // Pos:1172 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" { .Instruction = ND_INS_JrCXZ, .Category = ND_CAT_COND_BR, @@ -33414,7 +33131,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1183 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" + // Pos:1173 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33442,7 +33159,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1184 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" + // Pos:1174 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33470,7 +33187,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1185 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" + // Pos:1175 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33498,7 +33215,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1186 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" + // Pos:1176 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33526,7 +33243,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1187 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" + // Pos:1177 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" { .Instruction = ND_INS_JMPNR, .Category = ND_CAT_UNCOND_BR, @@ -33553,7 +33270,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1188 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" + // Pos:1178 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" { .Instruction = ND_INS_JMPNR, .Category = ND_CAT_UNCOND_BR, @@ -33580,7 +33297,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1189 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" + // Pos:1179 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" { .Instruction = ND_INS_JMPNI, .Category = ND_CAT_UNCOND_BR, @@ -33607,7 +33324,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1190 Instruction:"JMPABS Aq" Encoding:"rex2 w:0 0xA1 cq"/"D" + // Pos:1180 Instruction:"JMPABS Aq" Encoding:"rex2 w:0 0xA1 cq"/"D" { .Instruction = ND_INS_JMPABS, .Category = ND_CAT_UNCOND_BR, @@ -33634,7 +33351,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1191 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" + // Pos:1181 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" { .Instruction = ND_INS_JMPE, .Category = ND_CAT_SYSTEM, @@ -33661,7 +33378,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1192 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" + // Pos:1182 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" { .Instruction = ND_INS_JMPE, .Category = ND_CAT_UNCOND_BR, @@ -33688,7 +33405,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1193 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" + // Pos:1183 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" { .Instruction = ND_INS_JMPFD, .Category = ND_CAT_UNCOND_BR, @@ -33716,7 +33433,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1194 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" + // Pos:1184 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" { .Instruction = ND_INS_JMPFI, .Category = ND_CAT_UNCOND_BR, @@ -33744,7 +33461,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1195 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" + // Pos:1185 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33772,7 +33489,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1196 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" + // Pos:1186 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33800,7 +33517,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1197 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" + // Pos:1187 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33828,7 +33545,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1198 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" + // Pos:1188 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33856,7 +33573,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1199 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" + // Pos:1189 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33884,7 +33601,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1200 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" + // Pos:1190 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33912,7 +33629,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1201 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" + // Pos:1191 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33940,7 +33657,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1202 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" + // Pos:1192 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33968,7 +33685,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1203 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" + // Pos:1193 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -33996,7 +33713,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1204 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" + // Pos:1194 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34024,7 +33741,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1205 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" + // Pos:1195 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34052,7 +33769,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1206 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" + // Pos:1196 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34080,7 +33797,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1207 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" + // Pos:1197 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34108,7 +33825,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1208 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" + // Pos:1198 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34136,7 +33853,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1209 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" + // Pos:1199 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34164,7 +33881,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1210 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" + // Pos:1200 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34192,7 +33909,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1211 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" + // Pos:1201 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34220,7 +33937,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1212 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" + // Pos:1202 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34248,7 +33965,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1213 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" + // Pos:1203 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34276,7 +33993,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1214 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" + // Pos:1204 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34304,7 +34021,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1215 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" + // Pos:1205 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" { .Instruction = ND_INS_JrCXZ, .Category = ND_CAT_COND_BR, @@ -34332,7 +34049,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1216 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" + // Pos:1206 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34360,7 +34077,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1217 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" + // Pos:1207 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34388,7 +34105,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1218 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" + // Pos:1208 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34416,7 +34133,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1219 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" + // Pos:1209 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" { .Instruction = ND_INS_Jcc, .Category = ND_CAT_COND_BR, @@ -34444,7 +34161,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1220 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" + // Pos:1210 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" { .Instruction = ND_INS_KADD, .Category = ND_CAT_KMASK, @@ -34472,7 +34189,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1221 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" + // Pos:1211 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" { .Instruction = ND_INS_KADD, .Category = ND_CAT_KMASK, @@ -34500,7 +34217,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1222 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" + // Pos:1212 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" { .Instruction = ND_INS_KADD, .Category = ND_CAT_KMASK, @@ -34528,7 +34245,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1223 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" + // Pos:1213 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" { .Instruction = ND_INS_KADD, .Category = ND_CAT_KMASK, @@ -34556,7 +34273,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1224 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" + // Pos:1214 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" { .Instruction = ND_INS_KAND, .Category = ND_CAT_KMASK, @@ -34584,7 +34301,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1225 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" + // Pos:1215 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" { .Instruction = ND_INS_KAND, .Category = ND_CAT_KMASK, @@ -34612,7 +34329,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1226 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" + // Pos:1216 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" { .Instruction = ND_INS_KANDN, .Category = ND_CAT_KMASK, @@ -34640,7 +34357,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1227 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" + // Pos:1217 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" { .Instruction = ND_INS_KANDN, .Category = ND_CAT_KMASK, @@ -34668,7 +34385,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1228 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" + // Pos:1218 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" { .Instruction = ND_INS_KANDN, .Category = ND_CAT_KMASK, @@ -34696,7 +34413,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1229 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" + // Pos:1219 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" { .Instruction = ND_INS_KANDN, .Category = ND_CAT_KMASK, @@ -34724,7 +34441,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1230 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" + // Pos:1220 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" { .Instruction = ND_INS_KAND, .Category = ND_CAT_KMASK, @@ -34752,7 +34469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1231 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" + // Pos:1221 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" { .Instruction = ND_INS_KAND, .Category = ND_CAT_KMASK, @@ -34780,7 +34497,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1232 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" + // Pos:1222 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" { .Instruction = ND_INS_KMERGE2L1H, .Category = ND_CAT_UNKNOWN, @@ -34807,7 +34524,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1233 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" + // Pos:1223 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" { .Instruction = ND_INS_KMERGE2L1L, .Category = ND_CAT_UNKNOWN, @@ -34834,7 +34551,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1234 Instruction:"KMOVB rKb,Mb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem"/"RM" + // Pos:1224 Instruction:"KMOVB rKb,Mb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -34861,7 +34578,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1235 Instruction:"KMOVB rKb,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg"/"RM" + // Pos:1225 Instruction:"KMOVB rKb,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -34888,7 +34605,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1236 Instruction:"KMOVB Mb,rKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem"/"MR" + // Pos:1226 Instruction:"KMOVB Mb,rKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -34915,7 +34632,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1237 Instruction:"KMOVB rKb,Ry" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg"/"RM" + // Pos:1227 Instruction:"KMOVB rKb,Ry" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -34942,7 +34659,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1238 Instruction:"KMOVB Gy,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg"/"RM" + // Pos:1228 Instruction:"KMOVB Gy,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -34969,7 +34686,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1239 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" + // Pos:1229 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -34996,7 +34713,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1240 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" + // Pos:1230 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35023,7 +34740,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1241 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" + // Pos:1231 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35050,7 +34767,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1242 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:1232 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35077,7 +34794,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1243 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:1233 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35104,7 +34821,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1244 Instruction:"KMOVD rKd,Md" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem"/"RM" + // Pos:1234 Instruction:"KMOVD rKd,Md" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35131,7 +34848,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1245 Instruction:"KMOVD rKd,mKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg"/"RM" + // Pos:1235 Instruction:"KMOVD rKd,mKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35158,7 +34875,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1246 Instruction:"KMOVD Md,rKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem"/"MR" + // Pos:1236 Instruction:"KMOVD Md,rKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35185,7 +34902,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1247 Instruction:"KMOVD rKd,Ry" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg"/"RM" + // Pos:1237 Instruction:"KMOVD rKd,Ry" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35212,7 +34929,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1248 Instruction:"KMOVD Gy,mKd" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg"/"RM" + // Pos:1238 Instruction:"KMOVD Gy,mKd" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35239,7 +34956,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1249 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" + // Pos:1239 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35266,7 +34983,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1250 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" + // Pos:1240 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35293,7 +35010,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1251 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" + // Pos:1241 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35320,7 +35037,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1252 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:1242 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35347,7 +35064,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1253 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:1243 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35374,7 +35091,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1254 Instruction:"KMOVQ rKq,Mq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem"/"RM" + // Pos:1244 Instruction:"KMOVQ rKq,Mq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35401,7 +35118,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1255 Instruction:"KMOVQ rKq,mKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg"/"RM" + // Pos:1245 Instruction:"KMOVQ rKq,mKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35428,7 +35145,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1256 Instruction:"KMOVQ Mq,rKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem"/"MR" + // Pos:1246 Instruction:"KMOVQ Mq,rKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35455,7 +35172,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1257 Instruction:"KMOVQ rKq,Ry" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg"/"RM" + // Pos:1247 Instruction:"KMOVQ rKq,Ry" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35482,7 +35199,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1258 Instruction:"KMOVQ Gy,mKq" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg"/"RM" + // Pos:1248 Instruction:"KMOVQ Gy,mKq" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35509,7 +35226,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1259 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" + // Pos:1249 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35536,7 +35253,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1260 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" + // Pos:1250 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35563,7 +35280,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1261 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" + // Pos:1251 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35590,7 +35307,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1262 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" + // Pos:1252 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35617,7 +35334,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1263 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" + // Pos:1253 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35644,7 +35361,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1264 Instruction:"KMOVW rKw,Mw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem"/"RM" + // Pos:1254 Instruction:"KMOVW rKw,Mw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35671,7 +35388,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1265 Instruction:"KMOVW rKw,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg"/"RM" + // Pos:1255 Instruction:"KMOVW rKw,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35698,7 +35415,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1266 Instruction:"KMOVW Mw,rKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem"/"MR" + // Pos:1256 Instruction:"KMOVW Mw,rKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35725,7 +35442,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1267 Instruction:"KMOVW rKw,Ry" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg"/"RM" + // Pos:1257 Instruction:"KMOVW rKw,Ry" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35752,7 +35469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1268 Instruction:"KMOVW Gy,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg"/"RM" + // Pos:1258 Instruction:"KMOVW Gy,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35779,7 +35496,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1269 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" + // Pos:1259 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35806,7 +35523,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1270 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" + // Pos:1260 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35833,7 +35550,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1271 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" + // Pos:1261 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35860,7 +35577,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1272 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" + // Pos:1262 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35887,7 +35604,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1273 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" + // Pos:1263 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" { .Instruction = ND_INS_KMOV, .Category = ND_CAT_KMASK, @@ -35914,7 +35631,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1274 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" + // Pos:1264 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" { .Instruction = ND_INS_KNOT, .Category = ND_CAT_KMASK, @@ -35941,7 +35658,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1275 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" + // Pos:1265 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" { .Instruction = ND_INS_KNOT, .Category = ND_CAT_KMASK, @@ -35968,7 +35685,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1276 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" + // Pos:1266 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" { .Instruction = ND_INS_KNOT, .Category = ND_CAT_KMASK, @@ -35995,7 +35712,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1277 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" + // Pos:1267 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" { .Instruction = ND_INS_KNOT, .Category = ND_CAT_KMASK, @@ -36022,7 +35739,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1278 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" + // Pos:1268 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" { .Instruction = ND_INS_KOR, .Category = ND_CAT_KMASK, @@ -36050,7 +35767,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1279 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" + // Pos:1269 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" { .Instruction = ND_INS_KOR, .Category = ND_CAT_KMASK, @@ -36078,7 +35795,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1280 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" + // Pos:1270 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" { .Instruction = ND_INS_KOR, .Category = ND_CAT_KMASK, @@ -36106,7 +35823,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1281 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" + // Pos:1271 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" { .Instruction = ND_INS_KORTEST, .Category = ND_CAT_KMASK, @@ -36134,7 +35851,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1282 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" + // Pos:1272 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" { .Instruction = ND_INS_KORTEST, .Category = ND_CAT_KMASK, @@ -36162,7 +35879,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1283 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" + // Pos:1273 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" { .Instruction = ND_INS_KORTEST, .Category = ND_CAT_KMASK, @@ -36190,7 +35907,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1284 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" + // Pos:1274 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" { .Instruction = ND_INS_KORTEST, .Category = ND_CAT_KMASK, @@ -36218,7 +35935,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1285 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" + // Pos:1275 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" { .Instruction = ND_INS_KOR, .Category = ND_CAT_KMASK, @@ -36246,7 +35963,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1286 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" + // Pos:1276 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTL, .Category = ND_CAT_KMASK, @@ -36274,7 +35991,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1287 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" + // Pos:1277 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTL, .Category = ND_CAT_KMASK, @@ -36302,7 +36019,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1288 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" + // Pos:1278 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTL, .Category = ND_CAT_KMASK, @@ -36330,7 +36047,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1289 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" + // Pos:1279 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTL, .Category = ND_CAT_KMASK, @@ -36358,7 +36075,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1290 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" + // Pos:1280 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTR, .Category = ND_CAT_KMASK, @@ -36386,7 +36103,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1291 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" + // Pos:1281 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTR, .Category = ND_CAT_KMASK, @@ -36414,7 +36131,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1292 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" + // Pos:1282 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTR, .Category = ND_CAT_KMASK, @@ -36442,7 +36159,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1293 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" + // Pos:1283 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" { .Instruction = ND_INS_KSHIFTR, .Category = ND_CAT_KMASK, @@ -36470,7 +36187,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1294 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" + // Pos:1284 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" { .Instruction = ND_INS_KTEST, .Category = ND_CAT_KMASK, @@ -36497,7 +36214,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1295 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" + // Pos:1285 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" { .Instruction = ND_INS_KTEST, .Category = ND_CAT_KMASK, @@ -36524,7 +36241,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1296 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" + // Pos:1286 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" { .Instruction = ND_INS_KTEST, .Category = ND_CAT_KMASK, @@ -36551,7 +36268,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1297 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" + // Pos:1287 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" { .Instruction = ND_INS_KTEST, .Category = ND_CAT_KMASK, @@ -36578,7 +36295,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1298 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" + // Pos:1288 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" { .Instruction = ND_INS_KUNPCKBW, .Category = ND_CAT_KMASK, @@ -36606,7 +36323,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1299 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" + // Pos:1289 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" { .Instruction = ND_INS_KUNPCKDQ, .Category = ND_CAT_KMASK, @@ -36634,7 +36351,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1300 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" + // Pos:1290 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" { .Instruction = ND_INS_KUNPCKWD, .Category = ND_CAT_KMASK, @@ -36662,7 +36379,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1301 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" + // Pos:1291 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" { .Instruction = ND_INS_KXNOR, .Category = ND_CAT_KMASK, @@ -36690,7 +36407,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1302 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" + // Pos:1292 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" { .Instruction = ND_INS_KXNOR, .Category = ND_CAT_KMASK, @@ -36718,7 +36435,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1303 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" + // Pos:1293 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" { .Instruction = ND_INS_KXNOR, .Category = ND_CAT_KMASK, @@ -36746,7 +36463,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1304 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" + // Pos:1294 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" { .Instruction = ND_INS_KXNOR, .Category = ND_CAT_KMASK, @@ -36774,7 +36491,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1305 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" + // Pos:1295 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" { .Instruction = ND_INS_KXOR, .Category = ND_CAT_KMASK, @@ -36802,7 +36519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1306 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" + // Pos:1296 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" { .Instruction = ND_INS_KXOR, .Category = ND_CAT_KMASK, @@ -36830,7 +36547,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1307 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" + // Pos:1297 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" { .Instruction = ND_INS_KXOR, .Category = ND_CAT_KMASK, @@ -36858,7 +36575,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1308 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" + // Pos:1298 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" { .Instruction = ND_INS_KXOR, .Category = ND_CAT_KMASK, @@ -36886,7 +36603,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1309 Instruction:"LAHF" Encoding:"0x9F"/"" + // Pos:1299 Instruction:"LAHF" Encoding:"0x9F"/"" { .Instruction = ND_INS_LAHF, .Category = ND_CAT_FLAGOP, @@ -36913,7 +36630,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1310 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" + // Pos:1300 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" { .Instruction = ND_INS_LAR, .Category = ND_CAT_SYSTEM, @@ -36941,7 +36658,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1311 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" + // Pos:1301 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" { .Instruction = ND_INS_LAR, .Category = ND_CAT_SYSTEM, @@ -36969,7 +36686,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1312 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" + // Pos:1302 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" { .Instruction = ND_INS_LDDQU, .Category = ND_CAT_SSE, @@ -36996,7 +36713,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1313 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" + // Pos:1303 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" { .Instruction = ND_INS_LDMXCSR, .Category = ND_CAT_SSE, @@ -37023,7 +36740,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1314 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" + // Pos:1304 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" { .Instruction = ND_INS_LDS, .Category = ND_CAT_SEGOP, @@ -37051,7 +36768,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1315 Instruction:"LDTILECFG Moq" Encoding:"evex m:2 p:0 l:0 nf:0 w:0 0x49 /0:mem"/"M" + // Pos:1305 Instruction:"LDTILECFG Moq" Encoding:"evex m:2 p:0 l:0 nf:0 w:0 0x49 /0:mem"/"M" { .Instruction = ND_INS_LDTILECFG, .Category = ND_CAT_AMX, @@ -37077,7 +36794,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1316 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" + // Pos:1306 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" { .Instruction = ND_INS_LDTILECFG, .Category = ND_CAT_AMX, @@ -37103,7 +36820,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1317 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" + // Pos:1307 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" { .Instruction = ND_INS_LEA, .Category = ND_CAT_MISC, @@ -37130,7 +36847,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1318 Instruction:"LEAVE" Encoding:"0xC9"/"" + // Pos:1308 Instruction:"LEAVE" Encoding:"0xC9"/"" { .Instruction = ND_INS_LEAVE, .Category = ND_CAT_MISC, @@ -37154,12 +36871,12 @@ const ND_IDBE gInstructions[4075] = { OP(ND_OPT_rBP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_R, 0, 0), OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), }, }, - // Pos:1319 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" + // Pos:1309 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" { .Instruction = ND_INS_LES, .Category = ND_CAT_SEGOP, @@ -37187,7 +36904,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1320 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" + // Pos:1310 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" { .Instruction = ND_INS_LFENCE, .Category = ND_CAT_MISC, @@ -37213,7 +36930,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1321 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" + // Pos:1311 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" { .Instruction = ND_INS_LFS, .Category = ND_CAT_SEGOP, @@ -37241,7 +36958,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1322 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" + // Pos:1312 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" { .Instruction = ND_INS_LGDT, .Category = ND_CAT_SYSTEM, @@ -37268,7 +36985,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1323 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" + // Pos:1313 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" { .Instruction = ND_INS_LGS, .Category = ND_CAT_SEGOP, @@ -37296,7 +37013,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1324 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" + // Pos:1314 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" { .Instruction = ND_INS_LIDT, .Category = ND_CAT_SYSTEM, @@ -37323,7 +37040,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1325 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" + // Pos:1315 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" { .Instruction = ND_INS_LKGS, .Category = ND_CAT_LKGS, @@ -37350,7 +37067,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1326 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" + // Pos:1316 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" { .Instruction = ND_INS_LKGS, .Category = ND_CAT_LKGS, @@ -37377,7 +37094,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1327 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" + // Pos:1317 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" { .Instruction = ND_INS_LLDT, .Category = ND_CAT_SYSTEM, @@ -37404,7 +37121,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1328 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" + // Pos:1318 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" { .Instruction = ND_INS_LLWPCB, .Category = ND_CAT_LWP, @@ -37430,7 +37147,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1329 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" + // Pos:1319 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" { .Instruction = ND_INS_LMSW, .Category = ND_CAT_SYSTEM, @@ -37457,7 +37174,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1330 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" + // Pos:1320 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" { .Instruction = ND_INS_LOADIWKEY, .Category = ND_CAT_KL, @@ -37487,7 +37204,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1331 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" + // Pos:1321 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37516,7 +37233,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1332 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" + // Pos:1322 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37546,7 +37263,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1333 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" + // Pos:1323 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37575,7 +37292,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1334 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" + // Pos:1324 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37605,7 +37322,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1335 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" + // Pos:1325 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37634,7 +37351,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1336 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" + // Pos:1326 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37664,7 +37381,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1337 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" + // Pos:1327 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37693,7 +37410,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1338 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" + // Pos:1328 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" { .Instruction = ND_INS_LODS, .Category = ND_CAT_STRINGOP, @@ -37723,7 +37440,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1339 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" + // Pos:1329 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" { .Instruction = ND_INS_LOOP, .Category = ND_CAT_COND_BR, @@ -37752,7 +37469,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1340 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" + // Pos:1330 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" { .Instruction = ND_INS_LOOPNZ, .Category = ND_CAT_COND_BR, @@ -37781,7 +37498,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1341 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" + // Pos:1331 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" { .Instruction = ND_INS_LOOPZ, .Category = ND_CAT_COND_BR, @@ -37810,7 +37527,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1342 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" + // Pos:1332 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" { .Instruction = ND_INS_LSL, .Category = ND_CAT_SYSTEM, @@ -37838,7 +37555,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1343 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" + // Pos:1333 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" { .Instruction = ND_INS_LSL, .Category = ND_CAT_SYSTEM, @@ -37866,7 +37583,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1344 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" + // Pos:1334 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" { .Instruction = ND_INS_LSS, .Category = ND_CAT_SEGOP, @@ -37894,7 +37611,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1345 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" + // Pos:1335 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" { .Instruction = ND_INS_LTR, .Category = ND_CAT_SYSTEM, @@ -37921,7 +37638,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1346 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" + // Pos:1336 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" { .Instruction = ND_INS_LWPINS, .Category = ND_CAT_LWP, @@ -37949,7 +37666,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1347 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" + // Pos:1337 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" { .Instruction = ND_INS_LWPVAL, .Category = ND_CAT_LWP, @@ -37977,7 +37694,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1348 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF5 /r"/"RM" + // Pos:1338 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF5 /r"/"RM" { .Instruction = ND_INS_LZCNT, .Category = ND_CAT_LZCNT, @@ -38005,7 +37722,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1349 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF5 /r"/"RM" + // Pos:1339 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF5 /r"/"RM" { .Instruction = ND_INS_LZCNT, .Category = ND_CAT_LZCNT, @@ -38033,7 +37750,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1350 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF5 /r"/"RM" + // Pos:1340 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF5 /r"/"RM" { .Instruction = ND_INS_LZCNT, .Category = ND_CAT_LZCNT, @@ -38060,7 +37777,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1351 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF5 /r"/"RM" + // Pos:1341 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF5 /r"/"RM" { .Instruction = ND_INS_LZCNT, .Category = ND_CAT_LZCNT, @@ -38087,7 +37804,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1352 Instruction:"LZCNT Gv,Ev" Encoding:"repz 0x0F 0xBD /r"/"RM" + // Pos:1342 Instruction:"LZCNT Gv,Ev" Encoding:"repz 0x0F 0xBD /r"/"RM" { .Instruction = ND_INS_LZCNT, .Category = ND_CAT_LZCNT, @@ -38115,7 +37832,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1353 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" + // Pos:1343 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" { .Instruction = ND_INS_MASKMOVDQU, .Category = ND_CAT_DATAXFER, @@ -38143,7 +37860,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1354 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" + // Pos:1344 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" { .Instruction = ND_INS_MASKMOVQ, .Category = ND_CAT_DATAXFER, @@ -38171,7 +37888,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1355 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" + // Pos:1345 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" { .Instruction = ND_INS_MAXPD, .Category = ND_CAT_SSE, @@ -38198,7 +37915,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1356 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" + // Pos:1346 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" { .Instruction = ND_INS_MAXPS, .Category = ND_CAT_SSE, @@ -38225,7 +37942,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1357 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" + // Pos:1347 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" { .Instruction = ND_INS_MAXSD, .Category = ND_CAT_SSE, @@ -38252,7 +37969,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1358 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" + // Pos:1348 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" { .Instruction = ND_INS_MAXSS, .Category = ND_CAT_SSE, @@ -38279,7 +37996,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1359 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" + // Pos:1349 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" { .Instruction = ND_INS_MCOMMIT, .Category = ND_CAT_MISC, @@ -38305,7 +38022,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1360 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" + // Pos:1350 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" { .Instruction = ND_INS_MFENCE, .Category = ND_CAT_MISC, @@ -38331,7 +38048,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1361 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" + // Pos:1351 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" { .Instruction = ND_INS_MINPD, .Category = ND_CAT_SSE, @@ -38358,7 +38075,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1362 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" + // Pos:1352 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" { .Instruction = ND_INS_MINPS, .Category = ND_CAT_SSE, @@ -38385,7 +38102,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1363 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" + // Pos:1353 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" { .Instruction = ND_INS_MINSD, .Category = ND_CAT_SSE, @@ -38412,7 +38129,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1364 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" + // Pos:1354 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" { .Instruction = ND_INS_MINSS, .Category = ND_CAT_SSE, @@ -38439,7 +38156,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1365 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" + // Pos:1355 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" { .Instruction = ND_INS_MONITOR, .Category = ND_CAT_MISC, @@ -38467,7 +38184,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1366 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" + // Pos:1356 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" { .Instruction = ND_INS_MONITORX, .Category = ND_CAT_SYSTEM, @@ -38495,7 +38212,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1367 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" + // Pos:1357 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38522,7 +38239,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1368 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" + // Pos:1358 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38549,7 +38266,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1369 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" + // Pos:1359 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38576,7 +38293,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1370 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" + // Pos:1360 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38603,7 +38320,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1371 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" + // Pos:1361 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38630,7 +38347,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1372 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" + // Pos:1362 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38657,7 +38374,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1373 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" + // Pos:1363 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38684,7 +38401,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1374 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" + // Pos:1364 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38711,7 +38428,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1375 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" + // Pos:1365 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38738,7 +38455,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1376 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" + // Pos:1366 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38765,7 +38482,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1377 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" + // Pos:1367 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38792,7 +38509,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1378 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" + // Pos:1368 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38819,7 +38536,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1379 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" + // Pos:1369 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38846,7 +38563,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1380 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" + // Pos:1370 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38873,7 +38590,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1381 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" + // Pos:1371 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38900,7 +38617,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1382 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" + // Pos:1372 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38927,7 +38644,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1383 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" + // Pos:1373 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38954,7 +38671,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1384 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" + // Pos:1374 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -38981,7 +38698,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1385 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" + // Pos:1375 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39008,7 +38725,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1386 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" + // Pos:1376 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39035,7 +38752,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1387 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" + // Pos:1377 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39062,7 +38779,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1388 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" + // Pos:1378 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39089,7 +38806,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1389 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" + // Pos:1379 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39116,7 +38833,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1390 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" + // Pos:1380 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39143,7 +38860,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1391 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" + // Pos:1381 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39170,7 +38887,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1392 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" + // Pos:1382 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39197,7 +38914,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1393 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" + // Pos:1383 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39224,7 +38941,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1394 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" + // Pos:1384 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39251,7 +38968,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1395 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" + // Pos:1385 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39278,7 +38995,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1396 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" + // Pos:1386 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" { .Instruction = ND_INS_MOV, .Category = ND_CAT_DATAXFER, @@ -39305,7 +39022,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1397 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" + // Pos:1387 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" { .Instruction = ND_INS_MOV_CR, .Category = ND_CAT_DATAXFER, @@ -39332,7 +39049,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1398 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" + // Pos:1388 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" { .Instruction = ND_INS_MOV_DR, .Category = ND_CAT_DATAXFER, @@ -39359,7 +39076,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1399 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" + // Pos:1389 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" { .Instruction = ND_INS_MOV_CR, .Category = ND_CAT_DATAXFER, @@ -39386,7 +39103,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1400 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" + // Pos:1390 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" { .Instruction = ND_INS_MOV_DR, .Category = ND_CAT_DATAXFER, @@ -39413,7 +39130,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1401 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" + // Pos:1391 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" { .Instruction = ND_INS_MOV_TR, .Category = ND_CAT_DATAXFER, @@ -39440,7 +39157,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1402 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" + // Pos:1392 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" { .Instruction = ND_INS_MOV_TR, .Category = ND_CAT_DATAXFER, @@ -39467,7 +39184,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1403 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" + // Pos:1393 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" { .Instruction = ND_INS_MOVAPD, .Category = ND_CAT_DATAXFER, @@ -39494,7 +39211,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1404 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" + // Pos:1394 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" { .Instruction = ND_INS_MOVAPD, .Category = ND_CAT_DATAXFER, @@ -39521,7 +39238,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1405 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" + // Pos:1395 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" { .Instruction = ND_INS_MOVAPS, .Category = ND_CAT_DATAXFER, @@ -39548,7 +39265,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1406 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" + // Pos:1396 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" { .Instruction = ND_INS_MOVAPS, .Category = ND_CAT_DATAXFER, @@ -39575,7 +39292,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1407 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x60 /r"/"RM" + // Pos:1397 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x60 /r"/"RM" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39602,7 +39319,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1408 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x60 /r"/"RM" + // Pos:1398 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x60 /r"/"RM" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39629,7 +39346,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1409 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x61 /r"/"MR" + // Pos:1399 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x61 /r"/"MR" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39656,7 +39373,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1410 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x61 /r"/"MR" + // Pos:1400 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x61 /r"/"MR" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39683,7 +39400,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1411 Instruction:"MOVBE Gv,Mv" Encoding:"NP 0x0F 0x38 0xF0 /r:mem"/"RM" + // Pos:1401 Instruction:"MOVBE Gv,Mv" Encoding:"NP 0x0F 0x38 0xF0 /r:mem"/"RM" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39710,7 +39427,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1412 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" + // Pos:1402 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39737,7 +39454,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1413 Instruction:"MOVBE Mv,Gv" Encoding:"NP 0x0F 0x38 0xF1 /r:mem"/"MR" + // Pos:1403 Instruction:"MOVBE Mv,Gv" Encoding:"NP 0x0F 0x38 0xF1 /r:mem"/"MR" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39764,7 +39481,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1414 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" + // Pos:1404 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" { .Instruction = ND_INS_MOVBE, .Category = ND_CAT_DATAXFER, @@ -39791,7 +39508,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1415 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" + // Pos:1405 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" { .Instruction = ND_INS_MOVD, .Category = ND_CAT_DATAXFER, @@ -39818,7 +39535,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1416 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" + // Pos:1406 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" { .Instruction = ND_INS_MOVD, .Category = ND_CAT_DATAXFER, @@ -39845,7 +39562,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1417 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" + // Pos:1407 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" { .Instruction = ND_INS_MOVD, .Category = ND_CAT_DATAXFER, @@ -39872,7 +39589,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1418 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" + // Pos:1408 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" { .Instruction = ND_INS_MOVD, .Category = ND_CAT_DATAXFER, @@ -39899,7 +39616,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1419 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" + // Pos:1409 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" { .Instruction = ND_INS_MOVDDUP, .Category = ND_CAT_DATAXFER, @@ -39926,7 +39643,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1420 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF8 /r:mem"/"M" + // Pos:1410 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF8 /r:mem"/"M" { .Instruction = ND_INS_MOVDIR64B, .Category = ND_CAT_MOVDIR64B, @@ -39953,7 +39670,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1421 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" + // Pos:1411 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" { .Instruction = ND_INS_MOVDIR64B, .Category = ND_CAT_MOVDIR64B, @@ -39980,7 +39697,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1422 Instruction:"MOVDIRI My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF9 /r:mem"/"MR" + // Pos:1412 Instruction:"MOVDIRI My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF9 /r:mem"/"MR" { .Instruction = ND_INS_MOVDIRI, .Category = ND_CAT_MOVDIRI, @@ -40007,7 +39724,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1423 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" + // Pos:1413 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" { .Instruction = ND_INS_MOVDIRI, .Category = ND_CAT_MOVDIRI, @@ -40034,7 +39751,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1424 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" + // Pos:1414 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" { .Instruction = ND_INS_MOVDQ2Q, .Category = ND_CAT_DATAXFER, @@ -40061,7 +39778,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1425 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" + // Pos:1415 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" { .Instruction = ND_INS_MOVDQA, .Category = ND_CAT_DATAXFER, @@ -40088,7 +39805,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1426 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" + // Pos:1416 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" { .Instruction = ND_INS_MOVDQA, .Category = ND_CAT_DATAXFER, @@ -40115,7 +39832,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1427 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" + // Pos:1417 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" { .Instruction = ND_INS_MOVDQU, .Category = ND_CAT_DATAXFER, @@ -40142,7 +39859,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1428 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" + // Pos:1418 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" { .Instruction = ND_INS_MOVDQU, .Category = ND_CAT_DATAXFER, @@ -40169,7 +39886,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1429 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" + // Pos:1419 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" { .Instruction = ND_INS_MOVHLPS, .Category = ND_CAT_DATAXFER, @@ -40196,7 +39913,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1430 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" + // Pos:1420 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" { .Instruction = ND_INS_MOVHPD, .Category = ND_CAT_DATAXFER, @@ -40223,7 +39940,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1431 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" + // Pos:1421 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" { .Instruction = ND_INS_MOVHPD, .Category = ND_CAT_DATAXFER, @@ -40250,7 +39967,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1432 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" + // Pos:1422 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" { .Instruction = ND_INS_MOVHPS, .Category = ND_CAT_DATAXFER, @@ -40277,7 +39994,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1433 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" + // Pos:1423 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" { .Instruction = ND_INS_MOVHPS, .Category = ND_CAT_DATAXFER, @@ -40304,7 +40021,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1434 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" + // Pos:1424 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" { .Instruction = ND_INS_MOVLHPS, .Category = ND_CAT_DATAXFER, @@ -40331,7 +40048,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1435 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" + // Pos:1425 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" { .Instruction = ND_INS_MOVLPD, .Category = ND_CAT_DATAXFER, @@ -40358,7 +40075,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1436 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" + // Pos:1426 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" { .Instruction = ND_INS_MOVLPD, .Category = ND_CAT_DATAXFER, @@ -40385,7 +40102,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1437 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" + // Pos:1427 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" { .Instruction = ND_INS_MOVLPS, .Category = ND_CAT_DATAXFER, @@ -40412,7 +40129,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1438 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" + // Pos:1428 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" { .Instruction = ND_INS_MOVMSKPD, .Category = ND_CAT_DATAXFER, @@ -40439,7 +40156,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1439 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" + // Pos:1429 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" { .Instruction = ND_INS_MOVMSKPS, .Category = ND_CAT_DATAXFER, @@ -40466,7 +40183,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1440 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" + // Pos:1430 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" { .Instruction = ND_INS_MOVNTDQ, .Category = ND_CAT_DATAXFER, @@ -40493,7 +40210,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1441 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" + // Pos:1431 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" { .Instruction = ND_INS_MOVNTDQA, .Category = ND_CAT_SSE, @@ -40520,7 +40237,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1442 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" + // Pos:1432 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" { .Instruction = ND_INS_MOVNTI, .Category = ND_CAT_DATAXFER, @@ -40547,7 +40264,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1443 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" + // Pos:1433 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" { .Instruction = ND_INS_MOVNTPD, .Category = ND_CAT_DATAXFER, @@ -40574,7 +40291,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1444 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" + // Pos:1434 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" { .Instruction = ND_INS_MOVNTPS, .Category = ND_CAT_DATAXFER, @@ -40601,7 +40318,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1445 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" + // Pos:1435 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" { .Instruction = ND_INS_MOVNTQ, .Category = ND_CAT_DATAXFER, @@ -40628,7 +40345,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1446 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" + // Pos:1436 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" { .Instruction = ND_INS_MOVNTSD, .Category = ND_CAT_DATAXFER, @@ -40655,7 +40372,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1447 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" + // Pos:1437 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" { .Instruction = ND_INS_MOVNTSS, .Category = ND_CAT_DATAXFER, @@ -40682,7 +40399,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1448 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" + // Pos:1438 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40709,7 +40426,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1449 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" + // Pos:1439 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40736,7 +40453,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1450 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" + // Pos:1440 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40763,7 +40480,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1451 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" + // Pos:1441 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40790,7 +40507,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1452 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" + // Pos:1442 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40817,7 +40534,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1453 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" + // Pos:1443 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40844,7 +40561,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1454 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" + // Pos:1444 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40871,7 +40588,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1455 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" + // Pos:1445 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" { .Instruction = ND_INS_MOVQ, .Category = ND_CAT_DATAXFER, @@ -40898,7 +40615,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1456 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" + // Pos:1446 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" { .Instruction = ND_INS_MOVQ2DQ, .Category = ND_CAT_DATAXFER, @@ -40925,7 +40642,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1457 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + // Pos:1447 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -40955,7 +40672,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1458 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + // Pos:1448 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -40986,7 +40703,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1459 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + // Pos:1449 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -41016,7 +40733,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1460 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + // Pos:1450 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -41047,7 +40764,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1461 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + // Pos:1451 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVSD, .Category = ND_CAT_DATAXFER, @@ -41074,7 +40791,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1462 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + // Pos:1452 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVSD, .Category = ND_CAT_DATAXFER, @@ -41101,7 +40818,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1463 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + // Pos:1453 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" { .Instruction = ND_INS_MOVSHDUP, .Category = ND_CAT_DATAXFER, @@ -41128,7 +40845,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1464 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + // Pos:1454 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" { .Instruction = ND_INS_MOVSLDUP, .Category = ND_CAT_DATAXFER, @@ -41155,7 +40872,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1465 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + // Pos:1455 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -41185,7 +40902,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1466 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + // Pos:1456 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -41216,7 +40933,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1467 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + // Pos:1457 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVSS, .Category = ND_CAT_DATAXFER, @@ -41243,7 +40960,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1468 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + // Pos:1458 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVSS, .Category = ND_CAT_DATAXFER, @@ -41270,7 +40987,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1469 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + // Pos:1459 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -41300,7 +41017,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1470 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + // Pos:1460 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" { .Instruction = ND_INS_MOVS, .Category = ND_CAT_STRINGOP, @@ -41331,7 +41048,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1471 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + // Pos:1461 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" { .Instruction = ND_INS_MOVSX, .Category = ND_CAT_DATAXFER, @@ -41358,7 +41075,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1472 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + // Pos:1462 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" { .Instruction = ND_INS_MOVSX, .Category = ND_CAT_DATAXFER, @@ -41385,7 +41102,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1473 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM" + // Pos:1463 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM" { .Instruction = ND_INS_MOVSXD, .Category = ND_CAT_DATAXFER, @@ -41412,7 +41129,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1474 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + // Pos:1464 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVUPD, .Category = ND_CAT_DATAXFER, @@ -41439,7 +41156,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1475 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + // Pos:1465 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVUPD, .Category = ND_CAT_DATAXFER, @@ -41466,7 +41183,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1476 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + // Pos:1466 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" { .Instruction = ND_INS_MOVUPS, .Category = ND_CAT_DATAXFER, @@ -41493,7 +41210,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1477 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + // Pos:1467 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" { .Instruction = ND_INS_MOVUPS, .Category = ND_CAT_DATAXFER, @@ -41520,7 +41237,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1478 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + // Pos:1468 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" { .Instruction = ND_INS_MOVZX, .Category = ND_CAT_DATAXFER, @@ -41547,7 +41264,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1479 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + // Pos:1469 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" { .Instruction = ND_INS_MOVZX, .Category = ND_CAT_DATAXFER, @@ -41574,7 +41291,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1480 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + // Pos:1470 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" { .Instruction = ND_INS_MPSADBW, .Category = ND_CAT_SSE, @@ -41602,7 +41319,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1481 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M" + // Pos:1471 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41631,7 +41348,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1482 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M" + // Pos:1472 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41660,7 +41377,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1483 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M" + // Pos:1473 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41689,7 +41406,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1484 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M" + // Pos:1474 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41717,7 +41434,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1485 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M" + // Pos:1475 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41745,7 +41462,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1486 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M" + // Pos:1476 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41773,7 +41490,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1487 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + // Pos:1477 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41802,7 +41519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1488 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + // Pos:1478 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" { .Instruction = ND_INS_MUL, .Category = ND_CAT_ARITH, @@ -41831,7 +41548,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1489 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + // Pos:1479 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULPD, .Category = ND_CAT_SSE, @@ -41858,7 +41575,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1490 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + // Pos:1480 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULPS, .Category = ND_CAT_SSE, @@ -41885,7 +41602,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1491 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + // Pos:1481 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULSD, .Category = ND_CAT_SSE, @@ -41912,7 +41629,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1492 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + // Pos:1482 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" { .Instruction = ND_INS_MULSS, .Category = ND_CAT_SSE, @@ -41939,7 +41656,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1493 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM" + // Pos:1483 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM" { .Instruction = ND_INS_MULX, .Category = ND_CAT_BMI2, @@ -41968,7 +41685,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1494 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + // Pos:1484 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" { .Instruction = ND_INS_MULX, .Category = ND_CAT_BMI2, @@ -41997,7 +41714,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1495 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + // Pos:1485 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" { .Instruction = ND_INS_MWAIT, .Category = ND_CAT_MISC, @@ -42024,7 +41741,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1496 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + // Pos:1486 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" { .Instruction = ND_INS_MWAITX, .Category = ND_CAT_SYSTEM, @@ -42052,7 +41769,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1497 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M" + // Pos:1487 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42079,7 +41796,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1498 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M" + // Pos:1488 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42106,7 +41823,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1499 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M" + // Pos:1489 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42133,7 +41850,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1500 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M" + // Pos:1490 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42159,7 +41876,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1501 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M" + // Pos:1491 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42185,7 +41902,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1502 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M" + // Pos:1492 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42211,7 +41928,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1503 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM" + // Pos:1493 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42239,7 +41956,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1504 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM" + // Pos:1494 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42267,7 +41984,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1505 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM" + // Pos:1495 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42295,7 +42012,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1506 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM" + // Pos:1496 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42322,7 +42039,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1507 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM" + // Pos:1497 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42349,7 +42066,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1508 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM" + // Pos:1498 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42376,7 +42093,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1509 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + // Pos:1499 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42403,7 +42120,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1510 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + // Pos:1500 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" { .Instruction = ND_INS_NEG, .Category = ND_CAT_LOGIC, @@ -42430,7 +42147,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1511 Instruction:"NOP" Encoding:"0x90"/"" + // Pos:1501 Instruction:"NOP" Encoding:"0x90"/"" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42456,7 +42173,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1512 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + // Pos:1502 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42483,7 +42200,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1513 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + // Pos:1503 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42510,7 +42227,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1514 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + // Pos:1504 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42537,7 +42254,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1515 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + // Pos:1505 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42564,7 +42281,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1516 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + // Pos:1506 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42591,7 +42308,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1517 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + // Pos:1507 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42618,7 +42335,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1518 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + // Pos:1508 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42645,7 +42362,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1519 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + // Pos:1509 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_NOP, @@ -42672,7 +42389,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1520 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + // Pos:1510 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42698,7 +42415,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1521 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + // Pos:1511 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42724,7 +42441,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1522 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + // Pos:1512 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42750,7 +42467,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1523 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + // Pos:1513 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42776,7 +42493,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1524 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + // Pos:1514 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42802,7 +42519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1525 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + // Pos:1515 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42828,7 +42545,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1526 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + // Pos:1516 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42854,7 +42571,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1527 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + // Pos:1517 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42880,7 +42597,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1528 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + // Pos:1518 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42906,7 +42623,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1529 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" + // Pos:1519 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42932,7 +42649,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1530 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" + // Pos:1520 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42958,7 +42675,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1531 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" + // Pos:1521 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -42984,7 +42701,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1532 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" + // Pos:1522 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43010,7 +42727,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1533 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" + // Pos:1523 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43036,7 +42753,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1534 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" + // Pos:1524 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43062,7 +42779,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1535 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" + // Pos:1525 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43088,7 +42805,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1536 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" + // Pos:1526 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43114,7 +42831,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1537 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" + // Pos:1527 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43140,7 +42857,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1538 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" + // Pos:1528 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43166,7 +42883,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1539 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" + // Pos:1529 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43193,7 +42910,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1540 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" + // Pos:1530 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43220,7 +42937,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" + // Pos:1531 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43247,7 +42964,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + // Pos:1532 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43274,7 +42991,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" + // Pos:1533 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43301,7 +43018,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + // Pos:1534 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43328,7 +43045,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1545 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM" + // Pos:1535 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43355,7 +43072,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1546 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM" + // Pos:1536 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43382,7 +43099,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1547 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" + // Pos:1537 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43409,7 +43126,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" + // Pos:1538 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43436,7 +43153,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1549 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" + // Pos:1539 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43463,7 +43180,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1550 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" + // Pos:1540 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43490,7 +43207,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1551 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" + // Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43517,7 +43234,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1552 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" + // Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43544,7 +43261,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1553 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" + // Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43571,7 +43288,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1554 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" + // Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43598,7 +43315,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1555 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" + // Pos:1545 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43625,7 +43342,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1556 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" + // Pos:1546 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43652,7 +43369,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1557 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" + // Pos:1547 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43679,7 +43396,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1558 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" + // Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43706,7 +43423,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR" + // Pos:1549 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43733,7 +43450,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" + // Pos:1550 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43760,7 +43477,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR" + // Pos:1551 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43787,7 +43504,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" + // Pos:1552 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43814,7 +43531,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR" + // Pos:1553 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43841,7 +43558,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" + // Pos:1554 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43868,7 +43585,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1565 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR" + // Pos:1555 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43895,7 +43612,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" + // Pos:1556 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43922,7 +43639,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1567 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR" + // Pos:1557 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43949,7 +43666,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" + // Pos:1558 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -43976,7 +43693,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1569 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR" + // Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44003,7 +43720,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" + // Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44030,7 +43747,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1571 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR" + // Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44057,7 +43774,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1572 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" + // Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44084,7 +43801,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1573 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR" + // Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44111,7 +43828,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1574 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" + // Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44138,7 +43855,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1575 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" + // Pos:1565 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44165,7 +43882,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1576 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" + // Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44192,7 +43909,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1577 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" + // Pos:1567 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44219,7 +43936,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1578 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" + // Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44246,7 +43963,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1579 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" + // Pos:1569 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44273,7 +43990,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1580 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" + // Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44300,7 +44017,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1581 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" + // Pos:1571 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" { .Instruction = ND_INS_NOP, .Category = ND_CAT_WIDENOP, @@ -44327,7 +44044,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1582 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M" + // Pos:1572 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44353,7 +44070,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1583 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M" + // Pos:1573 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44379,7 +44096,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1584 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M" + // Pos:1574 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44405,7 +44122,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1585 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM" + // Pos:1575 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44432,7 +44149,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1586 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM" + // Pos:1576 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44459,7 +44176,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1587 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM" + // Pos:1577 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44486,7 +44203,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1588 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + // Pos:1578 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44512,7 +44229,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1589 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + // Pos:1579 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" { .Instruction = ND_INS_NOT, .Category = ND_CAT_LOGIC, @@ -44538,7 +44255,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1590 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR" + // Pos:1580 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44566,7 +44283,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1591 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR" + // Pos:1581 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44594,7 +44311,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1592 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR" + // Pos:1582 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44622,7 +44339,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1593 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM" + // Pos:1583 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44650,7 +44367,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1594 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM" + // Pos:1584 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44678,7 +44395,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1595 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM" + // Pos:1585 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44706,7 +44423,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1596 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI" + // Pos:1586 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44734,7 +44451,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1597 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI" + // Pos:1587 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44762,7 +44479,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1598 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI" + // Pos:1588 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44790,7 +44507,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1599 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI" + // Pos:1589 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44818,7 +44535,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1600 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI" + // Pos:1590 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44846,7 +44563,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1601 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR" + // Pos:1591 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44873,7 +44590,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1602 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR" + // Pos:1592 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44900,7 +44617,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1603 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR" + // Pos:1593 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44927,7 +44644,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1604 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM" + // Pos:1594 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44954,7 +44671,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1605 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM" + // Pos:1595 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -44981,7 +44698,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1606 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM" + // Pos:1596 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45008,7 +44725,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1607 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI" + // Pos:1597 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45035,7 +44752,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1608 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI" + // Pos:1598 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45062,7 +44779,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1609 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI" + // Pos:1599 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45089,7 +44806,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1610 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI" + // Pos:1600 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45116,7 +44833,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1611 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI" + // Pos:1601 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45143,7 +44860,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1612 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR" + // Pos:1602 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45172,7 +44889,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1613 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR" + // Pos:1603 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45201,7 +44918,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1614 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR" + // Pos:1604 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45230,7 +44947,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1615 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM" + // Pos:1605 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45259,7 +44976,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1616 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM" + // Pos:1606 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45288,7 +45005,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1617 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM" + // Pos:1607 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45317,7 +45034,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1618 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI" + // Pos:1608 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45346,7 +45063,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1619 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI" + // Pos:1609 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45375,7 +45092,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1620 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI" + // Pos:1610 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45404,7 +45121,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1621 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI" + // Pos:1611 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45433,7 +45150,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1622 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI" + // Pos:1612 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45462,7 +45179,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1623 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR" + // Pos:1613 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45490,7 +45207,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1624 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR" + // Pos:1614 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45518,7 +45235,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1625 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR" + // Pos:1615 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45546,7 +45263,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1626 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM" + // Pos:1616 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45574,7 +45291,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1627 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM" + // Pos:1617 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45602,7 +45319,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1628 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM" + // Pos:1618 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45630,7 +45347,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1629 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI" + // Pos:1619 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45658,7 +45375,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1630 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI" + // Pos:1620 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45686,7 +45403,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1631 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI" + // Pos:1621 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45714,7 +45431,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1632 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI" + // Pos:1622 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45742,7 +45459,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1633 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI" + // Pos:1623 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45770,7 +45487,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1634 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + // Pos:1624 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45798,7 +45515,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1635 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + // Pos:1625 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45826,7 +45543,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1636 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + // Pos:1626 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45854,7 +45571,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1637 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + // Pos:1627 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45882,7 +45599,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1638 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + // Pos:1628 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45910,7 +45627,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1639 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + // Pos:1629 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45938,7 +45655,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1640 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + // Pos:1630 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45966,7 +45683,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1641 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + // Pos:1631 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -45994,7 +45711,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1642 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" + // Pos:1632 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -46022,7 +45739,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1643 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + // Pos:1633 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" { .Instruction = ND_INS_OR, .Category = ND_CAT_LOGIC, @@ -46050,7 +45767,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1644 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + // Pos:1634 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" { .Instruction = ND_INS_ORPD, .Category = ND_CAT_LOGICAL_FP, @@ -46077,7 +45794,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1645 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + // Pos:1635 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" { .Instruction = ND_INS_ORPS, .Category = ND_CAT_LOGICAL_FP, @@ -46104,7 +45821,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1646 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + // Pos:1636 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, @@ -46132,7 +45849,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1647 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + // Pos:1637 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, @@ -46160,7 +45877,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1648 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + // Pos:1638 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, @@ -46188,7 +45905,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1649 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + // Pos:1639 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" { .Instruction = ND_INS_OUT, .Category = ND_CAT_IO, @@ -46216,7 +45933,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1650 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + // Pos:1640 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, @@ -46245,7 +45962,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1651 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + // Pos:1641 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, @@ -46275,7 +45992,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1652 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + // Pos:1642 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, @@ -46304,7 +46021,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1653 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + // Pos:1643 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, @@ -46334,7 +46051,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1654 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + // Pos:1644 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, @@ -46363,7 +46080,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1655 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + // Pos:1645 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" { .Instruction = ND_INS_OUTS, .Category = ND_CAT_IOSTRINGOP, @@ -46393,7 +46110,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1656 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + // Pos:1646 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" { .Instruction = ND_INS_PABSB, .Category = ND_CAT_MMX, @@ -46420,7 +46137,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1657 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + // Pos:1647 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" { .Instruction = ND_INS_PABSB, .Category = ND_CAT_SSE, @@ -46447,7 +46164,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1658 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + // Pos:1648 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" { .Instruction = ND_INS_PABSD, .Category = ND_CAT_MMX, @@ -46474,7 +46191,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1659 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + // Pos:1649 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" { .Instruction = ND_INS_PABSD, .Category = ND_CAT_SSE, @@ -46501,7 +46218,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1660 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + // Pos:1650 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" { .Instruction = ND_INS_PABSW, .Category = ND_CAT_MMX, @@ -46528,7 +46245,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1661 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + // Pos:1651 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" { .Instruction = ND_INS_PABSW, .Category = ND_CAT_SSE, @@ -46555,7 +46272,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1662 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + // Pos:1652 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" { .Instruction = ND_INS_PACKSSDW, .Category = ND_CAT_MMX, @@ -46582,7 +46299,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1663 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + // Pos:1653 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" { .Instruction = ND_INS_PACKSSDW, .Category = ND_CAT_SSE, @@ -46609,7 +46326,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1664 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + // Pos:1654 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" { .Instruction = ND_INS_PACKSSWB, .Category = ND_CAT_MMX, @@ -46636,7 +46353,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1665 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + // Pos:1655 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" { .Instruction = ND_INS_PACKSSWB, .Category = ND_CAT_SSE, @@ -46663,7 +46380,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1666 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + // Pos:1656 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" { .Instruction = ND_INS_PACKUSDW, .Category = ND_CAT_SSE, @@ -46690,7 +46407,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1667 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + // Pos:1657 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" { .Instruction = ND_INS_PACKUSWB, .Category = ND_CAT_MMX, @@ -46717,7 +46434,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1668 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + // Pos:1658 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" { .Instruction = ND_INS_PACKUSWB, .Category = ND_CAT_SSE, @@ -46744,7 +46461,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1669 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + // Pos:1659 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" { .Instruction = ND_INS_PADDB, .Category = ND_CAT_MMX, @@ -46771,7 +46488,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1670 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + // Pos:1660 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" { .Instruction = ND_INS_PADDB, .Category = ND_CAT_SSE, @@ -46798,7 +46515,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1671 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + // Pos:1661 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" { .Instruction = ND_INS_PADDD, .Category = ND_CAT_MMX, @@ -46825,7 +46542,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1672 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + // Pos:1662 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" { .Instruction = ND_INS_PADDD, .Category = ND_CAT_SSE, @@ -46852,7 +46569,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1673 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + // Pos:1663 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" { .Instruction = ND_INS_PADDQ, .Category = ND_CAT_MMX, @@ -46879,7 +46596,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1674 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + // Pos:1664 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" { .Instruction = ND_INS_PADDQ, .Category = ND_CAT_SSE, @@ -46906,7 +46623,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1675 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + // Pos:1665 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" { .Instruction = ND_INS_PADDSB, .Category = ND_CAT_MMX, @@ -46933,7 +46650,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1676 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + // Pos:1666 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" { .Instruction = ND_INS_PADDSB, .Category = ND_CAT_SSE, @@ -46960,7 +46677,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1677 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + // Pos:1667 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" { .Instruction = ND_INS_PADDSW, .Category = ND_CAT_MMX, @@ -46987,7 +46704,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1678 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + // Pos:1668 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" { .Instruction = ND_INS_PADDSW, .Category = ND_CAT_SSE, @@ -47014,7 +46731,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1679 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + // Pos:1669 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" { .Instruction = ND_INS_PADDUSB, .Category = ND_CAT_MMX, @@ -47041,7 +46758,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1680 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + // Pos:1670 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" { .Instruction = ND_INS_PADDUSB, .Category = ND_CAT_SSE, @@ -47068,7 +46785,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1681 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + // Pos:1671 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" { .Instruction = ND_INS_PADDUSW, .Category = ND_CAT_MMX, @@ -47095,7 +46812,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1682 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + // Pos:1672 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" { .Instruction = ND_INS_PADDUSW, .Category = ND_CAT_SSE, @@ -47122,7 +46839,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1683 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + // Pos:1673 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" { .Instruction = ND_INS_PADDW, .Category = ND_CAT_MMX, @@ -47149,7 +46866,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1684 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + // Pos:1674 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" { .Instruction = ND_INS_PADDW, .Category = ND_CAT_SSE, @@ -47176,7 +46893,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1685 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:1675 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" { .Instruction = ND_INS_PALIGNR, .Category = ND_CAT_MMX, @@ -47204,7 +46921,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1686 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + // Pos:1676 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" { .Instruction = ND_INS_PALIGNR, .Category = ND_CAT_SSE, @@ -47232,7 +46949,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1687 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + // Pos:1677 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" { .Instruction = ND_INS_PAND, .Category = ND_CAT_LOGICAL, @@ -47259,7 +46976,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1688 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + // Pos:1678 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" { .Instruction = ND_INS_PAND, .Category = ND_CAT_LOGICAL, @@ -47286,7 +47003,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1689 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + // Pos:1679 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" { .Instruction = ND_INS_PANDN, .Category = ND_CAT_LOGICAL, @@ -47313,7 +47030,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1690 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + // Pos:1680 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" { .Instruction = ND_INS_PANDN, .Category = ND_CAT_LOGICAL, @@ -47340,7 +47057,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1691 Instruction:"PAUSE" Encoding:"repz 0x90"/"" + // Pos:1681 Instruction:"PAUSE" Encoding:"repz 0x90"/"" { .Instruction = ND_INS_PAUSE, .Category = ND_CAT_MISC, @@ -47366,7 +47083,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1692 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + // Pos:1682 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" { .Instruction = ND_INS_PAVGB, .Category = ND_CAT_MMX, @@ -47393,7 +47110,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1693 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + // Pos:1683 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" { .Instruction = ND_INS_PAVGB, .Category = ND_CAT_SSE, @@ -47420,7 +47137,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1694 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + // Pos:1684 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" { .Instruction = ND_INS_PAVGUSB, .Category = ND_CAT_3DNOW, @@ -47447,7 +47164,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1695 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + // Pos:1685 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" { .Instruction = ND_INS_PAVGW, .Category = ND_CAT_MMX, @@ -47474,7 +47191,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1696 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + // Pos:1686 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" { .Instruction = ND_INS_PAVGW, .Category = ND_CAT_SSE, @@ -47501,7 +47218,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1697 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + // Pos:1687 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" { .Instruction = ND_INS_PBLENDVB, .Category = ND_CAT_SSE, @@ -47529,7 +47246,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1698 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + // Pos:1688 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" { .Instruction = ND_INS_PBLENDW, .Category = ND_CAT_SSE, @@ -47557,7 +47274,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1699 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" + // Pos:1689 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" { .Instruction = ND_INS_PBNDKB, .Category = ND_CAT_SYSTEM, @@ -47586,7 +47303,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1700 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + // Pos:1690 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" { .Instruction = ND_INS_PCLMULQDQ, .Category = ND_CAT_PCLMULQDQ, @@ -47614,7 +47331,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1701 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + // Pos:1691 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" { .Instruction = ND_INS_PCMPEQB, .Category = ND_CAT_MMX, @@ -47641,7 +47358,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1702 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + // Pos:1692 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" { .Instruction = ND_INS_PCMPEQB, .Category = ND_CAT_SSE, @@ -47668,7 +47385,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1703 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + // Pos:1693 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" { .Instruction = ND_INS_PCMPEQD, .Category = ND_CAT_MMX, @@ -47695,7 +47412,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1704 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + // Pos:1694 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" { .Instruction = ND_INS_PCMPEQD, .Category = ND_CAT_SSE, @@ -47722,7 +47439,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1705 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + // Pos:1695 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" { .Instruction = ND_INS_PCMPEQQ, .Category = ND_CAT_SSE, @@ -47749,7 +47466,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1706 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + // Pos:1696 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" { .Instruction = ND_INS_PCMPEQW, .Category = ND_CAT_MMX, @@ -47776,7 +47493,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1707 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + // Pos:1697 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" { .Instruction = ND_INS_PCMPEQW, .Category = ND_CAT_SSE, @@ -47803,7 +47520,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1708 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + // Pos:1698 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" { .Instruction = ND_INS_PCMPESTRI, .Category = ND_CAT_SSE, @@ -47835,7 +47552,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1709 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + // Pos:1699 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" { .Instruction = ND_INS_PCMPESTRM, .Category = ND_CAT_SSE, @@ -47867,7 +47584,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1710 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + // Pos:1700 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" { .Instruction = ND_INS_PCMPGTB, .Category = ND_CAT_MMX, @@ -47894,7 +47611,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1711 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + // Pos:1701 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" { .Instruction = ND_INS_PCMPGTB, .Category = ND_CAT_SSE, @@ -47921,7 +47638,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1712 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + // Pos:1702 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" { .Instruction = ND_INS_PCMPGTD, .Category = ND_CAT_MMX, @@ -47948,7 +47665,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1713 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + // Pos:1703 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" { .Instruction = ND_INS_PCMPGTD, .Category = ND_CAT_SSE, @@ -47975,7 +47692,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1714 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + // Pos:1704 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" { .Instruction = ND_INS_PCMPGTQ, .Category = ND_CAT_SSE, @@ -48002,7 +47719,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1715 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + // Pos:1705 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" { .Instruction = ND_INS_PCMPGTW, .Category = ND_CAT_MMX, @@ -48029,7 +47746,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1716 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + // Pos:1706 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" { .Instruction = ND_INS_PCMPGTW, .Category = ND_CAT_SSE, @@ -48056,7 +47773,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1717 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + // Pos:1707 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" { .Instruction = ND_INS_PCMPISTRI, .Category = ND_CAT_SSE, @@ -48086,7 +47803,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1718 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + // Pos:1708 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" { .Instruction = ND_INS_PCMPISTRM, .Category = ND_CAT_SSE, @@ -48116,7 +47833,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1719 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + // Pos:1709 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" { .Instruction = ND_INS_PCONFIG, .Category = ND_CAT_PCONFIG, @@ -48146,7 +47863,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1720 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM" + // Pos:1710 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM" { .Instruction = ND_INS_PDEP, .Category = ND_CAT_BMI2, @@ -48174,7 +47891,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1721 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + // Pos:1711 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" { .Instruction = ND_INS_PDEP, .Category = ND_CAT_BMI2, @@ -48202,7 +47919,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1722 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM" + // Pos:1712 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM" { .Instruction = ND_INS_PEXT, .Category = ND_CAT_BMI2, @@ -48230,7 +47947,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1723 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + // Pos:1713 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" { .Instruction = ND_INS_PEXT, .Category = ND_CAT_BMI2, @@ -48258,7 +47975,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1724 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + // Pos:1714 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRB, .Category = ND_CAT_SSE, @@ -48286,7 +48003,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1725 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + // Pos:1715 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRB, .Category = ND_CAT_SSE, @@ -48314,7 +48031,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1726 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" + // Pos:1716 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRD, .Category = ND_CAT_SSE, @@ -48342,7 +48059,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1727 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" + // Pos:1717 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRD, .Category = ND_CAT_SSE, @@ -48370,7 +48087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1728 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" + // Pos:1718 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRQ, .Category = ND_CAT_SSE, @@ -48398,7 +48115,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1729 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" + // Pos:1719 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRQ, .Category = ND_CAT_SSE, @@ -48426,7 +48143,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1730 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:1720 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_MMX, @@ -48454,7 +48171,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1731 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" + // Pos:1721 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_SSE, @@ -48482,7 +48199,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1732 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" + // Pos:1722 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_SSE, @@ -48510,7 +48227,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1733 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + // Pos:1723 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" { .Instruction = ND_INS_PEXTRW, .Category = ND_CAT_SSE, @@ -48538,7 +48255,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1734 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + // Pos:1724 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" { .Instruction = ND_INS_PF2ID, .Category = ND_CAT_3DNOW, @@ -48565,7 +48282,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1735 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + // Pos:1725 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" { .Instruction = ND_INS_PF2IW, .Category = ND_CAT_3DNOW, @@ -48592,7 +48309,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1736 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + // Pos:1726 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" { .Instruction = ND_INS_PFACC, .Category = ND_CAT_3DNOW, @@ -48619,7 +48336,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1737 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + // Pos:1727 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" { .Instruction = ND_INS_PFADD, .Category = ND_CAT_3DNOW, @@ -48646,7 +48363,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1738 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + // Pos:1728 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" { .Instruction = ND_INS_PFCMPEQ, .Category = ND_CAT_3DNOW, @@ -48673,7 +48390,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1739 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + // Pos:1729 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" { .Instruction = ND_INS_PFCMPGE, .Category = ND_CAT_3DNOW, @@ -48700,7 +48417,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1740 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + // Pos:1730 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" { .Instruction = ND_INS_PFCMPGT, .Category = ND_CAT_3DNOW, @@ -48727,7 +48444,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1741 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + // Pos:1731 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" { .Instruction = ND_INS_PFMAX, .Category = ND_CAT_3DNOW, @@ -48754,7 +48471,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1742 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + // Pos:1732 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" { .Instruction = ND_INS_PFMIN, .Category = ND_CAT_3DNOW, @@ -48781,7 +48498,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1743 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + // Pos:1733 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" { .Instruction = ND_INS_PFMUL, .Category = ND_CAT_3DNOW, @@ -48808,7 +48525,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1744 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + // Pos:1734 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" { .Instruction = ND_INS_PFNACC, .Category = ND_CAT_3DNOW, @@ -48835,7 +48552,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1745 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + // Pos:1735 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" { .Instruction = ND_INS_PFPNACC, .Category = ND_CAT_3DNOW, @@ -48862,7 +48579,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1746 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + // Pos:1736 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" { .Instruction = ND_INS_PFRCP, .Category = ND_CAT_3DNOW, @@ -48889,7 +48606,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1747 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + // Pos:1737 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" { .Instruction = ND_INS_PFRCPIT1, .Category = ND_CAT_3DNOW, @@ -48916,7 +48633,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1748 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + // Pos:1738 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" { .Instruction = ND_INS_PFRCPIT2, .Category = ND_CAT_3DNOW, @@ -48943,7 +48660,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1749 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + // Pos:1739 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" { .Instruction = ND_INS_PFRCPV, .Category = ND_CAT_3DNOW, @@ -48970,7 +48687,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1750 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + // Pos:1740 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" { .Instruction = ND_INS_PFRSQIT1, .Category = ND_CAT_3DNOW, @@ -48997,7 +48714,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1751 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + // Pos:1741 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" { .Instruction = ND_INS_PFRSQRT, .Category = ND_CAT_3DNOW, @@ -49024,7 +48741,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1752 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + // Pos:1742 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" { .Instruction = ND_INS_PFRSQRTV, .Category = ND_CAT_3DNOW, @@ -49051,7 +48768,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1753 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + // Pos:1743 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" { .Instruction = ND_INS_PFSUB, .Category = ND_CAT_3DNOW, @@ -49078,7 +48795,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1754 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + // Pos:1744 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" { .Instruction = ND_INS_PFSUBR, .Category = ND_CAT_3DNOW, @@ -49105,7 +48822,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1755 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + // Pos:1745 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" { .Instruction = ND_INS_PHADDD, .Category = ND_CAT_MMX, @@ -49132,7 +48849,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1756 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + // Pos:1746 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" { .Instruction = ND_INS_PHADDD, .Category = ND_CAT_SSE, @@ -49159,7 +48876,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1757 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + // Pos:1747 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" { .Instruction = ND_INS_PHADDSW, .Category = ND_CAT_MMX, @@ -49186,7 +48903,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1758 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + // Pos:1748 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" { .Instruction = ND_INS_PHADDSW, .Category = ND_CAT_SSE, @@ -49213,7 +48930,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1759 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + // Pos:1749 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" { .Instruction = ND_INS_PHADDW, .Category = ND_CAT_MMX, @@ -49240,7 +48957,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1760 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + // Pos:1750 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" { .Instruction = ND_INS_PHADDW, .Category = ND_CAT_SSE, @@ -49267,7 +48984,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1761 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + // Pos:1751 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" { .Instruction = ND_INS_PHMINPOSUW, .Category = ND_CAT_SSE, @@ -49294,7 +49011,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1762 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + // Pos:1752 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" { .Instruction = ND_INS_PHSUBD, .Category = ND_CAT_MMX, @@ -49321,7 +49038,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1763 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + // Pos:1753 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" { .Instruction = ND_INS_PHSUBD, .Category = ND_CAT_SSE, @@ -49348,7 +49065,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1764 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + // Pos:1754 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" { .Instruction = ND_INS_PHSUBSW, .Category = ND_CAT_MMX, @@ -49375,7 +49092,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1765 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + // Pos:1755 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" { .Instruction = ND_INS_PHSUBSW, .Category = ND_CAT_SSE, @@ -49402,7 +49119,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1766 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + // Pos:1756 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" { .Instruction = ND_INS_PHSUBW, .Category = ND_CAT_MMX, @@ -49429,7 +49146,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1767 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + // Pos:1757 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" { .Instruction = ND_INS_PHSUBW, .Category = ND_CAT_SSE, @@ -49456,7 +49173,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1768 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + // Pos:1758 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" { .Instruction = ND_INS_PI2FD, .Category = ND_CAT_3DNOW, @@ -49483,7 +49200,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1769 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + // Pos:1759 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" { .Instruction = ND_INS_PI2FW, .Category = ND_CAT_3DNOW, @@ -49510,7 +49227,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1770 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + // Pos:1760 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" { .Instruction = ND_INS_PINSRB, .Category = ND_CAT_SSE, @@ -49538,7 +49255,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1771 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + // Pos:1761 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" { .Instruction = ND_INS_PINSRB, .Category = ND_CAT_SSE, @@ -49566,7 +49283,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1772 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:1762 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { .Instruction = ND_INS_PINSRD, .Category = ND_CAT_SSE, @@ -49594,7 +49311,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1773 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + // Pos:1763 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { .Instruction = ND_INS_PINSRQ, .Category = ND_CAT_SSE, @@ -49622,7 +49339,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1774 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:1764 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_MMX, @@ -49650,7 +49367,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1775 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:1765 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_MMX, @@ -49678,7 +49395,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1776 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + // Pos:1766 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_SSE, @@ -49706,7 +49423,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1777 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + // Pos:1767 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" { .Instruction = ND_INS_PINSRW, .Category = ND_CAT_SSE, @@ -49734,7 +49451,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1778 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + // Pos:1768 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" { .Instruction = ND_INS_PMADDUBSW, .Category = ND_CAT_MMX, @@ -49761,7 +49478,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1779 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + // Pos:1769 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" { .Instruction = ND_INS_PMADDUBSW, .Category = ND_CAT_SSE, @@ -49788,7 +49505,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1780 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + // Pos:1770 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" { .Instruction = ND_INS_PMADDWD, .Category = ND_CAT_MMX, @@ -49815,7 +49532,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1781 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + // Pos:1771 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" { .Instruction = ND_INS_PMADDWD, .Category = ND_CAT_SSE, @@ -49842,7 +49559,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1782 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + // Pos:1772 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" { .Instruction = ND_INS_PMAXSB, .Category = ND_CAT_SSE, @@ -49869,7 +49586,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1783 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + // Pos:1773 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" { .Instruction = ND_INS_PMAXSD, .Category = ND_CAT_SSE, @@ -49896,7 +49613,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1784 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + // Pos:1774 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" { .Instruction = ND_INS_PMAXSW, .Category = ND_CAT_MMX, @@ -49923,7 +49640,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1785 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + // Pos:1775 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" { .Instruction = ND_INS_PMAXSW, .Category = ND_CAT_SSE, @@ -49950,7 +49667,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1786 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + // Pos:1776 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" { .Instruction = ND_INS_PMAXUB, .Category = ND_CAT_MMX, @@ -49977,7 +49694,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1787 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + // Pos:1777 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" { .Instruction = ND_INS_PMAXUB, .Category = ND_CAT_SSE, @@ -50004,7 +49721,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1788 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + // Pos:1778 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" { .Instruction = ND_INS_PMAXUD, .Category = ND_CAT_SSE, @@ -50031,7 +49748,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1789 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + // Pos:1779 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" { .Instruction = ND_INS_PMAXUW, .Category = ND_CAT_SSE, @@ -50058,7 +49775,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1790 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + // Pos:1780 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" { .Instruction = ND_INS_PMINSB, .Category = ND_CAT_SSE, @@ -50085,7 +49802,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1791 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + // Pos:1781 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" { .Instruction = ND_INS_PMINSD, .Category = ND_CAT_SSE, @@ -50112,7 +49829,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1792 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + // Pos:1782 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" { .Instruction = ND_INS_PMINSW, .Category = ND_CAT_MMX, @@ -50139,7 +49856,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1793 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + // Pos:1783 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" { .Instruction = ND_INS_PMINSW, .Category = ND_CAT_SSE, @@ -50166,7 +49883,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1794 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + // Pos:1784 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" { .Instruction = ND_INS_PMINUB, .Category = ND_CAT_MMX, @@ -50193,7 +49910,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1795 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + // Pos:1785 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" { .Instruction = ND_INS_PMINUB, .Category = ND_CAT_SSE, @@ -50220,7 +49937,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1796 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + // Pos:1786 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" { .Instruction = ND_INS_PMINUD, .Category = ND_CAT_SSE, @@ -50247,7 +49964,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1797 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + // Pos:1787 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" { .Instruction = ND_INS_PMINUW, .Category = ND_CAT_SSE, @@ -50274,7 +49991,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1798 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + // Pos:1788 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" { .Instruction = ND_INS_PMOVMSKB, .Category = ND_CAT_MMX, @@ -50301,7 +50018,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1799 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + // Pos:1789 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" { .Instruction = ND_INS_PMOVMSKB, .Category = ND_CAT_SSE, @@ -50328,7 +50045,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1800 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + // Pos:1790 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" { .Instruction = ND_INS_PMOVSXBD, .Category = ND_CAT_SSE, @@ -50355,7 +50072,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1801 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + // Pos:1791 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" { .Instruction = ND_INS_PMOVSXBQ, .Category = ND_CAT_SSE, @@ -50382,7 +50099,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1802 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + // Pos:1792 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" { .Instruction = ND_INS_PMOVSXBW, .Category = ND_CAT_SSE, @@ -50409,7 +50126,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1803 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + // Pos:1793 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" { .Instruction = ND_INS_PMOVSXDQ, .Category = ND_CAT_SSE, @@ -50436,7 +50153,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1804 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + // Pos:1794 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" { .Instruction = ND_INS_PMOVSXWD, .Category = ND_CAT_SSE, @@ -50463,7 +50180,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1805 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + // Pos:1795 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" { .Instruction = ND_INS_PMOVSXWQ, .Category = ND_CAT_SSE, @@ -50490,7 +50207,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1806 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + // Pos:1796 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" { .Instruction = ND_INS_PMOVZXBD, .Category = ND_CAT_SSE, @@ -50517,7 +50234,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1807 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + // Pos:1797 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" { .Instruction = ND_INS_PMOVZXBQ, .Category = ND_CAT_SSE, @@ -50544,7 +50261,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1808 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + // Pos:1798 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" { .Instruction = ND_INS_PMOVZXBW, .Category = ND_CAT_SSE, @@ -50571,7 +50288,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1809 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + // Pos:1799 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" { .Instruction = ND_INS_PMOVZXDQ, .Category = ND_CAT_SSE, @@ -50598,7 +50315,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1810 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + // Pos:1800 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" { .Instruction = ND_INS_PMOVZXWD, .Category = ND_CAT_SSE, @@ -50625,7 +50342,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1811 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + // Pos:1801 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" { .Instruction = ND_INS_PMOVZXWQ, .Category = ND_CAT_SSE, @@ -50652,7 +50369,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1812 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + // Pos:1802 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" { .Instruction = ND_INS_PMULDQ, .Category = ND_CAT_SSE, @@ -50679,7 +50396,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1813 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + // Pos:1803 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" { .Instruction = ND_INS_PMULHRSW, .Category = ND_CAT_MMX, @@ -50706,7 +50423,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1814 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + // Pos:1804 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" { .Instruction = ND_INS_PMULHRSW, .Category = ND_CAT_SSE, @@ -50733,7 +50450,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1815 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + // Pos:1805 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" { .Instruction = ND_INS_PMULHRW, .Category = ND_CAT_3DNOW, @@ -50760,7 +50477,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1816 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + // Pos:1806 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" { .Instruction = ND_INS_PMULHUW, .Category = ND_CAT_MMX, @@ -50787,7 +50504,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1817 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + // Pos:1807 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" { .Instruction = ND_INS_PMULHUW, .Category = ND_CAT_SSE, @@ -50814,7 +50531,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1818 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + // Pos:1808 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" { .Instruction = ND_INS_PMULHW, .Category = ND_CAT_MMX, @@ -50841,7 +50558,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1819 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + // Pos:1809 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" { .Instruction = ND_INS_PMULHW, .Category = ND_CAT_SSE, @@ -50868,7 +50585,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1820 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + // Pos:1810 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" { .Instruction = ND_INS_PMULLD, .Category = ND_CAT_SSE, @@ -50895,7 +50612,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1821 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + // Pos:1811 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" { .Instruction = ND_INS_PMULLW, .Category = ND_CAT_MMX, @@ -50922,7 +50639,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1822 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + // Pos:1812 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" { .Instruction = ND_INS_PMULLW, .Category = ND_CAT_SSE, @@ -50949,7 +50666,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1823 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + // Pos:1813 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" { .Instruction = ND_INS_PMULUDQ, .Category = ND_CAT_MMX, @@ -50976,7 +50693,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1824 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + // Pos:1814 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" { .Instruction = ND_INS_PMULUDQ, .Category = ND_CAT_SSE, @@ -51003,7 +50720,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1825 Instruction:"POP ES" Encoding:"0x07"/"" + // Pos:1815 Instruction:"POP ES" Encoding:"0x07"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51030,7 +50747,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1826 Instruction:"POP SS" Encoding:"0x17"/"" + // Pos:1816 Instruction:"POP SS" Encoding:"0x17"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51057,7 +50774,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1827 Instruction:"POP DS" Encoding:"0x1F"/"" + // Pos:1817 Instruction:"POP DS" Encoding:"0x1F"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51084,7 +50801,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1828 Instruction:"POP Zv" Encoding:"0x58"/"O" + // Pos:1818 Instruction:"POP Zv" Encoding:"0x58"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51111,7 +50828,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1829 Instruction:"POP Zv" Encoding:"0x59"/"O" + // Pos:1819 Instruction:"POP Zv" Encoding:"0x59"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51138,7 +50855,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1830 Instruction:"POP Zv" Encoding:"0x5A"/"O" + // Pos:1820 Instruction:"POP Zv" Encoding:"0x5A"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51165,7 +50882,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1831 Instruction:"POP Zv" Encoding:"0x5B"/"O" + // Pos:1821 Instruction:"POP Zv" Encoding:"0x5B"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51192,7 +50909,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1832 Instruction:"POP Zv" Encoding:"0x5C"/"O" + // Pos:1822 Instruction:"POP Zv" Encoding:"0x5C"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51219,7 +50936,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1833 Instruction:"POP Zv" Encoding:"0x5D"/"O" + // Pos:1823 Instruction:"POP Zv" Encoding:"0x5D"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51246,7 +50963,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1834 Instruction:"POP Zv" Encoding:"0x5E"/"O" + // Pos:1824 Instruction:"POP Zv" Encoding:"0x5E"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51273,7 +50990,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1835 Instruction:"POP Zv" Encoding:"0x5F"/"O" + // Pos:1825 Instruction:"POP Zv" Encoding:"0x5F"/"O" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51300,7 +51017,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1836 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + // Pos:1826 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51327,7 +51044,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1837 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + // Pos:1827 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51354,7 +51071,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1838 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + // Pos:1828 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" { .Instruction = ND_INS_POP, .Category = ND_CAT_POP, @@ -51381,7 +51098,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1839 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM" + // Pos:1829 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM" { .Instruction = ND_INS_POP2, .Category = ND_CAT_POP, @@ -51409,7 +51126,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1840 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM" + // Pos:1830 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM" { .Instruction = ND_INS_POP2P, .Category = ND_CAT_POP, @@ -51437,7 +51154,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1841 Instruction:"POPA" Encoding:"ds16 0x61"/"" + // Pos:1831 Instruction:"POPA" Encoding:"ds16 0x61"/"" { .Instruction = ND_INS_POPA, .Category = ND_CAT_POP, @@ -51464,7 +51181,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1842 Instruction:"POPAD" Encoding:"ds32 0x61"/"" + // Pos:1832 Instruction:"POPAD" Encoding:"ds32 0x61"/"" { .Instruction = ND_INS_POPAD, .Category = ND_CAT_POP, @@ -51491,7 +51208,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1843 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM" + // Pos:1833 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, @@ -51519,7 +51236,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1844 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM" + // Pos:1834 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, @@ -51547,7 +51264,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1845 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM" + // Pos:1835 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, @@ -51574,7 +51291,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1846 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM" + // Pos:1836 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_APX, @@ -51601,7 +51318,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1847 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM" + // Pos:1837 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM" { .Instruction = ND_INS_POPCNT, .Category = ND_CAT_SSE, @@ -51629,7 +51346,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1848 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + // Pos:1838 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" { .Instruction = ND_INS_POPF, .Category = ND_CAT_POP, @@ -51656,7 +51373,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1849 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + // Pos:1839 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" { .Instruction = ND_INS_POPF, .Category = ND_CAT_POP, @@ -51683,7 +51400,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1850 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + // Pos:1840 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" { .Instruction = ND_INS_POPF, .Category = ND_CAT_POP, @@ -51710,7 +51427,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1851 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O" + // Pos:1841 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51737,7 +51454,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1852 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O" + // Pos:1842 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51764,7 +51481,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1853 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O" + // Pos:1843 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51791,7 +51508,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1854 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O" + // Pos:1844 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51818,7 +51535,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1855 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O" + // Pos:1845 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51845,7 +51562,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1856 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O" + // Pos:1846 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51872,7 +51589,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1857 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O" + // Pos:1847 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51899,7 +51616,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1858 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O" + // Pos:1848 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O" { .Instruction = ND_INS_POPP, .Category = ND_CAT_POP, @@ -51926,7 +51643,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1859 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + // Pos:1849 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" { .Instruction = ND_INS_POR, .Category = ND_CAT_LOGICAL, @@ -51953,7 +51670,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1860 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + // Pos:1850 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" { .Instruction = ND_INS_POR, .Category = ND_CAT_LOGICAL, @@ -51980,7 +51697,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1861 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" + // Pos:1851 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, @@ -52006,7 +51723,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1862 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" + // Pos:1852 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, @@ -52032,7 +51749,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1863 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" + // Pos:1853 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, @@ -52058,7 +51775,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1864 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" + // Pos:1854 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" { .Instruction = ND_INS_PREFETCH, .Category = ND_CAT_PREFETCH, @@ -52084,7 +51801,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1865 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" + // Pos:1855 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" { .Instruction = ND_INS_PREFETCHE, .Category = ND_CAT_PREFETCH, @@ -52110,7 +51827,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1866 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" + // Pos:1856 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" { .Instruction = ND_INS_PREFETCHIT0, .Category = ND_CAT_PREFETCH, @@ -52136,7 +51853,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1867 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" + // Pos:1857 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" { .Instruction = ND_INS_PREFETCHIT1, .Category = ND_CAT_PREFETCH, @@ -52162,7 +51879,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1868 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" + // Pos:1858 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" { .Instruction = ND_INS_PREFETCHM, .Category = ND_CAT_PREFETCH, @@ -52188,7 +51905,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1869 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" + // Pos:1859 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" { .Instruction = ND_INS_PREFETCHNTA, .Category = ND_CAT_PREFETCH, @@ -52214,7 +51931,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1870 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" + // Pos:1860 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" { .Instruction = ND_INS_PREFETCHNTA, .Category = ND_CAT_PREFETCH, @@ -52240,7 +51957,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1871 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" + // Pos:1861 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" { .Instruction = ND_INS_PREFETCHT0, .Category = ND_CAT_PREFETCH, @@ -52266,7 +51983,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1872 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" + // Pos:1862 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" { .Instruction = ND_INS_PREFETCHT0, .Category = ND_CAT_PREFETCH, @@ -52292,7 +52009,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1873 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" + // Pos:1863 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" { .Instruction = ND_INS_PREFETCHT1, .Category = ND_CAT_PREFETCH, @@ -52318,7 +52035,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1874 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" + // Pos:1864 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" { .Instruction = ND_INS_PREFETCHT1, .Category = ND_CAT_PREFETCH, @@ -52344,7 +52061,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1875 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" + // Pos:1865 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" { .Instruction = ND_INS_PREFETCHT2, .Category = ND_CAT_PREFETCH, @@ -52370,7 +52087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1876 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" + // Pos:1866 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" { .Instruction = ND_INS_PREFETCHT2, .Category = ND_CAT_PREFETCH, @@ -52396,7 +52113,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1877 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" + // Pos:1867 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" { .Instruction = ND_INS_PREFETCHW, .Category = ND_CAT_PREFETCH, @@ -52422,7 +52139,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1878 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" + // Pos:1868 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" { .Instruction = ND_INS_PREFETCHWT1, .Category = ND_CAT_PREFETCH, @@ -52448,7 +52165,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1879 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + // Pos:1869 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" { .Instruction = ND_INS_PSADBW, .Category = ND_CAT_MMX, @@ -52475,7 +52192,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1880 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + // Pos:1870 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" { .Instruction = ND_INS_PSADBW, .Category = ND_CAT_SSE, @@ -52502,7 +52219,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1881 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + // Pos:1871 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" { .Instruction = ND_INS_PSHUFB, .Category = ND_CAT_MMX, @@ -52529,7 +52246,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1882 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + // Pos:1872 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" { .Instruction = ND_INS_PSHUFB, .Category = ND_CAT_SSE, @@ -52556,7 +52273,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1883 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + // Pos:1873 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFD, .Category = ND_CAT_SSE, @@ -52584,7 +52301,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1884 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + // Pos:1874 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFHW, .Category = ND_CAT_SSE, @@ -52612,7 +52329,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1885 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + // Pos:1875 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFLW, .Category = ND_CAT_SSE, @@ -52640,7 +52357,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1886 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + // Pos:1876 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" { .Instruction = ND_INS_PSHUFW, .Category = ND_CAT_MMX, @@ -52668,7 +52385,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1887 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + // Pos:1877 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" { .Instruction = ND_INS_PSIGNB, .Category = ND_CAT_MMX, @@ -52695,7 +52412,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1888 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + // Pos:1878 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" { .Instruction = ND_INS_PSIGNB, .Category = ND_CAT_SSE, @@ -52722,7 +52439,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1889 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + // Pos:1879 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" { .Instruction = ND_INS_PSIGND, .Category = ND_CAT_MMX, @@ -52749,7 +52466,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1890 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + // Pos:1880 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" { .Instruction = ND_INS_PSIGND, .Category = ND_CAT_SSE, @@ -52776,7 +52493,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1891 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + // Pos:1881 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" { .Instruction = ND_INS_PSIGNW, .Category = ND_CAT_MMX, @@ -52803,7 +52520,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1892 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + // Pos:1882 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" { .Instruction = ND_INS_PSIGNW, .Category = ND_CAT_SSE, @@ -52830,7 +52547,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1893 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1883 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_MMX, @@ -52857,7 +52574,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1894 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + // Pos:1884 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_SSE, @@ -52884,7 +52601,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1895 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + // Pos:1885 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_MMX, @@ -52911,7 +52628,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1896 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + // Pos:1886 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" { .Instruction = ND_INS_PSLLD, .Category = ND_CAT_SSE, @@ -52938,7 +52655,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1897 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + // Pos:1887 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" { .Instruction = ND_INS_PSLLDQ, .Category = ND_CAT_SSE, @@ -52965,7 +52682,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1898 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1888 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_MMX, @@ -52992,7 +52709,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1899 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + // Pos:1889 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_SSE, @@ -53019,7 +52736,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1900 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + // Pos:1890 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_MMX, @@ -53046,7 +52763,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1901 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + // Pos:1891 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" { .Instruction = ND_INS_PSLLQ, .Category = ND_CAT_SSE, @@ -53073,7 +52790,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1902 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1892 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_MMX, @@ -53100,7 +52817,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1903 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + // Pos:1893 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_SSE, @@ -53127,7 +52844,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1904 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + // Pos:1894 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_MMX, @@ -53154,7 +52871,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1905 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + // Pos:1895 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" { .Instruction = ND_INS_PSLLW, .Category = ND_CAT_SSE, @@ -53181,7 +52898,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1906 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + // Pos:1896 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" { .Instruction = ND_INS_PSMASH, .Category = ND_CAT_SYSTEM, @@ -53208,7 +52925,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1907 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1897 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_MMX, @@ -53235,7 +52952,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1908 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + // Pos:1898 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_SSE, @@ -53262,7 +52979,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1909 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + // Pos:1899 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_MMX, @@ -53289,7 +53006,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1910 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + // Pos:1900 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" { .Instruction = ND_INS_PSRAD, .Category = ND_CAT_SSE, @@ -53316,7 +53033,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1911 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1901 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_MMX, @@ -53343,7 +53060,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1912 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + // Pos:1902 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_SSE, @@ -53370,7 +53087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1913 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + // Pos:1903 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_MMX, @@ -53397,7 +53114,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1914 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + // Pos:1904 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" { .Instruction = ND_INS_PSRAW, .Category = ND_CAT_SSE, @@ -53424,7 +53141,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1915 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1905 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_MMX, @@ -53451,7 +53168,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1916 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + // Pos:1906 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_SSE, @@ -53478,7 +53195,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1917 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + // Pos:1907 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_MMX, @@ -53505,7 +53222,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1918 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + // Pos:1908 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" { .Instruction = ND_INS_PSRLD, .Category = ND_CAT_SSE, @@ -53532,7 +53249,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1919 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + // Pos:1909 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" { .Instruction = ND_INS_PSRLDQ, .Category = ND_CAT_SSE, @@ -53559,7 +53276,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1920 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1910 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_MMX, @@ -53586,7 +53303,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1921 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + // Pos:1911 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_SSE, @@ -53613,7 +53330,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1922 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + // Pos:1912 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_MMX, @@ -53640,7 +53357,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1923 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + // Pos:1913 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" { .Instruction = ND_INS_PSRLQ, .Category = ND_CAT_SSE, @@ -53667,7 +53384,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1924 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1914 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_MMX, @@ -53694,7 +53411,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1925 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + // Pos:1915 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_SSE, @@ -53721,7 +53438,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1926 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + // Pos:1916 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_MMX, @@ -53748,7 +53465,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1927 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + // Pos:1917 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" { .Instruction = ND_INS_PSRLW, .Category = ND_CAT_SSE, @@ -53775,7 +53492,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1928 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + // Pos:1918 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" { .Instruction = ND_INS_PSUBB, .Category = ND_CAT_MMX, @@ -53802,7 +53519,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1929 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + // Pos:1919 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" { .Instruction = ND_INS_PSUBB, .Category = ND_CAT_SSE, @@ -53829,7 +53546,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1930 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + // Pos:1920 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" { .Instruction = ND_INS_PSUBD, .Category = ND_CAT_MMX, @@ -53856,7 +53573,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1931 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + // Pos:1921 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" { .Instruction = ND_INS_PSUBD, .Category = ND_CAT_SSE, @@ -53883,7 +53600,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1932 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + // Pos:1922 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" { .Instruction = ND_INS_PSUBQ, .Category = ND_CAT_MMX, @@ -53910,7 +53627,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1933 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + // Pos:1923 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" { .Instruction = ND_INS_PSUBQ, .Category = ND_CAT_SSE, @@ -53937,7 +53654,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1934 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + // Pos:1924 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" { .Instruction = ND_INS_PSUBSB, .Category = ND_CAT_MMX, @@ -53964,7 +53681,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1935 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + // Pos:1925 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" { .Instruction = ND_INS_PSUBSB, .Category = ND_CAT_SSE, @@ -53991,7 +53708,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1936 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + // Pos:1926 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" { .Instruction = ND_INS_PSUBSW, .Category = ND_CAT_MMX, @@ -54018,7 +53735,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1937 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + // Pos:1927 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" { .Instruction = ND_INS_PSUBSW, .Category = ND_CAT_SSE, @@ -54045,7 +53762,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1938 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + // Pos:1928 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" { .Instruction = ND_INS_PSUBUSB, .Category = ND_CAT_MMX, @@ -54072,7 +53789,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1939 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + // Pos:1929 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" { .Instruction = ND_INS_PSUBUSB, .Category = ND_CAT_SSE, @@ -54099,7 +53816,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1940 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + // Pos:1930 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" { .Instruction = ND_INS_PSUBUSW, .Category = ND_CAT_MMX, @@ -54126,7 +53843,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1941 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + // Pos:1931 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" { .Instruction = ND_INS_PSUBUSW, .Category = ND_CAT_SSE, @@ -54153,7 +53870,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1942 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + // Pos:1932 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" { .Instruction = ND_INS_PSUBW, .Category = ND_CAT_MMX, @@ -54180,7 +53897,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1943 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + // Pos:1933 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" { .Instruction = ND_INS_PSUBW, .Category = ND_CAT_SSE, @@ -54207,7 +53924,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1944 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + // Pos:1934 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" { .Instruction = ND_INS_PSWAPD, .Category = ND_CAT_3DNOW, @@ -54234,7 +53951,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1945 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + // Pos:1935 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" { .Instruction = ND_INS_PTEST, .Category = ND_CAT_SSE, @@ -54262,7 +53979,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1946 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + // Pos:1936 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" { .Instruction = ND_INS_PTWRITE, .Category = ND_CAT_PTWRITE, @@ -54288,7 +54005,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1947 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + // Pos:1937 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" { .Instruction = ND_INS_PUNPCKHBW, .Category = ND_CAT_MMX, @@ -54315,7 +54032,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1948 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + // Pos:1938 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" { .Instruction = ND_INS_PUNPCKHBW, .Category = ND_CAT_SSE, @@ -54342,7 +54059,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1949 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + // Pos:1939 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" { .Instruction = ND_INS_PUNPCKHDQ, .Category = ND_CAT_MMX, @@ -54369,7 +54086,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1950 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + // Pos:1940 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" { .Instruction = ND_INS_PUNPCKHDQ, .Category = ND_CAT_SSE, @@ -54396,7 +54113,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1951 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + // Pos:1941 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" { .Instruction = ND_INS_PUNPCKHQDQ, .Category = ND_CAT_SSE, @@ -54423,7 +54140,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1952 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + // Pos:1942 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" { .Instruction = ND_INS_PUNPCKHWD, .Category = ND_CAT_MMX, @@ -54450,7 +54167,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1953 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + // Pos:1943 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" { .Instruction = ND_INS_PUNPCKHWD, .Category = ND_CAT_SSE, @@ -54477,7 +54194,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1954 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + // Pos:1944 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" { .Instruction = ND_INS_PUNPCKLBW, .Category = ND_CAT_MMX, @@ -54504,7 +54221,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1955 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + // Pos:1945 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" { .Instruction = ND_INS_PUNPCKLBW, .Category = ND_CAT_SSE, @@ -54531,7 +54248,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1956 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + // Pos:1946 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" { .Instruction = ND_INS_PUNPCKLDQ, .Category = ND_CAT_MMX, @@ -54558,7 +54275,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1957 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + // Pos:1947 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" { .Instruction = ND_INS_PUNPCKLDQ, .Category = ND_CAT_SSE, @@ -54585,7 +54302,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1958 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + // Pos:1948 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" { .Instruction = ND_INS_PUNPCKLQDQ, .Category = ND_CAT_SSE, @@ -54612,7 +54329,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1959 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + // Pos:1949 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" { .Instruction = ND_INS_PUNPCKLWD, .Category = ND_CAT_MMX, @@ -54639,7 +54356,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1960 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + // Pos:1950 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" { .Instruction = ND_INS_PUNPCKLWD, .Category = ND_CAT_SSE, @@ -54666,7 +54383,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1961 Instruction:"PUSH ES" Encoding:"0x06"/"" + // Pos:1951 Instruction:"PUSH ES" Encoding:"0x06"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54693,7 +54410,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1962 Instruction:"PUSH CS" Encoding:"0x0E"/"" + // Pos:1952 Instruction:"PUSH CS" Encoding:"0x0E"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54720,7 +54437,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1963 Instruction:"PUSH SS" Encoding:"0x16"/"" + // Pos:1953 Instruction:"PUSH SS" Encoding:"0x16"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54747,7 +54464,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1964 Instruction:"PUSH DS" Encoding:"0x1E"/"" + // Pos:1954 Instruction:"PUSH DS" Encoding:"0x1E"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54774,7 +54491,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1965 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + // Pos:1955 Instruction:"PUSH Zv" Encoding:"0x50"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54801,7 +54518,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1966 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + // Pos:1956 Instruction:"PUSH Zv" Encoding:"0x51"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54828,7 +54545,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1967 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + // Pos:1957 Instruction:"PUSH Zv" Encoding:"0x52"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54855,7 +54572,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1968 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + // Pos:1958 Instruction:"PUSH Zv" Encoding:"0x53"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54882,7 +54599,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1969 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + // Pos:1959 Instruction:"PUSH Zv" Encoding:"0x54"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54909,7 +54626,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1970 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + // Pos:1960 Instruction:"PUSH Zv" Encoding:"0x55"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54936,7 +54653,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1971 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + // Pos:1961 Instruction:"PUSH Zv" Encoding:"0x56"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54963,7 +54680,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1972 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + // Pos:1962 Instruction:"PUSH Zv" Encoding:"0x57"/"O" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -54990,7 +54707,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1973 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + // Pos:1963 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -55017,7 +54734,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1974 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + // Pos:1964 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -55044,7 +54761,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1975 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + // Pos:1965 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -55071,7 +54788,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1976 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + // Pos:1966 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -55098,7 +54815,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1977 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + // Pos:1967 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" { .Instruction = ND_INS_PUSH, .Category = ND_CAT_PUSH, @@ -55125,7 +54842,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1978 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM" + // Pos:1968 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM" { .Instruction = ND_INS_PUSH2, .Category = ND_CAT_PUSH, @@ -55153,7 +54870,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1979 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM" + // Pos:1969 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM" { .Instruction = ND_INS_PUSH2P, .Category = ND_CAT_PUSH, @@ -55181,7 +54898,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1980 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" + // Pos:1970 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" { .Instruction = ND_INS_PUSHA, .Category = ND_CAT_PUSH, @@ -55208,7 +54925,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1981 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" + // Pos:1971 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" { .Instruction = ND_INS_PUSHAD, .Category = ND_CAT_PUSH, @@ -55235,7 +54952,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1982 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + // Pos:1972 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" { .Instruction = ND_INS_PUSHF, .Category = ND_CAT_PUSH, @@ -55262,7 +54979,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1983 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + // Pos:1973 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" { .Instruction = ND_INS_PUSHF, .Category = ND_CAT_PUSH, @@ -55289,7 +55006,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1984 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + // Pos:1974 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" { .Instruction = ND_INS_PUSHF, .Category = ND_CAT_PUSH, @@ -55316,7 +55033,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1985 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O" + // Pos:1975 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55343,7 +55060,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1986 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O" + // Pos:1976 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55370,7 +55087,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1987 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O" + // Pos:1977 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55397,7 +55114,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1988 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O" + // Pos:1978 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55424,7 +55141,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1989 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O" + // Pos:1979 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55451,7 +55168,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1990 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O" + // Pos:1980 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55478,7 +55195,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1991 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O" + // Pos:1981 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55505,7 +55222,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1992 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O" + // Pos:1982 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O" { .Instruction = ND_INS_PUSHP, .Category = ND_CAT_PUSH, @@ -55532,7 +55249,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1993 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + // Pos:1983 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" { .Instruction = ND_INS_PVALIDATE, .Category = ND_CAT_SYSTEM, @@ -55561,7 +55278,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1994 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + // Pos:1984 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" { .Instruction = ND_INS_PXOR, .Category = ND_CAT_LOGICAL, @@ -55588,7 +55305,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1995 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + // Pos:1985 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" { .Instruction = ND_INS_PXOR, .Category = ND_CAT_LOGICAL, @@ -55615,7 +55332,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1996 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI" + // Pos:1986 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55643,7 +55360,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1997 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI" + // Pos:1987 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55671,7 +55388,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1998 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI" + // Pos:1988 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55699,7 +55416,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:1999 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1" + // Pos:1989 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55727,7 +55444,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2000 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1" + // Pos:1990 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55755,7 +55472,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2001 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1" + // Pos:1991 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55783,7 +55500,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2002 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC" + // Pos:1992 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55811,7 +55528,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2003 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC" + // Pos:1993 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55839,7 +55556,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2004 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC" + // Pos:1994 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55867,7 +55584,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2005 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI" + // Pos:1995 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55894,7 +55611,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2006 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI" + // Pos:1996 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55921,7 +55638,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2007 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI" + // Pos:1997 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55948,7 +55665,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2008 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1" + // Pos:1998 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -55975,7 +55692,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2009 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1" + // Pos:1999 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56002,7 +55719,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2010 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1" + // Pos:2000 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56029,7 +55746,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2011 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC" + // Pos:2001 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56056,7 +55773,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2012 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC" + // Pos:2002 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56083,7 +55800,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2013 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC" + // Pos:2003 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56110,7 +55827,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2014 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI" + // Pos:2004 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56139,7 +55856,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2015 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI" + // Pos:2005 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56168,7 +55885,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2016 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI" + // Pos:2006 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56197,7 +55914,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2017 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1" + // Pos:2007 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56226,7 +55943,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2018 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1" + // Pos:2008 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56255,7 +55972,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2019 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1" + // Pos:2009 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56284,7 +56001,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2020 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC" + // Pos:2010 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56313,7 +56030,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2021 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC" + // Pos:2011 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56342,7 +56059,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2022 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC" + // Pos:2012 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56371,7 +56088,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2023 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI" + // Pos:2013 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56399,7 +56116,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2024 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI" + // Pos:2014 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56427,7 +56144,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2025 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI" + // Pos:2015 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56455,7 +56172,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2026 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1" + // Pos:2016 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56483,7 +56200,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2027 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1" + // Pos:2017 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56511,7 +56228,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2028 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1" + // Pos:2018 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56539,7 +56256,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2029 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC" + // Pos:2019 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56567,7 +56284,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2030 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC" + // Pos:2020 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56595,7 +56312,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2031 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC" + // Pos:2021 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56623,7 +56340,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2032 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + // Pos:2022 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56651,7 +56368,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2033 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + // Pos:2023 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56679,7 +56396,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2034 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + // Pos:2024 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56707,7 +56424,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2035 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + // Pos:2025 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56735,7 +56452,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2036 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + // Pos:2026 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56763,7 +56480,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2037 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + // Pos:2027 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" { .Instruction = ND_INS_RCL, .Category = ND_CAT_ROTATE, @@ -56791,7 +56508,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2038 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + // Pos:2028 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" { .Instruction = ND_INS_RCPPS, .Category = ND_CAT_SSE, @@ -56818,7 +56535,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2039 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + // Pos:2029 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" { .Instruction = ND_INS_RCPSS, .Category = ND_CAT_SSE, @@ -56845,7 +56562,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2040 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI" + // Pos:2030 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -56873,7 +56590,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2041 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI" + // Pos:2031 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -56901,7 +56618,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2042 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI" + // Pos:2032 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -56929,7 +56646,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2043 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1" + // Pos:2033 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -56957,7 +56674,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2044 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1" + // Pos:2034 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -56985,7 +56702,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2045 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1" + // Pos:2035 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57013,7 +56730,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2046 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC" + // Pos:2036 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57041,7 +56758,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2047 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC" + // Pos:2037 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57069,7 +56786,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2048 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC" + // Pos:2038 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57097,7 +56814,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2049 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI" + // Pos:2039 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57124,7 +56841,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2050 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI" + // Pos:2040 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57151,7 +56868,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2051 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI" + // Pos:2041 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57178,7 +56895,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2052 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1" + // Pos:2042 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57205,7 +56922,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2053 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1" + // Pos:2043 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57232,7 +56949,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2054 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1" + // Pos:2044 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57259,7 +56976,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2055 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC" + // Pos:2045 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57286,7 +57003,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2056 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC" + // Pos:2046 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57313,7 +57030,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2057 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC" + // Pos:2047 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57340,7 +57057,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2058 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI" + // Pos:2048 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57369,7 +57086,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2059 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI" + // Pos:2049 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57398,7 +57115,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2060 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI" + // Pos:2050 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57427,7 +57144,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2061 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1" + // Pos:2051 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57456,7 +57173,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2062 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1" + // Pos:2052 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57485,7 +57202,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2063 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1" + // Pos:2053 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57514,7 +57231,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2064 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC" + // Pos:2054 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57543,7 +57260,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2065 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC" + // Pos:2055 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57572,7 +57289,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2066 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC" + // Pos:2056 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57601,7 +57318,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2067 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI" + // Pos:2057 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57629,7 +57346,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2068 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI" + // Pos:2058 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57657,7 +57374,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2069 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI" + // Pos:2059 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57685,7 +57402,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2070 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1" + // Pos:2060 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57713,7 +57430,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2071 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1" + // Pos:2061 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57741,7 +57458,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2072 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1" + // Pos:2062 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57769,7 +57486,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2073 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC" + // Pos:2063 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57797,7 +57514,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2074 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC" + // Pos:2064 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57825,7 +57542,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2075 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC" + // Pos:2065 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57853,7 +57570,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2076 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + // Pos:2066 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57881,7 +57598,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2077 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + // Pos:2067 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57909,7 +57626,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2078 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + // Pos:2068 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57937,7 +57654,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2079 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + // Pos:2069 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57965,7 +57682,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2080 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + // Pos:2070 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -57993,7 +57710,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2081 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + // Pos:2071 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" { .Instruction = ND_INS_RCR, .Category = ND_CAT_ROTATE, @@ -58021,7 +57738,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2082 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M" + // Pos:2072 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M" { .Instruction = ND_INS_RDFSBASE, .Category = ND_CAT_RDWRFSGS, @@ -58048,7 +57765,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2083 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M" + // Pos:2073 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M" { .Instruction = ND_INS_RDGSBASE, .Category = ND_CAT_RDWRFSGS, @@ -58075,7 +57792,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2084 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + // Pos:2074 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" { .Instruction = ND_INS_RDMSR, .Category = ND_CAT_SYSTEM, @@ -58104,7 +57821,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2085 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" + // Pos:2075 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" { .Instruction = ND_INS_RDMSRLIST, .Category = ND_CAT_SYSTEM, @@ -58132,7 +57849,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2086 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + // Pos:2076 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" { .Instruction = ND_INS_RDPID, .Category = ND_CAT_RDPID, @@ -58159,7 +57876,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2087 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + // Pos:2077 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" { .Instruction = ND_INS_RDPKRU, .Category = ND_CAT_MISC, @@ -58188,7 +57905,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2088 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + // Pos:2078 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" { .Instruction = ND_INS_RDPMC, .Category = ND_CAT_SYSTEM, @@ -58217,7 +57934,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2089 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/"" + // Pos:2079 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/"" { .Instruction = ND_INS_RDPRU, .Category = ND_CAT_MISC, @@ -58246,7 +57963,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2090 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M" + // Pos:2080 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M" { .Instruction = ND_INS_RDRAND, .Category = ND_CAT_RDRAND, @@ -58273,7 +57990,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2091 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + // Pos:2081 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" { .Instruction = ND_INS_RDRAND, .Category = ND_CAT_RDRAND, @@ -58300,7 +58017,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2092 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M" + // Pos:2082 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M" { .Instruction = ND_INS_RDSEED, .Category = ND_CAT_RDSEED, @@ -58327,7 +58044,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2093 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + // Pos:2083 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" { .Instruction = ND_INS_RDSEED, .Category = ND_CAT_RDSEED, @@ -58354,7 +58071,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2094 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M" + // Pos:2084 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M" { .Instruction = ND_INS_RSSSP, .Category = ND_CAT_CET, @@ -58381,7 +58098,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2095 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M" + // Pos:2085 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M" { .Instruction = ND_INS_RSSSP, .Category = ND_CAT_CET, @@ -58408,7 +58125,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2096 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + // Pos:2086 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" { .Instruction = ND_INS_RDTSC, .Category = ND_CAT_SYSTEM, @@ -58436,7 +58153,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2097 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + // Pos:2087 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" { .Instruction = ND_INS_RDTSCP, .Category = ND_CAT_SYSTEM, @@ -58466,7 +58183,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2098 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + // Pos:2088 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" { .Instruction = ND_INS_RETF, .Category = ND_CAT_RET, @@ -58496,7 +58213,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2099 Instruction:"RETF" Encoding:"0xCB"/"" + // Pos:2089 Instruction:"RETF" Encoding:"0xCB"/"" { .Instruction = ND_INS_RETF, .Category = ND_CAT_RET, @@ -58525,7 +58242,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2100 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + // Pos:2090 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" { .Instruction = ND_INS_RETN, .Category = ND_CAT_RET, @@ -58555,7 +58272,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2101 Instruction:"RETN" Encoding:"0xC3"/"" + // Pos:2091 Instruction:"RETN" Encoding:"0xC3"/"" { .Instruction = ND_INS_RETN, .Category = ND_CAT_RET, @@ -58583,7 +58300,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2102 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + // Pos:2092 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" { .Instruction = ND_INS_RMPADJUST, .Category = ND_CAT_SYSTEM, @@ -58613,7 +58330,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2103 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" + // Pos:2093 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" { .Instruction = ND_INS_RMPQUERY, .Category = ND_CAT_SYSTEM, @@ -58643,12 +58360,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2104 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + // Pos:2094 Instruction:"RMPREAD" Encoding:"0xF2 0x0F 0x01 /0xFD"/"" + { + .Instruction = ND_INS_RMPREAD, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SNP, + .Mnemonic = 759, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_RMPREAD, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_pCX, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2095 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" { .Instruction = ND_INS_RMPUPDATE, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SNP, - .Mnemonic = 759, + .Mnemonic = 760, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -58671,1187 +58416,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2105 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI" + // Pos:2096 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI" { .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2106 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2107 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2108 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2109 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2110 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2111 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2112 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2113 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2114 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2115 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2116 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2117 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2118 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2119 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2120 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2121 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2122 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_NF, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2123 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2124 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2125 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2126 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2127 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2128 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2129 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2130 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2131 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND, - .OpsCount = ND_OPS_CNT(3, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2132 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2133 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2134 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2135 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2136 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2137 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2138 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2139 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2140 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ND|ND_DECO_NF, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2141 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_I86, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2142 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_I86, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2143 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_I86, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2144 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_I86, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2145 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_I86, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2146 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" - { - .Instruction = ND_INS_ROL, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_I86, - .Mnemonic = 760, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2147 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI" - { - .Instruction = ND_INS_ROR, - .Category = ND_CAT_ROTATE, - .IsaSet = ND_SET_APX_F, .Mnemonic = 761, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, @@ -59875,9 +58444,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2148 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI" + // Pos:2097 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -59903,9 +58472,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2149 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI" + // Pos:2098 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -59931,9 +58500,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2150 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1" + // Pos:2099 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -59959,9 +58528,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2151 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1" + // Pos:2100 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -59987,9 +58556,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2152 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1" + // Pos:2101 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60015,9 +58584,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2153 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC" + // Pos:2102 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60043,9 +58612,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2154 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC" + // Pos:2103 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60071,9 +58640,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2155 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC" + // Pos:2104 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60099,9 +58668,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2156 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI" + // Pos:2105 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60126,9 +58695,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2157 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI" + // Pos:2106 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60153,9 +58722,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2158 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI" + // Pos:2107 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60180,9 +58749,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2159 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1" + // Pos:2108 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60207,9 +58776,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2160 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1" + // Pos:2109 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60234,9 +58803,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2161 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1" + // Pos:2110 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60261,9 +58830,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2162 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC" + // Pos:2111 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60288,9 +58857,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2163 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC" + // Pos:2112 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60315,9 +58884,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2164 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC" + // Pos:2113 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60342,9 +58911,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2165 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI" + // Pos:2114 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60371,9 +58940,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2166 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI" + // Pos:2115 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60400,9 +58969,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2167 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI" + // Pos:2116 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60429,9 +58998,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2168 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1" + // Pos:2117 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60458,9 +59027,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2169 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1" + // Pos:2118 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60487,9 +59056,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2170 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1" + // Pos:2119 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60516,9 +59085,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2171 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC" + // Pos:2120 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60545,9 +59114,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2172 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC" + // Pos:2121 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60574,9 +59143,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2173 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC" + // Pos:2122 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60603,9 +59172,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2174 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI" + // Pos:2123 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60631,9 +59200,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2175 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI" + // Pos:2124 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60659,9 +59228,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2176 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI" + // Pos:2125 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60687,9 +59256,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2177 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1" + // Pos:2126 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60715,9 +59284,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2178 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1" + // Pos:2127 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60743,9 +59312,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2179 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1" + // Pos:2128 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60771,9 +59340,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2180 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC" + // Pos:2129 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60799,9 +59368,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2181 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC" + // Pos:2130 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60827,9 +59396,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2182 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC" + // Pos:2131 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_APX_F, .Mnemonic = 761, @@ -60855,9 +59424,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2183 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + // Pos:2132 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, .Mnemonic = 761, @@ -60883,9 +59452,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2184 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + // Pos:2133 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, .Mnemonic = 761, @@ -60911,9 +59480,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2185 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + // Pos:2134 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, .Mnemonic = 761, @@ -60939,9 +59508,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2186 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + // Pos:2135 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, .Mnemonic = 761, @@ -60967,9 +59536,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2187 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + // Pos:2136 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, .Mnemonic = 761, @@ -60995,9 +59564,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2188 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + // Pos:2137 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { - .Instruction = ND_INS_ROR, + .Instruction = ND_INS_ROL, .Category = ND_CAT_ROTATE, .IsaSet = ND_SET_I86, .Mnemonic = 761, @@ -61023,12 +59592,1188 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2189 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI" + // Pos:2138 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2139 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2140 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2141 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2142 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2143 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2144 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2145 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2146 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2147 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2148 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2149 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2150 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2151 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2152 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2153 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2154 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2155 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2156 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2157 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2158 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2159 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2160 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2161 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2162 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2163 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2164 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2165 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2166 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2167 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2168 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2169 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2170 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2171 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2172 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2173 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2174 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2175 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2176 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2177 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2178 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2179 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2180 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI" { .Instruction = ND_INS_RORX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 762, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61051,12 +60796,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2190 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + // Pos:2181 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { .Instruction = ND_INS_RORX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 762, + .Mnemonic = 763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61079,39 +60824,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2191 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + // Pos:2182 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { .Instruction = ND_INS_ROUNDPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 763, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_2, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_SSE4, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2192 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" - { - .Instruction = ND_INS_ROUNDPS, - .Category = ND_CAT_SSE, - .IsaSet = ND_SET_SSE4, .Mnemonic = 764, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, @@ -61135,12 +60852,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2193 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + // Pos:2183 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + { + .Instruction = ND_INS_ROUNDPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 765, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2184 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { .Instruction = ND_INS_ROUNDSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 765, + .Mnemonic = 766, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61163,12 +60908,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2194 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + // Pos:2185 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { .Instruction = ND_INS_ROUNDSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE4, - .Mnemonic = 766, + .Mnemonic = 767, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61191,12 +60936,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2195 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + // Pos:2186 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { .Instruction = ND_INS_RSM, .Category = ND_CAT_SYSRET, .IsaSet = ND_SET_I486, - .Mnemonic = 767, + .Mnemonic = 768, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -61219,12 +60964,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2196 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + // Pos:2187 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { .Instruction = ND_INS_RSQRTPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 768, + .Mnemonic = 769, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61246,12 +60991,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2197 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + // Pos:2188 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { .Instruction = ND_INS_RSQRTSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 769, + .Mnemonic = 770, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61273,12 +61018,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2198 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + // Pos:2189 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { .Instruction = ND_INS_RSTORSSP, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 770, + .Mnemonic = 771, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61300,12 +61045,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2199 Instruction:"SAHF" Encoding:"0x9E"/"" + // Pos:2190 Instruction:"SAHF" Encoding:"0x9E"/"" { .Instruction = ND_INS_SAHF, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 771, + .Mnemonic = 772, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -61327,12 +61072,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2200 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI" + // Pos:2191 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61355,12 +61100,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2201 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI" + // Pos:2192 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61383,12 +61128,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2202 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI" + // Pos:2193 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61411,12 +61156,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2203 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1" + // Pos:2194 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61439,12 +61184,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2204 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1" + // Pos:2195 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61467,12 +61212,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2205 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1" + // Pos:2196 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61495,12 +61240,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2206 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC" + // Pos:2197 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61523,12 +61268,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2207 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC" + // Pos:2198 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61551,12 +61296,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2208 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC" + // Pos:2199 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -61579,12 +61324,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2209 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI" + // Pos:2200 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61606,12 +61351,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2210 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI" + // Pos:2201 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61633,12 +61378,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2211 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI" + // Pos:2202 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61660,12 +61405,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2212 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1" + // Pos:2203 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61687,12 +61432,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2213 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1" + // Pos:2204 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61714,12 +61459,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2214 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1" + // Pos:2205 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61741,12 +61486,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2215 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC" + // Pos:2206 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61768,12 +61513,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2216 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC" + // Pos:2207 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61795,12 +61540,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2217 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC" + // Pos:2208 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -61822,12 +61567,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2218 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI" + // Pos:2209 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61851,12 +61596,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2219 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI" + // Pos:2210 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61880,12 +61625,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2220 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI" + // Pos:2211 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61909,12 +61654,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2221 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1" + // Pos:2212 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61938,12 +61683,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2222 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1" + // Pos:2213 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61967,12 +61712,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2223 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1" + // Pos:2214 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -61996,12 +61741,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2224 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC" + // Pos:2215 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62025,12 +61770,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2225 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC" + // Pos:2216 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62054,12 +61799,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2226 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC" + // Pos:2217 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -62083,12 +61828,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2227 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI" + // Pos:2218 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62111,12 +61856,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2228 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI" + // Pos:2219 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62139,12 +61884,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2229 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI" + // Pos:2220 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62167,12 +61912,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2230 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1" + // Pos:2221 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62195,12 +61940,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2231 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1" + // Pos:2222 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62223,12 +61968,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2232 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1" + // Pos:2223 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62251,12 +61996,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2233 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC" + // Pos:2224 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62279,12 +62024,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2234 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC" + // Pos:2225 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62307,12 +62052,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2235 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC" + // Pos:2226 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -62335,12 +62080,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2236 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + // Pos:2227 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62363,12 +62108,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2237 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + // Pos:2228 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62391,12 +62136,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2238 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + // Pos:2229 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62419,12 +62164,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2239 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + // Pos:2230 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62447,12 +62192,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2240 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + // Pos:2231 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62475,12 +62220,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2241 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + // Pos:2232 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { .Instruction = ND_INS_SAL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 772, + .Mnemonic = 773, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62503,12 +62248,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2242 Instruction:"SALC" Encoding:"0xD6"/"" + // Pos:2233 Instruction:"SALC" Encoding:"0xD6"/"" { .Instruction = ND_INS_SALC, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 773, + .Mnemonic = 774, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -62530,12 +62275,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2243 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI" + // Pos:2234 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62558,12 +62303,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2244 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI" + // Pos:2235 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62586,12 +62331,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2245 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI" + // Pos:2236 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62614,12 +62359,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2246 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1" + // Pos:2237 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62642,12 +62387,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2247 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1" + // Pos:2238 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62670,12 +62415,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2248 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1" + // Pos:2239 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62698,12 +62443,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2249 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC" + // Pos:2240 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62726,12 +62471,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2250 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC" + // Pos:2241 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62754,12 +62499,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2251 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC" + // Pos:2242 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -62782,12 +62527,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2252 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI" + // Pos:2243 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62809,12 +62554,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2253 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI" + // Pos:2244 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62836,12 +62581,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2254 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI" + // Pos:2245 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62863,12 +62608,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2255 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1" + // Pos:2246 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62890,12 +62635,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2256 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1" + // Pos:2247 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62917,12 +62662,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2257 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1" + // Pos:2248 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62944,12 +62689,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2258 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC" + // Pos:2249 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62971,12 +62716,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2259 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC" + // Pos:2250 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -62998,12 +62743,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2260 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC" + // Pos:2251 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -63025,12 +62770,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2261 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI" + // Pos:2252 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63054,12 +62799,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2262 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI" + // Pos:2253 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63083,12 +62828,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2263 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI" + // Pos:2254 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63112,12 +62857,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2264 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1" + // Pos:2255 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63141,12 +62886,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2265 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1" + // Pos:2256 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63170,12 +62915,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2266 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1" + // Pos:2257 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63199,12 +62944,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2267 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC" + // Pos:2258 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63228,12 +62973,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2268 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC" + // Pos:2259 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63257,12 +63002,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2269 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC" + // Pos:2260 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -63286,12 +63031,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2270 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI" + // Pos:2261 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63314,12 +63059,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2271 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI" + // Pos:2262 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63342,12 +63087,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2272 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI" + // Pos:2263 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63370,12 +63115,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2273 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1" + // Pos:2264 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63398,12 +63143,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2274 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1" + // Pos:2265 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63426,12 +63171,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2275 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1" + // Pos:2266 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63454,12 +63199,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2276 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC" + // Pos:2267 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63482,12 +63227,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2277 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC" + // Pos:2268 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63510,12 +63255,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2278 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC" + // Pos:2269 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -63538,12 +63283,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2279 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + // Pos:2270 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63566,12 +63311,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2280 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + // Pos:2271 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63594,12 +63339,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2281 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + // Pos:2272 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63622,12 +63367,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2282 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + // Pos:2273 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63650,12 +63395,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2283 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + // Pos:2274 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63678,12 +63423,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2284 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + // Pos:2275 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { .Instruction = ND_INS_SAR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 774, + .Mnemonic = 775, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63706,12 +63451,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2285 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:2276 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_SARX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 775, + .Mnemonic = 776, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63734,12 +63479,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2286 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + // Pos:2277 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_SARX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 775, + .Mnemonic = 776, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63762,12 +63507,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2287 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + // Pos:2278 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { .Instruction = ND_INS_SAVEPREVSSP, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 776, + .Mnemonic = 777, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -63789,12 +63534,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2288 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR" + // Pos:2279 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63817,12 +63562,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2289 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR" + // Pos:2280 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63845,12 +63590,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2290 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR" + // Pos:2281 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63873,12 +63618,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2291 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM" + // Pos:2282 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63901,12 +63646,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2292 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM" + // Pos:2283 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63929,12 +63674,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2293 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM" + // Pos:2284 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63957,12 +63702,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2294 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI" + // Pos:2285 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -63985,12 +63730,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2295 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI" + // Pos:2286 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -64013,12 +63758,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2296 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI" + // Pos:2287 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -64041,12 +63786,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2297 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI" + // Pos:2288 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -64069,12 +63814,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2298 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI" + // Pos:2289 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -64097,12 +63842,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2299 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR" + // Pos:2290 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64126,12 +63871,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2300 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR" + // Pos:2291 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64155,12 +63900,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2301 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR" + // Pos:2292 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64184,12 +63929,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2302 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM" + // Pos:2293 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64213,12 +63958,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2303 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM" + // Pos:2294 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64242,12 +63987,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2304 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM" + // Pos:2295 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64271,12 +64016,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2305 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI" + // Pos:2296 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64300,12 +64045,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2306 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI" + // Pos:2297 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64329,12 +64074,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2307 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI" + // Pos:2298 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64358,12 +64103,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2308 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI" + // Pos:2299 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64387,12 +64132,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2309 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI" + // Pos:2300 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -64416,12 +64161,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2310 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + // Pos:2301 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64444,12 +64189,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2311 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + // Pos:2302 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64472,12 +64217,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2312 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + // Pos:2303 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64500,12 +64245,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2313 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + // Pos:2304 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64528,12 +64273,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2314 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + // Pos:2305 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64556,12 +64301,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2315 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + // Pos:2306 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64584,12 +64329,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2316 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + // Pos:2307 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64612,12 +64357,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2317 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + // Pos:2308 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64640,12 +64385,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2318 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" + // Pos:2309 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64668,12 +64413,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2319 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + // Pos:2310 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { .Instruction = ND_INS_SBB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 777, + .Mnemonic = 778, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64696,12 +64441,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2320 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + // Pos:2311 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 779, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64725,12 +64470,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2321 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + // Pos:2312 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 778, + .Mnemonic = 779, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64755,12 +64500,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2322 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + // Pos:2313 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 779, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64784,12 +64529,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2323 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + // Pos:2314 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 779, + .Mnemonic = 780, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64814,12 +64559,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2324 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + // Pos:2315 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 780, + .Mnemonic = 781, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64843,12 +64588,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2325 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + // Pos:2316 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 780, + .Mnemonic = 781, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64873,12 +64618,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2326 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + // Pos:2317 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 781, + .Mnemonic = 782, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64902,12 +64647,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2327 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + // Pos:2318 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { .Instruction = ND_INS_SCAS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 781, + .Mnemonic = 782, .ValidPrefixes = ND_PREF_REPC, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -64932,12 +64677,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2328 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" + // Pos:2319 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { .Instruction = ND_INS_SEAMCALL, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 782, + .Mnemonic = 783, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64958,12 +64703,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2329 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + // Pos:2320 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" { .Instruction = ND_INS_SEAMOPS, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 783, + .Mnemonic = 784, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -64988,12 +64733,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2330 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + // Pos:2321 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" { .Instruction = ND_INS_SEAMRET, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 784, + .Mnemonic = 785, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -65014,12 +64759,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2331 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" + // Pos:2322 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" { .Instruction = ND_INS_SENDUIPI, .Category = ND_CAT_UINTR, .IsaSet = ND_SET_UINTR, - .Mnemonic = 785, + .Mnemonic = 786, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -65040,12 +64785,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2332 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + // Pos:2323 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" { .Instruction = ND_INS_SERIALIZE, .Category = ND_CAT_MISC, .IsaSet = ND_SET_SERIALIZE, - .Mnemonic = 786, + .Mnemonic = 787, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65066,61 +64811,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2333 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 787, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ZU, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2334 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_I386, - .Mnemonic = 787, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2335 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M" + // Pos:2324 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, @@ -65134,7 +64825,7 @@ const ND_IDBE gInstructions[4075] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0|NDR_RFLAG_CF, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, @@ -65147,7 +64838,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2336 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + // Pos:2325 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, @@ -65161,6 +64852,60 @@ const ND_IDBE gInstructions[4075] = .ExcType = 0, .FpuFlags = 0, .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2326 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 789, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2327 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 789, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, .TestedFlags = 0|NDR_RFLAG_CF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65174,12 +64919,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2337 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M" + // Pos:2328 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 789, + .Mnemonic = 790, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65201,12 +64946,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2338 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + // Pos:2329 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 789, + .Mnemonic = 790, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65228,61 +64973,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2339 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 790, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ZU, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2340 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_I386, - .Mnemonic = 790, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2341 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M" + // Pos:2330 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, @@ -65296,6 +64987,60 @@ const ND_IDBE gInstructions[4075] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2331 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 791, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2332 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 792, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65309,12 +65054,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2342 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + // Pos:2333 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 791, + .Mnemonic = 792, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65336,12 +65081,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2343 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M" + // Pos:2334 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 792, + .Mnemonic = 793, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65363,12 +65108,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2344 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + // Pos:2335 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 792, + .Mnemonic = 793, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65390,12 +65135,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2345 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M" + // Pos:2336 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 793, + .Mnemonic = 794, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65417,12 +65162,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2346 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + // Pos:2337 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 793, + .Mnemonic = 794, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65444,61 +65189,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2347 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 794, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ZU, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2348 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_I386, - .Mnemonic = 794, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2349 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M" + // Pos:2338 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, @@ -65512,6 +65203,60 @@ const ND_IDBE gInstructions[4075] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2339 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 795, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2340 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 796, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, .TestedFlags = 0|NDR_RFLAG_OF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65525,12 +65270,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2350 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + // Pos:2341 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 795, + .Mnemonic = 796, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65552,12 +65297,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2351 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M" + // Pos:2342 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 796, + .Mnemonic = 797, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65579,12 +65324,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2352 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + // Pos:2343 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 796, + .Mnemonic = 797, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65606,61 +65351,7 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2353 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 797, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_ZU, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_INT, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0|NDR_RFLAG_SF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2354 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" - { - .Instruction = ND_INS_SETcc, - .Category = ND_CAT_BITBYTE, - .IsaSet = ND_SET_I386, - .Mnemonic = 797, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(1, 1), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0|NDR_RFLAG_SF, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2355 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M" + // Pos:2344 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, @@ -65674,6 +65365,60 @@ const ND_IDBE gInstructions[4075] = .ExcType = ND_EXT_APX_EVEX_INT, .FpuFlags = 0, .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2345 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 798, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2346 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 799, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, .TestedFlags = 0|NDR_RFLAG_ZF, .ModifiedFlags = 0, .SetFlags = 0, @@ -65687,12 +65432,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2356 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + // Pos:2347 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 798, + .Mnemonic = 799, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65714,12 +65459,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2357 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M" + // Pos:2348 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 799, + .Mnemonic = 800, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65741,12 +65486,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2358 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + // Pos:2349 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 799, + .Mnemonic = 800, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65768,12 +65513,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2359 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M" + // Pos:2350 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 800, + .Mnemonic = 801, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65795,12 +65540,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2360 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + // Pos:2351 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 800, + .Mnemonic = 801, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65822,12 +65567,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2361 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M" + // Pos:2352 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 801, + .Mnemonic = 802, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65849,12 +65594,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2362 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + // Pos:2353 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 801, + .Mnemonic = 802, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65876,12 +65621,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2363 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + // Pos:2354 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { .Instruction = ND_INS_SETSSBSY, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 802, + .Mnemonic = 803, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65903,12 +65648,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2364 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M" + // Pos:2355 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_APX_F, - .Mnemonic = 803, + .Mnemonic = 804, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ZU, @@ -65930,12 +65675,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2365 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + // Pos:2356 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { .Instruction = ND_INS_SETcc, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_I386, - .Mnemonic = 803, + .Mnemonic = 804, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65957,12 +65702,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2366 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + // Pos:2357 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { .Instruction = ND_INS_SFENCE, .Category = ND_CAT_MISC, .IsaSet = ND_SET_SSE2, - .Mnemonic = 804, + .Mnemonic = 805, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -65983,12 +65728,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2367 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + // Pos:2358 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { .Instruction = ND_INS_SGDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 805, + .Mnemonic = 806, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -66010,91 +65755,10 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2368 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r"/"RM" + // Pos:2359 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { .Instruction = ND_INS_SHA1MSG1, .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 806, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2369 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" - { - .Instruction = ND_INS_SHA1MSG1, - .Category = ND_CAT_SHA, - .IsaSet = ND_SET_SHA, - .Mnemonic = 806, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_SHA, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2370 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r"/"RM" - { - .Instruction = ND_INS_SHA1MSG2, - .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 807, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2371 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" - { - .Instruction = ND_INS_SHA1MSG2, - .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, .Mnemonic = 807, .ValidPrefixes = 0, @@ -66118,36 +65782,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2372 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r"/"RM" + // Pos:2360 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { - .Instruction = ND_INS_SHA1NEXTE, - .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 808, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2373 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" - { - .Instruction = ND_INS_SHA1NEXTE, + .Instruction = ND_INS_SHA1MSG2, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, .Mnemonic = 808, @@ -66172,40 +65809,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2374 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib"/"RMI" + // Pos:2361 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { - .Instruction = ND_INS_SHA1RNDS4, + .Instruction = ND_INS_SHA1NEXTE, .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, + .IsaSet = ND_SET_SHA, .Mnemonic = 809, .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, + .ExcType = ND_EXT_4, .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, + .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, .Operands = { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2375 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + // Pos:2362 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { .Instruction = ND_INS_SHA1RNDS4, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 809, + .Mnemonic = 810, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -66228,91 +65864,10 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2376 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r"/"RM" + // Pos:2363 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { .Instruction = ND_INS_SHA256MSG1, .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 810, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2377 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" - { - .Instruction = ND_INS_SHA256MSG1, - .Category = ND_CAT_SHA, - .IsaSet = ND_SET_SHA, - .Mnemonic = 810, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_SHA, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2378 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r"/"RM" - { - .Instruction = ND_INS_SHA256MSG2, - .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, - .Mnemonic = 811, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2379 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" - { - .Instruction = ND_INS_SHA256MSG2, - .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, .Mnemonic = 811, .ValidPrefixes = 0, @@ -66336,40 +65891,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2380 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r"/"RM" + // Pos:2364 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { - .Instruction = ND_INS_SHA256RNDS2, + .Instruction = ND_INS_SHA256MSG2, .Category = ND_CAT_SHA, - .IsaSet = ND_SET_APX_F, + .IsaSet = ND_SET_SHA, .Mnemonic = 812, .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 1), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_APX_EVEX_SHA, + .ExcType = ND_EXT_4, .FpuFlags = 0, - .EvexMode = ND_EVEXM_LEGACY, + .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_APX_F, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, .Operands = { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), }, }, - // Pos:2381 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + // Pos:2365 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { .Instruction = ND_INS_SHA256RNDS2, .Category = ND_CAT_SHA, .IsaSet = ND_SET_SHA, - .Mnemonic = 812, + .Mnemonic = 813, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -66392,12 +65946,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2382 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI" + // Pos:2366 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66420,12 +65974,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2383 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI" + // Pos:2367 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66448,12 +66002,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2384 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI" + // Pos:2368 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66476,12 +66030,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2385 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1" + // Pos:2369 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66504,12 +66058,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2386 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1" + // Pos:2370 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66532,12 +66086,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2387 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1" + // Pos:2371 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66560,12 +66114,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2388 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC" + // Pos:2372 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66588,12 +66142,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2389 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC" + // Pos:2373 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66616,12 +66170,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2390 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC" + // Pos:2374 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -66644,12 +66198,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2391 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI" + // Pos:2375 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66671,12 +66225,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2392 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI" + // Pos:2376 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66698,12 +66252,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2393 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI" + // Pos:2377 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66725,12 +66279,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2394 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1" + // Pos:2378 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66752,12 +66306,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2395 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1" + // Pos:2379 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66779,12 +66333,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2396 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1" + // Pos:2380 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66806,12 +66360,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2397 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC" + // Pos:2381 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66833,12 +66387,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2398 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC" + // Pos:2382 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66860,12 +66414,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2399 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC" + // Pos:2383 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -66887,12 +66441,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2400 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI" + // Pos:2384 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66916,12 +66470,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2401 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI" + // Pos:2385 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66945,12 +66499,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2402 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI" + // Pos:2386 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -66974,12 +66528,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2403 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1" + // Pos:2387 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67003,12 +66557,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2404 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1" + // Pos:2388 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67032,12 +66586,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2405 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1" + // Pos:2389 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67061,12 +66615,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2406 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC" + // Pos:2390 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67090,12 +66644,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2407 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC" + // Pos:2391 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67119,12 +66673,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2408 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC" + // Pos:2392 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67148,12 +66702,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2409 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI" + // Pos:2393 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67176,12 +66730,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2410 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI" + // Pos:2394 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67204,12 +66758,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2411 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI" + // Pos:2395 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67232,12 +66786,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2412 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1" + // Pos:2396 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67260,12 +66814,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2413 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1" + // Pos:2397 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67288,12 +66842,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2414 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1" + // Pos:2398 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67316,12 +66870,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2415 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC" + // Pos:2399 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67344,12 +66898,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2416 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC" + // Pos:2400 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67372,12 +66926,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2417 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC" + // Pos:2401 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67400,12 +66954,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2418 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + // Pos:2402 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67428,12 +66982,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2419 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + // Pos:2403 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67456,12 +67010,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2420 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + // Pos:2404 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67484,12 +67038,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2421 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + // Pos:2405 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67512,12 +67066,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2422 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + // Pos:2406 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67540,12 +67094,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2423 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + // Pos:2407 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { .Instruction = ND_INS_SHL, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 813, + .Mnemonic = 814, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -67568,12 +67122,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2424 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI" + // Pos:2408 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67597,12 +67151,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2425 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC" + // Pos:2409 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67626,12 +67180,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2426 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI" + // Pos:2410 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67655,12 +67209,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2427 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC" + // Pos:2411 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -67684,12 +67238,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2428 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI" + // Pos:2412 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67712,12 +67266,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2429 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC" + // Pos:2413 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67740,12 +67294,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2430 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI" + // Pos:2414 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67768,12 +67322,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2431 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC" + // Pos:2415 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -67796,12 +67350,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2432 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI" + // Pos:2416 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67826,12 +67380,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2433 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC" + // Pos:2417 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67856,12 +67410,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2434 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI" + // Pos:2418 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67886,12 +67440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2435 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC" + // Pos:2419 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -67916,12 +67470,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2436 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI" + // Pos:2420 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67945,12 +67499,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2437 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC" + // Pos:2421 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -67974,12 +67528,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2438 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI" + // Pos:2422 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68003,12 +67557,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2439 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC" + // Pos:2423 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68032,12 +67586,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2440 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + // Pos:2424 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68061,12 +67615,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2441 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + // Pos:2425 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { .Instruction = ND_INS_SHLD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 814, + .Mnemonic = 815, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -68090,12 +67644,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2442 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:2426 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHLX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 815, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68118,12 +67672,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2443 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + // Pos:2427 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHLX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 815, + .Mnemonic = 816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68146,12 +67700,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2444 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI" + // Pos:2428 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68174,12 +67728,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2445 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI" + // Pos:2429 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68202,12 +67756,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2446 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI" + // Pos:2430 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68230,12 +67784,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2447 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1" + // Pos:2431 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68258,12 +67812,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2448 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1" + // Pos:2432 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68286,12 +67840,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2449 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1" + // Pos:2433 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68314,12 +67868,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2450 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC" + // Pos:2434 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68342,12 +67896,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2451 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC" + // Pos:2435 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68370,12 +67924,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2452 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC" + // Pos:2436 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -68398,12 +67952,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2453 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI" + // Pos:2437 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68425,12 +67979,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2454 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI" + // Pos:2438 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68452,12 +68006,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2455 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI" + // Pos:2439 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68479,12 +68033,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2456 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1" + // Pos:2440 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68506,12 +68060,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2457 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1" + // Pos:2441 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68533,12 +68087,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2458 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1" + // Pos:2442 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68560,12 +68114,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2459 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC" + // Pos:2443 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68587,12 +68141,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2460 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC" + // Pos:2444 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68614,12 +68168,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2461 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC" + // Pos:2445 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -68641,12 +68195,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2462 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI" + // Pos:2446 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68670,12 +68224,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2463 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI" + // Pos:2447 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68699,12 +68253,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2464 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI" + // Pos:2448 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68728,12 +68282,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2465 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1" + // Pos:2449 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68757,12 +68311,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2466 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1" + // Pos:2450 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68786,12 +68340,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2467 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1" + // Pos:2451 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68815,12 +68369,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2468 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC" + // Pos:2452 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68844,12 +68398,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2469 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC" + // Pos:2453 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68873,12 +68427,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2470 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC" + // Pos:2454 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -68902,12 +68456,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2471 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI" + // Pos:2455 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68930,12 +68484,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2472 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI" + // Pos:2456 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68958,12 +68512,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2473 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI" + // Pos:2457 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -68986,12 +68540,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2474 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1" + // Pos:2458 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69014,12 +68568,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2475 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1" + // Pos:2459 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69042,12 +68596,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2476 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1" + // Pos:2460 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69070,12 +68624,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2477 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC" + // Pos:2461 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69098,12 +68652,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2478 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC" + // Pos:2462 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69126,12 +68680,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2479 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC" + // Pos:2463 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69154,12 +68708,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2480 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + // Pos:2464 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69182,12 +68736,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2481 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + // Pos:2465 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69210,12 +68764,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2482 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + // Pos:2466 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69238,12 +68792,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2483 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + // Pos:2467 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69266,12 +68820,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2484 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + // Pos:2468 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69294,12 +68848,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2485 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + // Pos:2469 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { .Instruction = ND_INS_SHR, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I86, - .Mnemonic = 816, + .Mnemonic = 817, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69322,12 +68876,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2486 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI" + // Pos:2470 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69351,12 +68905,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2487 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC" + // Pos:2471 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69380,12 +68934,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2488 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI" + // Pos:2472 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69409,12 +68963,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2489 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC" + // Pos:2473 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69438,12 +68992,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2490 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI" + // Pos:2474 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69466,12 +69020,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2491 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC" + // Pos:2475 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69494,12 +69048,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2492 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI" + // Pos:2476 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69522,12 +69076,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2493 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC" + // Pos:2477 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -69550,12 +69104,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2494 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI" + // Pos:2478 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69580,12 +69134,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2495 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC" + // Pos:2479 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69610,12 +69164,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2496 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI" + // Pos:2480 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69640,12 +69194,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2497 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC" + // Pos:2481 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -69670,12 +69224,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2498 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI" + // Pos:2482 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69699,12 +69253,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2499 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC" + // Pos:2483 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69728,12 +69282,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2500 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI" + // Pos:2484 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69757,12 +69311,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2501 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC" + // Pos:2485 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_APX_F, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -69786,12 +69340,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2502 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + // Pos:2486 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69815,12 +69369,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2503 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + // Pos:2487 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { .Instruction = ND_INS_SHRD, .Category = ND_CAT_SHIFT, .IsaSet = ND_SET_I386, - .Mnemonic = 817, + .Mnemonic = 818, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69844,12 +69398,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2504 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV" + // Pos:2488 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHRX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_APX_F, - .Mnemonic = 818, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69872,12 +69426,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2505 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + // Pos:2489 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { .Instruction = ND_INS_SHRX, .Category = ND_CAT_BMI2, .IsaSet = ND_SET_BMI2, - .Mnemonic = 818, + .Mnemonic = 819, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -69900,12 +69454,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2506 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + // Pos:2490 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { .Instruction = ND_INS_SHUFPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 819, + .Mnemonic = 820, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69928,12 +69482,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2507 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + // Pos:2491 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { .Instruction = ND_INS_SHUFPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 820, + .Mnemonic = 821, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -69956,12 +69510,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2508 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + // Pos:2492 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { .Instruction = ND_INS_SIDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 821, + .Mnemonic = 822, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -69983,12 +69537,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2509 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + // Pos:2493 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { .Instruction = ND_INS_SKINIT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 822, + .Mnemonic = 823, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -70009,12 +69563,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2510 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + // Pos:2494 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { .Instruction = ND_INS_SLDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 823, + .Mnemonic = 824, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70036,12 +69590,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2511 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + // Pos:2495 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { .Instruction = ND_INS_SLDT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 823, + .Mnemonic = 824, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70063,12 +69617,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2512 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + // Pos:2496 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { .Instruction = ND_INS_SLWPCB, .Category = ND_CAT_LWP, .IsaSet = ND_SET_LWP, - .Mnemonic = 824, + .Mnemonic = 825, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70089,12 +69643,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2513 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + // Pos:2497 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { .Instruction = ND_INS_SMSW, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 825, + .Mnemonic = 826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70116,12 +69670,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2514 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + // Pos:2498 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { .Instruction = ND_INS_SMSW, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286REAL, - .Mnemonic = 825, + .Mnemonic = 826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70143,12 +69697,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2515 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + // Pos:2499 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { .Instruction = ND_INS_SPFLT, .Category = ND_CAT_UNKNOWN, .IsaSet = ND_SET_UNKNOWN, - .Mnemonic = 826, + .Mnemonic = 827, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70169,12 +69723,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2516 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + // Pos:2500 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 827, + .Mnemonic = 828, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70196,12 +69750,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2517 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + // Pos:2501 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 828, + .Mnemonic = 829, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70223,12 +69777,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2518 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + // Pos:2502 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 829, + .Mnemonic = 830, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70250,12 +69804,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2519 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + // Pos:2503 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { .Instruction = ND_INS_SQRTSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 830, + .Mnemonic = 831, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70277,12 +69831,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2520 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + // Pos:2504 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { .Instruction = ND_INS_STAC, .Category = ND_CAT_SMAP, .IsaSet = ND_SET_SMAP, - .Mnemonic = 831, + .Mnemonic = 832, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70303,12 +69857,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2521 Instruction:"STC" Encoding:"0xF9"/"" + // Pos:2505 Instruction:"STC" Encoding:"0xF9"/"" { .Instruction = ND_INS_STC, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 832, + .Mnemonic = 833, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70329,12 +69883,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2522 Instruction:"STD" Encoding:"0xFD"/"" + // Pos:2506 Instruction:"STD" Encoding:"0xFD"/"" { .Instruction = ND_INS_STD, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 833, + .Mnemonic = 834, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70355,12 +69909,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2523 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + // Pos:2507 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { .Instruction = ND_INS_STGI, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 834, + .Mnemonic = 835, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -70381,12 +69935,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2524 Instruction:"STI" Encoding:"0xFB"/"" + // Pos:2508 Instruction:"STI" Encoding:"0xFB"/"" { .Instruction = ND_INS_STI, .Category = ND_CAT_FLAGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 835, + .Mnemonic = 836, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70407,12 +69961,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2525 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + // Pos:2509 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { .Instruction = ND_INS_STMXCSR, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 836, + .Mnemonic = 837, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70434,12 +69988,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2526 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + // Pos:2510 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 837, + .Mnemonic = 838, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70463,12 +70017,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2527 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + // Pos:2511 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 837, + .Mnemonic = 838, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70493,12 +70047,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2528 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + // Pos:2512 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 838, + .Mnemonic = 839, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70522,12 +70076,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2529 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + // Pos:2513 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 838, + .Mnemonic = 839, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70552,12 +70106,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2530 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + // Pos:2514 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 839, + .Mnemonic = 840, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70581,12 +70135,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2531 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + // Pos:2515 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 839, + .Mnemonic = 840, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70611,12 +70165,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2532 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + // Pos:2516 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 840, + .Mnemonic = 841, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70640,12 +70194,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2533 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + // Pos:2517 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { .Instruction = ND_INS_STOS, .Category = ND_CAT_STRINGOP, .IsaSet = ND_SET_I86, - .Mnemonic = 840, + .Mnemonic = 841, .ValidPrefixes = ND_PREF_REP, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -70670,12 +70224,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2534 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + // Pos:2518 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { .Instruction = ND_INS_STR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 841, + .Mnemonic = 842, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70697,12 +70251,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2535 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + // Pos:2519 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { .Instruction = ND_INS_STR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 841, + .Mnemonic = 842, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70724,12 +70278,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2536 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M" + // Pos:2520 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M" { .Instruction = ND_INS_STTILECFG, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 842, + .Mnemonic = 843, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70750,12 +70304,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2537 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + // Pos:2521 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { .Instruction = ND_INS_STTILECFG, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 842, + .Mnemonic = 843, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70776,12 +70330,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2538 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" + // Pos:2522 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" { .Instruction = ND_INS_STUI, .Category = ND_CAT_UINTR, .IsaSet = ND_SET_UINTR, - .Mnemonic = 843, + .Mnemonic = 844, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -70802,12 +70356,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2539 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR" + // Pos:2523 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70830,12 +70384,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2540 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR" + // Pos:2524 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70858,12 +70412,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2541 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR" + // Pos:2525 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70886,12 +70440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2542 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM" + // Pos:2526 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70914,12 +70468,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2543 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM" + // Pos:2527 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70942,12 +70496,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2544 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM" + // Pos:2528 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70970,12 +70524,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2545 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI" + // Pos:2529 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -70998,12 +70552,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2546 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI" + // Pos:2530 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -71026,12 +70580,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2547 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI" + // Pos:2531 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -71054,12 +70608,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2548 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI" + // Pos:2532 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -71082,12 +70636,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2549 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI" + // Pos:2533 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -71110,12 +70664,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2550 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR" + // Pos:2534 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71137,12 +70691,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2551 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR" + // Pos:2535 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71164,12 +70718,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2552 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR" + // Pos:2536 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71191,12 +70745,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2553 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM" + // Pos:2537 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71218,12 +70772,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2554 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM" + // Pos:2538 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71245,12 +70799,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2555 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM" + // Pos:2539 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71272,12 +70826,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2556 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI" + // Pos:2540 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71299,12 +70853,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2557 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI" + // Pos:2541 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71326,12 +70880,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2558 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI" + // Pos:2542 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71353,12 +70907,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2559 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI" + // Pos:2543 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71380,12 +70934,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2560 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI" + // Pos:2544 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -71407,12 +70961,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2561 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR" + // Pos:2545 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71436,12 +70990,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2562 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR" + // Pos:2546 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71465,12 +71019,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2563 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR" + // Pos:2547 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71494,12 +71048,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2564 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM" + // Pos:2548 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71523,12 +71077,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2565 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM" + // Pos:2549 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71552,12 +71106,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2566 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM" + // Pos:2550 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71581,12 +71135,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2567 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI" + // Pos:2551 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71610,12 +71164,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2568 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI" + // Pos:2552 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71639,12 +71193,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2569 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI" + // Pos:2553 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71668,12 +71222,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2570 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI" + // Pos:2554 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71697,12 +71251,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2571 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI" + // Pos:2555 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -71726,12 +71280,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2572 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR" + // Pos:2556 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71754,12 +71308,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2573 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR" + // Pos:2557 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71782,12 +71336,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2574 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR" + // Pos:2558 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71810,12 +71364,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2575 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM" + // Pos:2559 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71838,12 +71392,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2576 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM" + // Pos:2560 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71866,12 +71420,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2577 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM" + // Pos:2561 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71894,12 +71448,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2578 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI" + // Pos:2562 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71922,12 +71476,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2579 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI" + // Pos:2563 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71950,12 +71504,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2580 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI" + // Pos:2564 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -71978,12 +71532,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2581 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI" + // Pos:2565 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -72006,12 +71560,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2582 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI" + // Pos:2566 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_APX_F, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -72034,12 +71588,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2583 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + // Pos:2567 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72062,12 +71616,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2584 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + // Pos:2568 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72090,12 +71644,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2585 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + // Pos:2569 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72118,12 +71672,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2586 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + // Pos:2570 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72146,12 +71700,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2587 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + // Pos:2571 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72174,12 +71728,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2588 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + // Pos:2572 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72202,12 +71756,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2589 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + // Pos:2573 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72230,12 +71784,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2590 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + // Pos:2574 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72258,12 +71812,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2591 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + // Pos:2575 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72286,12 +71840,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2592 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + // Pos:2576 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { .Instruction = ND_INS_SUB, .Category = ND_CAT_ARITH, .IsaSet = ND_SET_I86, - .Mnemonic = 844, + .Mnemonic = 845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72314,12 +71868,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2593 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + // Pos:2577 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 845, + .Mnemonic = 846, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72341,12 +71895,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2594 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + // Pos:2578 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 846, + .Mnemonic = 847, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72368,12 +71922,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2595 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + // Pos:2579 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBSD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 847, + .Mnemonic = 848, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72395,12 +71949,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2596 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + // Pos:2580 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { .Instruction = ND_INS_SUBSS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 848, + .Mnemonic = 849, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72422,12 +71976,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2597 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + // Pos:2581 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { .Instruction = ND_INS_SWAPGS, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_LONGMODE, - .Mnemonic = 849, + .Mnemonic = 850, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72449,12 +72003,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2598 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + // Pos:2582 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { .Instruction = ND_INS_SYSCALL, .Category = ND_CAT_SYSCALL, .IsaSet = ND_SET_AMD, - .Mnemonic = 850, + .Mnemonic = 851, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72484,12 +72038,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2599 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + // Pos:2583 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { .Instruction = ND_INS_SYSENTER, .Category = ND_CAT_SYSCALL, .IsaSet = ND_SET_PPRO, - .Mnemonic = 851, + .Mnemonic = 852, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72518,12 +72072,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2600 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + // Pos:2584 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { .Instruction = ND_INS_SYSEXIT, .Category = ND_CAT_SYSRET, .IsaSet = ND_SET_PPRO, - .Mnemonic = 852, + .Mnemonic = 853, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72551,12 +72105,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2601 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + // Pos:2585 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { .Instruction = ND_INS_SYSRET, .Category = ND_CAT_SYSRET, .IsaSet = ND_SET_AMD, - .Mnemonic = 853, + .Mnemonic = 854, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72584,12 +72138,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2602 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + // Pos:2586 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { .Instruction = ND_INS_T1MSKC, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_TBM, - .Mnemonic = 854, + .Mnemonic = 855, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -72611,39 +72165,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2603 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" + // Pos:2587 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" { .Instruction = ND_INS_TCMMIMFP16PS, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXCOMPLEX, - .Mnemonic = 855, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_AMX_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, - .CpuidFlag = ND_CFF_AMXCOMPLEX, - .Operands = - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2604 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" - { - .Instruction = ND_INS_TCMMRLFP16PS, - .Category = ND_CAT_AMX, - .IsaSet = ND_SET_AMXCOMPLEX, .Mnemonic = 856, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, @@ -72667,12 +72193,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2605 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + // Pos:2588 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TCMMRLFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXCOMPLEX, + .Mnemonic = 857, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXCOMPLEX, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2589 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" { .Instruction = ND_INS_TDCALL, .Category = ND_CAT_TDX, .IsaSet = ND_SET_TDX, - .Mnemonic = 857, + .Mnemonic = 858, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72693,12 +72247,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2606 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + // Pos:2590 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { .Instruction = ND_INS_TDPBF16PS, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXBF16, - .Mnemonic = 858, + .Mnemonic = 859, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72721,39 +72275,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2607 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + // Pos:2591 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { .Instruction = ND_INS_TDPBSSD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, - .Mnemonic = 859, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_AMX_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, - .CpuidFlag = ND_CFF_AMXINT8, - .Operands = - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2608 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" - { - .Instruction = ND_INS_TDPBSUD, - .Category = ND_CAT_AMX, - .IsaSet = ND_SET_AMXINT8, .Mnemonic = 860, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, @@ -72777,9 +72303,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2609 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + // Pos:2592 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { - .Instruction = ND_INS_TDPBUSD, + .Instruction = ND_INS_TDPBSUD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, .Mnemonic = 861, @@ -72805,9 +72331,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2610 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + // Pos:2593 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { - .Instruction = ND_INS_TDPBUUD, + .Instruction = ND_INS_TDPBUSD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXINT8, .Mnemonic = 862, @@ -72833,12 +72359,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2611 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" + // Pos:2594 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + { + .Instruction = ND_INS_TDPBUUD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXINT8, + .Mnemonic = 863, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXINT8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2595 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" { .Instruction = ND_INS_TDPFP16PS, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXFP16, - .Mnemonic = 863, + .Mnemonic = 864, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -72861,12 +72415,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2612 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + // Pos:2596 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72889,12 +72443,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2613 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + // Pos:2597 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72917,12 +72471,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2614 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + // Pos:2598 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72945,12 +72499,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2615 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + // Pos:2599 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -72973,12 +72527,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2616 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + // Pos:2600 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73001,12 +72555,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2617 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + // Pos:2601 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73029,12 +72583,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2618 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + // Pos:2602 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73057,12 +72611,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2619 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + // Pos:2603 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { .Instruction = ND_INS_TEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 864, + .Mnemonic = 865, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73085,12 +72639,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2620 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" + // Pos:2604 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" { .Instruction = ND_INS_TESTUI, .Category = ND_CAT_UINTR, .IsaSet = ND_SET_UINTR, - .Mnemonic = 865, + .Mnemonic = 866, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73112,65 +72666,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2621 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + // Pos:2605 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" { .Instruction = ND_INS_TILELOADD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 866, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_AMX_EVEX_E3, - .FpuFlags = 0, - .EvexMode = ND_EVEXM_VEX, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, - .CpuidFlag = ND_CFF_APX_F, - .Operands = - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2622 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" - { - .Instruction = ND_INS_TILELOADD, - .Category = ND_CAT_AMX, - .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 866, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_AMX_E3, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, - .CpuidFlag = ND_CFF_AMXTILE, - .Operands = - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2623 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" - { - .Instruction = ND_INS_TILELOADDT1, - .Category = ND_CAT_AMX, - .IsaSet = ND_SET_APX_F, .Mnemonic = 867, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, @@ -73193,9 +72693,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2624 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:2606 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { - .Instruction = ND_INS_TILELOADDT1, + .Instruction = ND_INS_TILELOADD, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, .Mnemonic = 867, @@ -73220,12 +72720,66 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2625 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + // Pos:2607 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + { + .Instruction = ND_INS_TILELOADDT1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 868, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E3, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2608 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + .Instruction = ND_INS_TILELOADDT1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 868, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2609 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { .Instruction = ND_INS_TILERELEASE, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 868, + .Mnemonic = 869, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73246,12 +72800,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2626 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + // Pos:2610 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" { .Instruction = ND_INS_TILESTORED, .Category = ND_CAT_AMX, .IsaSet = ND_SET_APX_F, - .Mnemonic = 869, + .Mnemonic = 870, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73273,12 +72827,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2627 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:2611 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { .Instruction = ND_INS_TILESTORED, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 869, + .Mnemonic = 870, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73300,12 +72854,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2628 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + // Pos:2612 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { .Instruction = ND_INS_TILEZERO, .Category = ND_CAT_AMX, .IsaSet = ND_SET_AMXTILE, - .Mnemonic = 870, + .Mnemonic = 871, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73326,12 +72880,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2629 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/"" + // Pos:2613 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/"" { .Instruction = ND_INS_TLBSYNC, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_INVLPGB, - .Mnemonic = 871, + .Mnemonic = 872, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73352,12 +72906,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2630 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + // Pos:2614 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { .Instruction = ND_INS_TPAUSE, .Category = ND_CAT_WAITPKG, .IsaSet = ND_SET_WAITPKG, - .Mnemonic = 872, + .Mnemonic = 873, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73381,12 +72935,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2631 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM" + // Pos:2615 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 873, + .Mnemonic = 874, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73409,12 +72963,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2632 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM" + // Pos:2616 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 873, + .Mnemonic = 874, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73437,12 +72991,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2633 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM" + // Pos:2617 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 873, + .Mnemonic = 874, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -73464,12 +73018,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2634 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM" + // Pos:2618 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_APX_F, - .Mnemonic = 873, + .Mnemonic = 874, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -73491,12 +73045,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2635 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM" + // Pos:2619 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM" { .Instruction = ND_INS_TZCNT, .Category = ND_CAT_BMI1, .IsaSet = ND_SET_BMI1, - .Mnemonic = 873, + .Mnemonic = 874, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73519,12 +73073,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2636 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + // Pos:2620 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { .Instruction = ND_INS_TZMSK, .Category = ND_CAT_BITBYTE, .IsaSet = ND_SET_TBM, - .Mnemonic = 874, + .Mnemonic = 875, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73546,12 +73100,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2637 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + // Pos:2621 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { .Instruction = ND_INS_UCOMISD, .Category = ND_CAT_SSE2, .IsaSet = ND_SET_SSE2, - .Mnemonic = 875, + .Mnemonic = 876, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73574,12 +73128,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2638 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + // Pos:2622 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { .Instruction = ND_INS_UCOMISS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 876, + .Mnemonic = 877, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73602,38 +73156,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2639 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + // Pos:2623 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { .Instruction = ND_INS_UD0, .Category = ND_CAT_UD, .IsaSet = ND_SET_UD, - .Mnemonic = 877, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM, - .CpuidFlag = 0, - .Operands = - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2640 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" - { - .Instruction = ND_INS_UD1, - .Category = ND_CAT_UD, - .IsaSet = ND_SET_UD, .Mnemonic = 878, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, @@ -73656,12 +73183,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2641 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + // Pos:2624 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + { + .Instruction = ND_INS_UD1, + .Category = ND_CAT_UD, + .IsaSet = ND_SET_UD, + .Mnemonic = 879, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2625 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { .Instruction = ND_INS_UD2, .Category = ND_CAT_MISC, .IsaSet = ND_SET_PPRO, - .Mnemonic = 879, + .Mnemonic = 880, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73682,12 +73236,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2642 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" + // Pos:2626 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" { .Instruction = ND_INS_UIRET, .Category = ND_CAT_RET, .IsaSet = ND_SET_UINTR, - .Mnemonic = 880, + .Mnemonic = 881, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73713,12 +73267,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2643 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + // Pos:2627 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" { .Instruction = ND_INS_UMONITOR, .Category = ND_CAT_WAITPKG, .IsaSet = ND_SET_WAITPKG, - .Mnemonic = 881, + .Mnemonic = 882, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73740,12 +73294,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2644 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + // Pos:2628 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { .Instruction = ND_INS_UMWAIT, .Category = ND_CAT_WAITPKG, .IsaSet = ND_SET_WAITPKG, - .Mnemonic = 882, + .Mnemonic = 883, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73768,38 +73322,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2645 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + // Pos:2629 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { .Instruction = ND_INS_UNPCKHPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 883, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_ANY, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_SSE2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2646 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" - { - .Instruction = ND_INS_UNPCKHPS, - .Category = ND_CAT_SSE, - .IsaSet = ND_SET_SSE, .Mnemonic = 884, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, @@ -73814,6 +73341,33 @@ const ND_IDBE gInstructions[4075] = .SetFlags = 0, .ClearedFlags = 0, .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2630 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + { + .Instruction = ND_INS_UNPCKHPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 885, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, .CpuidFlag = ND_CFF_SSE, .Operands = { @@ -73822,12 +73376,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2647 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + // Pos:2631 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { .Instruction = ND_INS_UNPCKLPD, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE2, - .Mnemonic = 885, + .Mnemonic = 886, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73849,12 +73403,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2648 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + // Pos:2632 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { .Instruction = ND_INS_UNPCKLPS, .Category = ND_CAT_SSE, .IsaSet = ND_SET_SSE, - .Mnemonic = 886, + .Mnemonic = 887, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -73876,12 +73430,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2649 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR" + // Pos:2633 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 887, + .Mnemonic = 888, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -73903,12 +73457,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2650 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" + // Pos:2634 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 887, + .Mnemonic = 888, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73931,12 +73485,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2651 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR" + // Pos:2635 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 887, + .Mnemonic = 888, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73959,12 +73513,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2652 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" + // Pos:2636 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" { .Instruction = ND_INS_URDMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 887, + .Mnemonic = 888, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -73987,12 +73541,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2653 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM" + // Pos:2637 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 888, + .Mnemonic = 889, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74014,12 +73568,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2654 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" + // Pos:2638 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_APX_F, - .Mnemonic = 888, + .Mnemonic = 889, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -74042,12 +73596,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2655 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM" + // Pos:2639 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 888, + .Mnemonic = 889, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -74070,12 +73624,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2656 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" + // Pos:2640 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" { .Instruction = ND_INS_UWRMSR, .Category = ND_CAT_USER_MSR, .IsaSet = ND_SET_USER_MSR, - .Mnemonic = 888, + .Mnemonic = 889, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -74098,12 +73652,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2657 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + // Pos:2641 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { .Instruction = ND_INS_V4FMADDPS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 889, + .Mnemonic = 890, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -74127,12 +73681,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2658 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + // Pos:2642 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { .Instruction = ND_INS_V4FMADDSS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 890, + .Mnemonic = 891, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -74156,12 +73710,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2659 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + // Pos:2643 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { .Instruction = ND_INS_V4FNMADDPS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 891, + .Mnemonic = 892, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -74185,12 +73739,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2660 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + // Pos:2644 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { .Instruction = ND_INS_V4FNMADDSS, .Category = ND_CAT_VFMAPS, .IsaSet = ND_SET_AVX5124FMAPS, - .Mnemonic = 892, + .Mnemonic = 893, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -74214,12 +73768,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2661 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + // Pos:2645 Instruction:"VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDNEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 894, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2646 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 893, + .Mnemonic = 895, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -74243,12 +73826,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2662 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + // Pos:2647 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 893, + .Mnemonic = 895, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74271,12 +73854,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2663 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:2648 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 894, + .Mnemonic = 896, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -74300,12 +73883,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2664 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:2649 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 895, + .Mnemonic = 897, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -74329,12 +73912,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2665 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + // Pos:2650 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 895, + .Mnemonic = 897, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74357,12 +73940,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2666 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + // Pos:2651 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 896, + .Mnemonic = 898, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -74386,12 +73969,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2667 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + // Pos:2652 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 896, + .Mnemonic = 898, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74414,12 +73997,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2668 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:2653 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 897, + .Mnemonic = 899, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -74443,12 +74026,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2669 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:2654 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { .Instruction = ND_INS_VADDSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 898, + .Mnemonic = 900, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -74472,12 +74055,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2670 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + // Pos:2655 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { .Instruction = ND_INS_VADDSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 898, + .Mnemonic = 900, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74500,12 +74083,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2671 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + // Pos:2656 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { .Instruction = ND_INS_VADDSUBPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 899, + .Mnemonic = 901, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74528,12 +74111,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2672 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + // Pos:2657 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { .Instruction = ND_INS_VADDSUBPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 900, + .Mnemonic = 902, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -74556,123 +74139,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2673 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:2658 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { .Instruction = ND_INS_VAESDEC, .Category = ND_CAT_VAES, .IsaSet = ND_SET_VAES, - .Mnemonic = 901, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NF, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_VAES, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2674 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" - { - .Instruction = ND_INS_VAESDEC, - .Category = ND_CAT_AES, - .IsaSet = ND_SET_AES, - .Mnemonic = 901, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AES, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2675 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" - { - .Instruction = ND_INS_VAESDECLAST, - .Category = ND_CAT_VAES, - .IsaSet = ND_SET_VAES, - .Mnemonic = 902, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NF, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_VAES, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2676 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" - { - .Instruction = ND_INS_VAESDECLAST, - .Category = ND_CAT_AES, - .IsaSet = ND_SET_AES, - .Mnemonic = 902, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AES, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2677 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" - { - .Instruction = ND_INS_VAESENC, - .Category = ND_CAT_VAES, - .IsaSet = ND_SET_VAES, .Mnemonic = 903, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, @@ -74696,9 +74167,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2678 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:2659 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - .Instruction = ND_INS_VAESENC, + .Instruction = ND_INS_VAESDEC, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, .Mnemonic = 903, @@ -74724,9 +74195,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2679 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:2660 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - .Instruction = ND_INS_VAESENCLAST, + .Instruction = ND_INS_VAESDECLAST, .Category = ND_CAT_VAES, .IsaSet = ND_SET_VAES, .Mnemonic = 904, @@ -74752,9 +74223,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2680 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:2661 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - .Instruction = ND_INS_VAESENCLAST, + .Instruction = ND_INS_VAESDECLAST, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, .Mnemonic = 904, @@ -74780,16 +74251,44 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2681 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + // Pos:2662 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - .Instruction = ND_INS_VAESIMC, + .Instruction = ND_INS_VAESENC, + .Category = ND_CAT_VAES, + .IsaSet = ND_SET_VAES, + .Mnemonic = 905, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VAES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2663 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + .Instruction = ND_INS_VAESENC, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, .Mnemonic = 905, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), + .OpsCount = ND_OPS_CNT(3, 0), .TupleType = 0, .ExcType = ND_EXT_4, .FpuFlags = 0, @@ -74798,18 +74297,47 @@ const ND_IDBE gInstructions[4075] = .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, .CpuidFlag = ND_CFF_AES, .Operands = { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2682 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + // Pos:2664 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - .Instruction = ND_INS_VAESKEYGENASSIST, + .Instruction = ND_INS_VAESENCLAST, + .Category = ND_CAT_VAES, + .IsaSet = ND_SET_VAES, + .Mnemonic = 906, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VAES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2665 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + .Instruction = ND_INS_VAESENCLAST, .Category = ND_CAT_AES, .IsaSet = ND_SET_AES, .Mnemonic = 906, @@ -74825,6 +74353,61 @@ const ND_IDBE gInstructions[4075] = .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2666 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + { + .Instruction = ND_INS_VAESIMC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 907, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2667 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + { + .Instruction = ND_INS_VAESKEYGENASSIST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 908, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, .CpuidFlag = ND_CFF_AES, .Operands = @@ -74835,12 +74418,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2683 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + // Pos:2668 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { .Instruction = ND_INS_VALIGND, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 907, + .Mnemonic = 909, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74865,12 +74448,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2684 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + // Pos:2669 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { .Instruction = ND_INS_VALIGNQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 908, + .Mnemonic = 910, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -74895,125 +74478,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2685 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + // Pos:2670 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { .Instruction = ND_INS_VANDNPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 909, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2686 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" - { - .Instruction = ND_INS_VANDNPD, - .Category = ND_CAT_LOGICAL_FP, - .IsaSet = ND_SET_AVX, - .Mnemonic = 909, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2687 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" - { - .Instruction = ND_INS_VANDNPS, - .Category = ND_CAT_LOGICAL_FP, - .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 910, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2688 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" - { - .Instruction = ND_INS_VANDNPS, - .Category = ND_CAT_LOGICAL_FP, - .IsaSet = ND_SET_AVX, - .Mnemonic = 910, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2689 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" - { - .Instruction = ND_INS_VANDPD, - .Category = ND_CAT_LOGICAL_FP, - .IsaSet = ND_SET_AVX512DQ, .Mnemonic = 911, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, @@ -75038,9 +74507,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2690 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + // Pos:2671 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { - .Instruction = ND_INS_VANDPD, + .Instruction = ND_INS_VANDNPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, .Mnemonic = 911, @@ -75066,9 +74535,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2691 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + // Pos:2672 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { - .Instruction = ND_INS_VANDPS, + .Instruction = ND_INS_VANDNPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, .Mnemonic = 912, @@ -75095,9 +74564,9 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2692 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + // Pos:2673 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { - .Instruction = ND_INS_VANDPS, + .Instruction = ND_INS_VANDNPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, .Mnemonic = 912, @@ -75123,39 +74592,126 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2693 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" + // Pos:2674 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { - .Instruction = ND_INS_VBCSTNEBF162PS, - .Category = ND_CAT_AVXNECONVERT, - .IsaSet = ND_SET_AVXNECONVERT, + .Instruction = ND_INS_VANDPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 913, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:2675 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + { + .Instruction = ND_INS_VANDPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, .Mnemonic = 913, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), + .OpsCount = ND_OPS_CNT(3, 0), .TupleType = 0, - .ExcType = ND_EXT_5, + .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVXNECONVERT, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2694 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" + // Pos:2676 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { - .Instruction = ND_INS_VBCSTNESH2PS, + .Instruction = ND_INS_VANDPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 914, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2677 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + { + .Instruction = ND_INS_VANDPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 914, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2678 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" + { + .Instruction = ND_INS_VBCSTNEBF162PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 914, + .Mnemonic = 915, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75177,12 +74733,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2695 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + // Pos:2679 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" + { + .Instruction = ND_INS_VBCSTNESH2PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 916, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2680 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" { .Instruction = ND_INS_VBLENDMPD, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 915, + .Mnemonic = 917, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -75206,12 +74789,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2696 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + // Pos:2681 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { .Instruction = ND_INS_VBLENDMPS, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 916, + .Mnemonic = 918, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -75235,69 +74818,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2697 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + // Pos:2682 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { .Instruction = ND_INS_VBLENDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 917, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2698 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" - { - .Instruction = ND_INS_VBLENDPS, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 918, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2699 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" - { - .Instruction = ND_INS_VBLENDVPD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, .Mnemonic = 919, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, @@ -75311,20 +74836,20 @@ const ND_IDBE gInstructions[4075] = .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, .CpuidFlag = ND_CFF_AVX, .Operands = { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:2700 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + // Pos:2683 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { - .Instruction = ND_INS_VBLENDVPS, + .Instruction = ND_INS_VBLENDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 920, @@ -75340,6 +74865,35 @@ const ND_IDBE gInstructions[4075] = .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2684 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + { + .Instruction = ND_INS_VBLENDVPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 921, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, .CpuidFlag = ND_CFF_AVX, .Operands = @@ -75351,12 +74905,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2701 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + // Pos:2685 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + { + .Instruction = ND_INS_VBLENDVPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 922, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2686 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { .Instruction = ND_INS_VBROADCASTF128, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX, - .Mnemonic = 921, + .Mnemonic = 923, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75378,12 +74961,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2702 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + // Pos:2687 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTF32X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 922, + .Mnemonic = 924, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75406,12 +74989,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2703 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + // Pos:2688 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF32X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 923, + .Mnemonic = 925, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75434,12 +75017,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2704 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + // Pos:2689 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF32X8, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 924, + .Mnemonic = 926, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75462,12 +75045,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2705 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + // Pos:2690 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF64X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 925, + .Mnemonic = 927, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75490,12 +75073,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2706 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + // Pos:2691 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTF64X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 926, + .Mnemonic = 928, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75518,12 +75101,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2707 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + // Pos:2692 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { .Instruction = ND_INS_VBROADCASTI128, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 927, + .Mnemonic = 929, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75545,12 +75128,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2708 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + // Pos:2693 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTI32X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 928, + .Mnemonic = 930, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75573,12 +75156,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2709 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + // Pos:2694 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI32X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 929, + .Mnemonic = 931, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75601,12 +75184,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2710 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + // Pos:2695 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI32X8, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 930, + .Mnemonic = 932, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75629,12 +75212,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2711 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + // Pos:2696 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI64X2, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 931, + .Mnemonic = 933, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75657,12 +75240,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2712 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + // Pos:2697 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { .Instruction = ND_INS_VBROADCASTI64X4, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 932, + .Mnemonic = 934, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75685,12 +75268,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2713 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + // Pos:2698 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTSD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 933, + .Mnemonic = 935, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75713,12 +75296,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2714 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + // Pos:2699 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { .Instruction = ND_INS_VBROADCASTSD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX, - .Mnemonic = 933, + .Mnemonic = 935, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75740,12 +75323,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2715 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + // Pos:2700 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { .Instruction = ND_INS_VBROADCASTSS, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 934, + .Mnemonic = 936, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -75768,12 +75351,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2716 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + // Pos:2701 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { .Instruction = ND_INS_VBROADCASTSS, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX, - .Mnemonic = 934, + .Mnemonic = 936, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75795,12 +75378,42 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2717 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:2702 Instruction:"VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 937, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2703 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 935, + .Mnemonic = 938, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -75825,12 +75438,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2718 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + // Pos:2704 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 935, + .Mnemonic = 938, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75854,12 +75467,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2719 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2705 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 936, + .Mnemonic = 939, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -75884,12 +75497,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2720 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2706 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 937, + .Mnemonic = 940, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -75914,12 +75527,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2721 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:2707 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 937, + .Mnemonic = 940, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -75943,12 +75556,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2722 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:2708 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 938, + .Mnemonic = 941, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, @@ -75973,12 +75586,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2723 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:2709 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 938, + .Mnemonic = 941, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76002,12 +75615,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2724 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" + // Pos:2710 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 939, + .Mnemonic = 942, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, @@ -76032,12 +75645,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2725 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:2711 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { .Instruction = ND_INS_VCMPSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 940, + .Mnemonic = 943, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, @@ -76062,12 +75675,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2726 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:2712 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { .Instruction = ND_INS_VCMPSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 940, + .Mnemonic = 943, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76091,12 +75704,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2727 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + // Pos:2713 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 941, + .Mnemonic = 944, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -76119,12 +75732,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2728 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + // Pos:2714 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 941, + .Mnemonic = 944, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76147,12 +75760,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2729 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:2715 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 942, + .Mnemonic = 945, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -76175,12 +75788,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2730 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:2716 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 943, + .Mnemonic = 946, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -76203,12 +75816,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2731 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + // Pos:2717 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { .Instruction = ND_INS_VCOMISS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 943, + .Mnemonic = 946, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76231,12 +75844,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2732 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + // Pos:2718 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { .Instruction = ND_INS_VCOMPRESSPD, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 944, + .Mnemonic = 947, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -76259,12 +75872,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2733 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + // Pos:2719 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { .Instruction = ND_INS_VCOMPRESSPS, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 945, + .Mnemonic = 948, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -76287,12 +75900,269 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2734 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + // Pos:2720 Instruction:"VCOMSBF16 Vdq,Wsh" Encoding:"evex m:5 p:1 l:i w:0 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMSBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 949, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E10NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2721 Instruction:"VCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:2 l:0 w:1 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMXSD, + .Category = ND_CAT_AVX10CMPSFP, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 950, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2722 Instruction:"VCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:3 l:0 w:0 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMXSH, + .Category = ND_CAT_AVX10CMPSFP, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 951, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2723 Instruction:"VCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:3 l:0 w:0 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMXSS, + .Category = ND_CAT_AVX10CMPSFP, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 952, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2724 Instruction:"VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x67 /r"/"RAVM" + { + .Instruction = ND_INS_VCVT2PS2PHX, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 953, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2725 Instruction:"VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:2 p:0 l:x w:0 0x74 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTBIASPH2BF8, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 954, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2726 Instruction:"VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x74 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTBIASPH2BF8S, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 955, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2727 Instruction:"VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x18 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTBIASPH2HF8, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 956, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2728 Instruction:"VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:0 l:x w:0 0x1B /r"/"RAVM" + { + .Instruction = ND_INS_VCVTBIASPH2HF8S, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 957, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2729 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 946, + .Mnemonic = 958, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76315,12 +76185,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2735 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + // Pos:2730 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 946, + .Mnemonic = 958, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76342,12 +76212,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2736 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + // Pos:2731 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 946, + .Mnemonic = 958, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76369,12 +76239,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2737 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:2732 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTDQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 947, + .Mnemonic = 959, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76397,12 +76267,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2738 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:2733 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTDQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 948, + .Mnemonic = 960, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76425,12 +76295,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2739 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + // Pos:2734 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { .Instruction = ND_INS_VCVTDQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 948, + .Mnemonic = 960, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76452,12 +76322,156 @@ const ND_IDBE gInstructions[4075] = }, }, + // Pos:2735 Instruction:"VCVTHF82PH Vfv{K}{z},aKq,Whv" Encoding:"evex m:5 p:3 l:x w:0 0x1E /r"/"RAM" + { + .Instruction = ND_INS_VCVTHF82PH, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 961, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2736 Instruction:"VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:1 p:3 l:x w:0 0x74 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTNE2PH2BF8, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 962, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2737 Instruction:"VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x74 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTNE2PH2BF8S, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 963, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2738 Instruction:"VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x18 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTNE2PH2HF8, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 964, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2739 Instruction:"VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x1B /r"/"RAVM" + { + .Instruction = ND_INS_VCVTNE2PH2HF8S, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 965, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + // Pos:2740 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { .Instruction = ND_INS_VCVTNE2PS2BF16, .Category = ND_CAT_AVX512BF16, .IsaSet = ND_SET_AVX512BF16, - .Mnemonic = 949, + .Mnemonic = 966, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76481,12 +76495,68 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2741 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2741 Instruction:"VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x69 /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEBF162IBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 967, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2742 Instruction:"VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6B /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEBF162IUBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 968, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2743 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEEBF162PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 950, + .Mnemonic = 969, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76508,12 +76578,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2742 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2744 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEEPH2PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 951, + .Mnemonic = 970, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76535,12 +76605,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2743 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2745 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEOBF162PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 952, + .Mnemonic = 971, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76562,12 +76632,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2744 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" + // Pos:2746 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" { .Instruction = ND_INS_VCVTNEOPH2PS, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 953, + .Mnemonic = 972, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76589,12 +76659,124 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2745 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + // Pos:2747 Instruction:"VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:1 p:2 l:x w:0 0x74 /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEPH2BF8, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 973, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2748 Instruction:"VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x74 /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEPH2BF8S, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 974, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2749 Instruction:"VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x18 /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEPH2HF8, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 975, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2750 Instruction:"VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:2 l:x w:0 0x1B /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEPH2HF8S, + .Category = ND_CAT_AVX10CONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 976, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2751 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" { .Instruction = ND_INS_VCVTNEPS2BF16, .Category = ND_CAT_AVX512BF16, .IsaSet = ND_SET_AVX512BF16, - .Mnemonic = 954, + .Mnemonic = 977, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -76617,12 +76799,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2746 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" + // Pos:2752 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" { .Instruction = ND_INS_VCVTNEPS2BF16, .Category = ND_CAT_AVXNECONVERT, .IsaSet = ND_SET_AVXNECONVERT, - .Mnemonic = 954, + .Mnemonic = 977, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76644,12 +76826,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2747 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + // Pos:2753 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 955, + .Mnemonic = 978, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76672,12 +76854,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2748 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + // Pos:2754 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 955, + .Mnemonic = 978, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76699,12 +76881,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2749 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:2755 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPD2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 956, + .Mnemonic = 979, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76727,12 +76909,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2750 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:2756 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPD2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 957, + .Mnemonic = 980, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76755,12 +76937,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2751 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + // Pos:2757 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPD2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 957, + .Mnemonic = 980, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76782,12 +76964,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2752 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + // Pos:2758 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPD2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 957, + .Mnemonic = 980, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -76809,12 +76991,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2753 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + // Pos:2759 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { .Instruction = ND_INS_VCVTPD2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 958, + .Mnemonic = 981, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76837,12 +77019,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2754 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + // Pos:2760 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPD2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 959, + .Mnemonic = 982, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76865,12 +77047,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2755 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + // Pos:2761 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPD2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 960, + .Mnemonic = 983, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76893,12 +77075,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2756 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:2762 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTPH2DQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 961, + .Mnemonic = 984, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -76921,12 +77103,68 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2757 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:2763 Instruction:"VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x69 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2IBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 985, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2764 Instruction:"VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x6B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2IUBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 986, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2765 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPH2PD, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 962, + .Mnemonic = 987, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -76949,12 +77187,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2758 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:2766 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 963, + .Mnemonic = 988, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -76977,12 +77215,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2759 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + // Pos:2767 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { .Instruction = ND_INS_VCVTPH2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 963, + .Mnemonic = 988, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77004,12 +77242,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2760 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + // Pos:2768 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { .Instruction = ND_INS_VCVTPH2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 963, + .Mnemonic = 988, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77031,12 +77269,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2761 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:2769 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2PSX, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 964, + .Mnemonic = 989, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -77059,12 +77297,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2762 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:2770 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" { .Instruction = ND_INS_VCVTPH2QQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 965, + .Mnemonic = 990, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77087,12 +77325,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2763 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:2771 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2UDQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 966, + .Mnemonic = 991, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77115,12 +77353,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2764 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:2772 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPH2UQQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 967, + .Mnemonic = 992, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77143,12 +77381,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2765 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" + // Pos:2773 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTPH2UW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 968, + .Mnemonic = 993, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77171,12 +77409,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2766 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" + // Pos:2774 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTPH2W, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 969, + .Mnemonic = 994, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77199,12 +77437,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2767 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:2775 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 970, + .Mnemonic = 995, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77227,12 +77465,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2768 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + // Pos:2776 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { .Instruction = ND_INS_VCVTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 970, + .Mnemonic = 995, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77254,12 +77492,68 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2769 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:2777 Instruction:"VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x69 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2IBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 996, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2778 Instruction:"VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x6B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2IUBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 997, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2779 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { .Instruction = ND_INS_VCVTPS2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 971, + .Mnemonic = 998, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -77282,12 +77576,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2770 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + // Pos:2780 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPS2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 971, + .Mnemonic = 998, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77309,12 +77603,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2771 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + // Pos:2781 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { .Instruction = ND_INS_VCVTPS2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 971, + .Mnemonic = 998, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77336,12 +77630,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2772 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + // Pos:2782 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { .Instruction = ND_INS_VCVTPS2PH, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 972, + .Mnemonic = 999, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -77365,12 +77659,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2773 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + // Pos:2783 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { .Instruction = ND_INS_VCVTPS2PH, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 972, + .Mnemonic = 999, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77393,12 +77687,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2774 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + // Pos:2784 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { .Instruction = ND_INS_VCVTPS2PH, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_F16C, - .Mnemonic = 972, + .Mnemonic = 999, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77421,12 +77715,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2775 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" + // Pos:2785 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" { .Instruction = ND_INS_VCVTPS2PHX, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 973, + .Mnemonic = 1000, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77449,12 +77743,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2776 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:2786 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { .Instruction = ND_INS_VCVTPS2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 974, + .Mnemonic = 1001, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77477,12 +77771,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2777 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:2787 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPS2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 975, + .Mnemonic = 1002, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77505,12 +77799,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2778 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:2788 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VCVTPS2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 976, + .Mnemonic = 1003, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77533,12 +77827,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2779 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + // Pos:2789 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTQQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 977, + .Mnemonic = 1004, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77561,12 +77855,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2780 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:2790 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTQQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 978, + .Mnemonic = 1005, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77589,12 +77883,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2781 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:2791 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTQQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 979, + .Mnemonic = 1006, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -77617,12 +77911,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2782 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:2792 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSD2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 980, + .Mnemonic = 1007, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -77646,12 +77940,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2783 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:2793 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 981, + .Mnemonic = 1008, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -77673,12 +77967,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2784 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:2794 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 981, + .Mnemonic = 1008, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77700,12 +77994,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2785 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:2795 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSD2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 982, + .Mnemonic = 1009, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -77729,12 +78023,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2786 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + // Pos:2796 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { .Instruction = ND_INS_VCVTSD2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 982, + .Mnemonic = 1009, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77757,12 +78051,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2787 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + // Pos:2797 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { .Instruction = ND_INS_VCVTSD2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 983, + .Mnemonic = 1010, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -77784,12 +78078,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2788 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:2798 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSH2SD, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 984, + .Mnemonic = 1011, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -77813,12 +78107,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2789 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:2799 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSH2SI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 985, + .Mnemonic = 1012, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -77840,12 +78134,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2790 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" + // Pos:2800 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" { .Instruction = ND_INS_VCVTSH2SS, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 986, + .Mnemonic = 1013, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -77869,12 +78163,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2791 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:2801 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" { .Instruction = ND_INS_VCVTSH2USI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 987, + .Mnemonic = 1014, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -77896,12 +78190,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2792 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + // Pos:2802 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 988, + .Mnemonic = 1015, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77924,12 +78218,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2793 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + // Pos:2803 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 988, + .Mnemonic = 1015, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -77952,12 +78246,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2794 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + // Pos:2804 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 988, + .Mnemonic = 1015, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -77980,12 +78274,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2795 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:2805 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 989, + .Mnemonic = 1016, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78008,12 +78302,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2796 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:2806 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 990, + .Mnemonic = 1017, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78036,12 +78330,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2797 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:2807 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { .Instruction = ND_INS_VCVTSI2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 990, + .Mnemonic = 1017, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78064,12 +78358,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2798 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:2808 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { .Instruction = ND_INS_VCVTSS2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 991, + .Mnemonic = 1018, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -78093,12 +78387,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2799 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + // Pos:2809 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { .Instruction = ND_INS_VCVTSS2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 991, + .Mnemonic = 1018, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78121,12 +78415,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2800 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" + // Pos:2810 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" { .Instruction = ND_INS_VCVTSS2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 992, + .Mnemonic = 1019, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -78150,12 +78444,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2801 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:2811 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 993, + .Mnemonic = 1020, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78177,12 +78471,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2802 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:2812 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { .Instruction = ND_INS_VCVTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 993, + .Mnemonic = 1020, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78204,12 +78498,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2803 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:2813 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { .Instruction = ND_INS_VCVTSS2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 994, + .Mnemonic = 1021, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -78231,12 +78525,68 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2804 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + // Pos:2814 Instruction:"VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x68 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTNEBF162IBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1022, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2815 Instruction:"VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:3 l:x w:0 0x6A /r"/"RAM" + { + .Instruction = ND_INS_VCVTTNEBF162IUBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1023, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2816 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 995, + .Mnemonic = 1024, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78259,12 +78609,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2805 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + // Pos:2817 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { .Instruction = ND_INS_VCVTTPD2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 995, + .Mnemonic = 1024, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78286,12 +78636,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2806 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + // Pos:2818 Instruction:"VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6D /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2DQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1025, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2819 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 996, + .Mnemonic = 1026, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78314,12 +78692,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2807 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + // Pos:2820 Instruction:"VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6D /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2QQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1027, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2821 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 997, + .Mnemonic = 1028, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78342,12 +78748,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2808 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + // Pos:2822 Instruction:"VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:0 l:x w:1 0x6C /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2UDQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1029, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2823 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPD2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 998, + .Mnemonic = 1030, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78370,12 +78804,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2809 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:2824 Instruction:"VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:5 p:1 l:x w:1 0x6C /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2UQQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1031, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2825 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2DQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 999, + .Mnemonic = 1032, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78398,12 +78860,68 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2810 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:2826 Instruction:"VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x68 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2IBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1033, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2827 Instruction:"VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6A /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2IUBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1034, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2828 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2QQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1000, + .Mnemonic = 1035, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78426,12 +78944,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2811 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:2829 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2UDQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1001, + .Mnemonic = 1036, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78454,12 +78972,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2812 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:2830 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2UQQ, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1002, + .Mnemonic = 1037, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78482,12 +79000,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2813 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" + // Pos:2831 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2UW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1003, + .Mnemonic = 1038, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78510,12 +79028,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2814 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" + // Pos:2832 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" { .Instruction = ND_INS_VCVTTPH2W, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1004, + .Mnemonic = 1039, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78538,12 +79056,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2815 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:2833 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1005, + .Mnemonic = 1040, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78566,12 +79084,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2816 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + // Pos:2834 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { .Instruction = ND_INS_VCVTTPS2DQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1005, + .Mnemonic = 1040, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78593,12 +79111,96 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2817 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:2835 Instruction:"VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6D /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2DQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1041, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2836 Instruction:"VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x68 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2IBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1042, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2837 Instruction:"VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6A /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2IUBS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1043, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2838 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2QQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1006, + .Mnemonic = 1044, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78621,12 +79223,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2818 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:2839 Instruction:"VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6D /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2QQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1045, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2840 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2UDQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1007, + .Mnemonic = 1046, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78649,12 +79279,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2819 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:2841 Instruction:"VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x6C /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2UDQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1047, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2842 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VCVTTPS2UQQ, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1008, + .Mnemonic = 1048, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -78677,12 +79335,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2820 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:2843 Instruction:"VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x6C /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2UQQS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1049, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2844 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1009, + .Mnemonic = 1050, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -78704,12 +79390,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2821 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:2845 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSD2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1009, + .Mnemonic = 1050, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78731,12 +79417,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2822 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + // Pos:2846 Instruction:"VCVTTSD2SIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6D /r"/"RM" + { + .Instruction = ND_INS_VCVTTSD2SIS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1051, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2847 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { .Instruction = ND_INS_VCVTTSD2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1010, + .Mnemonic = 1052, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -78758,12 +79471,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2823 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:2848 Instruction:"VCVTTSD2USIS Gy,Wsd{sae}" Encoding:"evex m:5 p:3 l:i w:x 0x6C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSD2USIS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1053, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2849 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSH2SI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1011, + .Mnemonic = 1054, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -78785,12 +79525,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2824 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" + // Pos:2850 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" { .Instruction = ND_INS_VCVTTSH2USI, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1012, + .Mnemonic = 1055, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -78812,12 +79552,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2825 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:2851 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1013, + .Mnemonic = 1056, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -78839,12 +79579,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2826 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:2852 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { .Instruction = ND_INS_VCVTTSS2SI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX, - .Mnemonic = 1013, + .Mnemonic = 1056, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -78866,12 +79606,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2827 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + // Pos:2853 Instruction:"VCVTTSS2SIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6D /r"/"RM" + { + .Instruction = ND_INS_VCVTTSS2SIS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1057, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2854 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { .Instruction = ND_INS_VCVTTSS2USI, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1014, + .Mnemonic = 1058, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -78893,12 +79660,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2828 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + // Pos:2855 Instruction:"VCVTTSS2USIS Gy,Wss{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x6C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSS2USIS, + .Category = ND_CAT_AVX10SCONVERT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1059, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2856 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUDQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1015, + .Mnemonic = 1060, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -78921,12 +79715,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2829 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:2857 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUDQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1016, + .Mnemonic = 1061, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -78949,12 +79743,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2830 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:2858 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUDQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1017, + .Mnemonic = 1062, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -78977,12 +79771,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2831 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + // Pos:2859 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUQQ2PD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1018, + .Mnemonic = 1063, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79005,12 +79799,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2832 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:2860 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUQQ2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1019, + .Mnemonic = 1064, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79033,12 +79827,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2833 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:2861 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { .Instruction = ND_INS_VCVTUQQ2PS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1020, + .Mnemonic = 1065, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79061,12 +79855,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2834 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + // Pos:2862 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1021, + .Mnemonic = 1066, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79089,12 +79883,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2835 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + // Pos:2863 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SD, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1021, + .Mnemonic = 1066, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -79117,12 +79911,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2836 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:2864 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1022, + .Mnemonic = 1067, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -79145,12 +79939,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2837 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:2865 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { .Instruction = ND_INS_VCVTUSI2SS, .Category = ND_CAT_CONVERT, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1023, + .Mnemonic = 1068, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ER, @@ -79173,12 +79967,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2838 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" + // Pos:2866 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTUW2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1024, + .Mnemonic = 1069, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79201,12 +79995,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2839 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" + // Pos:2867 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" { .Instruction = ND_INS_VCVTW2PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1025, + .Mnemonic = 1070, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79229,12 +80023,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2840 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:2868 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { .Instruction = ND_INS_VDBPSADBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1026, + .Mnemonic = 1071, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79259,12 +80053,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2841 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + // Pos:2869 Instruction:"VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVNEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1072, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2870 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1027, + .Mnemonic = 1073, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79288,12 +80111,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2842 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + // Pos:2871 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1027, + .Mnemonic = 1073, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79316,12 +80139,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2843 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:2872 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1028, + .Mnemonic = 1074, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79345,12 +80168,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2844 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:2873 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1029, + .Mnemonic = 1075, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -79374,12 +80197,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2845 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + // Pos:2874 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1029, + .Mnemonic = 1075, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79402,12 +80225,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2846 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + // Pos:2875 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1030, + .Mnemonic = 1076, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -79431,12 +80254,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2847 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + // Pos:2876 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1030, + .Mnemonic = 1076, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79459,12 +80282,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2848 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:2877 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1031, + .Mnemonic = 1077, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -79488,12 +80311,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2849 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:2878 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { .Instruction = ND_INS_VDIVSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1032, + .Mnemonic = 1078, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -79517,12 +80340,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2850 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + // Pos:2879 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { .Instruction = ND_INS_VDIVSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1032, + .Mnemonic = 1078, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79545,12 +80368,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2851 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + // Pos:2880 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { .Instruction = ND_INS_VDPBF16PS, .Category = ND_CAT_AVX512BF16, .IsaSet = ND_SET_AVX512BF16, - .Mnemonic = 1033, + .Mnemonic = 1079, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -79574,12 +80397,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2852 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + // Pos:2881 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { .Instruction = ND_INS_VDPPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1034, + .Mnemonic = 1080, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79603,12 +80426,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2853 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + // Pos:2882 Instruction:"VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x52 /r"/"RAVM" + { + .Instruction = ND_INS_VDPPHPS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1081, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2883 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { .Instruction = ND_INS_VDPPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1035, + .Mnemonic = 1082, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79632,12 +80484,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2854 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + // Pos:2884 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { .Instruction = ND_INS_VERR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 1036, + .Mnemonic = 1083, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -79659,12 +80511,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2855 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + // Pos:2885 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { .Instruction = ND_INS_VERW, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I286PROT, - .Mnemonic = 1037, + .Mnemonic = 1084, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -79686,12 +80538,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2856 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + // Pos:2886 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { .Instruction = ND_INS_VEXP2PD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1038, + .Mnemonic = 1085, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79714,12 +80566,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2857 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + // Pos:2887 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { .Instruction = ND_INS_VEXP2PS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1039, + .Mnemonic = 1086, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -79742,12 +80594,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2858 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + // Pos:2888 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { .Instruction = ND_INS_VEXPANDPD, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1040, + .Mnemonic = 1087, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79770,12 +80622,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2859 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + // Pos:2889 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { .Instruction = ND_INS_VEXPANDPS, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1041, + .Mnemonic = 1088, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79798,12 +80650,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2860 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + // Pos:2890 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { .Instruction = ND_INS_VEXTRACTF128, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1042, + .Mnemonic = 1089, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79826,12 +80678,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2861 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + // Pos:2891 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1043, + .Mnemonic = 1090, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79855,12 +80707,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2862 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + // Pos:2892 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1044, + .Mnemonic = 1091, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79884,12 +80736,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2863 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + // Pos:2893 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1045, + .Mnemonic = 1092, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79913,12 +80765,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2864 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + // Pos:2894 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTF64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1046, + .Mnemonic = 1093, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79942,12 +80794,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2865 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + // Pos:2895 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { .Instruction = ND_INS_VEXTRACTI128, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1047, + .Mnemonic = 1094, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -79970,12 +80822,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2866 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + // Pos:2896 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1048, + .Mnemonic = 1095, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -79999,12 +80851,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2867 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + // Pos:2897 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1049, + .Mnemonic = 1096, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80028,12 +80880,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2868 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + // Pos:2898 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1050, + .Mnemonic = 1097, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80057,12 +80909,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2869 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + // Pos:2899 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { .Instruction = ND_INS_VEXTRACTI64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1051, + .Mnemonic = 1098, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -80086,12 +80938,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2870 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:2900 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1052, + .Mnemonic = 1099, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80114,12 +80966,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2871 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:2901 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1052, + .Mnemonic = 1099, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80142,12 +80994,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2872 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:2902 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1052, + .Mnemonic = 1099, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80170,12 +81022,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2873 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:2903 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { .Instruction = ND_INS_VEXTRACTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1052, + .Mnemonic = 1099, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80198,12 +81050,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2874 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" + // Pos:2904 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" { .Instruction = ND_INS_VFCMADDCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1053, + .Mnemonic = 1100, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80227,12 +81079,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2875 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" + // Pos:2905 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" { .Instruction = ND_INS_VFCMADDCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1054, + .Mnemonic = 1101, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80256,12 +81108,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2876 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" + // Pos:2906 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" { .Instruction = ND_INS_VFCMULCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1055, + .Mnemonic = 1102, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80285,12 +81137,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2877 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" + // Pos:2907 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" { .Instruction = ND_INS_VFCMULCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1056, + .Mnemonic = 1103, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80314,12 +81166,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2878 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + // Pos:2908 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1057, + .Mnemonic = 1104, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -80344,12 +81196,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2879 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + // Pos:2909 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1058, + .Mnemonic = 1105, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -80374,12 +81226,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2880 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + // Pos:2910 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1059, + .Mnemonic = 1106, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -80404,12 +81256,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2881 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + // Pos:2911 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { .Instruction = ND_INS_VFIXUPIMMSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1060, + .Mnemonic = 1107, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -80434,12 +81286,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2882 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + // Pos:2912 Instruction:"VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x98 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1108, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2913 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1061, + .Mnemonic = 1109, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80463,12 +81344,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2883 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + // Pos:2914 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { .Instruction = ND_INS_VFMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1061, + .Mnemonic = 1109, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80491,12 +81372,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2884 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:2915 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1062, + .Mnemonic = 1110, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80520,12 +81401,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2885 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:2916 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1063, + .Mnemonic = 1111, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80549,12 +81430,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2886 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + // Pos:2917 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { .Instruction = ND_INS_VFMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1063, + .Mnemonic = 1111, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80577,12 +81458,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2887 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + // Pos:2918 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1064, + .Mnemonic = 1112, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80606,12 +81487,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2888 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + // Pos:2919 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { .Instruction = ND_INS_VFMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1064, + .Mnemonic = 1112, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80634,12 +81515,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2889 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:2920 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1065, + .Mnemonic = 1113, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80663,12 +81544,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2890 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:2921 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { .Instruction = ND_INS_VFMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1066, + .Mnemonic = 1114, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80692,12 +81573,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2891 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + // Pos:2922 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { .Instruction = ND_INS_VFMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1066, + .Mnemonic = 1114, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80720,12 +81601,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2892 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + // Pos:2923 Instruction:"VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xA8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1115, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2924 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1067, + .Mnemonic = 1116, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80749,12 +81659,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2893 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + // Pos:2925 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { .Instruction = ND_INS_VFMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1067, + .Mnemonic = 1116, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80777,12 +81687,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2894 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:2926 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1068, + .Mnemonic = 1117, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80806,12 +81716,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2895 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:2927 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1069, + .Mnemonic = 1118, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -80835,12 +81745,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2896 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + // Pos:2928 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { .Instruction = ND_INS_VFMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1069, + .Mnemonic = 1118, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80863,12 +81773,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2897 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + // Pos:2929 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1070, + .Mnemonic = 1119, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80892,12 +81802,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2898 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + // Pos:2930 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { .Instruction = ND_INS_VFMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1070, + .Mnemonic = 1119, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -80920,12 +81830,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2899 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:2931 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1071, + .Mnemonic = 1120, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80949,12 +81859,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2900 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:2932 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1072, + .Mnemonic = 1121, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -80978,12 +81888,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2901 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + // Pos:2933 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { .Instruction = ND_INS_VFMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1072, + .Mnemonic = 1121, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81006,12 +81916,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2902 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + // Pos:2934 Instruction:"VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xB8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1122, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2935 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1073, + .Mnemonic = 1123, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81035,12 +81974,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2903 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + // Pos:2936 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { .Instruction = ND_INS_VFMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1073, + .Mnemonic = 1123, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81063,12 +82002,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2904 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:2937 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1074, + .Mnemonic = 1124, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81092,12 +82031,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2905 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:2938 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1075, + .Mnemonic = 1125, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81121,12 +82060,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2906 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + // Pos:2939 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { .Instruction = ND_INS_VFMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1075, + .Mnemonic = 1125, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81149,12 +82088,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2907 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + // Pos:2940 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1076, + .Mnemonic = 1126, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81178,12 +82117,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2908 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + // Pos:2941 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { .Instruction = ND_INS_VFMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1076, + .Mnemonic = 1126, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81206,12 +82145,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2909 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:2942 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1077, + .Mnemonic = 1127, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81235,12 +82174,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2910 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:2943 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { .Instruction = ND_INS_VFMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1078, + .Mnemonic = 1128, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81264,12 +82203,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2911 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + // Pos:2944 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { .Instruction = ND_INS_VFMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1078, + .Mnemonic = 1128, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81292,12 +82231,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2912 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" + // Pos:2945 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" { .Instruction = ND_INS_VFMADDCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1079, + .Mnemonic = 1129, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81321,12 +82260,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2913 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" + // Pos:2946 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" { .Instruction = ND_INS_VFMADDCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1080, + .Mnemonic = 1130, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -81350,12 +82289,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2914 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + // Pos:2947 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { .Instruction = ND_INS_VFMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1081, + .Mnemonic = 1131, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81379,12 +82318,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2915 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + // Pos:2948 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1081, + .Mnemonic = 1131, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81408,12 +82347,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2916 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + // Pos:2949 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { .Instruction = ND_INS_VFMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1082, + .Mnemonic = 1132, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81437,12 +82376,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2917 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + // Pos:2950 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1082, + .Mnemonic = 1132, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81466,12 +82405,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2918 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + // Pos:2951 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1083, + .Mnemonic = 1133, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81495,12 +82434,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2919 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + // Pos:2952 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1083, + .Mnemonic = 1133, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81524,12 +82463,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2920 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + // Pos:2953 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1084, + .Mnemonic = 1134, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81553,12 +82492,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2921 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + // Pos:2954 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1084, + .Mnemonic = 1134, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81582,12 +82521,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2922 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + // Pos:2955 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1085, + .Mnemonic = 1135, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81611,12 +82550,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2923 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + // Pos:2956 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1085, + .Mnemonic = 1135, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81639,12 +82578,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2924 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:2957 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1086, + .Mnemonic = 1136, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81668,12 +82607,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2925 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:2958 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1087, + .Mnemonic = 1137, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81697,12 +82636,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2926 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + // Pos:2959 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1087, + .Mnemonic = 1137, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81725,12 +82664,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2927 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + // Pos:2960 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1088, + .Mnemonic = 1138, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81754,12 +82693,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2928 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + // Pos:2961 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1088, + .Mnemonic = 1138, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81782,12 +82721,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2929 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:2962 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1089, + .Mnemonic = 1139, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81811,12 +82750,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2930 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:2963 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1090, + .Mnemonic = 1140, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81840,12 +82779,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2931 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + // Pos:2964 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1090, + .Mnemonic = 1140, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81868,12 +82807,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2932 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + // Pos:2965 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1091, + .Mnemonic = 1141, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81897,12 +82836,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2933 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + // Pos:2966 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1091, + .Mnemonic = 1141, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -81925,12 +82864,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2934 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:2967 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1092, + .Mnemonic = 1142, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81954,12 +82893,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2935 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:2968 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { .Instruction = ND_INS_VFMADDSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1093, + .Mnemonic = 1143, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -81983,12 +82922,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2936 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + // Pos:2969 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { .Instruction = ND_INS_VFMADDSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1093, + .Mnemonic = 1143, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82011,12 +82950,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2937 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + // Pos:2970 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1094, + .Mnemonic = 1144, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82040,12 +82979,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2938 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + // Pos:2971 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1094, + .Mnemonic = 1144, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82069,12 +83008,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2939 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + // Pos:2972 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { .Instruction = ND_INS_VFMADDSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1095, + .Mnemonic = 1145, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82098,12 +83037,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2940 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + // Pos:2973 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { .Instruction = ND_INS_VFMADDSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1095, + .Mnemonic = 1145, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82127,12 +83066,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2941 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + // Pos:2974 Instruction:"VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9A /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1146, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2975 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1096, + .Mnemonic = 1147, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82156,12 +83124,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2942 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + // Pos:2976 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { .Instruction = ND_INS_VFMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1096, + .Mnemonic = 1147, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82184,12 +83152,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2943 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:2977 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1097, + .Mnemonic = 1148, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82213,12 +83181,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2944 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:2978 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1098, + .Mnemonic = 1149, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82242,12 +83210,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2945 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + // Pos:2979 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { .Instruction = ND_INS_VFMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1098, + .Mnemonic = 1149, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82270,12 +83238,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2946 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + // Pos:2980 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1099, + .Mnemonic = 1150, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82299,12 +83267,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2947 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + // Pos:2981 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { .Instruction = ND_INS_VFMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1099, + .Mnemonic = 1150, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82327,12 +83295,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2948 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:2982 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1100, + .Mnemonic = 1151, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82356,12 +83324,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2949 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:2983 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { .Instruction = ND_INS_VFMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1101, + .Mnemonic = 1152, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82385,12 +83353,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2950 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + // Pos:2984 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { .Instruction = ND_INS_VFMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1101, + .Mnemonic = 1152, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82413,12 +83381,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2951 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + // Pos:2985 Instruction:"VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1153, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2986 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1102, + .Mnemonic = 1154, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82442,12 +83439,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2952 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + // Pos:2987 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { .Instruction = ND_INS_VFMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1102, + .Mnemonic = 1154, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82470,12 +83467,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2953 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:2988 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1103, + .Mnemonic = 1155, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82499,12 +83496,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2954 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:2989 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1104, + .Mnemonic = 1156, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82528,12 +83525,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2955 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + // Pos:2990 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { .Instruction = ND_INS_VFMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1104, + .Mnemonic = 1156, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82556,12 +83553,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2956 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + // Pos:2991 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1105, + .Mnemonic = 1157, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82585,12 +83582,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2957 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + // Pos:2992 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { .Instruction = ND_INS_VFMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1105, + .Mnemonic = 1157, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82613,12 +83610,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2958 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:2993 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1106, + .Mnemonic = 1158, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82642,12 +83639,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2959 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:2994 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1107, + .Mnemonic = 1159, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82671,12 +83668,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2960 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + // Pos:2995 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { .Instruction = ND_INS_VFMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1107, + .Mnemonic = 1159, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82699,12 +83696,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2961 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + // Pos:2996 Instruction:"VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1160, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:2997 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1108, + .Mnemonic = 1161, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82728,12 +83754,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2962 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + // Pos:2998 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { .Instruction = ND_INS_VFMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1108, + .Mnemonic = 1161, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82756,12 +83782,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2963 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:2999 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1109, + .Mnemonic = 1162, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82785,12 +83811,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2964 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:3000 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1110, + .Mnemonic = 1163, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -82814,12 +83840,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2965 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + // Pos:3001 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { .Instruction = ND_INS_VFMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1110, + .Mnemonic = 1163, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82842,12 +83868,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2966 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + // Pos:3002 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1111, + .Mnemonic = 1164, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82871,12 +83897,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2967 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + // Pos:3003 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { .Instruction = ND_INS_VFMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1111, + .Mnemonic = 1164, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82899,12 +83925,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2968 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:3004 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1112, + .Mnemonic = 1165, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82928,12 +83954,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2969 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:3005 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { .Instruction = ND_INS_VFMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1113, + .Mnemonic = 1166, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -82957,12 +83983,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2970 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + // Pos:3006 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { .Instruction = ND_INS_VFMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1113, + .Mnemonic = 1166, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -82985,12 +84011,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2971 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + // Pos:3007 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1114, + .Mnemonic = 1167, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83014,12 +84040,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2972 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + // Pos:3008 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1114, + .Mnemonic = 1167, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83042,12 +84068,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2973 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:3009 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1115, + .Mnemonic = 1168, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83071,12 +84097,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2974 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:3010 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1116, + .Mnemonic = 1169, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83100,12 +84126,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2975 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + // Pos:3011 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1116, + .Mnemonic = 1169, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83128,12 +84154,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2976 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + // Pos:3012 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1117, + .Mnemonic = 1170, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83157,12 +84183,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2977 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + // Pos:3013 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1117, + .Mnemonic = 1170, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83185,12 +84211,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2978 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:3014 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1118, + .Mnemonic = 1171, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83214,12 +84240,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2979 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:3015 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1119, + .Mnemonic = 1172, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83243,12 +84269,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2980 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + // Pos:3016 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1119, + .Mnemonic = 1172, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83271,12 +84297,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2981 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + // Pos:3017 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1120, + .Mnemonic = 1173, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83300,12 +84326,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2982 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + // Pos:3018 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1120, + .Mnemonic = 1173, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83328,12 +84354,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2983 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:3019 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1121, + .Mnemonic = 1174, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83357,12 +84383,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2984 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:3020 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { .Instruction = ND_INS_VFMSUBADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1122, + .Mnemonic = 1175, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83386,12 +84412,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2985 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + // Pos:3021 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { .Instruction = ND_INS_VFMSUBADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1122, + .Mnemonic = 1175, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83414,12 +84440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2986 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + // Pos:3022 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1123, + .Mnemonic = 1176, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83443,12 +84469,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2987 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + // Pos:3023 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1123, + .Mnemonic = 1176, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83472,12 +84498,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2988 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + // Pos:3024 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1124, + .Mnemonic = 1177, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83501,12 +84527,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2989 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + // Pos:3025 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1124, + .Mnemonic = 1177, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83530,12 +84556,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2990 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + // Pos:3026 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1125, + .Mnemonic = 1178, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83559,12 +84585,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2991 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + // Pos:3027 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1125, + .Mnemonic = 1178, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83588,12 +84614,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2992 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + // Pos:3028 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1126, + .Mnemonic = 1179, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83617,12 +84643,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2993 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + // Pos:3029 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1126, + .Mnemonic = 1179, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83646,12 +84672,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2994 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + // Pos:3030 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1127, + .Mnemonic = 1180, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83675,12 +84701,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2995 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + // Pos:3031 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1127, + .Mnemonic = 1180, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83704,12 +84730,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2996 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + // Pos:3032 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" { .Instruction = ND_INS_VFMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1128, + .Mnemonic = 1181, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83733,12 +84759,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2997 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + // Pos:3033 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" { .Instruction = ND_INS_VFMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1128, + .Mnemonic = 1181, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83762,12 +84788,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2998 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" + // Pos:3034 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" { .Instruction = ND_INS_VFMULCPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1129, + .Mnemonic = 1182, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83791,12 +84817,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:2999 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" + // Pos:3035 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" { .Instruction = ND_INS_VFMULCSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1130, + .Mnemonic = 1183, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83820,12 +84846,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3000 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + // Pos:3036 Instruction:"VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9C /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3037 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1131, + .Mnemonic = 1185, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83849,12 +84904,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3001 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + // Pos:3038 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" { .Instruction = ND_INS_VFNMADD132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1131, + .Mnemonic = 1185, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83877,12 +84932,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3002 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:3039 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1132, + .Mnemonic = 1186, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83906,12 +84961,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3003 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + // Pos:3040 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1133, + .Mnemonic = 1187, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -83935,12 +84990,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3004 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + // Pos:3041 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" { .Instruction = ND_INS_VFNMADD132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1133, + .Mnemonic = 1187, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -83963,12 +85018,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3005 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + // Pos:3042 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1134, + .Mnemonic = 1188, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -83992,12 +85047,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3006 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + // Pos:3043 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" { .Instruction = ND_INS_VFNMADD132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1134, + .Mnemonic = 1188, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84020,12 +85075,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3007 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:3044 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1135, + .Mnemonic = 1189, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84049,12 +85104,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3008 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + // Pos:3045 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" { .Instruction = ND_INS_VFNMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1136, + .Mnemonic = 1190, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84078,12 +85133,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3009 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + // Pos:3046 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" { .Instruction = ND_INS_VFNMADD132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1136, + .Mnemonic = 1190, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84106,12 +85161,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3010 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + // Pos:3047 Instruction:"VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1191, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3048 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1137, + .Mnemonic = 1192, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84135,12 +85219,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3011 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + // Pos:3049 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" { .Instruction = ND_INS_VFNMADD213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1137, + .Mnemonic = 1192, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84163,12 +85247,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3012 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:3050 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1138, + .Mnemonic = 1193, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84192,12 +85276,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3013 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + // Pos:3051 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1139, + .Mnemonic = 1194, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84221,12 +85305,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3014 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + // Pos:3052 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" { .Instruction = ND_INS_VFNMADD213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1139, + .Mnemonic = 1194, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84249,12 +85333,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3015 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + // Pos:3053 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1140, + .Mnemonic = 1195, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84278,12 +85362,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3016 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" + // Pos:3054 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" { .Instruction = ND_INS_VFNMADD213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1140, + .Mnemonic = 1195, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84306,12 +85390,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3017 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:3055 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1141, + .Mnemonic = 1196, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84335,12 +85419,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3018 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + // Pos:3056 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1142, + .Mnemonic = 1197, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84364,12 +85448,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3019 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" + // Pos:3057 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" { .Instruction = ND_INS_VFNMADD213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1142, + .Mnemonic = 1197, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84392,12 +85476,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3020 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + // Pos:3058 Instruction:"VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1198, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3059 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1143, + .Mnemonic = 1199, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84421,12 +85534,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3021 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + // Pos:3060 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" { .Instruction = ND_INS_VFNMADD231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1143, + .Mnemonic = 1199, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84449,12 +85562,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3022 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:3061 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1144, + .Mnemonic = 1200, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84478,12 +85591,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3023 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + // Pos:3062 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1145, + .Mnemonic = 1201, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84507,12 +85620,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3024 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + // Pos:3063 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" { .Instruction = ND_INS_VFNMADD231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1145, + .Mnemonic = 1201, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84535,12 +85648,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3025 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + // Pos:3064 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1146, + .Mnemonic = 1202, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84564,12 +85677,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3026 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" + // Pos:3065 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" { .Instruction = ND_INS_VFNMADD231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1146, + .Mnemonic = 1202, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84592,12 +85705,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3027 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:3066 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1147, + .Mnemonic = 1203, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84621,12 +85734,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3028 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + // Pos:3067 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" { .Instruction = ND_INS_VFNMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1148, + .Mnemonic = 1204, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -84650,12 +85763,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3029 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" + // Pos:3068 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" { .Instruction = ND_INS_VFNMADD231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1148, + .Mnemonic = 1204, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84678,12 +85791,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3030 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + // Pos:3069 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1149, + .Mnemonic = 1205, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84707,12 +85820,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3031 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + // Pos:3070 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1149, + .Mnemonic = 1205, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84736,12 +85849,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3032 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + // Pos:3071 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1150, + .Mnemonic = 1206, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84765,12 +85878,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3033 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + // Pos:3072 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1150, + .Mnemonic = 1206, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84794,12 +85907,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3034 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + // Pos:3073 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1151, + .Mnemonic = 1207, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84823,12 +85936,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3035 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + // Pos:3074 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1151, + .Mnemonic = 1207, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84852,12 +85965,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3036 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + // Pos:3075 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" { .Instruction = ND_INS_VFNMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1152, + .Mnemonic = 1208, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84881,12 +85994,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3037 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + // Pos:3076 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" { .Instruction = ND_INS_VFNMADDSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1152, + .Mnemonic = 1208, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84910,12 +86023,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3038 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + // Pos:3077 Instruction:"VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x9E /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1209, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3078 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1153, + .Mnemonic = 1210, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84939,12 +86081,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3039 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + // Pos:3079 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1153, + .Mnemonic = 1210, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -84967,12 +86109,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3040 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:3080 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1154, + .Mnemonic = 1211, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -84996,12 +86138,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3041 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + // Pos:3081 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1155, + .Mnemonic = 1212, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85025,12 +86167,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3042 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + // Pos:3082 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1155, + .Mnemonic = 1212, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85053,12 +86195,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3043 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + // Pos:3083 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1156, + .Mnemonic = 1213, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85082,12 +86224,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3044 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" + // Pos:3084 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1156, + .Mnemonic = 1213, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85110,12 +86252,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3045 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:3085 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1157, + .Mnemonic = 1214, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85139,12 +86281,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3046 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + // Pos:3086 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1158, + .Mnemonic = 1215, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85168,12 +86310,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3047 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" + // Pos:3087 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" { .Instruction = ND_INS_VFNMSUB132SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1158, + .Mnemonic = 1215, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85196,12 +86338,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3048 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + // Pos:3088 Instruction:"VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xAE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1216, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3089 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1159, + .Mnemonic = 1217, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85225,12 +86396,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3049 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + // Pos:3090 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1159, + .Mnemonic = 1217, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85253,12 +86424,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3050 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:3091 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1160, + .Mnemonic = 1218, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85282,12 +86453,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3051 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + // Pos:3092 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1161, + .Mnemonic = 1219, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85311,12 +86482,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3052 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + // Pos:3093 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1161, + .Mnemonic = 1219, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85339,12 +86510,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3053 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + // Pos:3094 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1162, + .Mnemonic = 1220, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85368,12 +86539,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3054 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" + // Pos:3095 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1162, + .Mnemonic = 1220, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85396,12 +86567,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3055 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:3096 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1163, + .Mnemonic = 1221, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85425,12 +86596,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3056 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + // Pos:3097 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1164, + .Mnemonic = 1222, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85454,12 +86625,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3057 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" + // Pos:3098 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB213SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1164, + .Mnemonic = 1222, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85482,12 +86653,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3058 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + // Pos:3099 Instruction:"VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0xBE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231NEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1223, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3100 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1165, + .Mnemonic = 1224, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85511,12 +86711,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3059 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + // Pos:3101 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231PD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1165, + .Mnemonic = 1224, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85539,12 +86739,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3060 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:3102 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231PH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1166, + .Mnemonic = 1225, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85568,12 +86768,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3061 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + // Pos:3103 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1167, + .Mnemonic = 1226, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -85597,12 +86797,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3062 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + // Pos:3104 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231PS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1167, + .Mnemonic = 1226, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85625,12 +86825,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3063 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + // Pos:3105 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1168, + .Mnemonic = 1227, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85654,12 +86854,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3064 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" + // Pos:3106 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231SD, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1168, + .Mnemonic = 1227, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85682,12 +86882,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3065 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:3107 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231SH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1169, + .Mnemonic = 1228, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85711,12 +86911,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3066 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + // Pos:3108 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" { .Instruction = ND_INS_VFNMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1170, + .Mnemonic = 1229, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -85740,12 +86940,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3067 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" + // Pos:3109 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" { .Instruction = ND_INS_VFNMSUB231SS, .Category = ND_CAT_VFMA, .IsaSet = ND_SET_FMA, - .Mnemonic = 1170, + .Mnemonic = 1229, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85768,12 +86968,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3068 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + // Pos:3110 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1171, + .Mnemonic = 1230, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85797,12 +86997,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3069 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + // Pos:3111 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBPD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1171, + .Mnemonic = 1230, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85826,12 +87026,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3070 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + // Pos:3112 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1172, + .Mnemonic = 1231, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85855,12 +87055,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3071 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + // Pos:3113 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBPS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1172, + .Mnemonic = 1231, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85884,12 +87084,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3072 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + // Pos:3114 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1173, + .Mnemonic = 1232, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85913,12 +87113,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3073 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + // Pos:3115 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBSD, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1173, + .Mnemonic = 1232, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85942,12 +87142,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3074 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + // Pos:3116 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" { .Instruction = ND_INS_VFNMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1174, + .Mnemonic = 1233, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -85971,12 +87171,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3075 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + // Pos:3117 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" { .Instruction = ND_INS_VFNMSUBSS, .Category = ND_CAT_FMA4, .IsaSet = ND_SET_FMA4, - .Mnemonic = 1174, + .Mnemonic = 1233, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86000,12 +87200,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3076 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + // Pos:3118 Instruction:"VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x66 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1234, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3119 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1175, + .Mnemonic = 1235, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -86029,12 +87258,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3077 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:3120 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1176, + .Mnemonic = 1236, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -86058,12 +87287,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3078 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + // Pos:3121 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1177, + .Mnemonic = 1237, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -86087,12 +87316,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3079 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + // Pos:3122 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1178, + .Mnemonic = 1238, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86116,12 +87345,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3080 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:3123 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1179, + .Mnemonic = 1239, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86145,12 +87374,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3081 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + // Pos:3124 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" { .Instruction = ND_INS_VFPCLASSSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1180, + .Mnemonic = 1240, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86174,12 +87403,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3082 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + // Pos:3125 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" { .Instruction = ND_INS_VFRCZPD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1181, + .Mnemonic = 1241, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86201,12 +87430,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3083 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + // Pos:3126 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" { .Instruction = ND_INS_VFRCZPS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1182, + .Mnemonic = 1242, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86228,12 +87457,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3084 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + // Pos:3127 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" { .Instruction = ND_INS_VFRCZSD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1183, + .Mnemonic = 1243, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86255,12 +87484,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3085 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + // Pos:3128 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" { .Instruction = ND_INS_VFRCZSS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1184, + .Mnemonic = 1244, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86282,12 +87511,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3086 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + // Pos:3129 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERDPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1185, + .Mnemonic = 1245, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86310,12 +87539,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3087 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + // Pos:3130 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERDPD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1185, + .Mnemonic = 1245, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86338,12 +87567,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3088 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + // Pos:3131 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERDPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1186, + .Mnemonic = 1246, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86366,12 +87595,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3089 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + // Pos:3132 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERDPS, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1186, + .Mnemonic = 1246, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86394,12 +87623,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3090 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + // Pos:3133 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0DPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1187, + .Mnemonic = 1247, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86421,12 +87650,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3091 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + // Pos:3134 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0DPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1188, + .Mnemonic = 1248, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86448,12 +87677,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3092 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + // Pos:3135 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0QPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1189, + .Mnemonic = 1249, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86475,12 +87704,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3093 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + // Pos:3136 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF0QPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1190, + .Mnemonic = 1250, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86502,12 +87731,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3094 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + // Pos:3137 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1DPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1191, + .Mnemonic = 1251, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86529,12 +87758,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3095 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + // Pos:3138 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1DPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1192, + .Mnemonic = 1252, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86556,12 +87785,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3096 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + // Pos:3139 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1QPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1193, + .Mnemonic = 1253, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86583,12 +87812,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3097 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + // Pos:3140 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" { .Instruction = ND_INS_VGATHERPF1QPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1194, + .Mnemonic = 1254, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86610,12 +87839,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3098 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + // Pos:3141 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERQPD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1195, + .Mnemonic = 1255, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86638,12 +87867,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3099 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + // Pos:3142 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERQPD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1195, + .Mnemonic = 1255, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86666,12 +87895,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3100 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + // Pos:3143 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VGATHERQPS, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1196, + .Mnemonic = 1256, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -86694,12 +87923,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3101 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + // Pos:3144 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VGATHERQPS, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1196, + .Mnemonic = 1256, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -86722,12 +87951,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3102 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + // Pos:3145 Instruction:"VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x42 /r"/"RAM" + { + .Instruction = ND_INS_VGETEXPPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1257, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3146 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1197, + .Mnemonic = 1258, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -86750,12 +88007,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3103 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:3147 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1198, + .Mnemonic = 1259, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -86778,12 +88035,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3104 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + // Pos:3148 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" { .Instruction = ND_INS_VGETEXPPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1199, + .Mnemonic = 1260, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -86806,12 +88063,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3105 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + // Pos:3149 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" { .Instruction = ND_INS_VGETEXPSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1200, + .Mnemonic = 1261, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -86835,12 +88092,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3106 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" + // Pos:3150 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" { .Instruction = ND_INS_VGETEXPSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1201, + .Mnemonic = 1262, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -86864,12 +88121,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3107 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + // Pos:3151 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" { .Instruction = ND_INS_VGETEXPSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1202, + .Mnemonic = 1263, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -86893,12 +88150,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3108 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + // Pos:3152 Instruction:"VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x26 /r ib"/"RAMI" + { + .Instruction = ND_INS_VGETMANTPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1264, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3153 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1203, + .Mnemonic = 1265, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -86922,12 +88208,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3109 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:3154 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1204, + .Mnemonic = 1266, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -86951,12 +88237,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3110 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + // Pos:3155 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" { .Instruction = ND_INS_VGETMANTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1205, + .Mnemonic = 1267, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -86980,12 +88266,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3111 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + // Pos:3156 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" { .Instruction = ND_INS_VGETMANTSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1206, + .Mnemonic = 1268, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -87010,12 +88296,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3112 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:3157 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" { .Instruction = ND_INS_VGETMANTSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1207, + .Mnemonic = 1269, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -87040,12 +88326,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3113 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + // Pos:3158 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" { .Instruction = ND_INS_VGETMANTSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1208, + .Mnemonic = 1270, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -87070,12 +88356,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3114 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + // Pos:3159 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" { .Instruction = ND_INS_VGF2P8AFFINEINVQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1209, + .Mnemonic = 1271, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -87100,12 +88386,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3115 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + // Pos:3160 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" { .Instruction = ND_INS_VGF2P8AFFINEINVQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1209, + .Mnemonic = 1271, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87129,12 +88415,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3116 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + // Pos:3161 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" { .Instruction = ND_INS_VGF2P8AFFINEQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1210, + .Mnemonic = 1272, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -87159,12 +88445,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3117 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + // Pos:3162 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" { .Instruction = ND_INS_VGF2P8AFFINEQB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1210, + .Mnemonic = 1272, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87188,12 +88474,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3118 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + // Pos:3163 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" { .Instruction = ND_INS_VGF2P8MULB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1211, + .Mnemonic = 1273, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87217,12 +88503,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3119 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + // Pos:3164 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" { .Instruction = ND_INS_VGF2P8MULB, .Category = ND_CAT_GFNI, .IsaSet = ND_SET_GFNI, - .Mnemonic = 1211, + .Mnemonic = 1273, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87245,12 +88531,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3120 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + // Pos:3165 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" { .Instruction = ND_INS_VHADDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1212, + .Mnemonic = 1274, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87273,12 +88559,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3121 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + // Pos:3166 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" { .Instruction = ND_INS_VHADDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1213, + .Mnemonic = 1275, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87301,12 +88587,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3122 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + // Pos:3167 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" { .Instruction = ND_INS_VHSUBPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1214, + .Mnemonic = 1276, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87329,12 +88615,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3123 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + // Pos:3168 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" { .Instruction = ND_INS_VHSUBPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1215, + .Mnemonic = 1277, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87357,12 +88643,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3124 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + // Pos:3169 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" { .Instruction = ND_INS_VINSERTF128, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1216, + .Mnemonic = 1278, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87386,12 +88672,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3125 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + // Pos:3170 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1217, + .Mnemonic = 1279, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87416,12 +88702,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3126 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + // Pos:3171 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1218, + .Mnemonic = 1280, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87446,12 +88732,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3127 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + // Pos:3172 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1219, + .Mnemonic = 1281, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87476,12 +88762,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3128 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + // Pos:3173 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTF64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1220, + .Mnemonic = 1282, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87506,12 +88792,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3129 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + // Pos:3174 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" { .Instruction = ND_INS_VINSERTI128, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1221, + .Mnemonic = 1283, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87535,12 +88821,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3130 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + // Pos:3175 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1222, + .Mnemonic = 1284, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87565,12 +88851,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3131 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + // Pos:3176 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI32X8, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1223, + .Mnemonic = 1285, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87595,12 +88881,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3132 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + // Pos:3177 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1224, + .Mnemonic = 1286, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87625,12 +88911,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3133 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + // Pos:3178 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" { .Instruction = ND_INS_VINSERTI64X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1225, + .Mnemonic = 1287, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -87655,12 +88941,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3134 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:3179 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1226, + .Mnemonic = 1288, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87684,12 +88970,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3135 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:3180 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1226, + .Mnemonic = 1288, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87713,12 +88999,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3136 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + // Pos:3181 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1226, + .Mnemonic = 1288, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87742,12 +89028,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3137 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + // Pos:3182 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VINSERTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1226, + .Mnemonic = 1288, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87771,12 +89057,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3138 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + // Pos:3183 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" { .Instruction = ND_INS_VLDDQU, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1227, + .Mnemonic = 1289, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87798,12 +89084,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3139 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + // Pos:3184 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" { .Instruction = ND_INS_VLDMXCSR, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1228, + .Mnemonic = 1290, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87825,12 +89111,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3140 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + // Pos:3185 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" { .Instruction = ND_INS_VMASKMOVDQU, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1229, + .Mnemonic = 1291, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87853,12 +89139,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3141 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + // Pos:3186 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" { .Instruction = ND_INS_VMASKMOVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1230, + .Mnemonic = 1292, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87881,12 +89167,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3142 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + // Pos:3187 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" { .Instruction = ND_INS_VMASKMOVPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1230, + .Mnemonic = 1292, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87909,12 +89195,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3143 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + // Pos:3188 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" { .Instruction = ND_INS_VMASKMOVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1231, + .Mnemonic = 1293, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87937,12 +89223,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3144 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + // Pos:3189 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" { .Instruction = ND_INS_VMASKMOVPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1231, + .Mnemonic = 1293, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -87965,12 +89251,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3145 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + // Pos:3190 Instruction:"VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1294, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3191 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1232, + .Mnemonic = 1295, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -87994,12 +89309,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3146 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + // Pos:3192 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1232, + .Mnemonic = 1295, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88022,12 +89337,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3147 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:3193 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1233, + .Mnemonic = 1296, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88051,12 +89366,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3148 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + // Pos:3194 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1234, + .Mnemonic = 1297, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88080,12 +89395,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3149 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + // Pos:3195 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1234, + .Mnemonic = 1297, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88108,12 +89423,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3150 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + // Pos:3196 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1235, + .Mnemonic = 1298, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88137,12 +89452,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3151 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + // Pos:3197 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1235, + .Mnemonic = 1298, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88165,12 +89480,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3152 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:3198 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1236, + .Mnemonic = 1299, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88194,12 +89509,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3153 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + // Pos:3199 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" { .Instruction = ND_INS_VMAXSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1237, + .Mnemonic = 1300, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88223,12 +89538,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3154 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + // Pos:3200 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" { .Instruction = ND_INS_VMAXSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1237, + .Mnemonic = 1300, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88251,12 +89566,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3155 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" + // Pos:3201 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" { .Instruction = ND_INS_VMCALL, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1238, + .Mnemonic = 1301, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -88277,12 +89592,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3156 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + // Pos:3202 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" { .Instruction = ND_INS_VMCLEAR, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1239, + .Mnemonic = 1302, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -88304,12 +89619,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3157 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + // Pos:3203 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" { .Instruction = ND_INS_VMFUNC, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1240, + .Mnemonic = 1303, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -88330,12 +89645,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3158 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + // Pos:3204 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMGEXIT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1241, + .Mnemonic = 1304, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -88356,12 +89671,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3159 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + // Pos:3205 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMGEXIT, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1241, + .Mnemonic = 1304, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -88382,12 +89697,251 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3160 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + // Pos:3206 Instruction:"VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x52 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXNEPBF16, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1305, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3207 Instruction:"VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x52 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXPD, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1306, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3208 Instruction:"VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x52 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXPH, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1307, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3209 Instruction:"VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x52 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXPS, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1308, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3210 Instruction:"VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x53 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXSD, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1309, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3211 Instruction:"VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x53 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXSH, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1310, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3212 Instruction:"VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x53 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMINMAXSS, + .Category = ND_CAT_AVX10MINMAX, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1311, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3213 Instruction:"VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3214 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1242, + .Mnemonic = 1313, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88411,12 +89965,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3161 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + // Pos:3215 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1242, + .Mnemonic = 1313, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88439,12 +89993,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3162 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:3216 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1243, + .Mnemonic = 1314, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88468,12 +90022,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3163 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + // Pos:3217 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1244, + .Mnemonic = 1315, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -88497,12 +90051,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3164 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + // Pos:3218 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1244, + .Mnemonic = 1315, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88525,12 +90079,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3165 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + // Pos:3219 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1245, + .Mnemonic = 1316, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88554,12 +90108,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3166 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + // Pos:3220 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1245, + .Mnemonic = 1316, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88582,12 +90136,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3167 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:3221 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1246, + .Mnemonic = 1317, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88611,12 +90165,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3168 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + // Pos:3222 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" { .Instruction = ND_INS_VMINSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1247, + .Mnemonic = 1318, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -88640,12 +90194,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3169 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + // Pos:3223 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" { .Instruction = ND_INS_VMINSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1247, + .Mnemonic = 1318, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88668,12 +90222,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3170 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" + // Pos:3224 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" { .Instruction = ND_INS_VMLAUNCH, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1248, + .Mnemonic = 1319, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -88694,12 +90248,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3171 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + // Pos:3225 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" { .Instruction = ND_INS_VMLOAD, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1249, + .Mnemonic = 1320, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -88720,12 +90274,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3172 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/"" + // Pos:3226 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMMCALL, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1250, + .Mnemonic = 1321, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -88746,12 +90300,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3173 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" + // Pos:3227 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" { .Instruction = ND_INS_VMMCALL, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1250, + .Mnemonic = 1321, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -88772,12 +90326,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3174 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + // Pos:3228 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1251, + .Mnemonic = 1322, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88800,12 +90354,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3175 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + // Pos:3229 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1251, + .Mnemonic = 1322, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88828,12 +90382,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3176 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + // Pos:3230 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1251, + .Mnemonic = 1322, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88855,12 +90409,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3177 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + // Pos:3231 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" { .Instruction = ND_INS_VMOVAPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1251, + .Mnemonic = 1322, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88882,12 +90436,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3178 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + // Pos:3232 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1252, + .Mnemonic = 1323, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88910,12 +90464,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3179 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + // Pos:3233 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1252, + .Mnemonic = 1323, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -88938,12 +90492,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3180 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + // Pos:3234 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1252, + .Mnemonic = 1323, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88965,12 +90519,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3181 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + // Pos:3235 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" { .Instruction = ND_INS_VMOVAPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1252, + .Mnemonic = 1323, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -88992,12 +90546,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3182 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:3236 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1253, + .Mnemonic = 1324, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89019,12 +90573,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3183 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:3237 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1253, + .Mnemonic = 1324, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89046,12 +90600,66 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3184 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + // Pos:3238 Instruction:"VMOVD Vdq,Wd" Encoding:"evex m:1 p:2 l:0 w:0 0x7E /r"/"RM" + { + .Instruction = ND_INS_VMOVD, + .Category = ND_CAT_AVX10PARTCOPY, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1324, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3239 Instruction:"VMOVD Wd,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0xD6 /r"/"MR" + { + .Instruction = ND_INS_VMOVD, + .Category = ND_CAT_AVX10PARTCOPY, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1324, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3240 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1253, + .Mnemonic = 1324, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89073,12 +90681,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3185 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + // Pos:3241 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1253, + .Mnemonic = 1324, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89100,12 +90708,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3186 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + // Pos:3242 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1254, + .Mnemonic = 1325, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89128,12 +90736,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3187 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + // Pos:3243 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1254, + .Mnemonic = 1325, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89156,12 +90764,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3188 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + // Pos:3244 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1254, + .Mnemonic = 1325, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89184,12 +90792,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3189 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + // Pos:3245 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1254, + .Mnemonic = 1325, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89211,12 +90819,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3190 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + // Pos:3246 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" { .Instruction = ND_INS_VMOVDDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1254, + .Mnemonic = 1325, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89238,12 +90846,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3191 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + // Pos:3247 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" { .Instruction = ND_INS_VMOVDQA, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1255, + .Mnemonic = 1326, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89265,12 +90873,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3192 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + // Pos:3248 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" { .Instruction = ND_INS_VMOVDQA, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1255, + .Mnemonic = 1326, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89292,12 +90900,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3193 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + // Pos:3249 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQA32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1256, + .Mnemonic = 1327, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89320,12 +90928,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3194 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + // Pos:3250 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQA32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1256, + .Mnemonic = 1327, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89348,12 +90956,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3195 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + // Pos:3251 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQA64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1257, + .Mnemonic = 1328, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89376,12 +90984,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3196 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + // Pos:3252 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQA64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1257, + .Mnemonic = 1328, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89404,12 +91012,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3197 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + // Pos:3253 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" { .Instruction = ND_INS_VMOVDQU, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1258, + .Mnemonic = 1329, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89431,12 +91039,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3198 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + // Pos:3254 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" { .Instruction = ND_INS_VMOVDQU, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1258, + .Mnemonic = 1329, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89458,12 +91066,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3199 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + // Pos:3255 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU16, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1259, + .Mnemonic = 1330, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89486,12 +91094,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3200 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + // Pos:3256 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU16, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1259, + .Mnemonic = 1330, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89514,12 +91122,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3201 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + // Pos:3257 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1260, + .Mnemonic = 1331, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89542,12 +91150,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3202 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + // Pos:3258 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU32, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1260, + .Mnemonic = 1331, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89570,12 +91178,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3203 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + // Pos:3259 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1261, + .Mnemonic = 1332, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89598,12 +91206,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3204 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + // Pos:3260 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU64, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1261, + .Mnemonic = 1332, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89626,12 +91234,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3205 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + // Pos:3261 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" { .Instruction = ND_INS_VMOVDQU8, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1262, + .Mnemonic = 1333, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89654,12 +91262,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3206 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + // Pos:3262 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" { .Instruction = ND_INS_VMOVDQU8, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1262, + .Mnemonic = 1333, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -89682,12 +91290,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3207 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + // Pos:3263 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVHLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1263, + .Mnemonic = 1334, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89710,12 +91318,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3208 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + // Pos:3264 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVHLPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1263, + .Mnemonic = 1334, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89738,12 +91346,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3209 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + // Pos:3265 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1264, + .Mnemonic = 1335, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89766,12 +91374,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3210 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + // Pos:3266 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1264, + .Mnemonic = 1335, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89793,12 +91401,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3211 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:3267 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1264, + .Mnemonic = 1335, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89821,12 +91429,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3212 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:3268 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1264, + .Mnemonic = 1335, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89848,12 +91456,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3213 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + // Pos:3269 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1265, + .Mnemonic = 1336, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89876,12 +91484,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3214 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + // Pos:3270 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1265, + .Mnemonic = 1336, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89903,12 +91511,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3215 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + // Pos:3271 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1265, + .Mnemonic = 1336, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89931,12 +91539,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3216 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + // Pos:3272 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" { .Instruction = ND_INS_VMOVHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1265, + .Mnemonic = 1336, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89958,12 +91566,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3217 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + // Pos:3273 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVLHPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1266, + .Mnemonic = 1337, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -89986,12 +91594,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3218 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + // Pos:3274 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVLHPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1266, + .Mnemonic = 1337, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90014,12 +91622,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3219 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + // Pos:3275 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1267, + .Mnemonic = 1338, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90042,12 +91650,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3220 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + // Pos:3276 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1267, + .Mnemonic = 1338, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90069,12 +91677,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3221 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:3277 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1267, + .Mnemonic = 1338, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90097,12 +91705,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3222 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:3278 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1267, + .Mnemonic = 1338, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90124,12 +91732,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3223 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + // Pos:3279 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1268, + .Mnemonic = 1339, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90152,12 +91760,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3224 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + // Pos:3280 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1268, + .Mnemonic = 1339, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90179,12 +91787,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3225 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + // Pos:3281 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1268, + .Mnemonic = 1339, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90207,12 +91815,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3226 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + // Pos:3282 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" { .Instruction = ND_INS_VMOVLPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1268, + .Mnemonic = 1339, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90234,12 +91842,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3227 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + // Pos:3283 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" { .Instruction = ND_INS_VMOVMSKPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1269, + .Mnemonic = 1340, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90261,12 +91869,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3228 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + // Pos:3284 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" { .Instruction = ND_INS_VMOVMSKPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1270, + .Mnemonic = 1341, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90288,12 +91896,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3229 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + // Pos:3285 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTDQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1271, + .Mnemonic = 1342, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90315,12 +91923,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3230 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + // Pos:3286 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1271, + .Mnemonic = 1342, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90342,12 +91950,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3231 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + // Pos:3287 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" { .Instruction = ND_INS_VMOVNTDQA, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1272, + .Mnemonic = 1343, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90369,12 +91977,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3232 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + // Pos:3288 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" { .Instruction = ND_INS_VMOVNTDQA, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1272, + .Mnemonic = 1343, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90396,12 +92004,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3233 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + // Pos:3289 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1273, + .Mnemonic = 1344, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90423,12 +92031,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3234 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + // Pos:3290 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1273, + .Mnemonic = 1344, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90450,12 +92058,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3235 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + // Pos:3291 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1274, + .Mnemonic = 1345, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90477,12 +92085,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3236 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + // Pos:3292 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" { .Instruction = ND_INS_VMOVNTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1274, + .Mnemonic = 1345, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90504,12 +92112,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3237 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:3293 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90531,12 +92139,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3238 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:3294 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90558,12 +92166,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3239 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + // Pos:3295 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90585,12 +92193,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3240 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + // Pos:3296 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90612,12 +92220,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3241 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + // Pos:3297 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90639,12 +92247,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3242 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + // Pos:3298 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90666,12 +92274,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3243 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + // Pos:3299 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90693,12 +92301,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3244 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + // Pos:3300 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" { .Instruction = ND_INS_VMOVQ, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1275, + .Mnemonic = 1346, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90720,12 +92328,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3245 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + // Pos:3301 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90748,12 +92356,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3246 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + // Pos:3302 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90777,12 +92385,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3247 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + // Pos:3303 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -90805,12 +92413,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3248 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + // Pos:3304 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90834,12 +92442,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3249 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:3305 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90862,12 +92470,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3250 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + // Pos:3306 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90889,12 +92497,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3251 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:3307 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90917,12 +92525,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3252 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + // Pos:3308 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" { .Instruction = ND_INS_VMOVSD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1276, + .Mnemonic = 1347, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -90944,12 +92552,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3253 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:3309 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1277, + .Mnemonic = 1348, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -90972,12 +92580,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3254 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:3310 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1277, + .Mnemonic = 1348, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91001,12 +92609,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3255 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:3311 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1277, + .Mnemonic = 1348, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -91029,12 +92637,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3256 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:3312 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { .Instruction = ND_INS_VMOVSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1277, + .Mnemonic = 1348, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91058,12 +92666,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3257 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + // Pos:3313 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" { .Instruction = ND_INS_VMOVSHDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1278, + .Mnemonic = 1349, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91086,12 +92694,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3258 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + // Pos:3314 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" { .Instruction = ND_INS_VMOVSHDUP, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1278, + .Mnemonic = 1349, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91113,12 +92721,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3259 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + // Pos:3315 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" { .Instruction = ND_INS_VMOVSLDUP, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1279, + .Mnemonic = 1350, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91141,12 +92749,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3260 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + // Pos:3316 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" { .Instruction = ND_INS_VMOVSLDUP, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1279, + .Mnemonic = 1350, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91168,12 +92776,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3261 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + // Pos:3317 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91196,12 +92804,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3262 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + // Pos:3318 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91225,12 +92833,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3263 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + // Pos:3319 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -91253,12 +92861,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3264 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + // Pos:3320 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91282,12 +92890,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3265 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + // Pos:3321 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91310,12 +92918,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3266 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + // Pos:3322 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91337,12 +92945,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3267 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + // Pos:3323 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91365,12 +92973,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3268 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + // Pos:3324 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" { .Instruction = ND_INS_VMOVSS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1280, + .Mnemonic = 1351, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91392,12 +93000,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3269 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + // Pos:3325 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1281, + .Mnemonic = 1352, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91420,12 +93028,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3270 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + // Pos:3326 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1281, + .Mnemonic = 1352, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91448,12 +93056,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3271 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + // Pos:3327 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1281, + .Mnemonic = 1352, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91475,12 +93083,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3272 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + // Pos:3328 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" { .Instruction = ND_INS_VMOVUPD, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1281, + .Mnemonic = 1352, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91502,12 +93110,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3273 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + // Pos:3329 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1282, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91530,12 +93138,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3274 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + // Pos:3330 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1282, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -91558,12 +93166,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3275 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + // Pos:3331 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1282, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91585,12 +93193,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3276 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + // Pos:3332 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" { .Instruction = ND_INS_VMOVUPS, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX, - .Mnemonic = 1282, + .Mnemonic = 1353, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91612,12 +93220,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3277 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" + // Pos:3333 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1283, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91639,12 +93247,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3278 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" + // Pos:3334 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1283, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91666,12 +93274,39 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3279 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" + // Pos:3335 Instruction:"VMOVW Vdq,Ww" Encoding:"evex m:5 p:2 l:0 w:0 0x6E /r"/"RM" + { + .Instruction = ND_INS_VMOVW, + .Category = ND_CAT_AVX10PARTCOPY, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1354, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3336 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1283, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91693,12 +93328,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3280 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" + // Pos:3337 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" { .Instruction = ND_INS_VMOVW, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1283, + .Mnemonic = 1354, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91720,12 +93355,69 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3281 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + // Pos:3338 Instruction:"VMOVW Ww,Vdq" Encoding:"evex m:5 p:2 l:0 w:0 0x7E /r"/"MR" + { + .Instruction = ND_INS_VMOVW, + .Category = ND_CAT_AVX10PARTCOPY, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1354, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3339 Instruction:"VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:2 l:x w:0 0x42 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VMPSADBW, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1355, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3340 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" { .Instruction = ND_INS_VMPSADBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1284, + .Mnemonic = 1355, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91749,12 +93441,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3282 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + // Pos:3341 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" { .Instruction = ND_INS_VMPTRLD, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1285, + .Mnemonic = 1356, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -91776,12 +93468,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3283 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + // Pos:3342 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" { .Instruction = ND_INS_VMPTRST, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1286, + .Mnemonic = 1357, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -91803,12 +93495,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3284 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + // Pos:3343 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" { .Instruction = ND_INS_VMREAD, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1287, + .Mnemonic = 1358, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -91831,12 +93523,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3285 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" + // Pos:3344 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" { .Instruction = ND_INS_VMRESUME, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1288, + .Mnemonic = 1359, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -91857,12 +93549,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3286 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + // Pos:3345 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" { .Instruction = ND_INS_VMRUN, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1289, + .Mnemonic = 1360, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -91883,12 +93575,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3287 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + // Pos:3346 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" { .Instruction = ND_INS_VMSAVE, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_SVM, - .Mnemonic = 1290, + .Mnemonic = 1361, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -91909,12 +93601,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3288 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + // Pos:3347 Instruction:"VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULNEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1362, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3348 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1291, + .Mnemonic = 1363, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -91938,12 +93659,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3289 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + // Pos:3349 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1291, + .Mnemonic = 1363, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -91966,12 +93687,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3290 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:3350 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1292, + .Mnemonic = 1364, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -91995,12 +93716,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3291 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + // Pos:3351 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1293, + .Mnemonic = 1365, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -92024,12 +93745,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3292 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + // Pos:3352 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1293, + .Mnemonic = 1365, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92052,12 +93773,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3293 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + // Pos:3353 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1294, + .Mnemonic = 1366, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -92081,12 +93802,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3294 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + // Pos:3354 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1294, + .Mnemonic = 1366, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92109,12 +93830,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3295 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:3355 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1295, + .Mnemonic = 1367, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -92138,12 +93859,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3296 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + // Pos:3356 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" { .Instruction = ND_INS_VMULSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1296, + .Mnemonic = 1368, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -92167,12 +93888,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3297 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + // Pos:3357 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" { .Instruction = ND_INS_VMULSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1296, + .Mnemonic = 1368, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92195,12 +93916,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3298 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + // Pos:3358 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" { .Instruction = ND_INS_VMWRITE, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1297, + .Mnemonic = 1369, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -92223,12 +93944,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3299 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" + // Pos:3359 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" { .Instruction = ND_INS_VMXOFF, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1298, + .Mnemonic = 1370, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -92249,12 +93970,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3300 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + // Pos:3360 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" { .Instruction = ND_INS_VMXON, .Category = ND_CAT_VTX, .IsaSet = ND_SET_VTX, - .Mnemonic = 1299, + .Mnemonic = 1371, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, .ValidDecorators = 0, @@ -92276,12 +93997,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3301 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + // Pos:3361 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" { .Instruction = ND_INS_VORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1300, + .Mnemonic = 1372, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -92305,12 +94026,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3302 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + // Pos:3362 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" { .Instruction = ND_INS_VORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1300, + .Mnemonic = 1372, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92333,12 +94054,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3303 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + // Pos:3363 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" { .Instruction = ND_INS_VORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1301, + .Mnemonic = 1373, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -92362,12 +94083,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3304 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + // Pos:3364 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" { .Instruction = ND_INS_VORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1301, + .Mnemonic = 1373, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92390,12 +94111,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3305 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + // Pos:3365 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" { .Instruction = ND_INS_VP2INTERSECTD, .Category = ND_CAT_AVX512VP2INTERSECT, .IsaSet = ND_SET_AVX512VP2INTERSECT, - .Mnemonic = 1302, + .Mnemonic = 1374, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_BROADCAST, @@ -92418,12 +94139,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3306 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + // Pos:3366 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" { .Instruction = ND_INS_VP2INTERSECTQ, .Category = ND_CAT_AVX512VP2INTERSECT, .IsaSet = ND_SET_AVX512VP2INTERSECT, - .Mnemonic = 1303, + .Mnemonic = 1375, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_BROADCAST, @@ -92446,12 +94167,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3307 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + // Pos:3367 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" { .Instruction = ND_INS_VP4DPWSSD, .Category = ND_CAT_VNNIW, .IsaSet = ND_SET_AVX5124VNNIW, - .Mnemonic = 1304, + .Mnemonic = 1376, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92475,12 +94196,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3308 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + // Pos:3368 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" { .Instruction = ND_INS_VP4DPWSSDS, .Category = ND_CAT_VNNIW, .IsaSet = ND_SET_AVX5124VNNIW, - .Mnemonic = 1305, + .Mnemonic = 1377, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92504,12 +94225,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3309 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + // Pos:3369 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" { .Instruction = ND_INS_VPABSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1306, + .Mnemonic = 1378, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92532,12 +94253,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3310 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + // Pos:3370 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" { .Instruction = ND_INS_VPABSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1306, + .Mnemonic = 1378, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92559,12 +94280,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3311 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + // Pos:3371 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" { .Instruction = ND_INS_VPABSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1307, + .Mnemonic = 1379, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -92587,12 +94308,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3312 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + // Pos:3372 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" { .Instruction = ND_INS_VPABSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1307, + .Mnemonic = 1379, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92614,12 +94335,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3313 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + // Pos:3373 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" { .Instruction = ND_INS_VPABSQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1308, + .Mnemonic = 1380, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -92642,12 +94363,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3314 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + // Pos:3374 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" { .Instruction = ND_INS_VPABSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1309, + .Mnemonic = 1381, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92670,12 +94391,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3315 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + // Pos:3375 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" { .Instruction = ND_INS_VPABSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1309, + .Mnemonic = 1381, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92697,12 +94418,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3316 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + // Pos:3376 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" { .Instruction = ND_INS_VPACKSSDW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1310, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -92726,12 +94447,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3317 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + // Pos:3377 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" { .Instruction = ND_INS_VPACKSSDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1310, + .Mnemonic = 1382, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92754,12 +94475,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3318 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + // Pos:3378 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" { .Instruction = ND_INS_VPACKSSWB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1311, + .Mnemonic = 1383, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92783,12 +94504,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3319 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + // Pos:3379 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" { .Instruction = ND_INS_VPACKSSWB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1311, + .Mnemonic = 1383, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92811,12 +94532,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3320 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + // Pos:3380 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" { .Instruction = ND_INS_VPACKUSDW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1312, + .Mnemonic = 1384, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -92840,12 +94561,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3321 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + // Pos:3381 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" { .Instruction = ND_INS_VPACKUSDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1312, + .Mnemonic = 1384, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92868,12 +94589,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3322 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + // Pos:3382 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" { .Instruction = ND_INS_VPACKUSWB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1313, + .Mnemonic = 1385, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92897,12 +94618,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3323 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + // Pos:3383 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" { .Instruction = ND_INS_VPACKUSWB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1313, + .Mnemonic = 1385, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92925,12 +94646,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3324 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + // Pos:3384 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" { .Instruction = ND_INS_VPADDB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1314, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -92954,12 +94675,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3325 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + // Pos:3385 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" { .Instruction = ND_INS_VPADDB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1314, + .Mnemonic = 1386, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -92982,12 +94703,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3326 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + // Pos:3386 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" { .Instruction = ND_INS_VPADDD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1315, + .Mnemonic = 1387, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93011,12 +94732,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3327 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + // Pos:3387 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" { .Instruction = ND_INS_VPADDD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1315, + .Mnemonic = 1387, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93039,12 +94760,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3328 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + // Pos:3388 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" { .Instruction = ND_INS_VPADDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1316, + .Mnemonic = 1388, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93068,12 +94789,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3329 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + // Pos:3389 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" { .Instruction = ND_INS_VPADDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1316, + .Mnemonic = 1388, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93096,12 +94817,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3330 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + // Pos:3390 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" { .Instruction = ND_INS_VPADDSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1317, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93125,12 +94846,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3331 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + // Pos:3391 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" { .Instruction = ND_INS_VPADDSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1317, + .Mnemonic = 1389, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93153,12 +94874,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3332 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + // Pos:3392 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" { .Instruction = ND_INS_VPADDSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1318, + .Mnemonic = 1390, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93182,12 +94903,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3333 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + // Pos:3393 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" { .Instruction = ND_INS_VPADDSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1318, + .Mnemonic = 1390, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93210,12 +94931,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3334 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + // Pos:3394 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" { .Instruction = ND_INS_VPADDUSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1319, + .Mnemonic = 1391, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93239,12 +94960,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3335 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:3395 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" { .Instruction = ND_INS_VPADDUSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1319, + .Mnemonic = 1391, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93267,12 +94988,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3336 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + // Pos:3396 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" { .Instruction = ND_INS_VPADDUSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1320, + .Mnemonic = 1392, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93296,12 +95017,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3337 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:3397 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" { .Instruction = ND_INS_VPADDUSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1320, + .Mnemonic = 1392, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93324,12 +95045,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3338 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + // Pos:3398 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" { .Instruction = ND_INS_VPADDW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1321, + .Mnemonic = 1393, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93353,12 +95074,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3339 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + // Pos:3399 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" { .Instruction = ND_INS_VPADDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1321, + .Mnemonic = 1393, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93381,12 +95102,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3340 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + // Pos:3400 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" { .Instruction = ND_INS_VPALIGNR, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1322, + .Mnemonic = 1394, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93411,12 +95132,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3341 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + // Pos:3401 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" { .Instruction = ND_INS_VPALIGNR, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1322, + .Mnemonic = 1394, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93440,12 +95161,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3342 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + // Pos:3402 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" { .Instruction = ND_INS_VPAND, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1323, + .Mnemonic = 1395, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93468,12 +95189,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3343 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + // Pos:3403 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" { .Instruction = ND_INS_VPANDD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1324, + .Mnemonic = 1396, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93497,12 +95218,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3344 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:3404 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" { .Instruction = ND_INS_VPANDN, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1325, + .Mnemonic = 1397, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93525,12 +95246,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3345 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + // Pos:3405 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" { .Instruction = ND_INS_VPANDND, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1326, + .Mnemonic = 1398, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93554,12 +95275,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3346 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + // Pos:3406 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" { .Instruction = ND_INS_VPANDNQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1327, + .Mnemonic = 1399, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93583,12 +95304,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3347 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + // Pos:3407 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" { .Instruction = ND_INS_VPANDQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1328, + .Mnemonic = 1400, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93612,12 +95333,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3348 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + // Pos:3408 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" { .Instruction = ND_INS_VPAVGB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1329, + .Mnemonic = 1401, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93641,12 +95362,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3349 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + // Pos:3409 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" { .Instruction = ND_INS_VPAVGB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1329, + .Mnemonic = 1401, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93669,12 +95390,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3350 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + // Pos:3410 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" { .Instruction = ND_INS_VPAVGW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1330, + .Mnemonic = 1402, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93698,12 +95419,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3351 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + // Pos:3411 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" { .Instruction = ND_INS_VPAVGW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1330, + .Mnemonic = 1402, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93726,12 +95447,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3352 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + // Pos:3412 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" { .Instruction = ND_INS_VPBLENDD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1331, + .Mnemonic = 1403, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93755,12 +95476,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3353 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:3413 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMB, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1332, + .Mnemonic = 1404, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93784,12 +95505,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3354 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + // Pos:3414 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMD, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1333, + .Mnemonic = 1405, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93813,12 +95534,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3355 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + // Pos:3415 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMQ, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1334, + .Mnemonic = 1406, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -93842,12 +95563,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3356 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + // Pos:3416 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" { .Instruction = ND_INS_VPBLENDMW, .Category = ND_CAT_BLEND, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1335, + .Mnemonic = 1407, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93871,12 +95592,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3357 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + // Pos:3417 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" { .Instruction = ND_INS_VPBLENDVB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1336, + .Mnemonic = 1408, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93900,12 +95621,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3358 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + // Pos:3418 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" { .Instruction = ND_INS_VPBLENDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1337, + .Mnemonic = 1409, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -93929,12 +95650,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3359 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:3419 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTB, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1338, + .Mnemonic = 1410, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93957,12 +95678,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3360 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + // Pos:3420 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTB, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1338, + .Mnemonic = 1410, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -93985,12 +95706,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3361 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + // Pos:3421 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTB, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1338, + .Mnemonic = 1410, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94012,12 +95733,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3362 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + // Pos:3422 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1339, + .Mnemonic = 1411, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94040,12 +95761,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3363 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + // Pos:3423 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1339, + .Mnemonic = 1411, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94068,12 +95789,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3364 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + // Pos:3424 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTD, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1339, + .Mnemonic = 1411, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94095,12 +95816,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3365 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + // Pos:3425 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" { .Instruction = ND_INS_VPBROADCASTMB2Q, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1340, + .Mnemonic = 1412, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94122,12 +95843,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3366 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + // Pos:3426 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" { .Instruction = ND_INS_VPBROADCASTMW2D, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1341, + .Mnemonic = 1413, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94149,12 +95870,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3367 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + // Pos:3427 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTQ, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1342, + .Mnemonic = 1414, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94177,12 +95898,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3368 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + // Pos:3428 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTQ, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1342, + .Mnemonic = 1414, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94205,12 +95926,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3369 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + // Pos:3429 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTQ, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1342, + .Mnemonic = 1414, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94232,12 +95953,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3370 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:3430 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" { .Instruction = ND_INS_VPBROADCASTW, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1343, + .Mnemonic = 1415, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94260,12 +95981,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3371 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + // Pos:3431 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" { .Instruction = ND_INS_VPBROADCASTW, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1343, + .Mnemonic = 1415, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -94288,12 +96009,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3372 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + // Pos:3432 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" { .Instruction = ND_INS_VPBROADCASTW, .Category = ND_CAT_BROADCAST, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1343, + .Mnemonic = 1415, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94315,12 +96036,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3373 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:3433 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { .Instruction = ND_INS_VPCLMULQDQ, .Category = ND_CAT_VPCLMULQDQ, .IsaSet = ND_SET_VPCLMULQDQ, - .Mnemonic = 1344, + .Mnemonic = 1416, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94344,12 +96065,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3374 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + // Pos:3434 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { .Instruction = ND_INS_VPCLMULQDQ, .Category = ND_CAT_VPCLMULQDQ, .IsaSet = ND_SET_VPCLMULQDQ, - .Mnemonic = 1344, + .Mnemonic = 1416, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94373,12 +96094,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3375 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + // Pos:3435 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" { .Instruction = ND_INS_VPCMOV, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1345, + .Mnemonic = 1417, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94402,12 +96123,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3376 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + // Pos:3436 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" { .Instruction = ND_INS_VPCMOV, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1345, + .Mnemonic = 1417, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94431,12 +96152,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3377 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + // Pos:3437 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1346, + .Mnemonic = 1418, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -94461,12 +96182,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3378 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + // Pos:3438 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1347, + .Mnemonic = 1419, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -94491,12 +96212,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3379 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + // Pos:3439 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1348, + .Mnemonic = 1420, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -94520,12 +96241,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3380 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + // Pos:3440 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1348, + .Mnemonic = 1420, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94548,12 +96269,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3381 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + // Pos:3441 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1349, + .Mnemonic = 1421, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -94577,12 +96298,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3382 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + // Pos:3442 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1349, + .Mnemonic = 1421, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94605,12 +96326,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3383 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + // Pos:3443 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1350, + .Mnemonic = 1422, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -94634,12 +96355,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3384 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + // Pos:3444 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1350, + .Mnemonic = 1422, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94662,12 +96383,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3385 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + // Pos:3445 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" { .Instruction = ND_INS_VPCMPEQW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1351, + .Mnemonic = 1423, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -94691,12 +96412,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3386 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + // Pos:3446 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" { .Instruction = ND_INS_VPCMPEQW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1351, + .Mnemonic = 1423, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94719,12 +96440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3387 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + // Pos:3447 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPESTRI, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1352, + .Mnemonic = 1424, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94751,12 +96472,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3388 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + // Pos:3448 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPESTRM, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1353, + .Mnemonic = 1425, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94783,12 +96504,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3389 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + // Pos:3449 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1354, + .Mnemonic = 1426, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -94812,12 +96533,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3390 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + // Pos:3450 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1354, + .Mnemonic = 1426, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94840,12 +96561,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3391 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + // Pos:3451 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1355, + .Mnemonic = 1427, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -94869,12 +96590,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3392 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + // Pos:3452 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1355, + .Mnemonic = 1427, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94897,12 +96618,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3393 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + // Pos:3453 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1356, + .Mnemonic = 1428, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -94926,12 +96647,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3394 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + // Pos:3454 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1356, + .Mnemonic = 1428, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -94954,12 +96675,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3395 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + // Pos:3455 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" { .Instruction = ND_INS_VPCMPGTW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1357, + .Mnemonic = 1429, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -94983,12 +96704,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3396 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + // Pos:3456 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" { .Instruction = ND_INS_VPCMPGTW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1357, + .Mnemonic = 1429, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95011,12 +96732,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3397 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + // Pos:3457 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPISTRI, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1358, + .Mnemonic = 1430, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95041,12 +96762,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3398 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + // Pos:3458 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" { .Instruction = ND_INS_VPCMPISTRM, .Category = ND_CAT_STTNI, .IsaSet = ND_SET_AVX, - .Mnemonic = 1359, + .Mnemonic = 1431, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95071,12 +96792,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3399 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + // Pos:3459 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1360, + .Mnemonic = 1432, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -95101,12 +96822,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3400 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + // Pos:3460 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1361, + .Mnemonic = 1433, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -95131,12 +96852,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3401 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + // Pos:3461 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1362, + .Mnemonic = 1434, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -95161,12 +96882,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3402 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + // Pos:3462 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1363, + .Mnemonic = 1435, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -95191,12 +96912,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3403 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + // Pos:3463 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPUW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1364, + .Mnemonic = 1436, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -95221,12 +96942,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3404 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + // Pos:3464 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" { .Instruction = ND_INS_VPCMPW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1365, + .Mnemonic = 1437, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -95251,12 +96972,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3405 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + // Pos:3465 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1366, + .Mnemonic = 1438, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95280,12 +97001,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3406 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + // Pos:3466 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1367, + .Mnemonic = 1439, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95309,12 +97030,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3407 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + // Pos:3467 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1368, + .Mnemonic = 1440, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95337,12 +97058,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3408 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + // Pos:3468 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSD, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1369, + .Mnemonic = 1441, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95365,12 +97086,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3409 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + // Pos:3469 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSQ, .Category = ND_CAT_COMPRESS, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1370, + .Mnemonic = 1442, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95393,12 +97114,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3410 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + // Pos:3470 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" { .Instruction = ND_INS_VPCOMPRESSW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1371, + .Mnemonic = 1443, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -95421,12 +97142,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3411 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + // Pos:3471 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1372, + .Mnemonic = 1444, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95450,12 +97171,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3412 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + // Pos:3472 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUB, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1373, + .Mnemonic = 1445, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95479,12 +97200,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3413 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + // Pos:3473 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1374, + .Mnemonic = 1446, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95508,12 +97229,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3414 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + // Pos:3474 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1375, + .Mnemonic = 1447, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95537,12 +97258,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3415 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + // Pos:3475 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMUW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1376, + .Mnemonic = 1448, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95566,12 +97287,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3416 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + // Pos:3476 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" { .Instruction = ND_INS_VPCOMW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1377, + .Mnemonic = 1449, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95595,12 +97316,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3417 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + // Pos:3477 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" { .Instruction = ND_INS_VPCONFLICTD, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1378, + .Mnemonic = 1450, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95623,12 +97344,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3418 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + // Pos:3478 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" { .Instruction = ND_INS_VPCONFLICTQ, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1379, + .Mnemonic = 1451, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95651,12 +97372,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3419 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" + // Pos:3479 Instruction:"VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x50 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBSSD, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1452, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3480 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBSSD, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1380, + .Mnemonic = 1452, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95679,12 +97429,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3420 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" + // Pos:3481 Instruction:"VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBSSDS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1453, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3482 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBSSDS, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1381, + .Mnemonic = 1453, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95707,12 +97486,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3421 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" + // Pos:3483 Instruction:"VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x50 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBSUD, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1454, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3484 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBSUD, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1382, + .Mnemonic = 1454, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95735,12 +97543,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3422 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" + // Pos:3485 Instruction:"VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBSUDS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1455, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3486 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBSUDS, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1383, + .Mnemonic = 1455, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95763,12 +97600,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3423 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + // Pos:3487 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" { .Instruction = ND_INS_VPDPBUSD, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1384, + .Mnemonic = 1456, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95792,12 +97629,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3424 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" + // Pos:3488 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBUSD, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1384, + .Mnemonic = 1456, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95820,12 +97657,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3425 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + // Pos:3489 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VPDPBUSDS, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1385, + .Mnemonic = 1457, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95849,12 +97686,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3426 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" + // Pos:3490 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBUSDS, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1385, + .Mnemonic = 1457, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95877,12 +97714,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3427 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" + // Pos:3491 Instruction:"VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x50 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBUUD, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1458, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3492 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" { .Instruction = ND_INS_VPDPBUUD, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1386, + .Mnemonic = 1458, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95905,12 +97771,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3428 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" + // Pos:3493 Instruction:"VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBUUDS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1459, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3494 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" { .Instruction = ND_INS_VPDPBUUDS, .Category = ND_CAT_AVXVNNIINT8, .IsaSet = ND_SET_AVXVNNIINT8, - .Mnemonic = 1387, + .Mnemonic = 1459, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95933,12 +97828,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3429 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + // Pos:3495 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" { .Instruction = ND_INS_VPDPWSSD, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1388, + .Mnemonic = 1460, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -95962,12 +97857,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3430 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" + // Pos:3496 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" { .Instruction = ND_INS_VPDPWSSD, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1388, + .Mnemonic = 1460, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -95990,12 +97885,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3431 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + // Pos:3497 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" { .Instruction = ND_INS_VPDPWSSDS, .Category = ND_CAT_VNNI, .IsaSet = ND_SET_AVX512VNNI, - .Mnemonic = 1389, + .Mnemonic = 1461, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96019,12 +97914,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3432 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" + // Pos:3498 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" { .Instruction = ND_INS_VPDPWSSDS, .Category = ND_CAT_AVXVNNI, .IsaSet = ND_SET_AVXVNNI, - .Mnemonic = 1389, + .Mnemonic = 1461, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96047,12 +97942,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3433 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" + // Pos:3499 Instruction:"VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD2 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWSUD, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1462, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3500 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPDPWSUD, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1390, + .Mnemonic = 1462, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96075,12 +97999,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3434 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" + // Pos:3501 Instruction:"VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0xD3 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWSUDS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1463, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3502 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPDPWSUDS, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1391, + .Mnemonic = 1463, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96103,12 +98056,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3435 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" + // Pos:3503 Instruction:"VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD2 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWUSD, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1464, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3504 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPDPWUSD, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1392, + .Mnemonic = 1464, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96131,12 +98113,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3436 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" + // Pos:3505 Instruction:"VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xD3 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWUSDS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1465, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3506 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPDPWUSDS, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1393, + .Mnemonic = 1465, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96159,12 +98170,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3437 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" + // Pos:3507 Instruction:"VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD2 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWUUD, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1466, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3508 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" { .Instruction = ND_INS_VPDPWUUD, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1394, + .Mnemonic = 1466, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96187,12 +98227,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3438 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" + // Pos:3509 Instruction:"VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:0 l:x w:0 0xD3 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWUUDS, + .Category = ND_CAT_AVX10INT, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1467, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3510 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" { .Instruction = ND_INS_VPDPWUUDS, .Category = ND_CAT_AVXVNNIINT16, .IsaSet = ND_SET_AVXVNNIINT16, - .Mnemonic = 1395, + .Mnemonic = 1467, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96215,12 +98284,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3439 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + // Pos:3511 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" { .Instruction = ND_INS_VPERM2F128, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1396, + .Mnemonic = 1468, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96244,12 +98313,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3440 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + // Pos:3512 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" { .Instruction = ND_INS_VPERM2I128, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1397, + .Mnemonic = 1469, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96273,12 +98342,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3441 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + // Pos:3513 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" { .Instruction = ND_INS_VPERMB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1398, + .Mnemonic = 1470, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -96302,12 +98371,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3442 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + // Pos:3514 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" { .Instruction = ND_INS_VPERMD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1399, + .Mnemonic = 1471, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96331,12 +98400,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3443 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + // Pos:3515 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" { .Instruction = ND_INS_VPERMD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1399, + .Mnemonic = 1471, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96359,12 +98428,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3444 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + // Pos:3516 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2B, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1400, + .Mnemonic = 1472, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -96388,12 +98457,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3445 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + // Pos:3517 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2D, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1401, + .Mnemonic = 1473, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96417,12 +98486,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3446 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + // Pos:3518 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1402, + .Mnemonic = 1474, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96446,12 +98515,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3447 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + // Pos:3519 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1403, + .Mnemonic = 1475, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96475,12 +98544,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3448 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + // Pos:3520 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2Q, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1404, + .Mnemonic = 1476, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96504,12 +98573,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3449 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + // Pos:3521 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" { .Instruction = ND_INS_VPERMI2W, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1405, + .Mnemonic = 1477, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -96533,12 +98602,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3450 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL" + // Pos:3522 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL" { .Instruction = ND_INS_VPERMIL2PD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1406, + .Mnemonic = 1478, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96563,12 +98632,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3451 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML" + // Pos:3523 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML" { .Instruction = ND_INS_VPERMIL2PD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1406, + .Mnemonic = 1478, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96593,12 +98662,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3452 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL" + // Pos:3524 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL" { .Instruction = ND_INS_VPERMIL2PS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1407, + .Mnemonic = 1479, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96623,12 +98692,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3453 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML" + // Pos:3525 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML" { .Instruction = ND_INS_VPERMIL2PS, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1407, + .Mnemonic = 1479, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96653,12 +98722,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3454 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + // Pos:3526 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1408, + .Mnemonic = 1480, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96682,12 +98751,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3455 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + // Pos:3527 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1408, + .Mnemonic = 1480, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96711,12 +98780,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3456 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + // Pos:3528 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1408, + .Mnemonic = 1480, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96739,12 +98808,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3457 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + // Pos:3529 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" { .Instruction = ND_INS_VPERMILPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1408, + .Mnemonic = 1480, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96767,12 +98836,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3458 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + // Pos:3530 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1409, + .Mnemonic = 1481, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96796,12 +98865,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3459 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + // Pos:3531 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1409, + .Mnemonic = 1481, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96825,12 +98894,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3460 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + // Pos:3532 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1409, + .Mnemonic = 1481, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96853,12 +98922,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3461 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + // Pos:3533 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" { .Instruction = ND_INS_VPERMILPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1409, + .Mnemonic = 1481, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96881,12 +98950,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3462 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + // Pos:3534 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1410, + .Mnemonic = 1482, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96910,12 +98979,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3463 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + // Pos:3535 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1410, + .Mnemonic = 1482, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96939,12 +99008,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3464 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + // Pos:3536 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1410, + .Mnemonic = 1482, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -96968,12 +99037,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3465 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + // Pos:3537 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" { .Instruction = ND_INS_VPERMPD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1410, + .Mnemonic = 1482, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -96996,12 +99065,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3466 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + // Pos:3538 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1411, + .Mnemonic = 1483, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97025,12 +99094,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3467 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + // Pos:3539 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" { .Instruction = ND_INS_VPERMPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1411, + .Mnemonic = 1483, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97054,12 +99123,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3468 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + // Pos:3540 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" { .Instruction = ND_INS_VPERMPS, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1411, + .Mnemonic = 1483, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97082,12 +99151,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3469 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + // Pos:3541 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" { .Instruction = ND_INS_VPERMQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1412, + .Mnemonic = 1484, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97111,12 +99180,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3470 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + // Pos:3542 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" { .Instruction = ND_INS_VPERMQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1412, + .Mnemonic = 1484, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97140,12 +99209,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3471 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + // Pos:3543 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" { .Instruction = ND_INS_VPERMQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1412, + .Mnemonic = 1484, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97168,12 +99237,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3472 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + // Pos:3544 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" { .Instruction = ND_INS_VPERMT2B, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1413, + .Mnemonic = 1485, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97197,12 +99266,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3473 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + // Pos:3545 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" { .Instruction = ND_INS_VPERMT2D, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1414, + .Mnemonic = 1486, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97226,12 +99295,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3474 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + // Pos:3546 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" { .Instruction = ND_INS_VPERMT2PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1415, + .Mnemonic = 1487, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97255,12 +99324,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3475 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + // Pos:3547 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" { .Instruction = ND_INS_VPERMT2PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1416, + .Mnemonic = 1488, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97284,12 +99353,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3476 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + // Pos:3548 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" { .Instruction = ND_INS_VPERMT2Q, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1417, + .Mnemonic = 1489, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -97313,12 +99382,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3477 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + // Pos:3549 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" { .Instruction = ND_INS_VPERMT2W, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1418, + .Mnemonic = 1490, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97342,12 +99411,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3478 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + // Pos:3550 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" { .Instruction = ND_INS_VPERMW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1419, + .Mnemonic = 1491, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97371,12 +99440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3479 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + // Pos:3551 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDB, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1420, + .Mnemonic = 1492, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97399,12 +99468,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3480 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + // Pos:3552 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDD, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1421, + .Mnemonic = 1493, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97427,12 +99496,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3481 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + // Pos:3553 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDQ, .Category = ND_CAT_EXPAND, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1422, + .Mnemonic = 1494, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97455,12 +99524,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3482 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + // Pos:3554 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" { .Instruction = ND_INS_VPEXPANDW, .Category = ND_CAT_AVX512VBMI, .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1423, + .Mnemonic = 1495, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -97483,12 +99552,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3483 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:3555 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1424, + .Mnemonic = 1496, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97511,12 +99580,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3484 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:3556 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1424, + .Mnemonic = 1496, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97539,12 +99608,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3485 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + // Pos:3557 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1424, + .Mnemonic = 1496, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97567,12 +99636,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3486 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + // Pos:3558 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1424, + .Mnemonic = 1496, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97595,12 +99664,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3487 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + // Pos:3559 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1425, + .Mnemonic = 1497, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97623,12 +99692,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3488 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + // Pos:3560 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1425, + .Mnemonic = 1497, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97651,12 +99720,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3489 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + // Pos:3561 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1425, + .Mnemonic = 1497, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97679,12 +99748,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3490 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + // Pos:3562 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1425, + .Mnemonic = 1497, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97707,12 +99776,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3491 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + // Pos:3563 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1426, + .Mnemonic = 1498, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97735,12 +99804,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3492 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + // Pos:3564 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1426, + .Mnemonic = 1498, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97763,12 +99832,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3493 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + // Pos:3565 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1426, + .Mnemonic = 1498, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97791,12 +99860,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3494 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + // Pos:3566 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1426, + .Mnemonic = 1498, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97819,12 +99888,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3495 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:3567 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1427, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97847,12 +99916,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3496 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:3568 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1427, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97875,12 +99944,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3497 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:3569 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1427, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97903,12 +99972,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3498 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + // Pos:3570 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1427, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97931,12 +100000,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3499 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + // Pos:3571 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1427, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97959,12 +100028,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3500 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + // Pos:3572 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { .Instruction = ND_INS_VPEXTRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1427, + .Mnemonic = 1499, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -97987,12 +100056,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3501 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + // Pos:3573 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERDD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1428, + .Mnemonic = 1500, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -98015,12 +100084,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3502 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + // Pos:3574 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERDD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1428, + .Mnemonic = 1500, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98043,12 +100112,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3503 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + // Pos:3575 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERDQ, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1429, + .Mnemonic = 1501, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -98071,12 +100140,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3504 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + // Pos:3576 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERDQ, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1429, + .Mnemonic = 1501, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98099,12 +100168,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3505 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + // Pos:3577 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERQD, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1430, + .Mnemonic = 1502, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -98127,12 +100196,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3506 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + // Pos:3578 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERQD, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1430, + .Mnemonic = 1502, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98155,12 +100224,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3507 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + // Pos:3579 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" { .Instruction = ND_INS_VPGATHERQQ, .Category = ND_CAT_GATHER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1431, + .Mnemonic = 1503, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -98183,12 +100252,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3508 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + // Pos:3580 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" { .Instruction = ND_INS_VPGATHERQQ, .Category = ND_CAT_AVX2GATHER, .IsaSet = ND_SET_AVX2GATHER, - .Mnemonic = 1431, + .Mnemonic = 1503, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98211,12 +100280,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3509 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + // Pos:3581 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" { .Instruction = ND_INS_VPHADDBD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1432, + .Mnemonic = 1504, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98238,12 +100307,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3510 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + // Pos:3582 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" { .Instruction = ND_INS_VPHADDBQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1433, + .Mnemonic = 1505, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98265,12 +100334,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3511 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + // Pos:3583 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" { .Instruction = ND_INS_VPHADDBW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1434, + .Mnemonic = 1506, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98292,12 +100361,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3512 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + // Pos:3584 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" { .Instruction = ND_INS_VPHADDD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1435, + .Mnemonic = 1507, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98320,12 +100389,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3513 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + // Pos:3585 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" { .Instruction = ND_INS_VPHADDDQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1436, + .Mnemonic = 1508, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98347,12 +100416,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3514 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + // Pos:3586 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" { .Instruction = ND_INS_VPHADDSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1437, + .Mnemonic = 1509, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98375,12 +100444,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3515 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + // Pos:3587 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" { .Instruction = ND_INS_VPHADDUBD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1438, + .Mnemonic = 1510, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98402,12 +100471,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3516 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + // Pos:3588 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" { .Instruction = ND_INS_VPHADDUBQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1439, + .Mnemonic = 1511, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98429,12 +100498,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3517 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + // Pos:3589 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" { .Instruction = ND_INS_VPHADDUBW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1440, + .Mnemonic = 1512, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98456,12 +100525,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3518 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + // Pos:3590 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" { .Instruction = ND_INS_VPHADDUDQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1441, + .Mnemonic = 1513, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98483,12 +100552,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3519 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + // Pos:3591 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" { .Instruction = ND_INS_VPHADDUWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1442, + .Mnemonic = 1514, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98510,12 +100579,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3520 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + // Pos:3592 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" { .Instruction = ND_INS_VPHADDUWQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1443, + .Mnemonic = 1515, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98537,12 +100606,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3521 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + // Pos:3593 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" { .Instruction = ND_INS_VPHADDW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1444, + .Mnemonic = 1516, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98565,12 +100634,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3522 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + // Pos:3594 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" { .Instruction = ND_INS_VPHADDWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1445, + .Mnemonic = 1517, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98592,12 +100661,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3523 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + // Pos:3595 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" { .Instruction = ND_INS_VPHADDWQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1446, + .Mnemonic = 1518, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98619,12 +100688,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3524 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + // Pos:3596 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" { .Instruction = ND_INS_VPHMINPOSUW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1447, + .Mnemonic = 1519, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98646,12 +100715,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3525 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + // Pos:3597 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" { .Instruction = ND_INS_VPHSUBBW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1448, + .Mnemonic = 1520, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98673,12 +100742,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3526 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + // Pos:3598 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" { .Instruction = ND_INS_VPHSUBD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1449, + .Mnemonic = 1521, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98701,12 +100770,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3527 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + // Pos:3599 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" { .Instruction = ND_INS_VPHSUBDQ, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1450, + .Mnemonic = 1522, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98728,12 +100797,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3528 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + // Pos:3600 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" { .Instruction = ND_INS_VPHSUBSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1451, + .Mnemonic = 1523, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98756,12 +100825,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3529 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + // Pos:3601 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" { .Instruction = ND_INS_VPHSUBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1452, + .Mnemonic = 1524, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98784,12 +100853,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3530 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + // Pos:3602 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" { .Instruction = ND_INS_VPHSUBWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1453, + .Mnemonic = 1525, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98811,12 +100880,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3531 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:3603 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1454, + .Mnemonic = 1526, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98840,12 +100909,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3532 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:3604 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1454, + .Mnemonic = 1526, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98869,12 +100938,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3533 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + // Pos:3605 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1454, + .Mnemonic = 1526, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98898,12 +100967,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3534 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + // Pos:3606 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1454, + .Mnemonic = 1526, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98927,12 +100996,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3535 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:3607 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1455, + .Mnemonic = 1527, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98956,12 +101025,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3536 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + // Pos:3608 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1455, + .Mnemonic = 1527, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -98985,12 +101054,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3537 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:3609 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1456, + .Mnemonic = 1528, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99014,12 +101083,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3538 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + // Pos:3610 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { .Instruction = ND_INS_VPINSRQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1456, + .Mnemonic = 1528, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99043,12 +101112,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3539 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:3611 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1457, + .Mnemonic = 1529, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99072,12 +101141,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3540 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:3612 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1457, + .Mnemonic = 1529, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99101,12 +101170,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3541 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + // Pos:3613 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1457, + .Mnemonic = 1529, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99130,12 +101199,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3542 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + // Pos:3614 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { .Instruction = ND_INS_VPINSRW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1457, + .Mnemonic = 1529, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99159,12 +101228,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3543 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + // Pos:3615 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" { .Instruction = ND_INS_VPLZCNTD, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1458, + .Mnemonic = 1530, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99187,12 +101256,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3544 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + // Pos:3616 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" { .Instruction = ND_INS_VPLZCNTQ, .Category = ND_CAT_CONFLICT, .IsaSet = ND_SET_AVX512CD, - .Mnemonic = 1459, + .Mnemonic = 1531, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99215,12 +101284,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3545 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + // Pos:3617 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" { .Instruction = ND_INS_VPMACSDD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1460, + .Mnemonic = 1532, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99244,12 +101313,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3546 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + // Pos:3618 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" { .Instruction = ND_INS_VPMACSDQH, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1461, + .Mnemonic = 1533, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99273,12 +101342,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3547 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + // Pos:3619 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSDQL, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1462, + .Mnemonic = 1534, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99302,12 +101371,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3548 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + // Pos:3620 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSDD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1463, + .Mnemonic = 1535, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99331,12 +101400,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3549 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + // Pos:3621 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSDQH, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1464, + .Mnemonic = 1536, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99360,12 +101429,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3550 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + // Pos:3622 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSDQL, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1465, + .Mnemonic = 1537, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99389,12 +101458,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3551 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + // Pos:3623 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1466, + .Mnemonic = 1538, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99418,12 +101487,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3552 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + // Pos:3624 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSSWW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1467, + .Mnemonic = 1539, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99447,12 +101516,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3553 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + // Pos:3625 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1468, + .Mnemonic = 1540, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99476,12 +101545,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3554 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + // Pos:3626 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" { .Instruction = ND_INS_VPMACSWW, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1469, + .Mnemonic = 1541, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99505,12 +101574,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3555 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + // Pos:3627 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" { .Instruction = ND_INS_VPMADCSSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1470, + .Mnemonic = 1542, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99534,12 +101603,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3556 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + // Pos:3628 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" { .Instruction = ND_INS_VPMADCSWD, .Category = ND_CAT_XOP, .IsaSet = ND_SET_XOP, - .Mnemonic = 1471, + .Mnemonic = 1543, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99563,12 +101632,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3557 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + // Pos:3629 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" { .Instruction = ND_INS_VPMADD52HUQ, .Category = ND_CAT_IFMA, .IsaSet = ND_SET_AVX512IFMA, - .Mnemonic = 1472, + .Mnemonic = 1544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99592,12 +101661,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3558 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" + // Pos:3630 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" { .Instruction = ND_INS_VPMADD52HUQ, .Category = ND_CAT_AVXIFMA, .IsaSet = ND_SET_AVXIFMA, - .Mnemonic = 1472, + .Mnemonic = 1544, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99620,12 +101689,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3559 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + // Pos:3631 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" { .Instruction = ND_INS_VPMADD52LUQ, .Category = ND_CAT_IFMA, .IsaSet = ND_SET_AVX512IFMA, - .Mnemonic = 1473, + .Mnemonic = 1545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -99649,12 +101718,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3560 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" + // Pos:3632 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" { .Instruction = ND_INS_VPMADD52LUQ, .Category = ND_CAT_AVXIFMA, .IsaSet = ND_SET_AVXIFMA, - .Mnemonic = 1473, + .Mnemonic = 1545, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -99677,12 +101746,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3561 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + // Pos:3633 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" { .Instruction = ND_INS_VPMADDUBSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1474, + .Mnemonic = 1546, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -99706,3308 +101775,11 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3562 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + // Pos:3634 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" { .Instruction = ND_INS_VPMADDUBSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1474, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3563 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" - { - .Instruction = ND_INS_VPMADDWD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1475, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3564 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" - { - .Instruction = ND_INS_VPMADDWD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1475, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3565 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" - { - .Instruction = ND_INS_VPMASKMOVD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1476, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3566 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" - { - .Instruction = ND_INS_VPMASKMOVD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1476, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3567 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" - { - .Instruction = ND_INS_VPMASKMOVQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1477, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3568 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" - { - .Instruction = ND_INS_VPMASKMOVQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1477, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3569 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXSB, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1478, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3570 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" - { - .Instruction = ND_INS_VPMAXSB, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1478, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3571 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXSD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1479, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3572 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" - { - .Instruction = ND_INS_VPMAXSD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1479, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3573 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXSQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1480, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3574 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXSW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1481, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3575 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" - { - .Instruction = ND_INS_VPMAXSW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1481, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3576 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXUB, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1482, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3577 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" - { - .Instruction = ND_INS_VPMAXUB, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1482, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3578 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXUD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1483, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3579 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" - { - .Instruction = ND_INS_VPMAXUD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1483, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3580 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXUQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1484, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3581 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" - { - .Instruction = ND_INS_VPMAXUW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1485, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3582 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" - { - .Instruction = ND_INS_VPMAXUW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1485, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3583 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" - { - .Instruction = ND_INS_VPMINSB, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1486, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3584 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" - { - .Instruction = ND_INS_VPMINSB, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1486, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3585 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" - { - .Instruction = ND_INS_VPMINSD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1487, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3586 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" - { - .Instruction = ND_INS_VPMINSD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1487, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3587 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" - { - .Instruction = ND_INS_VPMINSQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1488, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3588 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" - { - .Instruction = ND_INS_VPMINSW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1489, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3589 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" - { - .Instruction = ND_INS_VPMINSW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1489, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3590 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" - { - .Instruction = ND_INS_VPMINUB, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1490, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3591 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" - { - .Instruction = ND_INS_VPMINUB, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1490, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3592 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" - { - .Instruction = ND_INS_VPMINUD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1491, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3593 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" - { - .Instruction = ND_INS_VPMINUD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1491, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3594 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" - { - .Instruction = ND_INS_VPMINUQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1492, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3595 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" - { - .Instruction = ND_INS_VPMINUW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1493, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3596 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" - { - .Instruction = ND_INS_VPMINUW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1493, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3597 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVB2M, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1494, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3598 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVD2M, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1495, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3599 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVDB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1496, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3600 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVDW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1497, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3601 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVM2B, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1498, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3602 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVM2D, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1499, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3603 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVM2Q, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1500, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3604 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVM2W, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1501, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3605 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVMSKB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1502, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_7, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3606 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVQ2M, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1503, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3607 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVQB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1504, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_OVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3608 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVQD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1505, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3609 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVQW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1506, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3610 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVSDB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1507, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3611 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVSDW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1508, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3612 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVSQB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1509, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_OVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3613 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVSQD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1510, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3614 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVSQW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1511, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3615 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVSWB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1512, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3616 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVSXBD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1513, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3617 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXBD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1513, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3618 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXBD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1513, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3619 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVSXBQ, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1514, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_OVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3620 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXBQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1514, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3621 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXBQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1514, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3622 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVSXBW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1515, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3623 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXBW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1515, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3624 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXBW, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1515, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3625 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVSXDQ, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1516, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3626 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXDQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1516, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3627 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXDQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1516, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3628 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVSXWD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1517, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3629 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXWD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1517, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3630 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXWD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1517, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3631 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVSXWQ, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1518, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3632 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXWQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1518, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3633 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" - { - .Instruction = ND_INS_VPMOVSXWQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1518, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3634 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVUSDB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1519, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3635 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVUSDW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1520, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3636 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVUSQB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1521, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_OVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3637 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVUSQD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1522, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3638 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVUSQW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1523, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3639 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVUSWB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1524, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3640 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" - { - .Instruction = ND_INS_VPMOVW2M, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1525, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_E7NM, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3641 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" - { - .Instruction = ND_INS_VPMOVWB, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1526, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E6, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3642 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVZXBD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1527, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3643 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXBD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1527, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3644 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXBD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1527, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3645 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVZXBQ, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1528, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_OVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3646 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXBQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1528, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3647 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXBQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1528, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3648 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVZXBW, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1529, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3649 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXBW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1529, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3650 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXBW, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1529, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3651 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVZXDQ, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1530, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3652 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXDQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1530, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3653 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXDQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1530, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3654 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVZXWD, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1531, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_HVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3655 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXWD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1531, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3656 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXWD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1531, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3657 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" - { - .Instruction = ND_INS_VPMOVZXWQ, - .Category = ND_CAT_DATAXFER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1532, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_QVM, - .ExcType = ND_EXT_E5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3658 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXWQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1532, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3659 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" - { - .Instruction = ND_INS_VPMOVZXWQ, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1532, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(2, 0), - .TupleType = 0, - .ExcType = ND_EXT_5, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3660 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULDQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1533, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3661 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" - { - .Instruction = ND_INS_VPMULDQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1533, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3662 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" - { - .Instruction = ND_INS_VPMULHRSW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1534, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3663 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" - { - .Instruction = ND_INS_VPMULHRSW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1534, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3664 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULHUW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1535, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3665 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" - { - .Instruction = ND_INS_VPMULHUW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1535, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3666 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULHW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1536, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3667 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" - { - .Instruction = ND_INS_VPMULHW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1536, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3668 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULLD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1537, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3669 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" - { - .Instruction = ND_INS_VPMULLD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1537, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3670 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULLQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1538, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512DQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3671 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULLW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1539, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3672 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" - { - .Instruction = ND_INS_VPMULLW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1539, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3673 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULTISHIFTQB, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI, - .Mnemonic = 1540, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4NF, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3674 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" - { - .Instruction = ND_INS_VPMULUDQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1541, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3675 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" - { - .Instruction = ND_INS_VPMULUDQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1541, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3676 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" - { - .Instruction = ND_INS_VPOPCNTB, - .Category = ND_CAT_VPOPCNT, - .IsaSet = ND_SET_AVX512BITALG, - .Mnemonic = 1542, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BITALG, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3677 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" - { - .Instruction = ND_INS_VPOPCNTD, - .Category = ND_CAT_VPOPCNT, - .IsaSet = ND_SET_AVX512VPOPCNTDQ, - .Mnemonic = 1543, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3678 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" - { - .Instruction = ND_INS_VPOPCNTQ, - .Category = ND_CAT_VPOPCNT, - .IsaSet = ND_SET_AVX512VPOPCNTDQ, - .Mnemonic = 1544, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3679 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" - { - .Instruction = ND_INS_VPOPCNTW, - .Category = ND_CAT_VPOPCNT, - .IsaSet = ND_SET_AVX512BITALG, - .Mnemonic = 1545, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BITALG, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3680 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" - { - .Instruction = ND_INS_VPOR, - .Category = ND_CAT_LOGICAL, - .IsaSet = ND_SET_AVX, .Mnemonic = 1546, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, @@ -103031,47 +101803,75 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3681 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + // Pos:3635 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" { - .Instruction = ND_INS_VPORD, - .Category = ND_CAT_LOGICAL, - .IsaSet = ND_SET_AVX512F, + .Instruction = ND_INS_VPMADDWD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, .Mnemonic = 1547, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3682 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + // Pos:3636 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" { - .Instruction = ND_INS_VPORQ, - .Category = ND_CAT_LOGICAL, - .IsaSet = ND_SET_AVX512F, + .Instruction = ND_INS_VPMADDWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1547, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3637 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + { + .Instruction = ND_INS_VPMASKMOVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, .Mnemonic = 1548, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -103079,106 +101879,159 @@ const ND_IDBE gInstructions[4075] = .SetFlags = 0, .ClearedFlags = 0, .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3638 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + { + .Instruction = ND_INS_VPMASKMOVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1548, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3639 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + { + .Instruction = ND_INS_VPMASKMOVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1549, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3640 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + { + .Instruction = ND_INS_VPMASKMOVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1549, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3641 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1550, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3683 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + // Pos:3642 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" { - .Instruction = ND_INS_VPPERM, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1549, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3684 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" - { - .Instruction = ND_INS_VPPERM, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1549, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3685 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" - { - .Instruction = ND_INS_VPROLD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, + .Instruction = ND_INS_VPMAXSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, .Mnemonic = 1550, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3686 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + // Pos:3643 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" { - .Instruction = ND_INS_VPROLQ, + .Instruction = ND_INS_VPMAXSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1551, @@ -103198,16 +102051,44 @@ const ND_IDBE gInstructions[4075] = .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, - // Pos:3687 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + // Pos:3644 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" { - .Instruction = ND_INS_VPROLVD, + .Instruction = ND_INS_VPMAXSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1551, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3645 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXSQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1552, @@ -103230,22 +102111,136 @@ const ND_IDBE gInstructions[4075] = OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, - // Pos:3688 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:3646 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" { - .Instruction = ND_INS_VPROLVQ, + .Instruction = ND_INS_VPMAXSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1553, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3647 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + { + .Instruction = ND_INS_VPMAXSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1553, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3648 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1554, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3649 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + { + .Instruction = ND_INS_VPMAXUB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1554, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3650 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1553, + .Mnemonic = 1555, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, .OpsCount = ND_OPS_CNT(4, 0), .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -103259,71 +102254,41 @@ const ND_IDBE gInstructions[4075] = OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3689 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" - { - .Instruction = ND_INS_VPRORD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1554, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3690 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + // Pos:3651 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" { - .Instruction = ND_INS_VPRORQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, + .Instruction = ND_INS_VPMAXUD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, .Mnemonic = 1555, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3691 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + // Pos:3652 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" { - .Instruction = ND_INS_VPRORVD, + .Instruction = ND_INS_VPMAXUQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1556, @@ -103342,6 +102307,149 @@ const ND_IDBE gInstructions[4075] = .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, .CpuidFlag = ND_CFF_AVX512F, .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3653 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1557, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3654 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + { + .Instruction = ND_INS_VPMAXUW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1557, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3655 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3656 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + { + .Instruction = ND_INS_VPMINSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3657 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), @@ -103350,12 +102458,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3692 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:3658 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" { - .Instruction = ND_INS_VPRORVQ, + .Instruction = ND_INS_VPMINSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3659 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1557, + .Mnemonic = 1560, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -103379,354 +102515,18 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3693 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + // Pos:3660 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" { - .Instruction = ND_INS_VPROTB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1558, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3694 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" - { - .Instruction = ND_INS_VPROTB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1558, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3695 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" - { - .Instruction = ND_INS_VPROTB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1558, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3696 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" - { - .Instruction = ND_INS_VPROTD, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1559, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3697 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" - { - .Instruction = ND_INS_VPROTD, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1559, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3698 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" - { - .Instruction = ND_INS_VPROTD, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1559, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3699 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" - { - .Instruction = ND_INS_VPROTQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1560, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3700 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" - { - .Instruction = ND_INS_VPROTQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1560, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3701 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" - { - .Instruction = ND_INS_VPROTQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1560, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3702 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" - { - .Instruction = ND_INS_VPROTW, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1561, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3703 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" - { - .Instruction = ND_INS_VPROTW, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1561, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3704 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" - { - .Instruction = ND_INS_VPROTW, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1561, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3705 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" - { - .Instruction = ND_INS_VPSADBW, + .Instruction = ND_INS_VPMINSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1562, + .Mnemonic = 1561, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NFnb, + .ExcType = ND_EXT_E4nb, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -103737,15 +102537,73 @@ const ND_IDBE gInstructions[4075] = .CpuidFlag = ND_CFF_AVX512BW, .Operands = { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3706 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + // Pos:3661 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" { - .Instruction = ND_INS_VPSADBW, + .Instruction = ND_INS_VPMINSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1561, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3662 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + { + .Instruction = ND_INS_VPMINUB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1562, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3663 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VPMINUB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 1562, @@ -103771,955 +102629,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3707 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + // Pos:3664 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" { - .Instruction = ND_INS_VPSCATTERDD, - .Category = ND_CAT_SCATTER, + .Instruction = ND_INS_VPMINUD, + .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1563, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_T1S, - .ExcType = ND_EXT_E12, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, .CpuidFlag = ND_CFF_AVX512F, .Operands = - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:3708 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" - { - .Instruction = ND_INS_VPSCATTERDQ, - .Category = ND_CAT_SCATTER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1564, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_T1S, - .ExcType = ND_EXT_E12, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:3709 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" - { - .Instruction = ND_INS_VPSCATTERQD, - .Category = ND_CAT_SCATTER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1565, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_T1S, - .ExcType = ND_EXT_E12, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:3710 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" - { - .Instruction = ND_INS_VPSCATTERQQ, - .Category = ND_CAT_SCATTER, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1566, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_T1S, - .ExcType = ND_EXT_E12, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:3711 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" - { - .Instruction = ND_INS_VPSHAB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1567, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3712 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" - { - .Instruction = ND_INS_VPSHAB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1567, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3713 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" - { - .Instruction = ND_INS_VPSHAD, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1568, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3714 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" - { - .Instruction = ND_INS_VPSHAD, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1568, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3715 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" - { - .Instruction = ND_INS_VPSHAQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1569, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3716 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" - { - .Instruction = ND_INS_VPSHAQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1569, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3717 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" - { - .Instruction = ND_INS_VPSHAW, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1570, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3718 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" - { - .Instruction = ND_INS_VPSHAW, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1570, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3719 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" - { - .Instruction = ND_INS_VPSHLB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1571, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3720 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" - { - .Instruction = ND_INS_VPSHLB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1571, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3721 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" - { - .Instruction = ND_INS_VPSHLB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1571, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3722 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" - { - .Instruction = ND_INS_VPSHLB, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1571, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3723 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" - { - .Instruction = ND_INS_VPSHLD, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1572, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3724 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" - { - .Instruction = ND_INS_VPSHLDD, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1573, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(5, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3725 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" - { - .Instruction = ND_INS_VPSHLDQ, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1574, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(5, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3726 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHLDVD, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1575, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3727 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHLDVQ, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1576, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3728 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHLDVW, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1577, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3729 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" - { - .Instruction = ND_INS_VPSHLDW, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1578, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(5, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3730 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" - { - .Instruction = ND_INS_VPSHLQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1579, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3731 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" - { - .Instruction = ND_INS_VPSHLQ, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1579, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3732 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" - { - .Instruction = ND_INS_VPSHLW, - .Category = ND_CAT_XOP, - .IsaSet = ND_SET_XOP, - .Mnemonic = 1580, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = 0, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_XOP, - .Operands = - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3733 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" - { - .Instruction = ND_INS_VPSHRDD, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1581, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(5, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3734 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" - { - .Instruction = ND_INS_VPSHRDQ, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1582, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(5, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3735 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHRDVD, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1583, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3736 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHRDVQ, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1584, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:3737 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHRDVW, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1585, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3738 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" - { - .Instruction = ND_INS_VPSHRDW, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512VBMI2, - .Mnemonic = 1586, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(5, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512VBMI2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3739 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" - { - .Instruction = ND_INS_VPSHUFB, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1587, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NFnb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, - // Pos:3740 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + // Pos:3665 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" { - .Instruction = ND_INS_VPSHUFB, + .Instruction = ND_INS_VPMINUD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1587, + .Mnemonic = 1563, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -104742,18 +102686,18 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3741 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + // Pos:3666 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" { - .Instruction = ND_INS_VPSHUFBITQMB, - .Category = ND_CAT_AVX512VBMI, - .IsaSet = ND_SET_AVX512BITALG, - .Mnemonic = 1588, + .Instruction = ND_INS_VPMINUQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1564, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = 0, + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -104761,28 +102705,855 @@ const ND_IDBE gInstructions[4075] = .SetFlags = 0, .ClearedFlags = 0, .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BITALG, + .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3667 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + { + .Instruction = ND_INS_VPMINUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1565, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3742 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + // Pos:3668 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" { - .Instruction = ND_INS_VPSHUFD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1589, + .Instruction = ND_INS_VPMINUW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1565, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4NF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3669 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVB2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1566, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3670 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVD2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1567, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3671 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVDB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1568, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3672 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVDW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1569, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3673 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2B, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1570, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3674 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2D, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1571, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3675 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2Q, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1572, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3676 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2W, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1573, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3677 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVMSKB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1574, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3678 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVQ2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1575, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3679 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVQB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1576, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3680 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVQD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1577, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3681 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVQW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1578, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3682 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSDB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1579, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3683 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSDW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1580, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3684 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSQB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1581, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3685 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSQD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1582, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3686 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSQW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1583, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3687 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSWB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1584, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3688 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXBD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1585, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3689 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1585, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3690 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1585, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3691 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXBQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1586, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3692 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1586, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3693 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1586, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3694 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXBW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1587, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3695 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1587, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3696 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBW, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1587, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3697 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXDQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1588, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -104795,23 +103566,104 @@ const ND_IDBE gInstructions[4075] = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3743 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + // Pos:3698 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" { - .Instruction = ND_INS_VPSHUFD, + .Instruction = ND_INS_VPMOVSXDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1588, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3699 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXDQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1588, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3700 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXWD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1589, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3701 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 1589, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_4, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -104822,24 +103674,50 @@ const ND_IDBE gInstructions[4075] = .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3744 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:3702 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" { - .Instruction = ND_INS_VPSHUFHW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, + .Instruction = ND_INS_VPMOVSXWD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1589, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3703 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXWQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, .Mnemonic = 1590, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NFnb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -104847,28 +103725,27 @@ const ND_IDBE gInstructions[4075] = .SetFlags = 0, .ClearedFlags = 0, .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, + .CpuidFlag = ND_CFF_AVX512F, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3745 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + // Pos:3704 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" { - .Instruction = ND_INS_VPSHUFHW, + .Instruction = ND_INS_VPMOVSXWQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 1590, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_4, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -104879,926 +103756,756 @@ const ND_IDBE gInstructions[4075] = .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3746 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + // Pos:3705 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" { - .Instruction = ND_INS_VPSHUFLW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, + .Instruction = ND_INS_VPMOVSXWQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1590, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3706 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSDB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, .Mnemonic = 1591, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NFnb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3747 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" - { - .Instruction = ND_INS_VPSHUFLW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1591, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3748 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + // Pos:3707 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" { - .Instruction = ND_INS_VPSIGNB, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, + .Instruction = ND_INS_VPMOVUSDW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, .Mnemonic = 1592, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3749 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + // Pos:3708 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" { - .Instruction = ND_INS_VPSIGND, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, + .Instruction = ND_INS_VPMOVUSQB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, .Mnemonic = 1593, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3750 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + // Pos:3709 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" { - .Instruction = ND_INS_VPSIGNW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, + .Instruction = ND_INS_VPMOVUSQD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, .Mnemonic = 1594, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3751 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" - { - .Instruction = ND_INS_VPSLLD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1595, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3752 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + // Pos:3710 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" { - .Instruction = ND_INS_VPSLLD, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVUSQW, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1595, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_M128, - .ExcType = ND_EXT_E4NFnb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512F, .Operands = { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3753 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + // Pos:3711 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" { - .Instruction = ND_INS_VPSLLD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1595, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_7, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3754 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" - { - .Instruction = ND_INS_VPSLLD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1595, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3755 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" - { - .Instruction = ND_INS_VPSLLDQ, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVUSWB, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, .Mnemonic = 1596, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4NFnb, + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512BW, .Operands = { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3756 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + // Pos:3712 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" { - .Instruction = ND_INS_VPSLLDQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1596, + .Instruction = ND_INS_VPMOVW2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1597, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_7, + .ExcType = ND_EXT_E7NM, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, .Operands = { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3757 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + // Pos:3713 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" { - .Instruction = ND_INS_VPSLLQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1597, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3758 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" - { - .Instruction = ND_INS_VPSLLQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1597, + .Instruction = ND_INS_VPMOVWB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1598, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_M128, - .ExcType = ND_EXT_E4NFnb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, .Operands = { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3759 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + // Pos:3714 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" { - .Instruction = ND_INS_VPSLLQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1597, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_7, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3760 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" - { - .Instruction = ND_INS_VPSLLQ, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1597, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3761 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" - { - .Instruction = ND_INS_VPSLLVD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1598, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:3762 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" - { - .Instruction = ND_INS_VPSLLVD, - .Category = ND_CAT_AVX2, - .IsaSet = ND_SET_AVX2, - .Mnemonic = 1598, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), - .TupleType = 0, - .ExcType = ND_EXT_4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX2, - .Operands = - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3763 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" - { - .Instruction = ND_INS_VPSLLVQ, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVZXBD, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1599, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512F, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3764 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + // Pos:3715 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" { - .Instruction = ND_INS_VPSLLVQ, + .Instruction = ND_INS_VPMOVZXBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1599, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3716 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, .Mnemonic = 1599, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_4, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, .CpuidFlag = ND_CFF_AVX2, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3765 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + // Pos:3717 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" { - .Instruction = ND_INS_VPSLLVW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, + .Instruction = ND_INS_VPMOVZXBQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, .Mnemonic = 1600, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3766 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + // Pos:3718 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" { - .Instruction = ND_INS_VPSLLW, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVZXBQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1600, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3719 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1600, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3720 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXBW, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512BW, .Mnemonic = 1601, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3767 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" - { - .Instruction = ND_INS_VPSLLW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1601, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_M128, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512BW, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3768 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + // Pos:3721 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" { - .Instruction = ND_INS_VPSLLW, + .Instruction = ND_INS_VPMOVZXBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 1601, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_7, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3769 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + // Pos:3722 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" { - .Instruction = ND_INS_VPSLLW, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, + .Instruction = ND_INS_VPMOVZXBW, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, .Mnemonic = 1601, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_4, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3770 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + // Pos:3723 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" { - .Instruction = ND_INS_VPSRAD, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1602, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3771 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" - { - .Instruction = ND_INS_VPSRAD, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVZXDQ, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1602, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_M128, - .ExcType = ND_EXT_E4NFnb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512F, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3772 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + // Pos:3724 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" { - .Instruction = ND_INS_VPSRAD, + .Instruction = ND_INS_VPMOVZXDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 1602, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_7, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3773 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + // Pos:3725 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" { - .Instruction = ND_INS_VPSRAD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, + .Instruction = ND_INS_VPMOVZXDQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, .Mnemonic = 1602, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_4, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3774 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + // Pos:3726 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" { - .Instruction = ND_INS_VPSRAQ, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1603, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512F, - .Operands = - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3775 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" - { - .Instruction = ND_INS_VPSRAQ, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVZXWD, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1603, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_M128, - .ExcType = ND_EXT_E4NFnb, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512F, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3727 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1603, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3728 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1603, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3776 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + // Pos:3729 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" { - .Instruction = ND_INS_VPSRAVD, - .Category = ND_CAT_AVX512, + .Instruction = ND_INS_VPMOVZXWQ, + .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1604, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FV, - .ExcType = ND_EXT_E4, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, .CpuidFlag = ND_CFF_AVX512F, .Operands = { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3777 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + // Pos:3730 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" { - .Instruction = ND_INS_VPSRAVD, + .Instruction = ND_INS_VPMOVZXWQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1604, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3731 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, .Mnemonic = 1604, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, - .OpsCount = ND_OPS_CNT(3, 0), + .OpsCount = ND_OPS_CNT(2, 0), .TupleType = 0, - .ExcType = ND_EXT_4, + .ExcType = ND_EXT_5, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, .CpuidFlag = ND_CFF_AVX2, .Operands = { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3778 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + // Pos:3732 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" { - .Instruction = ND_INS_VPSRAVQ, + .Instruction = ND_INS_VPMULDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, .Mnemonic = 1605, @@ -105825,105 +104532,18 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3779 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + // Pos:3733 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" { - .Instruction = ND_INS_VPSRAVW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1606, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3780 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" - { - .Instruction = ND_INS_VPSRAW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1607, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3781 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" - { - .Instruction = ND_INS_VPSRAW, - .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1607, - .ValidPrefixes = 0, - .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, - .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_M128, - .ExcType = ND_EXT_E4nb, - .FpuFlags = 0, - .EvexMode = 0, - .TestedFlags = 0, - .ModifiedFlags = 0, - .SetFlags = 0, - .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, - .Operands = - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3782 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" - { - .Instruction = ND_INS_VPSRAW, + .Instruction = ND_INS_VPMULDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1607, + .Mnemonic = 1605, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, .OpsCount = ND_OPS_CNT(3, 0), .TupleType = 0, - .ExcType = ND_EXT_7, + .ExcType = ND_EXT_4, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -105934,15 +104554,101 @@ const ND_IDBE gInstructions[4075] = .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3783 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + // Pos:3734 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" { - .Instruction = ND_INS_VPSRAW, + .Instruction = ND_INS_VPMULHRSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1606, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3735 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + { + .Instruction = ND_INS_VPMULHRSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1606, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3736 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULHUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1607, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3737 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + { + .Instruction = ND_INS_VPMULHUW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, .Mnemonic = 1607, @@ -105964,16 +104670,558 @@ const ND_IDBE gInstructions[4075] = { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3784 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + // Pos:3738 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" { - .Instruction = ND_INS_VPSRLD, + .Instruction = ND_INS_VPMULHW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3739 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + { + .Instruction = ND_INS_VPMULHW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3740 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULLD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1608, + .Mnemonic = 1609, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3741 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + { + .Instruction = ND_INS_VPMULLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1609, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3742 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1610, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3743 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1611, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3744 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + { + .Instruction = ND_INS_VPMULLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1611, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3745 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULTISHIFTQB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI, + .Mnemonic = 1612, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3746 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULUDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1613, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3747 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + { + .Instruction = ND_INS_VPMULUDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1613, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3748 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTB, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512BITALG, + .Mnemonic = 1614, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BITALG, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3749 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTD, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512VPOPCNTDQ, + .Mnemonic = 1615, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3750 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTQ, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512VPOPCNTDQ, + .Mnemonic = 1616, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3751 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTW, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512BITALG, + .Mnemonic = 1617, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BITALG, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3752 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + { + .Instruction = ND_INS_VPOR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1618, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3753 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + { + .Instruction = ND_INS_VPORD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1619, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3754 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + { + .Instruction = ND_INS_VPORQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1620, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3755 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + { + .Instruction = ND_INS_VPPERM, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1621, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3756 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + { + .Instruction = ND_INS_VPPERM, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1621, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3757 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + { + .Instruction = ND_INS_VPROLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1622, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -105997,12 +105245,1891 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3785 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + // Pos:3758 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" { - .Instruction = ND_INS_VPSRLD, + .Instruction = ND_INS_VPROLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1608, + .Mnemonic = 1623, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3759 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + { + .Instruction = ND_INS_VPROLVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1624, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3760 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + { + .Instruction = ND_INS_VPROLVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1625, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3761 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + { + .Instruction = ND_INS_VPRORD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1626, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3762 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + { + .Instruction = ND_INS_VPRORQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1627, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3763 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + { + .Instruction = ND_INS_VPRORVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1628, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3764 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + { + .Instruction = ND_INS_VPRORVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1629, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3765 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1630, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3766 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + { + .Instruction = ND_INS_VPROTB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1630, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3767 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + { + .Instruction = ND_INS_VPROTB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1630, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3768 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1631, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3769 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + { + .Instruction = ND_INS_VPROTD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1631, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3770 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + { + .Instruction = ND_INS_VPROTD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1631, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3771 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1632, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3772 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + { + .Instruction = ND_INS_VPROTQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1632, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3773 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + { + .Instruction = ND_INS_VPROTQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1632, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3774 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1633, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3775 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + { + .Instruction = ND_INS_VPROTW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1633, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3776 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + { + .Instruction = ND_INS_VPROTW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1633, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3777 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + { + .Instruction = ND_INS_VPSADBW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1634, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3778 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + { + .Instruction = ND_INS_VPSADBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1634, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3779 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERDD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1635, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3780 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERDQ, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1636, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3781 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERQD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1637, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3782 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERQQ, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1638, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3783 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + { + .Instruction = ND_INS_VPSHAB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1639, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3784 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + { + .Instruction = ND_INS_VPSHAB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1639, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3785 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + { + .Instruction = ND_INS_VPSHAD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1640, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3786 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + { + .Instruction = ND_INS_VPSHAD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1640, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3787 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + { + .Instruction = ND_INS_VPSHAQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1641, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3788 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + { + .Instruction = ND_INS_VPSHAQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1641, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3789 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + { + .Instruction = ND_INS_VPSHAW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1642, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3790 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + { + .Instruction = ND_INS_VPSHAW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1642, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3791 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1643, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3792 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1643, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3793 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1643, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3794 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1643, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3795 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1644, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3796 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHLDD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1645, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3797 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHLDQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1646, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3798 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHLDVD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1647, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3799 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHLDVQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1648, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3800 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHLDVW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1649, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3801 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHLDW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1650, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3802 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1651, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3803 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1651, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3804 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1652, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3805 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHRDD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1653, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3806 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHRDQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1654, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3807 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHRDVD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1655, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3808 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHRDVQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1656, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3809 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHRDVW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1657, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3810 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHRDW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1658, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3811 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHUFB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1659, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3812 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + { + .Instruction = ND_INS_VPSHUFB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1659, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3813 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + { + .Instruction = ND_INS_VPSHUFBITQMB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512BITALG, + .Mnemonic = 1660, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BITALG, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3814 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPSHUFD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1661, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3815 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_VPSHUFD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1661, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3816 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPSHUFHW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1662, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3817 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_VPSHUFHW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1662, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3818 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPSHUFLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1663, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3819 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_VPSHUFLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1663, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3820 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + { + .Instruction = ND_INS_VPSIGNB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1664, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3821 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + { + .Instruction = ND_INS_VPSIGND, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3822 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + { + .Instruction = ND_INS_VPSIGNW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1666, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3823 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + { + .Instruction = ND_INS_VPSLLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1667, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3824 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106026,12 +107153,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3786 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + // Pos:3825 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" { - .Instruction = ND_INS_VPSRLD, + .Instruction = ND_INS_VPSLLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1608, + .Mnemonic = 1667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106054,12 +107181,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3787 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + // Pos:3826 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" { - .Instruction = ND_INS_VPSRLD, + .Instruction = ND_INS_VPSLLD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1608, + .Mnemonic = 1667, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106082,12 +107209,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3788 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + // Pos:3827 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" { - .Instruction = ND_INS_VPSRLDQ, + .Instruction = ND_INS_VPSLLDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1609, + .Mnemonic = 1668, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106110,12 +107237,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3789 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + // Pos:3828 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" { - .Instruction = ND_INS_VPSRLDQ, + .Instruction = ND_INS_VPSLLDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1609, + .Mnemonic = 1668, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106138,12 +107265,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3790 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + // Pos:3829 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" { - .Instruction = ND_INS_VPSRLQ, + .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1610, + .Mnemonic = 1669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106167,12 +107294,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3791 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + // Pos:3830 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" { - .Instruction = ND_INS_VPSRLQ, + .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1610, + .Mnemonic = 1669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106196,12 +107323,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3792 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + // Pos:3831 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" { - .Instruction = ND_INS_VPSRLQ, + .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1610, + .Mnemonic = 1669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106224,12 +107351,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3793 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + // Pos:3832 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" { - .Instruction = ND_INS_VPSRLQ, + .Instruction = ND_INS_VPSLLQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1610, + .Mnemonic = 1669, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106252,12 +107379,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3794 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + // Pos:3833 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" { - .Instruction = ND_INS_VPSRLVD, + .Instruction = ND_INS_VPSLLVD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1611, + .Mnemonic = 1670, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106281,12 +107408,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3795 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + // Pos:3834 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" { - .Instruction = ND_INS_VPSRLVD, + .Instruction = ND_INS_VPSLLVD, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1611, + .Mnemonic = 1670, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106309,12 +107436,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3796 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + // Pos:3835 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" { - .Instruction = ND_INS_VPSRLVQ, + .Instruction = ND_INS_VPSLLVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1612, + .Mnemonic = 1671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106338,12 +107465,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3797 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + // Pos:3836 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" { - .Instruction = ND_INS_VPSRLVQ, + .Instruction = ND_INS_VPSLLVQ, .Category = ND_CAT_AVX2, .IsaSet = ND_SET_AVX2, - .Mnemonic = 1612, + .Mnemonic = 1671, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106366,12 +107493,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3798 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + // Pos:3837 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" { - .Instruction = ND_INS_VPSRLVW, + .Instruction = ND_INS_VPSLLVW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1613, + .Mnemonic = 1672, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106395,12 +107522,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3799 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + // Pos:3838 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" { - .Instruction = ND_INS_VPSRLW, + .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1614, + .Mnemonic = 1673, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106424,12 +107551,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3800 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + // Pos:3839 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" { - .Instruction = ND_INS_VPSRLW, + .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1614, + .Mnemonic = 1673, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106453,12 +107580,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3801 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + // Pos:3840 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" { - .Instruction = ND_INS_VPSRLW, + .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1614, + .Mnemonic = 1673, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106481,12 +107608,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3802 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + // Pos:3841 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" { - .Instruction = ND_INS_VPSRLW, + .Instruction = ND_INS_VPSLLW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1614, + .Mnemonic = 1673, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106509,18 +107636,76 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3803 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + // Pos:3842 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" { - .Instruction = ND_INS_VPSUBB, + .Instruction = ND_INS_VPSRAD, .Category = ND_CAT_AVX512, - .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1615, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3843 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1674, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, .OpsCount = ND_OPS_CNT(4, 0), - .TupleType = ND_TUPLE_FVM, - .ExcType = ND_EXT_E4nb, + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3844 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRAD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, .FpuFlags = 0, .EvexMode = 0, .TestedFlags = 0, @@ -106528,22 +107713,21 @@ const ND_IDBE gInstructions[4075] = .SetFlags = 0, .ClearedFlags = 0, .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX512BW, + .CpuidFlag = ND_CFF_AVX, .Operands = { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3804 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + // Pos:3845 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" { - .Instruction = ND_INS_VPSUBB, + .Instruction = ND_INS_VPSRAD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1615, + .Mnemonic = 1674, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106562,16 +107746,74 @@ const ND_IDBE gInstructions[4075] = { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, - // Pos:3805 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + // Pos:3846 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" { - .Instruction = ND_INS_VPSUBD, + .Instruction = ND_INS_VPSRAQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1616, + .Mnemonic = 1675, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3847 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1675, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3848 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1676, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106595,12 +107837,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3806 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + // Pos:3849 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" { - .Instruction = ND_INS_VPSUBD, - .Category = ND_CAT_AVX, - .IsaSet = ND_SET_AVX, - .Mnemonic = 1616, + .Instruction = ND_INS_VPSRAVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1676, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106613,8 +107855,8 @@ const ND_IDBE gInstructions[4075] = .ModifiedFlags = 0, .SetFlags = 0, .ClearedFlags = 0, - .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, - .CpuidFlag = ND_CFF_AVX, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, .Operands = { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), @@ -106623,12 +107865,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3807 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + // Pos:3850 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" { - .Instruction = ND_INS_VPSUBQ, + .Instruction = ND_INS_VPSRAVQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1617, + .Mnemonic = 1677, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106652,12 +107894,839 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3808 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + // Pos:3851 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAVW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1678, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3852 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1679, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3853 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1679, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3854 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1679, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3855 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1679, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3856 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1680, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3857 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1680, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3858 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1680, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3859 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1680, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3860 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + { + .Instruction = ND_INS_VPSRLDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1681, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3861 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1681, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3862 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3863 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3864 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3865 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3866 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3867 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3868 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1684, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3869 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1684, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3870 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLVW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1685, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3871 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1686, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3872 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1686, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3873 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1686, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3874 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1686, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3875 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1687, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3876 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1687, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3877 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1688, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3878 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + { + .Instruction = ND_INS_VPSUBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1688, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3879 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1689, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3880 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" { .Instruction = ND_INS_VPSUBQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1617, + .Mnemonic = 1689, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106680,12 +108749,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3809 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + // Pos:3881 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" { .Instruction = ND_INS_VPSUBSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1618, + .Mnemonic = 1690, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106709,12 +108778,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3810 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + // Pos:3882 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" { .Instruction = ND_INS_VPSUBSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1618, + .Mnemonic = 1690, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106737,12 +108806,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3811 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + // Pos:3883 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" { .Instruction = ND_INS_VPSUBSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1619, + .Mnemonic = 1691, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106766,12 +108835,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3812 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + // Pos:3884 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" { .Instruction = ND_INS_VPSUBSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1619, + .Mnemonic = 1691, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106794,12 +108863,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3813 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + // Pos:3885 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" { .Instruction = ND_INS_VPSUBUSB, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1620, + .Mnemonic = 1692, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106823,12 +108892,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3814 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + // Pos:3886 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" { .Instruction = ND_INS_VPSUBUSB, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1620, + .Mnemonic = 1692, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106851,12 +108920,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3815 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + // Pos:3887 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" { .Instruction = ND_INS_VPSUBUSW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1621, + .Mnemonic = 1693, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106880,12 +108949,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3816 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + // Pos:3888 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" { .Instruction = ND_INS_VPSUBUSW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1621, + .Mnemonic = 1693, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106908,12 +108977,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3817 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + // Pos:3889 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" { .Instruction = ND_INS_VPSUBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1622, + .Mnemonic = 1694, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -106937,12 +109006,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3818 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + // Pos:3890 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" { .Instruction = ND_INS_VPSUBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1622, + .Mnemonic = 1694, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -106965,12 +109034,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3819 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + // Pos:3891 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" { .Instruction = ND_INS_VPTERNLOGD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1623, + .Mnemonic = 1695, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -106995,12 +109064,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3820 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + // Pos:3892 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" { .Instruction = ND_INS_VPTERNLOGQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1624, + .Mnemonic = 1696, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107025,12 +109094,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3821 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + // Pos:3893 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" { .Instruction = ND_INS_VPTEST, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1625, + .Mnemonic = 1697, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107053,12 +109122,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3822 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + // Pos:3894 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMB, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1626, + .Mnemonic = 1698, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -107082,12 +109151,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3823 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + // Pos:3895 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1627, + .Mnemonic = 1699, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -107111,12 +109180,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3824 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + // Pos:3896 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1628, + .Mnemonic = 1700, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -107140,12 +109209,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3825 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + // Pos:3897 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTMW, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1629, + .Mnemonic = 1701, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -107169,12 +109238,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3826 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + // Pos:3898 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMB, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1630, + .Mnemonic = 1702, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -107198,12 +109267,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3827 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + // Pos:3899 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1631, + .Mnemonic = 1703, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -107227,12 +109296,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3828 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + // Pos:3900 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1632, + .Mnemonic = 1704, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, @@ -107256,12 +109325,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3829 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + // Pos:3901 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" { .Instruction = ND_INS_VPTESTNMW, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1633, + .Mnemonic = 1705, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -107285,12 +109354,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3830 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + // Pos:3902 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1634, + .Mnemonic = 1706, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107314,12 +109383,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3831 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + // Pos:3903 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1634, + .Mnemonic = 1706, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107342,12 +109411,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3832 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + // Pos:3904 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1635, + .Mnemonic = 1707, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107371,12 +109440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3833 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + // Pos:3905 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1635, + .Mnemonic = 1707, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107399,12 +109468,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3834 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + // Pos:3906 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHQDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1636, + .Mnemonic = 1708, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107428,12 +109497,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3835 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + // Pos:3907 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHQDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1636, + .Mnemonic = 1708, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107456,12 +109525,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3836 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + // Pos:3908 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKHWD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1637, + .Mnemonic = 1709, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107485,12 +109554,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3837 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + // Pos:3909 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKHWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1637, + .Mnemonic = 1709, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107513,12 +109582,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3838 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + // Pos:3910 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLBW, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1638, + .Mnemonic = 1710, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107542,12 +109611,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3839 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + // Pos:3911 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLBW, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1638, + .Mnemonic = 1710, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107570,12 +109639,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3840 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + // Pos:3912 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1639, + .Mnemonic = 1711, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107599,12 +109668,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3841 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + // Pos:3913 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1639, + .Mnemonic = 1711, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107627,12 +109696,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3842 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + // Pos:3914 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLQDQ, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1640, + .Mnemonic = 1712, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107656,12 +109725,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3843 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + // Pos:3915 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLQDQ, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1640, + .Mnemonic = 1712, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107684,12 +109753,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3844 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + // Pos:3916 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" { .Instruction = ND_INS_VPUNPCKLWD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512BW, - .Mnemonic = 1641, + .Mnemonic = 1713, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -107713,12 +109782,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3845 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + // Pos:3917 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" { .Instruction = ND_INS_VPUNPCKLWD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1641, + .Mnemonic = 1713, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107741,12 +109810,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3846 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + // Pos:3918 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" { .Instruction = ND_INS_VPXOR, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX, - .Mnemonic = 1642, + .Mnemonic = 1714, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -107769,12 +109838,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3847 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + // Pos:3919 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" { .Instruction = ND_INS_VPXORD, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1643, + .Mnemonic = 1715, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107798,12 +109867,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3848 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + // Pos:3920 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" { .Instruction = ND_INS_VPXORQ, .Category = ND_CAT_LOGICAL, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1644, + .Mnemonic = 1716, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107827,12 +109896,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3849 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + // Pos:3921 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGEPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1645, + .Mnemonic = 1717, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -107857,12 +109926,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3850 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + // Pos:3922 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGEPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1646, + .Mnemonic = 1718, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -107887,12 +109956,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3851 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + // Pos:3923 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGESD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1647, + .Mnemonic = 1719, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -107917,12 +109986,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3852 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + // Pos:3924 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" { .Instruction = ND_INS_VRANGESS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1648, + .Mnemonic = 1720, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -107947,12 +110016,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3853 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + // Pos:3925 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCP14PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1649, + .Mnemonic = 1721, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -107975,12 +110044,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3854 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:3926 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCP14PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1650, + .Mnemonic = 1722, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108003,12 +110072,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3855 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + // Pos:3927 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" { .Instruction = ND_INS_VRCP14SD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1651, + .Mnemonic = 1723, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108032,12 +110101,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3856 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + // Pos:3928 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" { .Instruction = ND_INS_VRCP14SS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1652, + .Mnemonic = 1724, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108061,12 +110130,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3857 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + // Pos:3929 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" { .Instruction = ND_INS_VRCP28PD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1653, + .Mnemonic = 1725, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108089,12 +110158,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3858 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + // Pos:3930 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" { .Instruction = ND_INS_VRCP28PS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1654, + .Mnemonic = 1726, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108117,12 +110186,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3859 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + // Pos:3931 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" { .Instruction = ND_INS_VRCP28SD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1655, + .Mnemonic = 1727, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108146,12 +110215,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3860 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + // Pos:3932 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" { .Instruction = ND_INS_VRCP28SS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1656, + .Mnemonic = 1728, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108175,12 +110244,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3861 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" + // Pos:3933 Instruction:"VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4C /r"/"RAM" + { + .Instruction = ND_INS_VRCPPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1729, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3934 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" { .Instruction = ND_INS_VRCPPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1657, + .Mnemonic = 1730, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108203,12 +110300,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3862 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + // Pos:3935 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" { .Instruction = ND_INS_VRCPPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1658, + .Mnemonic = 1731, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108230,12 +110327,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3863 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" + // Pos:3936 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" { .Instruction = ND_INS_VRCPSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1659, + .Mnemonic = 1732, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108259,12 +110356,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3864 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + // Pos:3937 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" { .Instruction = ND_INS_VRCPSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1660, + .Mnemonic = 1733, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108287,12 +110384,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3865 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + // Pos:3938 Instruction:"VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x56 /r ib"/"RAMI" + { + .Instruction = ND_INS_VREDUCENEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3939 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCEPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1661, + .Mnemonic = 1735, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108316,12 +110442,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3866 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:3940 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCEPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1662, + .Mnemonic = 1736, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108345,12 +110471,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3867 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + // Pos:3941 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" { .Instruction = ND_INS_VREDUCEPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1663, + .Mnemonic = 1737, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108374,12 +110500,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3868 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + // Pos:3942 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" { .Instruction = ND_INS_VREDUCESD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1664, + .Mnemonic = 1738, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108404,12 +110530,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3869 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:3943 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" { .Instruction = ND_INS_VREDUCESH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1665, + .Mnemonic = 1739, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108434,12 +110560,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3870 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + // Pos:3944 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" { .Instruction = ND_INS_VREDUCESS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1666, + .Mnemonic = 1740, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108464,12 +110590,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3871 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + // Pos:3945 Instruction:"VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:3 l:x w:0 0x08 /r ib"/"RAMI" + { + .Instruction = ND_INS_VRNDSCALENEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1741, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3946 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALEPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1667, + .Mnemonic = 1742, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108493,12 +110648,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3872 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:3947 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALEPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1668, + .Mnemonic = 1743, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108522,12 +110677,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3873 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + // Pos:3948 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" { .Instruction = ND_INS_VRNDSCALEPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1669, + .Mnemonic = 1744, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108551,12 +110706,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3874 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + // Pos:3949 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" { .Instruction = ND_INS_VRNDSCALESD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1670, + .Mnemonic = 1745, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108581,12 +110736,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3875 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:3950 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" { .Instruction = ND_INS_VRNDSCALESH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1671, + .Mnemonic = 1746, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108611,12 +110766,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3876 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + // Pos:3951 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" { .Instruction = ND_INS_VRNDSCALESS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1672, + .Mnemonic = 1747, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108641,12 +110796,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3877 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + // Pos:3952 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" { .Instruction = ND_INS_VROUNDPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1673, + .Mnemonic = 1748, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108669,12 +110824,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3878 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + // Pos:3953 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" { .Instruction = ND_INS_VROUNDPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1674, + .Mnemonic = 1749, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108697,12 +110852,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3879 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + // Pos:3954 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" { .Instruction = ND_INS_VROUNDSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1675, + .Mnemonic = 1750, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108726,12 +110881,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3880 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + // Pos:3955 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" { .Instruction = ND_INS_VROUNDSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1676, + .Mnemonic = 1751, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -108755,12 +110910,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3881 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + // Pos:3956 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRT14PD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1677, + .Mnemonic = 1752, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108783,12 +110938,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3882 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:3957 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRT14PS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1678, + .Mnemonic = 1753, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -108811,12 +110966,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3883 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + // Pos:3958 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" { .Instruction = ND_INS_VRSQRT14SD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1679, + .Mnemonic = 1754, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108840,12 +110995,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3884 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + // Pos:3959 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" { .Instruction = ND_INS_VRSQRT14SS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1680, + .Mnemonic = 1755, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -108869,12 +111024,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3885 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + // Pos:3960 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" { .Instruction = ND_INS_VRSQRT28PD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1681, + .Mnemonic = 1756, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108897,12 +111052,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3886 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + // Pos:3961 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" { .Instruction = ND_INS_VRSQRT28PS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1682, + .Mnemonic = 1757, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -108925,12 +111080,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3887 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + // Pos:3962 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" { .Instruction = ND_INS_VRSQRT28SD, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1683, + .Mnemonic = 1758, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108954,12 +111109,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3888 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + // Pos:3963 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" { .Instruction = ND_INS_VRSQRT28SS, .Category = ND_CAT_KNL, .IsaSet = ND_SET_AVX512ER, - .Mnemonic = 1684, + .Mnemonic = 1759, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -108983,12 +111138,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3889 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" + // Pos:3964 Instruction:"VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x4E /r"/"RAM" + { + .Instruction = ND_INS_VRSQRTPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3965 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" { .Instruction = ND_INS_VRSQRTPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1685, + .Mnemonic = 1761, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109011,12 +111194,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3890 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + // Pos:3966 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" { .Instruction = ND_INS_VRSQRTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1686, + .Mnemonic = 1762, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109038,12 +111221,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3891 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" + // Pos:3967 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" { .Instruction = ND_INS_VRSQRTSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1687, + .Mnemonic = 1763, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, @@ -109067,12 +111250,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3892 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + // Pos:3968 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" { .Instruction = ND_INS_VRSQRTSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1688, + .Mnemonic = 1764, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109095,12 +111278,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3893 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + // Pos:3969 Instruction:"VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:6 p:0 l:x w:0 0x2C /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1765, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3970 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1689, + .Mnemonic = 1766, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -109124,12 +111336,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3894 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:3971 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1690, + .Mnemonic = 1767, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -109153,12 +111365,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3895 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + // Pos:3972 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" { .Instruction = ND_INS_VSCALEFPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1691, + .Mnemonic = 1768, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -109182,12 +111394,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3896 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + // Pos:3973 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" { .Instruction = ND_INS_VSCALEFSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1692, + .Mnemonic = 1769, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -109211,12 +111423,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3897 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:3974 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" { .Instruction = ND_INS_VSCALEFSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1693, + .Mnemonic = 1770, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -109240,12 +111452,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3898 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + // Pos:3975 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" { .Instruction = ND_INS_VSCALEFSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1694, + .Mnemonic = 1771, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -109269,12 +111481,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3899 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + // Pos:3976 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERDPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1695, + .Mnemonic = 1772, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109297,12 +111509,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3900 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + // Pos:3977 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERDPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1696, + .Mnemonic = 1773, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109325,12 +111537,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3901 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + // Pos:3978 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0DPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1697, + .Mnemonic = 1774, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109352,12 +111564,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3902 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + // Pos:3979 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0DPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1698, + .Mnemonic = 1775, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109379,12 +111591,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3903 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + // Pos:3980 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0QPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1699, + .Mnemonic = 1776, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109406,12 +111618,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3904 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + // Pos:3981 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF0QPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1700, + .Mnemonic = 1777, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109433,12 +111645,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3905 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + // Pos:3982 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1DPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1701, + .Mnemonic = 1778, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109460,12 +111672,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3906 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + // Pos:3983 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1DPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1702, + .Mnemonic = 1779, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109487,12 +111699,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3907 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + // Pos:3984 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1QPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1703, + .Mnemonic = 1780, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109514,12 +111726,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3908 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + // Pos:3985 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" { .Instruction = ND_INS_VSCATTERPF1QPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512PF, - .Mnemonic = 1704, + .Mnemonic = 1781, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109541,12 +111753,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3909 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + // Pos:3986 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERQPD, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1705, + .Mnemonic = 1782, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109569,12 +111781,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3910 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + // Pos:3987 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" { .Instruction = ND_INS_VSCATTERQPS, .Category = ND_CAT_SCATTER, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1706, + .Mnemonic = 1783, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK, @@ -109597,12 +111809,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3911 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" + // Pos:3988 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" { .Instruction = ND_INS_VSHA512MSG1, .Category = ND_CAT_SHA512, .IsaSet = ND_SET_SHA512, - .Mnemonic = 1707, + .Mnemonic = 1784, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109624,12 +111836,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3912 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" + // Pos:3989 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" { .Instruction = ND_INS_VSHA512MSG2, .Category = ND_CAT_SHA512, .IsaSet = ND_SET_SHA512, - .Mnemonic = 1708, + .Mnemonic = 1785, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109651,12 +111863,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3913 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" + // Pos:3990 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" { .Instruction = ND_INS_VSHA512RNDS2, .Category = ND_CAT_SHA512, .IsaSet = ND_SET_SHA512, - .Mnemonic = 1709, + .Mnemonic = 1786, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109679,12 +111891,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3914 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + // Pos:3991 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFF32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1710, + .Mnemonic = 1787, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109709,12 +111921,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3915 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + // Pos:3992 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFF64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1711, + .Mnemonic = 1788, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109739,12 +111951,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3916 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + // Pos:3993 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFI32X4, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1712, + .Mnemonic = 1789, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109769,12 +111981,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3917 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + // Pos:3994 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFI64X2, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1713, + .Mnemonic = 1790, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109799,12 +112011,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3918 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + // Pos:3995 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1714, + .Mnemonic = 1791, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109829,12 +112041,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3919 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:3996 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" { .Instruction = ND_INS_VSHUFPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1714, + .Mnemonic = 1791, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109858,12 +112070,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3920 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + // Pos:3997 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" { .Instruction = ND_INS_VSHUFPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1715, + .Mnemonic = 1792, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -109888,12 +112100,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3921 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + // Pos:3998 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" { .Instruction = ND_INS_VSHUFPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1715, + .Mnemonic = 1792, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109917,12 +112129,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3922 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" + // Pos:3999 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM3MSG1, .Category = ND_CAT_SM3, .IsaSet = ND_SET_SM3, - .Mnemonic = 1716, + .Mnemonic = 1793, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109945,12 +112157,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3923 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" + // Pos:4000 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM3MSG2, .Category = ND_CAT_SM3, .IsaSet = ND_SET_SM3, - .Mnemonic = 1717, + .Mnemonic = 1794, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -109973,12 +112185,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3924 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" + // Pos:4001 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" { .Instruction = ND_INS_VSM3RNDS2, .Category = ND_CAT_SM3, .IsaSet = ND_SET_SM3, - .Mnemonic = 1718, + .Mnemonic = 1795, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110002,12 +112214,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3925 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" + // Pos:4002 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM4KEY4, .Category = ND_CAT_SM4, .IsaSet = ND_SET_SM4, - .Mnemonic = 1719, + .Mnemonic = 1796, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110030,12 +112242,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3926 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" + // Pos:4003 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" { .Instruction = ND_INS_VSM4RNDS4, .Category = ND_CAT_SM4, .IsaSet = ND_SET_SM4, - .Mnemonic = 1720, + .Mnemonic = 1797, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110058,12 +112270,40 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3927 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + // Pos:4004 Instruction:"VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x51 /r"/"RAM" + { + .Instruction = ND_INS_VSQRTNEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1798, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:4005 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1721, + .Mnemonic = 1799, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -110086,12 +112326,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3928 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + // Pos:4006 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" { .Instruction = ND_INS_VSQRTPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1721, + .Mnemonic = 1799, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110113,12 +112353,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3929 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:4007 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1722, + .Mnemonic = 1800, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -110141,12 +112381,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3930 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + // Pos:4008 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" { .Instruction = ND_INS_VSQRTPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1723, + .Mnemonic = 1801, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -110169,12 +112409,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3931 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + // Pos:4009 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" { .Instruction = ND_INS_VSQRTPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1723, + .Mnemonic = 1801, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110196,12 +112436,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3932 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + // Pos:4010 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" { .Instruction = ND_INS_VSQRTSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1724, + .Mnemonic = 1802, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -110225,12 +112465,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3933 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + // Pos:4011 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" { .Instruction = ND_INS_VSQRTSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1724, + .Mnemonic = 1802, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110253,12 +112493,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3934 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:4012 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VSQRTSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1725, + .Mnemonic = 1803, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -110282,12 +112522,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3935 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + // Pos:4013 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" { .Instruction = ND_INS_VSQRTSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1726, + .Mnemonic = 1804, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -110311,12 +112551,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3936 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + // Pos:4014 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" { .Instruction = ND_INS_VSQRTSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1726, + .Mnemonic = 1804, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110339,12 +112579,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3937 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + // Pos:4015 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" { .Instruction = ND_INS_VSTMXCSR, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1727, + .Mnemonic = 1805, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110366,12 +112606,41 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3938 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + // Pos:4016 Instruction:"VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16" Encoding:"evex m:5 p:1 l:x w:0 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBNEPBF16, + .Category = ND_CAT_AVX10BF16, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1806, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:4017 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1728, + .Mnemonic = 1807, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -110395,12 +112664,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3939 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + // Pos:4018 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1728, + .Mnemonic = 1807, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110423,12 +112692,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3940 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:4019 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBPH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1729, + .Mnemonic = 1808, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, @@ -110452,12 +112721,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3941 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + // Pos:4020 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1730, + .Mnemonic = 1809, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, @@ -110481,12 +112750,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3942 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + // Pos:4021 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1730, + .Mnemonic = 1809, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110509,12 +112778,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3943 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + // Pos:4022 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBSD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1731, + .Mnemonic = 1810, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -110538,12 +112807,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3944 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + // Pos:4023 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBSD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1731, + .Mnemonic = 1810, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110566,12 +112835,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3945 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:4024 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBSH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1732, + .Mnemonic = 1811, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, @@ -110595,12 +112864,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3946 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + // Pos:4025 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" { .Instruction = ND_INS_VSUBSS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1733, + .Mnemonic = 1812, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, @@ -110624,12 +112893,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3947 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + // Pos:4026 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" { .Instruction = ND_INS_VSUBSS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1733, + .Mnemonic = 1812, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110652,12 +112921,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3948 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + // Pos:4027 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" { .Instruction = ND_INS_VTESTPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1734, + .Mnemonic = 1813, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110680,12 +112949,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3949 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + // Pos:4028 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" { .Instruction = ND_INS_VTESTPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1735, + .Mnemonic = 1814, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110708,12 +112977,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3950 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + // Pos:4029 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1736, + .Mnemonic = 1815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -110736,12 +113005,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3951 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + // Pos:4030 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1736, + .Mnemonic = 1815, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110764,12 +113033,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3952 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:4031 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISH, .Category = ND_CAT_AVX512FP16, .IsaSet = ND_SET_AVX512FP16, - .Mnemonic = 1737, + .Mnemonic = 1816, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -110792,12 +113061,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3953 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + // Pos:4032 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1738, + .Mnemonic = 1817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_SAE, @@ -110820,12 +113089,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3954 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + // Pos:4033 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" { .Instruction = ND_INS_VUCOMISS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1738, + .Mnemonic = 1817, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110848,12 +113117,96 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3955 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + // Pos:4034 Instruction:"VUCOMXSD Vdq,Wsd{sae}" Encoding:"evex m:1 p:2 l:0 w:1 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMXSD, + .Category = ND_CAT_AVX10CMPSFP, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1818, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4035 Instruction:"VUCOMXSH Vdq,Wsh{sae}" Encoding:"evex m:5 p:3 l:0 w:0 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMXSH, + .Category = ND_CAT_AVX10CMPSFP, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1819, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4036 Instruction:"VUCOMXSS Vdq,Wss{sae}" Encoding:"evex m:1 p:3 l:0 w:0 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMXSS, + .Category = ND_CAT_AVX10CMPSFP, + .IsaSet = ND_SET_AVX102, + .Mnemonic = 1820, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4037 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKHPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1739, + .Mnemonic = 1821, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110877,12 +113230,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3956 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + // Pos:4038 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" { .Instruction = ND_INS_VUNPCKHPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1739, + .Mnemonic = 1821, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110905,12 +113258,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3957 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + // Pos:4039 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKHPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1740, + .Mnemonic = 1822, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110934,12 +113287,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3958 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + // Pos:4040 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" { .Instruction = ND_INS_VUNPCKHPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1740, + .Mnemonic = 1822, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -110962,12 +113315,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3959 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + // Pos:4041 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKLPD, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1741, + .Mnemonic = 1823, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -110991,12 +113344,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3960 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + // Pos:4042 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" { .Instruction = ND_INS_VUNPCKLPD, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1741, + .Mnemonic = 1823, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111019,12 +113372,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3961 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + // Pos:4043 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" { .Instruction = ND_INS_VUNPCKLPS, .Category = ND_CAT_AVX512, .IsaSet = ND_SET_AVX512F, - .Mnemonic = 1742, + .Mnemonic = 1824, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111048,12 +113401,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3962 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + // Pos:4044 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" { .Instruction = ND_INS_VUNPCKLPS, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1742, + .Mnemonic = 1824, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111076,12 +113429,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3963 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + // Pos:4045 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" { .Instruction = ND_INS_VXORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1743, + .Mnemonic = 1825, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111105,12 +113458,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3964 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + // Pos:4046 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" { .Instruction = ND_INS_VXORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1743, + .Mnemonic = 1825, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111133,12 +113486,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3965 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + // Pos:4047 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" { .Instruction = ND_INS_VXORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX512DQ, - .Mnemonic = 1744, + .Mnemonic = 1826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, @@ -111162,12 +113515,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3966 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + // Pos:4048 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" { .Instruction = ND_INS_VXORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_AVX, - .Mnemonic = 1744, + .Mnemonic = 1826, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111190,12 +113543,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3967 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + // Pos:4049 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" { .Instruction = ND_INS_VZEROALL, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1745, + .Mnemonic = 1827, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111216,12 +113569,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3968 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + // Pos:4050 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" { .Instruction = ND_INS_VZEROUPPER, .Category = ND_CAT_AVX, .IsaSet = ND_SET_AVX, - .Mnemonic = 1746, + .Mnemonic = 1828, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111242,12 +113595,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3969 Instruction:"WAIT" Encoding:"0x9B"/"" + // Pos:4051 Instruction:"WAIT" Encoding:"0x9B"/"" { .Instruction = ND_INS_WAIT, .Category = ND_CAT_X87_ALU, .IsaSet = ND_SET_X87, - .Mnemonic = 1747, + .Mnemonic = 1829, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111268,12 +113621,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3970 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" + // Pos:4052 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" { .Instruction = ND_INS_WBINVD, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_I486REAL, - .Mnemonic = 1748, + .Mnemonic = 1830, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111294,12 +113647,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3971 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/"" + // Pos:4053 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/"" { .Instruction = ND_INS_WBNOINVD, .Category = ND_CAT_WBNOINVD, .IsaSet = ND_SET_WBNOINVD, - .Mnemonic = 1749, + .Mnemonic = 1831, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111320,12 +113673,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3972 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M" + // Pos:4054 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M" { .Instruction = ND_INS_WRFSBASE, .Category = ND_CAT_RDWRFSGS, .IsaSet = ND_SET_RDWRFSGS, - .Mnemonic = 1750, + .Mnemonic = 1832, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111347,12 +113700,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3973 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M" + // Pos:4055 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M" { .Instruction = ND_INS_WRGSBASE, .Category = ND_CAT_RDWRFSGS, .IsaSet = ND_SET_RDWRFSGS, - .Mnemonic = 1751, + .Mnemonic = 1833, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111374,12 +113727,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3974 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + // Pos:4056 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" { .Instruction = ND_INS_WRMSR, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_PENTIUMREAL, - .Mnemonic = 1752, + .Mnemonic = 1834, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111403,12 +113756,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3975 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" + // Pos:4057 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" { .Instruction = ND_INS_WRMSRLIST, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_MSRLIST, - .Mnemonic = 1753, + .Mnemonic = 1835, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111431,12 +113784,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3976 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" + // Pos:4058 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" { .Instruction = ND_INS_WRMSRNS, .Category = ND_CAT_SYSTEM, .IsaSet = ND_SET_WRMSRNS, - .Mnemonic = 1754, + .Mnemonic = 1836, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111460,12 +113813,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3977 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + // Pos:4059 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" { .Instruction = ND_INS_WRPKRU, .Category = ND_CAT_MISC, .IsaSet = ND_SET_PKU, - .Mnemonic = 1755, + .Mnemonic = 1837, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111489,12 +113842,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3978 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR" + // Pos:4060 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1756, + .Mnemonic = 1838, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111516,12 +113869,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3979 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:4061 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1756, + .Mnemonic = 1838, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111543,12 +113896,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3980 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR" + // Pos:4062 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1757, + .Mnemonic = 1839, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -111570,12 +113923,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3981 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + // Pos:4063 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" { .Instruction = ND_INS_WRSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1757, + .Mnemonic = 1839, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111597,12 +113950,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3982 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR" + // Pos:4064 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1758, + .Mnemonic = 1840, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111624,12 +113977,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3983 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:4065 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1758, + .Mnemonic = 1840, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111651,12 +114004,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3984 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR" + // Pos:4066 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1759, + .Mnemonic = 1841, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111678,12 +114031,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3985 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + // Pos:4067 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { .Instruction = ND_INS_WRUSS, .Category = ND_CAT_CET, .IsaSet = ND_SET_CET_SS, - .Mnemonic = 1759, + .Mnemonic = 1841, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -111705,12 +114058,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3986 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + // Pos:4068 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" { .Instruction = ND_INS_XABORT, .Category = ND_CAT_UNCOND_BR, .IsaSet = ND_SET_TSX, - .Mnemonic = 1760, + .Mnemonic = 1842, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111733,12 +114086,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3987 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + // Pos:4069 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" { .Instruction = ND_INS_XADD, .Category = ND_CAT_SEMAPHORE, .IsaSet = ND_SET_I486REAL, - .Mnemonic = 1761, + .Mnemonic = 1843, .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111761,12 +114114,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3988 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + // Pos:4070 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" { .Instruction = ND_INS_XADD, .Category = ND_CAT_SEMAPHORE, .IsaSet = ND_SET_I486REAL, - .Mnemonic = 1761, + .Mnemonic = 1843, .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111789,12 +114142,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3989 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + // Pos:4071 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" { .Instruction = ND_INS_XBEGIN, .Category = ND_CAT_COND_BR, .IsaSet = ND_SET_TSX, - .Mnemonic = 1762, + .Mnemonic = 1844, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111817,12 +114170,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3990 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + // Pos:4072 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111844,12 +114197,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3991 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + // Pos:4073 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111871,12 +114224,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3992 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" + // Pos:4074 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111898,12 +114251,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3993 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" + // Pos:4075 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111925,12 +114278,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3994 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" + // Pos:4076 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111952,12 +114305,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3995 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" + // Pos:4077 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -111979,12 +114332,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3996 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" + // Pos:4078 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112006,12 +114359,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3997 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" + // Pos:4079 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112033,12 +114386,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3998 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" + // Pos:4080 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112060,12 +114413,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:3999 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" + // Pos:4081 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" { .Instruction = ND_INS_XCHG, .Category = ND_CAT_DATAXFER, .IsaSet = ND_SET_I86, - .Mnemonic = 1763, + .Mnemonic = 1845, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112087,12 +114440,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4000 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + // Pos:4082 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" { .Instruction = ND_INS_XEND, .Category = ND_CAT_COND_BR, .IsaSet = ND_SET_TSX, - .Mnemonic = 1764, + .Mnemonic = 1846, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112113,12 +114466,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4001 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + // Pos:4083 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" { .Instruction = ND_INS_XGETBV, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1765, + .Mnemonic = 1847, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112142,12 +114495,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4002 Instruction:"XLATB" Encoding:"0xD7"/"" + // Pos:4084 Instruction:"XLATB" Encoding:"0xD7"/"" { .Instruction = ND_INS_XLATB, .Category = ND_CAT_MISC, .IsaSet = ND_SET_I86, - .Mnemonic = 1766, + .Mnemonic = 1848, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -112169,12 +114522,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4003 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR" + // Pos:4085 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112197,12 +114550,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4004 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR" + // Pos:4086 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112225,12 +114578,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4005 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR" + // Pos:4087 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112253,12 +114606,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4006 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM" + // Pos:4088 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112281,12 +114634,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4007 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM" + // Pos:4089 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112309,12 +114662,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4008 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM" + // Pos:4090 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112337,12 +114690,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4009 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI" + // Pos:4091 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112365,12 +114718,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4010 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI" + // Pos:4092 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112393,12 +114746,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4011 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI" + // Pos:4093 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112421,12 +114774,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4012 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI" + // Pos:4094 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112449,12 +114802,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4013 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI" + // Pos:4095 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = 0, @@ -112477,12 +114830,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4014 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR" + // Pos:4096 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112504,12 +114857,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4015 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR" + // Pos:4097 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112531,12 +114884,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4016 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR" + // Pos:4098 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112558,12 +114911,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4017 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM" + // Pos:4099 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112585,12 +114938,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4018 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM" + // Pos:4100 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112612,12 +114965,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4019 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM" + // Pos:4101 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112639,12 +114992,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4020 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI" + // Pos:4102 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112666,12 +115019,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4021 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI" + // Pos:4103 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112693,12 +115046,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4022 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI" + // Pos:4104 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112720,12 +115073,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4023 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI" + // Pos:4105 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112747,12 +115100,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4024 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI" + // Pos:4106 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_NF, @@ -112774,12 +115127,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4025 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR" + // Pos:4107 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112803,12 +115156,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4026 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR" + // Pos:4108 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112832,12 +115185,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4027 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR" + // Pos:4109 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112861,12 +115214,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4028 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM" + // Pos:4110 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112890,12 +115243,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4029 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM" + // Pos:4111 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112919,12 +115272,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4030 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM" + // Pos:4112 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112948,12 +115301,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4031 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI" + // Pos:4113 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -112977,12 +115330,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4032 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI" + // Pos:4114 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -113006,12 +115359,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4033 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI" + // Pos:4115 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -113035,12 +115388,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4034 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI" + // Pos:4116 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -113064,12 +115417,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4035 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI" + // Pos:4117 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND, @@ -113093,12 +115446,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4036 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR" + // Pos:4118 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113121,12 +115474,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4037 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR" + // Pos:4119 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113149,12 +115502,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4038 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR" + // Pos:4120 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113177,12 +115530,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4039 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM" + // Pos:4121 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113205,12 +115558,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4040 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM" + // Pos:4122 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113233,12 +115586,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4041 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM" + // Pos:4123 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113261,12 +115614,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4042 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI" + // Pos:4124 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113289,12 +115642,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4043 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI" + // Pos:4125 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113317,12 +115670,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4044 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI" + // Pos:4126 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113345,12 +115698,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4045 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI" + // Pos:4127 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113373,12 +115726,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4046 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI" + // Pos:4128 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_APX_F, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, .ValidDecorators = ND_DECO_ND|ND_DECO_NF, @@ -113401,12 +115754,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4047 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + // Pos:4129 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113429,12 +115782,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4048 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + // Pos:4130 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113457,12 +115810,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4049 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + // Pos:4131 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113485,12 +115838,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4050 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + // Pos:4132 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113513,12 +115866,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4051 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + // Pos:4133 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113541,12 +115894,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4052 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + // Pos:4134 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113569,12 +115922,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4053 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + // Pos:4135 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113597,12 +115950,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4054 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + // Pos:4136 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113625,12 +115978,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4055 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" + // Pos:4137 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -113653,12 +116006,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4056 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + // Pos:4138 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" { .Instruction = ND_INS_XOR, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_I86, - .Mnemonic = 1767, + .Mnemonic = 1849, .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113681,12 +116034,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4057 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + // Pos:4139 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" { .Instruction = ND_INS_XORPD, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_SSE2, - .Mnemonic = 1768, + .Mnemonic = 1850, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113708,12 +116061,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4058 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + // Pos:4140 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" { .Instruction = ND_INS_XORPS, .Category = ND_CAT_LOGICAL_FP, .IsaSet = ND_SET_SSE, - .Mnemonic = 1769, + .Mnemonic = 1851, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113735,12 +116088,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4059 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + // Pos:4141 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" { .Instruction = ND_INS_XRESLDTRK, .Category = ND_CAT_MISC, .IsaSet = ND_SET_TSXLDTRK, - .Mnemonic = 1770, + .Mnemonic = 1852, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113761,12 +116114,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4060 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" + // Pos:4142 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" { .Instruction = ND_INS_XRSTOR, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1771, + .Mnemonic = 1853, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113791,12 +116144,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4061 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + // Pos:4143 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" { .Instruction = ND_INS_XRSTOR, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1772, + .Mnemonic = 1854, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113821,12 +116174,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4062 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + // Pos:4144 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" { .Instruction = ND_INS_XRSTORS, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1773, + .Mnemonic = 1855, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113851,12 +116204,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4063 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + // Pos:4145 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" { .Instruction = ND_INS_XRSTORS, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1774, + .Mnemonic = 1856, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113881,12 +116234,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4064 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + // Pos:4146 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" { .Instruction = ND_INS_XSAVE, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1775, + .Mnemonic = 1857, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113911,12 +116264,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4065 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + // Pos:4147 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" { .Instruction = ND_INS_XSAVE, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1776, + .Mnemonic = 1858, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113941,12 +116294,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4066 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + // Pos:4148 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" { .Instruction = ND_INS_XSAVEC, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVEC, - .Mnemonic = 1777, + .Mnemonic = 1859, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -113971,12 +116324,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4067 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + // Pos:4149 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" { .Instruction = ND_INS_XSAVEC, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVEC, - .Mnemonic = 1778, + .Mnemonic = 1860, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114001,12 +116354,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4068 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + // Pos:4150 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" { .Instruction = ND_INS_XSAVEOPT, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1779, + .Mnemonic = 1861, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114031,12 +116384,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4069 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + // Pos:4151 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" { .Instruction = ND_INS_XSAVEOPT, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1780, + .Mnemonic = 1862, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114061,12 +116414,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4070 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + // Pos:4152 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" { .Instruction = ND_INS_XSAVES, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1781, + .Mnemonic = 1863, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114091,12 +116444,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4071 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + // Pos:4153 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" { .Instruction = ND_INS_XSAVES, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVES, - .Mnemonic = 1782, + .Mnemonic = 1864, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114121,12 +116474,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4072 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + // Pos:4154 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" { .Instruction = ND_INS_XSETBV, .Category = ND_CAT_XSAVE, .IsaSet = ND_SET_XSAVE, - .Mnemonic = 1783, + .Mnemonic = 1865, .ValidPrefixes = 0, .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, .ValidDecorators = 0, @@ -114150,12 +116503,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4073 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + // Pos:4155 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" { .Instruction = ND_INS_XSUSLDTRK, .Category = ND_CAT_MISC, .IsaSet = ND_SET_TSXLDTRK, - .Mnemonic = 1784, + .Mnemonic = 1866, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, @@ -114176,12 +116529,12 @@ const ND_IDBE gInstructions[4075] = }, }, - // Pos:4074 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + // Pos:4156 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" { .Instruction = ND_INS_XTEST, .Category = ND_CAT_LOGIC, .IsaSet = ND_SET_TSX, - .Mnemonic = 1785, + .Mnemonic = 1867, .ValidPrefixes = 0, .ValidModes = ND_MOD_ANY, .ValidDecorators = 0, diff --git a/bddisasm/include/bdx86_mnemonics.h b/bddisasm/include/bdx86_mnemonics.h index 01eea3a..09ef09a 100644 --- a/bddisasm/include/bdx86_mnemonics.h +++ b/bddisasm/include/bdx86_mnemonics.h @@ -12,7 +12,7 @@ #ifndef BDDISASM_NO_MNEMONIC -const char *gMnemonics[1786] = +const char *gMnemonics[1868] = { "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", @@ -128,109 +128,125 @@ const char *gMnemonics[1786] = "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN", - "RMPADJUST", "RMPQUERY", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", - "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS", "RSQRTSS", - "RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", - "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", - "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", - "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", - "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", - "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", - "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", - "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", - "SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", - "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", - "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", - "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL", "SYSENTER", - "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS", + "RMPADJUST", "RMPQUERY", "RMPREAD", "RMPUPDATE", "ROL", "ROR", + "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS", + "RSQRTSS", "RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX", + "SAVEPREVSSP", "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", + "SEAMOPS", "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC", + "SETL", "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", + "SETNP", "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", + "SETZ", "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", + "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", + "SHLD", "SHLX", "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", + "SKINIT", "SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", + "SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", + "STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", + "SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL", + "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS", "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR", "UWRMSR", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", - "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", - "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", - "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", - "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", - "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", - "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", - "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", - "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", - "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", - "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", - "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", - "VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS", - "VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16", - "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", - "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", - "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", - "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", - "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", - "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", - "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", - "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", - "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ", - "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W", - "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI", - "VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI", - "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH", - "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH", - "VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", - "VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", - "VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", - "VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4", - "VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2", - "VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", - "VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", + "VADDNEPBF16", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", + "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", + "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", + "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", + "VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", + "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", + "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", + "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", + "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", + "VCMPPBF16", "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", + "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", + "VCOMSBF16", "VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX", + "VCVTBIASPH2BF8", "VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S", + "VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8", + "VCVTNE2PH2BF8S", "VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16", + "VCVTNEBF162IBS", "VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS", + "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S", + "VCVTNEPH2HF8", "VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ", + "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", + "VCVTPH2DQ", "VCVTPH2IBS", "VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS", + "VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", + "VCVTPH2W", "VCVTPS2DQ", "VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD", + "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", + "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", + "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", + "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", + "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS", + "VCVTTPD2DQ", "VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ", + "VCVTTPD2UDQS", "VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ", + "VCVTTPH2IBS", "VCVTTPH2IUBS", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", + "VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS", + "VCVTTPS2IUBS", "VCVTTPS2QQ", "VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS", + "VCVTTPS2UQQ", "VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI", + "VCVTTSD2USIS", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS", + "VCVTTSS2USI", "VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", + "VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", + "VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16", + "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS", + "VDPPD", "VDPPHPS", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", + "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", + "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", + "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", + "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", "VFCMULCSH", "VFIXUPIMMPD", + "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132NEPBF16", "VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH", - "VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD", - "VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", - "VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", - "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", - "VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH", - "VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS", - "VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", - "VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH", - "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD", - "VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", - "VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", - "VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", - "VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", - "VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD", + "VFMADD132SS", "VFMADD213NEPBF16", "VFMADD213PD", "VFMADD213PH", + "VFMADD213PS", "VFMADD213SD", "VFMADD213SH", "VFMADD213SS", "VFMADD231NEPBF16", + "VFMADD231PD", "VFMADD231PH", "VFMADD231PS", "VFMADD231SD", "VFMADD231SH", + "VFMADD231SS", "VFMADDCPH", "VFMADDCSH", "VFMADDPD", "VFMADDPS", + "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", "VFMADDSUB132PH", "VFMADDSUB132PS", + "VFMADDSUB213PD", "VFMADDSUB213PH", "VFMADDSUB213PS", "VFMADDSUB231PD", + "VFMADDSUB231PH", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS", + "VFMSUB132NEPBF16", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS", + "VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213NEPBF16", + "VFMSUB213PD", "VFMSUB213PH", "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", + "VFMSUB213SS", "VFMSUB231NEPBF16", "VFMSUB231PD", "VFMSUB231PH", + "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", "VFMSUBADD132PD", + "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", "VFMSUBADD213PH", + "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", "VFMSUBADD231PS", + "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD", + "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132NEPBF16", "VFNMADD132PD", "VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH", - "VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS", - "VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD", - "VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH", - "VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", - "VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", - "VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH", + "VFNMADD132SS", "VFNMADD213NEPBF16", "VFNMADD213PD", "VFNMADD213PH", + "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", + "VFNMADD231NEPBF16", "VFNMADD231PD", "VFNMADD231PH", "VFNMADD231PS", + "VFNMADD231SD", "VFNMADD231SH", "VFNMADD231SS", "VFNMADDPD", + "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132NEPBF16", "VFNMSUB132PD", + "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SH", + "VFNMSUB132SS", "VFNMSUB213NEPBF16", "VFNMSUB213PD", "VFNMSUB213PH", "VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS", - "VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD", - "VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD", - "VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", - "VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD", - "VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS", - "VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS", - "VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS", - "VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", - "VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", - "VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", - "VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", - "VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", - "VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", - "VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", - "VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", + "VFNMSUB231NEPBF16", "VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", + "VFNMSUB231SD", "VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", + "VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", "VFPCLASSPBF16", "VFPCLASSPD", + "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", "VFPCLASSSH", "VFPCLASSSS", + "VFRCZPD", "VFRCZPS", "VFRCZSD", "VFRCZSS", "VGATHERDPD", "VGATHERDPS", + "VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", "VGATHERPF0QPS", + "VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", "VGATHERPF1QPS", + "VGATHERQPD", "VGATHERQPS", "VGETEXPPBF16", "VGETEXPPD", "VGETEXPPH", + "VGETEXPPS", "VGETEXPSD", "VGETEXPSH", "VGETEXPSS", "VGETMANTPBF16", + "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", "VGETMANTSH", + "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", "VGF2P8MULB", + "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", "VINSERTF32X4", + "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", "VINSERTI128", + "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", "VINSERTI64X4", + "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", "VMASKMOVPD", + "VMASKMOVPS", "VMAXPBF16", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD", "VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT", - "VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", - "VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", - "VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16", - "VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", - "VMOVHPS", "VMOVLHPS", "VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", - "VMOVNTDQ", "VMOVNTDQA", "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", - "VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS", - "VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME", - "VMRUN", "VMSAVE", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH", + "VMINMAXNEPBF16", "VMINMAXPD", "VMINMAXPH", "VMINMAXPS", "VMINMAXSD", + "VMINMAXSH", "VMINMAXSS", "VMINPBF16", "VMINPD", "VMINPH", "VMINPS", + "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", "VMLOAD", "VMMCALL", + "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA", "VMOVDQA32", + "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64", + "VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS", "VMOVLPD", + "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA", + "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSH", "VMOVSHDUP", + "VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW", + "VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME", "VMRUN", "VMSAVE", + "VMULNEPBF16", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH", "VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD", "VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD", "VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB", @@ -296,27 +312,29 @@ const char *gMnemonics[1786] = "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", "VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", "VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", "VRCP28PD", "VRCP28PS", - "VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS", - "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH", - "VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD", - "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", "VROUNDSD", - "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS", - "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", "VRSQRTPH", - "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD", "VSCALEFPH", + "VRCP28SD", "VRCP28SS", "VRCPPBF16", "VRCPPH", "VRCPPS", "VRCPSH", + "VRCPSS", "VREDUCENEPBF16", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", + "VREDUCESD", "VREDUCESH", "VREDUCESS", "VRNDSCALENEPBF16", "VRNDSCALEPD", + "VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", + "VROUNDPD", "VROUNDPS", "VROUNDSD", "VROUNDSS", "VRSQRT14PD", + "VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", + "VRSQRT28SD", "VRSQRT28SS", "VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS", + "VRSQRTSH", "VRSQRTSS", "VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH", "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", "VSHA512MSG1", "VSHA512MSG2", "VSHA512RNDS2", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD", "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2", - "VSM4KEY4", "VSM4RNDS4", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", - "VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS", - "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", - "VUCOMISH", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", - "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", - "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", - "WRMSRNS", "WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", - "XADD", "XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", + "VSM4KEY4", "VSM4RNDS4", "VSQRTNEPBF16", "VSQRTPD", "VSQRTPH", + "VSQRTPS", "VSQRTSD", "VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBNEPBF16", + "VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", + "VTESTPS", "VUCOMISD", "VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH", + "VUCOMXSS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", + "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD", + "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS", + "WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD", + "XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV", "XSUSLDTRK", "XTEST", diff --git a/bddisasm/include/bdx86_table_evex.h b/bddisasm/include/bdx86_table_evex.h index cd5bc49..872303f 100644 --- a/bddisasm/include/bdx86_table_evex.h +++ b/bddisasm/include/bdx86_table_evex.h @@ -13,7 +13,7 @@ const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2650] // URDMSR Rq,Id + (const void *)&gInstructions[ 2634] // URDMSR Rq,Id }; const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf = @@ -72,7 +72,7 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2654] // UWRMSR Id,Rq + (const void *)&gInstructions[ 2638] // UWRMSR Id,Rq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf = @@ -405,7 +405,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_07_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2877] // VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 2907] // VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_03_w = @@ -420,7 +420,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2999] // VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 3035] // VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_02_w = @@ -446,7 +446,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2876] // VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2906] // VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_03_w = @@ -461,7 +461,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2998] // VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3034] // VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_02_w = @@ -487,7 +487,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3065] // VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3107] // VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bf_pp_01_w = @@ -513,7 +513,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3060] // VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3102] // VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_01_w = @@ -525,11 +525,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3099] // VFNMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_be_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -539,7 +554,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_be_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3027] // VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3066] // VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bd_pp_01_w = @@ -565,7 +580,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3022] // VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3061] // VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_01_w = @@ -577,11 +592,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3058] // VFNMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bc_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -591,7 +621,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2968] // VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3004] // VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bb_pp_01_w = @@ -617,7 +647,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2963] // VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2999] // VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_01_w = @@ -629,11 +659,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2996] // VFMSUB231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ba_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -643,7 +688,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ba_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2909] // VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2942] // VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b9_pp_01_w = @@ -669,7 +714,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2904] // VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2937] // VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_01_w = @@ -681,11 +726,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2934] // VFMADD231NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b8_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -695,7 +755,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2983] // VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3019] // VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b7_pp_01_w = @@ -721,7 +781,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2934] // VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2967] // VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b6_pp_01_w = @@ -747,7 +807,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_af_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3055] // VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3096] // VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_af_pp_01_w = @@ -773,7 +833,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_af_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3050] // VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3091] // VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_01_w = @@ -785,11 +845,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3088] // VFNMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ae_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -799,7 +874,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ae_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ad_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3017] // VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3055] // VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ad_pp_01_w = @@ -825,7 +900,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ad_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3012] // VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3050] // VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_01_w = @@ -837,11 +912,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3047] // VFNMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ac_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -851,7 +941,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ac_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ab_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2958] // VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2993] // VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ab_pp_01_w = @@ -877,7 +967,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ab_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2953] // VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2988] // VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_01_w = @@ -889,11 +979,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2985] // VFMSUB213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_aa_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -903,7 +1008,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_aa_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2899] // VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2931] // VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a9_pp_01_w = @@ -929,7 +1034,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2894] // VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2926] // VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_01_w = @@ -941,11 +1046,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2923] // VFMADD213NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a8_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -955,7 +1075,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2978] // VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3014] // VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a7_pp_01_w = @@ -981,7 +1101,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2929] // VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2962] // VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a6_pp_01_w = @@ -1007,7 +1127,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3045] // VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3085] // VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9f_pp_01_w = @@ -1033,7 +1153,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3040] // VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3080] // VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_01_w = @@ -1045,11 +1165,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3077] // VFNMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9e_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1059,7 +1194,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3007] // VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3044] // VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9d_pp_01_w = @@ -1085,7 +1220,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3002] // VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3039] // VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_01_w = @@ -1097,11 +1232,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3036] // VFNMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9c_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1111,7 +1261,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2948] // VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2982] // VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9b_pp_01_w = @@ -1137,7 +1287,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2943] // VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2977] // VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_01_w = @@ -1149,11 +1299,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2974] // VFMSUB132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9a_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1163,7 +1328,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_99_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2889] // VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2920] // VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_99_pp_01_w = @@ -1189,7 +1354,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_99_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2884] // VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2915] // VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_01_w = @@ -1201,11 +1366,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2912] // VFMADD132NEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_98_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1215,7 +1395,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_98_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_97_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2973] // VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3009] // VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_97_pp_01_w = @@ -1241,7 +1421,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_97_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_96_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2924] // VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2957] // VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_96_pp_01_w = @@ -1267,7 +1447,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_96_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2875] // VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 2905] // VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_03_w = @@ -1282,7 +1462,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2913] // VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} + (const void *)&gInstructions[ 2946] // VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_02_w = @@ -1308,7 +1488,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_57_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2874] // VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2904] // VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_03_w = @@ -1323,7 +1503,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2912] // VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2945] // VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_02_w = @@ -1349,7 +1529,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_56_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3891] // VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh + (const void *)&gInstructions[ 3967] // VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4f_pp_01_w = @@ -1375,7 +1555,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3889] // VRSQRTPH Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 3965] // VRSQRTPH Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_01_w = @@ -1387,11 +1567,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3964] // VRSQRTPBF16 Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4e_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1401,7 +1596,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3863] // VRCPSH Vdq{K}{z},aKq,Hdq,Wsh + (const void *)&gInstructions[ 3936] // VRCPSH Vdq{K}{z},aKq,Hdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4d_pp_01_w = @@ -1427,7 +1622,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3861] // VRCPPH Vfv{K}{z},aKq,Wfv|B16 + (const void *)&gInstructions[ 3934] // VRCPPH Vfv{K}{z},aKq,Wfv|B16 }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_01_w = @@ -1439,11 +1634,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3933] // VRCPPBF16 Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4c_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1453,7 +1663,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_43_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3106] // VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 3150] // VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_43_pp_01_w = @@ -1479,7 +1689,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_42_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3103] // VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 3147] // VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_01_w = @@ -1505,7 +1715,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3897] // VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3974] // VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2d_pp_01_w = @@ -1531,7 +1741,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3894] // VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3971] // VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_01_w = @@ -1543,11 +1753,26 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3969] // VSCALEFPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2c_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_01_w, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -1557,7 +1782,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2761] // VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae} + (const void *)&gInstructions[ 2769] // VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_01_w = @@ -1572,7 +1797,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2790] // VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 2800] // VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_00_w = @@ -1858,10 +2083,36 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_06_opcode = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3338] // VMOVW Ww,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_02_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3280] // VMOVW Rd,Vdq + (const void *)&gInstructions[ 3337] // VMOVW Rd,Vdq }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l = @@ -1878,7 +2129,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3279] // VMOVW Mw,Vdq + (const void *)&gInstructions[ 3336] // VMOVW Mw,Vdq }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l = @@ -1907,7 +2158,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7e_pp = { /* 00 */ (const void *)ND_NULL, /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_02_l, /* 03 */ (const void *)ND_NULL, } }; @@ -1915,7 +2166,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2838] // VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2866] // VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_03_w = @@ -1930,7 +2181,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2839] // VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2867] // VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_02_w = @@ -1945,7 +2196,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2766] // VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2774] // VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_01_w = @@ -1960,7 +2211,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2765] // VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 2773] // VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_00_w = @@ -1986,7 +2237,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2814] // VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 2832] // VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_01_w = @@ -2001,7 +2252,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2813] // VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae} + (const void *)&gInstructions[ 2831] // VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_00_w = @@ -2027,13 +2278,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2836] // VCVTUSI2SH Vdq,Hdq,Ey{er} + (const void *)&gInstructions[ 2864] // VCVTUSI2SH Vdq,Hdq,Ey{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2762] // VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er} + (const void *)&gInstructions[ 2770] // VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7b_pp_01_w = @@ -2059,13 +2310,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2832] // VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2860] // VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2829] // VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2857] // VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_03_w = @@ -2080,7 +2331,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2810] // VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae} + (const void *)&gInstructions[ 2828] // VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_01_w = @@ -2106,13 +2357,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2791] // VCVTSH2USI Gy,Wsh{er} + (const void *)&gInstructions[ 2801] // VCVTSH2USI Gy,Wsh{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2764] // VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er} + (const void *)&gInstructions[ 2772] // VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_01_w = @@ -2127,7 +2378,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2763] // VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er} + (const void *)&gInstructions[ 2771] // VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_00_w = @@ -2153,7 +2404,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_79_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_02_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2824] // VCVTTSH2USI Gy,Wsh{sae} + (const void *)&gInstructions[ 2850] // VCVTTSH2USI Gy,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_02_wi = @@ -2168,7 +2419,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_02_wi = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2812] // VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae} + (const void *)&gInstructions[ 2830] // VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_01_w = @@ -2183,7 +2434,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2811] // VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae} + (const void *)&gInstructions[ 2829] // VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_00_w = @@ -2206,10 +2457,92 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_78_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2737] // VCVTNE2PH2BF8S Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2748] // VCVTNEPH2BF8S Vhv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_74_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2726] // VCVTBIASPH2BF8S Vhv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_74_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_74_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3335] // VMOVW Vdq,Ww +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_02_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3278] // VMOVW Vdq,Rd + (const void *)&gInstructions[ 3334] // VMOVW Vdq,Rd }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l = @@ -2226,7 +2559,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3277] // VMOVW Vdq,Mw + (const void *)&gInstructions[ 3333] // VMOVW Vdq,Mw }; const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l = @@ -2255,15 +2588,369 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6e_pp = { /* 00 */ (const void *)ND_NULL, /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod, - /* 02 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_02_l, /* 03 */ (const void *)ND_NULL, } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2846] // VCVTTSD2SIS Gy,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2853] // VCVTTSS2SIS Gy,Wss{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2820] // VCVTTPD2QQS Vfv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2839] // VCVTTPS2QQS Vfv{K}{z},aKq,Whv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2818] // VCVTTPD2DQS Vhv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6d_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2835] // VCVTTPS2DQS Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6d_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2848] // VCVTTSD2USIS Gy,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2855] // VCVTTSS2USIS Gy,Wss{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2824] // VCVTTPD2UQQS Vfv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2843] // VCVTTPS2UQQS Vfv{K}{z},aKq,Whv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2822] // VCVTTPD2UDQS Vhv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2841] // VCVTTPS2UDQS Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2742] // VCVTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2778] // VCVTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6b_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2764] // VCVTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6b_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2815] // VCVTTNEBF162IUBS Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2837] // VCVTTPS2IUBS Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6a_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2827] // VCVTTPH2IUBS Vfv{K}{z},aKq,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_6a_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2741] // VCVTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2777] // VCVTPS2IBS Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_69_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2763] // VCVTPH2IBS Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_69_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_69_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2814] // VCVTTNEBF162IBS Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2836] // VCVTTPS2IBS Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_68_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2826] // VCVTTPH2IBS Vfv{K}{z},aKq,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_68_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_68_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp_03_w, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3152] // VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 3198] // VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_02_w = @@ -2275,10 +2962,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3190] // VMAXPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3147] // VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} + (const void *)&gInstructions[ 3193] // VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_00_w = @@ -2295,7 +2997,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5f_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_02_w, /* 03 */ (const void *)ND_NULL, } @@ -2304,7 +3006,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2848] // VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2877] // VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_02_w = @@ -2316,10 +3018,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2869] // VDIVNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2843] // VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2872] // VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_00_w = @@ -2336,7 +3053,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5e_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_02_w, /* 03 */ (const void *)ND_NULL, } @@ -2345,7 +3062,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3167] // VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 3221] // VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_02_w = @@ -2357,10 +3074,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3213] // VMINPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3162] // VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} + (const void *)&gInstructions[ 3216] // VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_00_w = @@ -2377,7 +3109,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5d_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_02_w, /* 03 */ (const void *)ND_NULL, } @@ -2386,7 +3118,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3945] // VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 4024] // VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_02_w = @@ -2398,10 +3130,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4016] // VSUBNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3940] // VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} + (const void *)&gInstructions[ 4019] // VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_00_w = @@ -2418,7 +3165,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5c_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_02_w, /* 03 */ (const void *)ND_NULL, } @@ -2427,7 +3174,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2809] // VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae} + (const void *)&gInstructions[ 2825] // VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_02_w = @@ -2442,7 +3189,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2756] // VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er} + (const void *)&gInstructions[ 2762] // VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_01_w = @@ -2457,13 +3204,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2780] // VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2790] // VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2737] // VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2732] // VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_00_w = @@ -2489,7 +3236,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2782] // VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2792] // VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_03_w = @@ -2504,7 +3251,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2788] // VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae} + (const void *)&gInstructions[ 2798] // VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_02_w = @@ -2519,7 +3266,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2749] // VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2755] // VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_01_w = @@ -2534,7 +3281,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2757] // VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae} + (const void *)&gInstructions[ 2765] // VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_00_w = @@ -2560,7 +3307,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3295] // VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 3355] // VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_02_w = @@ -2572,10 +3319,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3347] // VMULNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3290] // VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 3350] // VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_00_w = @@ -2592,7 +3354,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_59_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_02_w, /* 03 */ (const void *)ND_NULL, } @@ -2601,7 +3363,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_59_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2668] // VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 2653] // VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_02_w = @@ -2613,10 +3375,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2645] // VADDNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2663] // VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} + (const void *)&gInstructions[ 2648] // VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_00_w = @@ -2633,7 +3410,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_58_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_02_w, /* 03 */ (const void *)ND_NULL, } @@ -2642,7 +3419,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_58_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3934] // VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er} + (const void *)&gInstructions[ 4012] // VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_02_w = @@ -2654,10 +3431,25 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_02_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4004] // VSQRTNEPBF16 Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3929] // VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er} + (const void *)&gInstructions[ 4007] // VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_00_w = @@ -2674,16 +3466,83 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_51_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_00_w, - /* 01 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_02_w, /* 03 */ (const void *)ND_NULL, } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_42_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3145] // VGETEXPPBF16 Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_42_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_42_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_42_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2722] // VCOMXSH Vdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_2f_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_03_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2720] // VCOMSBF16 Vdq,Wsh +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2729] // VCOMISH Vdq,Wsh{sae} + (const void *)&gInstructions[ 2715] // VCOMISH Vdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_00_w = @@ -2700,6 +3559,32 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2f_pp = ND_ILUT_EX_PP, { /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4035] // VUCOMXSH Vdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_2e_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_03_l_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, @@ -2709,7 +3594,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3952] // VUCOMISH Vdq,Wsh{sae} + (const void *)&gInstructions[ 4031] // VUCOMISH Vdq,Wsh{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_00_w = @@ -2728,14 +3613,14 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2e_pp = /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_03_l, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2789] // VCVTSH2SI Gy,Wsh{er} + (const void *)&gInstructions[ 2799] // VCVTSH2SI Gy,Wsh{er} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2d_pp = @@ -2752,7 +3637,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2823] // VCVTTSH2SI Gy,Wsh{sae} + (const void *)&gInstructions[ 2849] // VCVTTSH2SI Gy,Wsh{sae} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2c_pp = @@ -2769,7 +3654,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2795] // VCVTSI2SH Vdq,Hdq,Ey + (const void *)&gInstructions[ 2805] // VCVTSI2SH Vdq,Hdq,Ey }; const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2a_pp = @@ -2783,10 +3668,36 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2a_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1e_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2735] // VCVTHF82PH Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1e_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1e_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_1e_pp_03_w, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2775] // VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2785] // VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_01_w = @@ -2801,7 +3712,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2800] // VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2810] // VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_00_w = @@ -2824,10 +3735,122 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1d_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2739] // VCVTNE2PH2HF8S Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2750] // VCVTNEPH2HF8S Vhv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1b_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2728] // VCVTBIASPH2HF8S Vhv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1b_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2738] // VCVTNE2PH2HF8 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2749] // VCVTNEPH2HF8 Vhv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_18_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2727] // VCVTBIASPH2HF8 Vhv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_18_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_18_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp_03_w, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3256] // VMOVSH Wsh{K}{z},aKq,Hdq,Vdq + (const void *)&gInstructions[ 3312] // VMOVSH Wsh{K}{z},aKq,Hdq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w = @@ -2842,7 +3865,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3255] // VMOVSH Wsh{K},aKq,Vdq + (const void *)&gInstructions[ 3311] // VMOVSH Wsh{K},aKq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w = @@ -2877,7 +3900,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_11_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3254] // VMOVSH Vdq{K}{z},aKq,Hdq,Wsh + (const void *)&gInstructions[ 3310] // VMOVSH Vdq{K}{z},aKq,Hdq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w = @@ -2892,7 +3915,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3253] // VMOVSH Vdq{K}{z},aKq,Wsh + (const void *)&gInstructions[ 3309] // VMOVSH Vdq{K}{z},aKq,Wsh }; const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w = @@ -2952,13 +3975,13 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = /* 15 */ (const void *)ND_NULL, /* 16 */ (const void *)ND_NULL, /* 17 */ (const void *)ND_NULL, - /* 18 */ (const void *)ND_NULL, + /* 18 */ (const void *)&gEvexMap_mmmmm_05_opcode_18_pp, /* 19 */ (const void *)ND_NULL, /* 1a */ (const void *)ND_NULL, - /* 1b */ (const void *)ND_NULL, + /* 1b */ (const void *)&gEvexMap_mmmmm_05_opcode_1b_pp, /* 1c */ (const void *)ND_NULL, /* 1d */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp, - /* 1e */ (const void *)ND_NULL, + /* 1e */ (const void *)&gEvexMap_mmmmm_05_opcode_1e_pp, /* 1f */ (const void *)ND_NULL, /* 20 */ (const void *)ND_NULL, /* 21 */ (const void *)ND_NULL, @@ -2994,7 +4017,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = /* 3f */ (const void *)ND_NULL, /* 40 */ (const void *)ND_NULL, /* 41 */ (const void *)ND_NULL, - /* 42 */ (const void *)ND_NULL, + /* 42 */ (const void *)&gEvexMap_mmmmm_05_opcode_42_pp, /* 43 */ (const void *)ND_NULL, /* 44 */ (const void *)ND_NULL, /* 45 */ (const void *)ND_NULL, @@ -3032,19 +4055,19 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = /* 65 */ (const void *)ND_NULL, /* 66 */ (const void *)ND_NULL, /* 67 */ (const void *)ND_NULL, - /* 68 */ (const void *)ND_NULL, - /* 69 */ (const void *)ND_NULL, - /* 6a */ (const void *)ND_NULL, - /* 6b */ (const void *)ND_NULL, - /* 6c */ (const void *)ND_NULL, - /* 6d */ (const void *)ND_NULL, + /* 68 */ (const void *)&gEvexMap_mmmmm_05_opcode_68_pp, + /* 69 */ (const void *)&gEvexMap_mmmmm_05_opcode_69_pp, + /* 6a */ (const void *)&gEvexMap_mmmmm_05_opcode_6a_pp, + /* 6b */ (const void *)&gEvexMap_mmmmm_05_opcode_6b_pp, + /* 6c */ (const void *)&gEvexMap_mmmmm_05_opcode_6c_pp, + /* 6d */ (const void *)&gEvexMap_mmmmm_05_opcode_6d_pp, /* 6e */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp, /* 6f */ (const void *)ND_NULL, /* 70 */ (const void *)ND_NULL, /* 71 */ (const void *)ND_NULL, /* 72 */ (const void *)ND_NULL, /* 73 */ (const void *)ND_NULL, - /* 74 */ (const void *)ND_NULL, + /* 74 */ (const void *)&gEvexMap_mmmmm_05_opcode_74_pp, /* 75 */ (const void *)ND_NULL, /* 76 */ (const void *)ND_NULL, /* 77 */ (const void *)ND_NULL, @@ -3190,13 +4213,13 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 871] // DEC Bv,Ev + (const void *)&gInstructions[ 863] // DEC Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 868] // DEC Bv,Ev + (const void *)&gInstructions[ 860] // DEC Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -3211,13 +4234,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 865] // DEC Ev + (const void *)&gInstructions[ 857] // DEC Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 862] // DEC Ev + (const void *)&gInstructions[ 854] // DEC Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -3252,13 +4275,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1137] // INC Bv,Ev + (const void *)&gInstructions[ 1127] // INC Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1134] // INC Bv,Ev + (const void *)&gInstructions[ 1124] // INC Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -3273,13 +4296,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1131] // INC Ev + (const void *)&gInstructions[ 1121] // INC Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1128] // INC Ev + (const void *)&gInstructions[ 1118] // INC Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -3329,7 +4352,7 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1979] // PUSH2P Bv,Rv + (const void *)&gInstructions[ 1969] // PUSH2P Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf = @@ -3353,7 +4376,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1978] // PUSH2 Bv,Rv + (const void *)&gInstructions[ 1968] // PUSH2 Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf = @@ -3406,13 +4429,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 870] // DEC Bv,Ev + (const void *)&gInstructions[ 862] // DEC Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 867] // DEC Bv,Ev + (const void *)&gInstructions[ 859] // DEC Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -3427,13 +4450,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 864] // DEC Ev + (const void *)&gInstructions[ 856] // DEC Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 861] // DEC Ev + (const void *)&gInstructions[ 853] // DEC Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -3468,13 +4491,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1136] // INC Bv,Ev + (const void *)&gInstructions[ 1126] // INC Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1133] // INC Bv,Ev + (const void *)&gInstructions[ 1123] // INC Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -3489,13 +4512,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1130] // INC Ev + (const void *)&gInstructions[ 1120] // INC Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1127] // INC Ev + (const void *)&gInstructions[ 1117] // INC Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -3556,13 +4579,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ff_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 869] // DEC Bb,Eb + (const void *)&gInstructions[ 861] // DEC Bb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 866] // DEC Bb,Eb + (const void *)&gInstructions[ 858] // DEC Bb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -3577,13 +4600,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 863] // DEC Eb + (const void *)&gInstructions[ 855] // DEC Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 860] // DEC Eb + (const void *)&gInstructions[ 852] // DEC Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -3618,13 +4641,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1135] // INC Bb,Eb + (const void *)&gInstructions[ 1125] // INC Bb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1132] // INC Bb,Eb + (const void *)&gInstructions[ 1122] // INC Bb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -3639,13 +4662,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1129] // INC Eb + (const void *)&gInstructions[ 1119] // INC Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1126] // INC Eb + (const void *)&gInstructions[ 1116] // INC Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -3706,7 +4729,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_fe_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 189] // AOR My,Gy + (const void *)&gInstructions[ 181] // AOR My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf = @@ -3750,7 +4773,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 192] // AXOR My,Gy + (const void *)&gInstructions[ 184] // AXOR My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf = @@ -3893,7 +4916,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_fc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1422] // MOVDIRI My,Gy + (const void *)&gInstructions[ 1412] // MOVDIRI My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf = @@ -3948,7 +4971,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2649] // URDMSR Eq,Gq + (const void *)&gInstructions[ 2633] // URDMSR Eq,Gq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf = @@ -3992,7 +5015,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 907] // ENQCMD rM?,Moq + (const void *)&gInstructions[ 897] // ENQCMD rM?,Moq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf = @@ -4036,7 +5059,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2653] // UWRMSR Gq,Eq + (const void *)&gInstructions[ 2637] // UWRMSR Gq,Eq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf = @@ -4080,7 +5103,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 909] // ENQCMDS rM?,Moq + (const void *)&gInstructions[ 899] // ENQCMDS rM?,Moq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf = @@ -4124,7 +5147,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1420] // MOVDIR64B rMoq,Moq + (const void *)&gInstructions[ 1410] // MOVDIR64B rMoq,Moq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf = @@ -4179,13 +5202,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1084] // IDIV Ev + (const void *)&gInstructions[ 1074] // IDIV Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1081] // IDIV Ev + (const void *)&gInstructions[ 1071] // IDIV Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -4220,13 +5243,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 888] // DIV Ev + (const void *)&gInstructions[ 880] // DIV Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 885] // DIV Ev + (const void *)&gInstructions[ 877] // DIV Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -4261,13 +5284,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1112] // IMUL Ev + (const void *)&gInstructions[ 1102] // IMUL Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1107] // IMUL Ev + (const void *)&gInstructions[ 1097] // IMUL Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -4302,13 +5325,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1486] // MUL Ev + (const void *)&gInstructions[ 1476] // MUL Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1483] // MUL Ev + (const void *)&gInstructions[ 1473] // MUL Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -4343,13 +5366,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1508] // NEG Bv,Ev + (const void *)&gInstructions[ 1498] // NEG Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1505] // NEG Bv,Ev + (const void *)&gInstructions[ 1495] // NEG Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -4364,13 +5387,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1502] // NEG Ev + (const void *)&gInstructions[ 1492] // NEG Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1499] // NEG Ev + (const void *)&gInstructions[ 1489] // NEG Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -4405,7 +5428,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1587] // NOT Bv,Ev + (const void *)&gInstructions[ 1577] // NOT Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -4420,7 +5443,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1584] // NOT Ev + (const void *)&gInstructions[ 1574] // NOT Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -4455,97 +5478,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 770] // CTESTNLE Ev,Iz,dfv + (const void *)&gInstructions[ 762] // CTESTNLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 734] // CTESTLE Ev,Iz,dfv + (const void *)&gInstructions[ 726] // CTESTLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 761] // CTESTNL Ev,Iz,dfv + (const void *)&gInstructions[ 753] // CTESTNL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 725] // CTESTL Ev,Iz,dfv + (const void *)&gInstructions[ 717] // CTESTL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 716] // CTESTF Ev,Iz,dfv + (const void *)&gInstructions[ 708] // CTESTF Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 824] // CTESTT Ev,Iz,dfv + (const void *)&gInstructions[ 816] // CTESTT Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 788] // CTESTNS Ev,Iz,dfv + (const void *)&gInstructions[ 780] // CTESTNS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 815] // CTESTS Ev,Iz,dfv + (const void *)&gInstructions[ 807] // CTESTS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 743] // CTESTNBE Ev,Iz,dfv + (const void *)&gInstructions[ 735] // CTESTNBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 698] // CTESTBE Ev,Iz,dfv + (const void *)&gInstructions[ 690] // CTESTBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 797] // CTESTNZ Ev,Iz,dfv + (const void *)&gInstructions[ 789] // CTESTNZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 833] // CTESTZ Ev,Iz,dfv + (const void *)&gInstructions[ 825] // CTESTZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 752] // CTESTNC Ev,Iz,dfv + (const void *)&gInstructions[ 744] // CTESTNC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 707] // CTESTC Ev,Iz,dfv + (const void *)&gInstructions[ 699] // CTESTC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 779] // CTESTNO Ev,Iz,dfv + (const void *)&gInstructions[ 771] // CTESTNO Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 806] // CTESTO Ev,Iz,dfv + (const void *)&gInstructions[ 798] // CTESTO Ev,Iz,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc = @@ -4594,97 +5617,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 768] // CTESTNLE Ev,Iz,dfv + (const void *)&gInstructions[ 760] // CTESTNLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 732] // CTESTLE Ev,Iz,dfv + (const void *)&gInstructions[ 724] // CTESTLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 759] // CTESTNL Ev,Iz,dfv + (const void *)&gInstructions[ 751] // CTESTNL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 723] // CTESTL Ev,Iz,dfv + (const void *)&gInstructions[ 715] // CTESTL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 714] // CTESTF Ev,Iz,dfv + (const void *)&gInstructions[ 706] // CTESTF Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 822] // CTESTT Ev,Iz,dfv + (const void *)&gInstructions[ 814] // CTESTT Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 786] // CTESTNS Ev,Iz,dfv + (const void *)&gInstructions[ 778] // CTESTNS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 813] // CTESTS Ev,Iz,dfv + (const void *)&gInstructions[ 805] // CTESTS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 741] // CTESTNBE Ev,Iz,dfv + (const void *)&gInstructions[ 733] // CTESTNBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 696] // CTESTBE Ev,Iz,dfv + (const void *)&gInstructions[ 688] // CTESTBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 795] // CTESTNZ Ev,Iz,dfv + (const void *)&gInstructions[ 787] // CTESTNZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 831] // CTESTZ Ev,Iz,dfv + (const void *)&gInstructions[ 823] // CTESTZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 750] // CTESTNC Ev,Iz,dfv + (const void *)&gInstructions[ 742] // CTESTNC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 705] // CTESTC Ev,Iz,dfv + (const void *)&gInstructions[ 697] // CTESTC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 777] // CTESTNO Ev,Iz,dfv + (const void *)&gInstructions[ 769] // CTESTNO Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 804] // CTESTO Ev,Iz,dfv + (const void *)&gInstructions[ 796] // CTESTO Ev,Iz,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc = @@ -4748,13 +5771,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1083] // IDIV Ev + (const void *)&gInstructions[ 1073] // IDIV Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1080] // IDIV Ev + (const void *)&gInstructions[ 1070] // IDIV Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -4789,13 +5812,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 887] // DIV Ev + (const void *)&gInstructions[ 879] // DIV Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 884] // DIV Ev + (const void *)&gInstructions[ 876] // DIV Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -4830,13 +5853,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1111] // IMUL Ev + (const void *)&gInstructions[ 1101] // IMUL Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1106] // IMUL Ev + (const void *)&gInstructions[ 1096] // IMUL Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -4871,13 +5894,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1485] // MUL Ev + (const void *)&gInstructions[ 1475] // MUL Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1482] // MUL Ev + (const void *)&gInstructions[ 1472] // MUL Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -4912,13 +5935,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1507] // NEG Bv,Ev + (const void *)&gInstructions[ 1497] // NEG Bv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1504] // NEG Bv,Ev + (const void *)&gInstructions[ 1494] // NEG Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -4933,13 +5956,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1501] // NEG Ev + (const void *)&gInstructions[ 1491] // NEG Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1498] // NEG Ev + (const void *)&gInstructions[ 1488] // NEG Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -4974,7 +5997,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1586] // NOT Bv,Ev + (const void *)&gInstructions[ 1576] // NOT Bv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -4989,7 +6012,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1583] // NOT Ev + (const void *)&gInstructions[ 1573] // NOT Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -5024,97 +6047,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 769] // CTESTNLE Ev,Iz,dfv + (const void *)&gInstructions[ 761] // CTESTNLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 733] // CTESTLE Ev,Iz,dfv + (const void *)&gInstructions[ 725] // CTESTLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 760] // CTESTNL Ev,Iz,dfv + (const void *)&gInstructions[ 752] // CTESTNL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 724] // CTESTL Ev,Iz,dfv + (const void *)&gInstructions[ 716] // CTESTL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 715] // CTESTF Ev,Iz,dfv + (const void *)&gInstructions[ 707] // CTESTF Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 823] // CTESTT Ev,Iz,dfv + (const void *)&gInstructions[ 815] // CTESTT Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 787] // CTESTNS Ev,Iz,dfv + (const void *)&gInstructions[ 779] // CTESTNS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 814] // CTESTS Ev,Iz,dfv + (const void *)&gInstructions[ 806] // CTESTS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 742] // CTESTNBE Ev,Iz,dfv + (const void *)&gInstructions[ 734] // CTESTNBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 697] // CTESTBE Ev,Iz,dfv + (const void *)&gInstructions[ 689] // CTESTBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 796] // CTESTNZ Ev,Iz,dfv + (const void *)&gInstructions[ 788] // CTESTNZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 832] // CTESTZ Ev,Iz,dfv + (const void *)&gInstructions[ 824] // CTESTZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 751] // CTESTNC Ev,Iz,dfv + (const void *)&gInstructions[ 743] // CTESTNC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 706] // CTESTC Ev,Iz,dfv + (const void *)&gInstructions[ 698] // CTESTC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 778] // CTESTNO Ev,Iz,dfv + (const void *)&gInstructions[ 770] // CTESTNO Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 805] // CTESTO Ev,Iz,dfv + (const void *)&gInstructions[ 797] // CTESTO Ev,Iz,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc = @@ -5163,97 +6186,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 767] // CTESTNLE Ev,Iz,dfv + (const void *)&gInstructions[ 759] // CTESTNLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 731] // CTESTLE Ev,Iz,dfv + (const void *)&gInstructions[ 723] // CTESTLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 758] // CTESTNL Ev,Iz,dfv + (const void *)&gInstructions[ 750] // CTESTNL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 722] // CTESTL Ev,Iz,dfv + (const void *)&gInstructions[ 714] // CTESTL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 713] // CTESTF Ev,Iz,dfv + (const void *)&gInstructions[ 705] // CTESTF Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 821] // CTESTT Ev,Iz,dfv + (const void *)&gInstructions[ 813] // CTESTT Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 785] // CTESTNS Ev,Iz,dfv + (const void *)&gInstructions[ 777] // CTESTNS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 812] // CTESTS Ev,Iz,dfv + (const void *)&gInstructions[ 804] // CTESTS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 740] // CTESTNBE Ev,Iz,dfv + (const void *)&gInstructions[ 732] // CTESTNBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 695] // CTESTBE Ev,Iz,dfv + (const void *)&gInstructions[ 687] // CTESTBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 794] // CTESTNZ Ev,Iz,dfv + (const void *)&gInstructions[ 786] // CTESTNZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 830] // CTESTZ Ev,Iz,dfv + (const void *)&gInstructions[ 822] // CTESTZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 749] // CTESTNC Ev,Iz,dfv + (const void *)&gInstructions[ 741] // CTESTNC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 704] // CTESTC Ev,Iz,dfv + (const void *)&gInstructions[ 696] // CTESTC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 776] // CTESTNO Ev,Iz,dfv + (const void *)&gInstructions[ 768] // CTESTNO Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 803] // CTESTO Ev,Iz,dfv + (const void *)&gInstructions[ 795] // CTESTO Ev,Iz,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc = @@ -5328,13 +6351,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1082] // IDIV Eb + (const void *)&gInstructions[ 1072] // IDIV Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1079] // IDIV Eb + (const void *)&gInstructions[ 1069] // IDIV Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -5369,13 +6392,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 886] // DIV Eb + (const void *)&gInstructions[ 878] // DIV Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 883] // DIV Eb + (const void *)&gInstructions[ 875] // DIV Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -5410,13 +6433,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1110] // IMUL Eb + (const void *)&gInstructions[ 1100] // IMUL Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1105] // IMUL Eb + (const void *)&gInstructions[ 1095] // IMUL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -5451,13 +6474,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1484] // MUL Eb + (const void *)&gInstructions[ 1474] // MUL Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1481] // MUL Eb + (const void *)&gInstructions[ 1471] // MUL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -5492,13 +6515,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1506] // NEG Bb,Eb + (const void *)&gInstructions[ 1496] // NEG Bb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1503] // NEG Bb,Eb + (const void *)&gInstructions[ 1493] // NEG Bb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -5513,13 +6536,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1500] // NEG Eb + (const void *)&gInstructions[ 1490] // NEG Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1497] // NEG Eb + (const void *)&gInstructions[ 1487] // NEG Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -5554,7 +6577,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1585] // NOT Bb,Eb + (const void *)&gInstructions[ 1575] // NOT Bb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -5569,7 +6592,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1582] // NOT Eb + (const void *)&gInstructions[ 1572] // NOT Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -5604,97 +6627,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 766] // CTESTNLE Eb,Ib,dfv + (const void *)&gInstructions[ 758] // CTESTNLE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 730] // CTESTLE Eb,Ib,dfv + (const void *)&gInstructions[ 722] // CTESTLE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 757] // CTESTNL Eb,Ib,dfv + (const void *)&gInstructions[ 749] // CTESTNL Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 721] // CTESTL Eb,Ib,dfv + (const void *)&gInstructions[ 713] // CTESTL Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 712] // CTESTF Eb,Ib,dfv + (const void *)&gInstructions[ 704] // CTESTF Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 820] // CTESTT Eb,Ib,dfv + (const void *)&gInstructions[ 812] // CTESTT Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 784] // CTESTNS Eb,Ib,dfv + (const void *)&gInstructions[ 776] // CTESTNS Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 811] // CTESTS Eb,Ib,dfv + (const void *)&gInstructions[ 803] // CTESTS Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 739] // CTESTNBE Eb,Ib,dfv + (const void *)&gInstructions[ 731] // CTESTNBE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 694] // CTESTBE Eb,Ib,dfv + (const void *)&gInstructions[ 686] // CTESTBE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 793] // CTESTNZ Eb,Ib,dfv + (const void *)&gInstructions[ 785] // CTESTNZ Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 829] // CTESTZ Eb,Ib,dfv + (const void *)&gInstructions[ 821] // CTESTZ Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 748] // CTESTNC Eb,Ib,dfv + (const void *)&gInstructions[ 740] // CTESTNC Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 703] // CTESTC Eb,Ib,dfv + (const void *)&gInstructions[ 695] // CTESTC Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 775] // CTESTNO Eb,Ib,dfv + (const void *)&gInstructions[ 767] // CTESTNO Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 802] // CTESTO Eb,Ib,dfv + (const void *)&gInstructions[ 794] // CTESTO Eb,Ib,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc = @@ -5743,97 +6766,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 765] // CTESTNLE Eb,Ib,dfv + (const void *)&gInstructions[ 757] // CTESTNLE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 729] // CTESTLE Eb,Ib,dfv + (const void *)&gInstructions[ 721] // CTESTLE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 756] // CTESTNL Eb,Ib,dfv + (const void *)&gInstructions[ 748] // CTESTNL Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 720] // CTESTL Eb,Ib,dfv + (const void *)&gInstructions[ 712] // CTESTL Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 711] // CTESTF Eb,Ib,dfv + (const void *)&gInstructions[ 703] // CTESTF Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 819] // CTESTT Eb,Ib,dfv + (const void *)&gInstructions[ 811] // CTESTT Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 783] // CTESTNS Eb,Ib,dfv + (const void *)&gInstructions[ 775] // CTESTNS Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 810] // CTESTS Eb,Ib,dfv + (const void *)&gInstructions[ 802] // CTESTS Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 738] // CTESTNBE Eb,Ib,dfv + (const void *)&gInstructions[ 730] // CTESTNBE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 693] // CTESTBE Eb,Ib,dfv + (const void *)&gInstructions[ 685] // CTESTBE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 792] // CTESTNZ Eb,Ib,dfv + (const void *)&gInstructions[ 784] // CTESTNZ Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 828] // CTESTZ Eb,Ib,dfv + (const void *)&gInstructions[ 820] // CTESTZ Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 747] // CTESTNC Eb,Ib,dfv + (const void *)&gInstructions[ 739] // CTESTNC Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 702] // CTESTC Eb,Ib,dfv + (const void *)&gInstructions[ 694] // CTESTC Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 774] // CTESTNO Eb,Ib,dfv + (const void *)&gInstructions[ 766] // CTESTNO Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 801] // CTESTO Eb,Ib,dfv + (const void *)&gInstructions[ 793] // CTESTO Eb,Ib,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc = @@ -5908,13 +6931,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1351] // LZCNT Gv,Ev + (const void *)&gInstructions[ 1341] // LZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1349] // LZCNT Gv,Ev + (const void *)&gInstructions[ 1339] // LZCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf = @@ -5949,13 +6972,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f5_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1350] // LZCNT Gv,Ev + (const void *)&gInstructions[ 1340] // LZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1348] // LZCNT Gv,Ev + (const void *)&gInstructions[ 1338] // LZCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf = @@ -6001,13 +7024,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2634] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2618] // TZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2632] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2616] // TZCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf = @@ -6042,13 +7065,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f4_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2633] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2617] // TZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2631] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2615] // TZCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf = @@ -6094,7 +7117,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1170] // INVPCID Gy,Mdq + (const void *)&gInstructions[ 1160] // INVPCID Gy,Mdq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf = @@ -6149,7 +7172,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1172] // INVVPID Gy,Mdq + (const void *)&gInstructions[ 1162] // INVVPID Gy,Mdq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf = @@ -6193,7 +7216,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 687] // CRC32 Gy,Ev + (const void *)&gInstructions[ 679] // CRC32 Gy,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf = @@ -6228,7 +7251,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 686] // CRC32 Gy,Ev + (const void *)&gInstructions[ 678] // CRC32 Gy,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf = @@ -6274,7 +7297,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1165] // INVEPT Gy,Mdq + (const void *)&gInstructions[ 1155] // INVEPT Gy,Mdq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf = @@ -6318,7 +7341,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 685] // CRC32 Gy,Eb + (const void *)&gInstructions[ 677] // CRC32 Gy,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf = @@ -6361,815 +7384,16 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f0_pp = } }; -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 109] // AESDEC256KL Vdq,M512 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_df_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 119] // AESENC256KL Vdq,M512 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_de_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 107] // AESDEC128KL Vdq,M384 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2378] // SHA256MSG2 Vdq,Wdq -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dd_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_dd_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 117] // AESENC128KL Vdq,M384 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2376] // SHA256MSG1 Vdq,Wdq -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dc_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_dc_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 903] // ENCODEKEY256 Gd,Rd -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2380] // SHA256RNDS2 Vdq,Wdq -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_db_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_db_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 901] // ENCODEKEY128 Gd,Rd -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)ND_NULL, - /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2370] // SHA1MSG2 Vdq,Wdq -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_da_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_da_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2368] // SHA1MSG1 Vdq,Wdq -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d9_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d9_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 114] // AESDECWIDE256KL M512 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 124] // AESENCWIDE256KL M512 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 112] // AESDECWIDE128KL M384 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 122] // AESENCWIDE128KL M384 -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod, - /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod, - /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod, - /* 04 */ (const void *)ND_NULL, - /* 05 */ (const void *)ND_NULL, - /* 06 */ (const void *)ND_NULL, - /* 07 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2372] // SHA1NEXTE Vdq,Wdq -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d8_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2374] // SHA1RNDS4 Vdq,Wdq,Ib -}; - -const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf = -{ - ND_ILUT_EX_NF, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf_00_leaf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd = -{ - ND_ILUT_EX_ND, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf, - /* 01 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d4_pp_00_l = -{ - ND_ILUT_EX_L, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - -const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d4_pp = -{ - ND_ILUT_EX_PP, - { - /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l, - /* 01 */ (const void *)ND_NULL, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, - } -}; - const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2278] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2269] // SAR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2269] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2260] // SAR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf = @@ -7184,13 +7408,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2260] // SAR Ev,CL + (const void *)&gInstructions[ 2251] // SAR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2251] // SAR Ev,CL + (const void *)&gInstructions[ 2242] // SAR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -7225,13 +7449,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2235] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2226] // SAL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2226] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2217] // SAL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -7246,13 +7470,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2217] // SAL Ev,CL + (const void *)&gInstructions[ 2208] // SAL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2208] // SAL Ev,CL + (const void *)&gInstructions[ 2199] // SAL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -7287,13 +7511,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2479] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2463] // SHR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2470] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2454] // SHR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -7308,13 +7532,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2461] // SHR Ev,CL + (const void *)&gInstructions[ 2445] // SHR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2452] // SHR Ev,CL + (const void *)&gInstructions[ 2436] // SHR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -7349,13 +7573,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2417] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2401] // SHL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2408] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2392] // SHL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -7370,13 +7594,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2399] // SHL Ev,CL + (const void *)&gInstructions[ 2383] // SHL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2390] // SHL Ev,CL + (const void *)&gInstructions[ 2374] // SHL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -7411,13 +7635,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2075] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2065] // RCR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2066] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2056] // RCR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -7432,13 +7656,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2057] // RCR Ev,CL + (const void *)&gInstructions[ 2047] // RCR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2048] // RCR Ev,CL + (const void *)&gInstructions[ 2038] // RCR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -7473,13 +7697,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2031] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2021] // RCL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2022] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2012] // RCL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -7494,13 +7718,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2013] // RCL Ev,CL + (const void *)&gInstructions[ 2003] // RCL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2004] // RCL Ev,CL + (const void *)&gInstructions[ 1994] // RCL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -7535,13 +7759,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2182] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2173] // ROR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2173] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2164] // ROR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -7556,13 +7780,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2164] // ROR Ev,CL + (const void *)&gInstructions[ 2155] // ROR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2155] // ROR Ev,CL + (const void *)&gInstructions[ 2146] // ROR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -7597,13 +7821,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2140] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2131] // ROL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2131] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2122] // ROL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -7618,13 +7842,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2122] // ROL Ev,CL + (const void *)&gInstructions[ 2113] // ROL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2113] // ROL Ev,CL + (const void *)&gInstructions[ 2104] // ROL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -7674,13 +7898,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2277] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2268] // SAR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2268] // SAR Bv,Ev,CL + (const void *)&gInstructions[ 2259] // SAR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -7695,13 +7919,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2259] // SAR Ev,CL + (const void *)&gInstructions[ 2250] // SAR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2250] // SAR Ev,CL + (const void *)&gInstructions[ 2241] // SAR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -7736,13 +7960,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2234] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2225] // SAL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2225] // SAL Bv,Ev,CL + (const void *)&gInstructions[ 2216] // SAL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -7757,13 +7981,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2216] // SAL Ev,CL + (const void *)&gInstructions[ 2207] // SAL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2207] // SAL Ev,CL + (const void *)&gInstructions[ 2198] // SAL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -7798,13 +8022,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2478] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2462] // SHR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2469] // SHR Bv,Ev,CL + (const void *)&gInstructions[ 2453] // SHR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -7819,13 +8043,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2460] // SHR Ev,CL + (const void *)&gInstructions[ 2444] // SHR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2451] // SHR Ev,CL + (const void *)&gInstructions[ 2435] // SHR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -7860,13 +8084,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2416] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2400] // SHL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2407] // SHL Bv,Ev,CL + (const void *)&gInstructions[ 2391] // SHL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -7881,13 +8105,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2398] // SHL Ev,CL + (const void *)&gInstructions[ 2382] // SHL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2389] // SHL Ev,CL + (const void *)&gInstructions[ 2373] // SHL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -7922,13 +8146,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2074] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2064] // RCR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2065] // RCR Bv,Ev,CL + (const void *)&gInstructions[ 2055] // RCR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -7943,13 +8167,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2056] // RCR Ev,CL + (const void *)&gInstructions[ 2046] // RCR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2047] // RCR Ev,CL + (const void *)&gInstructions[ 2037] // RCR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -7984,13 +8208,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2030] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2020] // RCL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2021] // RCL Bv,Ev,CL + (const void *)&gInstructions[ 2011] // RCL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -8005,13 +8229,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2012] // RCL Ev,CL + (const void *)&gInstructions[ 2002] // RCL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2003] // RCL Ev,CL + (const void *)&gInstructions[ 1993] // RCL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -8046,13 +8270,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2181] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2172] // ROR Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2172] // ROR Bv,Ev,CL + (const void *)&gInstructions[ 2163] // ROR Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -8067,13 +8291,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2163] // ROR Ev,CL + (const void *)&gInstructions[ 2154] // ROR Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2154] // ROR Ev,CL + (const void *)&gInstructions[ 2145] // ROR Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -8108,13 +8332,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2139] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2130] // ROL Bv,Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2130] // ROL Bv,Ev,CL + (const void *)&gInstructions[ 2121] // ROL Bv,Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -8129,13 +8353,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2121] // ROL Ev,CL + (const void *)&gInstructions[ 2112] // ROL Ev,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2112] // ROL Ev,CL + (const void *)&gInstructions[ 2103] // ROL Ev,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -8196,13 +8420,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2276] // SAR Bb,Eb,CL + (const void *)&gInstructions[ 2267] // SAR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2267] // SAR Bb,Eb,CL + (const void *)&gInstructions[ 2258] // SAR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -8217,13 +8441,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2258] // SAR Eb,CL + (const void *)&gInstructions[ 2249] // SAR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2249] // SAR Eb,CL + (const void *)&gInstructions[ 2240] // SAR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -8258,13 +8482,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2233] // SAL Bb,Eb,CL + (const void *)&gInstructions[ 2224] // SAL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2224] // SAL Bb,Eb,CL + (const void *)&gInstructions[ 2215] // SAL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -8279,13 +8503,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2215] // SAL Eb,CL + (const void *)&gInstructions[ 2206] // SAL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2206] // SAL Eb,CL + (const void *)&gInstructions[ 2197] // SAL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -8320,13 +8544,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2477] // SHR Bb,Eb,CL + (const void *)&gInstructions[ 2461] // SHR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2468] // SHR Bb,Eb,CL + (const void *)&gInstructions[ 2452] // SHR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -8341,13 +8565,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2459] // SHR Eb,CL + (const void *)&gInstructions[ 2443] // SHR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2450] // SHR Eb,CL + (const void *)&gInstructions[ 2434] // SHR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -8382,13 +8606,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2415] // SHL Bb,Eb,CL + (const void *)&gInstructions[ 2399] // SHL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2406] // SHL Bb,Eb,CL + (const void *)&gInstructions[ 2390] // SHL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -8403,13 +8627,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2397] // SHL Eb,CL + (const void *)&gInstructions[ 2381] // SHL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2388] // SHL Eb,CL + (const void *)&gInstructions[ 2372] // SHL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -8444,13 +8668,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2073] // RCR Bb,Eb,CL + (const void *)&gInstructions[ 2063] // RCR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2064] // RCR Bb,Eb,CL + (const void *)&gInstructions[ 2054] // RCR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -8465,13 +8689,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2055] // RCR Eb,CL + (const void *)&gInstructions[ 2045] // RCR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2046] // RCR Eb,CL + (const void *)&gInstructions[ 2036] // RCR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -8506,13 +8730,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2029] // RCL Bb,Eb,CL + (const void *)&gInstructions[ 2019] // RCL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2020] // RCL Bb,Eb,CL + (const void *)&gInstructions[ 2010] // RCL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -8527,13 +8751,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2011] // RCL Eb,CL + (const void *)&gInstructions[ 2001] // RCL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2002] // RCL Eb,CL + (const void *)&gInstructions[ 1992] // RCL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -8568,13 +8792,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2180] // ROR Bb,Eb,CL + (const void *)&gInstructions[ 2171] // ROR Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2171] // ROR Bb,Eb,CL + (const void *)&gInstructions[ 2162] // ROR Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -8589,13 +8813,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2162] // ROR Eb,CL + (const void *)&gInstructions[ 2153] // ROR Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2153] // ROR Eb,CL + (const void *)&gInstructions[ 2144] // ROR Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -8630,13 +8854,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2138] // ROL Bb,Eb,CL + (const void *)&gInstructions[ 2129] // ROL Bb,Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2129] // ROL Bb,Eb,CL + (const void *)&gInstructions[ 2120] // ROL Bb,Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -8651,13 +8875,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2120] // ROL Eb,CL + (const void *)&gInstructions[ 2111] // ROL Eb,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2111] // ROL Eb,CL + (const void *)&gInstructions[ 2102] // ROL Eb,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -8718,13 +8942,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2275] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2266] // SAR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2266] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2257] // SAR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf = @@ -8739,13 +8963,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2257] // SAR Ev,1 + (const void *)&gInstructions[ 2248] // SAR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2248] // SAR Ev,1 + (const void *)&gInstructions[ 2239] // SAR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -8780,13 +9004,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2232] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2223] // SAL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2223] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2214] // SAL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -8801,13 +9025,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2214] // SAL Ev,1 + (const void *)&gInstructions[ 2205] // SAL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2205] // SAL Ev,1 + (const void *)&gInstructions[ 2196] // SAL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -8842,13 +9066,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2476] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2460] // SHR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2467] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2451] // SHR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -8863,13 +9087,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2458] // SHR Ev,1 + (const void *)&gInstructions[ 2442] // SHR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2449] // SHR Ev,1 + (const void *)&gInstructions[ 2433] // SHR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -8904,13 +9128,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2414] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2398] // SHL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2405] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2389] // SHL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -8925,13 +9149,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2396] // SHL Ev,1 + (const void *)&gInstructions[ 2380] // SHL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2387] // SHL Ev,1 + (const void *)&gInstructions[ 2371] // SHL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -8966,13 +9190,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2072] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2062] // RCR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2063] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2053] // RCR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -8987,13 +9211,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2054] // RCR Ev,1 + (const void *)&gInstructions[ 2044] // RCR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2045] // RCR Ev,1 + (const void *)&gInstructions[ 2035] // RCR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -9028,13 +9252,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2028] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2018] // RCL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2019] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2009] // RCL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -9049,13 +9273,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2010] // RCL Ev,1 + (const void *)&gInstructions[ 2000] // RCL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2001] // RCL Ev,1 + (const void *)&gInstructions[ 1991] // RCL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -9090,13 +9314,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2179] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2170] // ROR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2170] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2161] // ROR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -9111,13 +9335,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2161] // ROR Ev,1 + (const void *)&gInstructions[ 2152] // ROR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2152] // ROR Ev,1 + (const void *)&gInstructions[ 2143] // ROR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -9152,13 +9376,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2137] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2128] // ROL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2128] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2119] // ROL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -9173,13 +9397,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2119] // ROL Ev,1 + (const void *)&gInstructions[ 2110] // ROL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2110] // ROL Ev,1 + (const void *)&gInstructions[ 2101] // ROL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -9229,13 +9453,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2274] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2265] // SAR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2265] // SAR Bv,Ev,1 + (const void *)&gInstructions[ 2256] // SAR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -9250,13 +9474,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2256] // SAR Ev,1 + (const void *)&gInstructions[ 2247] // SAR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2247] // SAR Ev,1 + (const void *)&gInstructions[ 2238] // SAR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -9291,13 +9515,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2231] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2222] // SAL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2222] // SAL Bv,Ev,1 + (const void *)&gInstructions[ 2213] // SAL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -9312,13 +9536,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2213] // SAL Ev,1 + (const void *)&gInstructions[ 2204] // SAL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2204] // SAL Ev,1 + (const void *)&gInstructions[ 2195] // SAL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -9353,13 +9577,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2475] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2459] // SHR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2466] // SHR Bv,Ev,1 + (const void *)&gInstructions[ 2450] // SHR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -9374,13 +9598,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2457] // SHR Ev,1 + (const void *)&gInstructions[ 2441] // SHR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2448] // SHR Ev,1 + (const void *)&gInstructions[ 2432] // SHR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -9415,13 +9639,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2413] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2397] // SHL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2404] // SHL Bv,Ev,1 + (const void *)&gInstructions[ 2388] // SHL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -9436,13 +9660,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2395] // SHL Ev,1 + (const void *)&gInstructions[ 2379] // SHL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2386] // SHL Ev,1 + (const void *)&gInstructions[ 2370] // SHL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -9477,13 +9701,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2071] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2061] // RCR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2062] // RCR Bv,Ev,1 + (const void *)&gInstructions[ 2052] // RCR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -9498,13 +9722,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2053] // RCR Ev,1 + (const void *)&gInstructions[ 2043] // RCR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2044] // RCR Ev,1 + (const void *)&gInstructions[ 2034] // RCR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -9539,13 +9763,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2027] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2017] // RCL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2018] // RCL Bv,Ev,1 + (const void *)&gInstructions[ 2008] // RCL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -9560,13 +9784,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2009] // RCL Ev,1 + (const void *)&gInstructions[ 1999] // RCL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2000] // RCL Ev,1 + (const void *)&gInstructions[ 1990] // RCL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -9601,13 +9825,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2178] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2169] // ROR Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2169] // ROR Bv,Ev,1 + (const void *)&gInstructions[ 2160] // ROR Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -9622,13 +9846,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2160] // ROR Ev,1 + (const void *)&gInstructions[ 2151] // ROR Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2151] // ROR Ev,1 + (const void *)&gInstructions[ 2142] // ROR Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -9663,13 +9887,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2136] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2127] // ROL Bv,Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2127] // ROL Bv,Ev,1 + (const void *)&gInstructions[ 2118] // ROL Bv,Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -9684,13 +9908,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2118] // ROL Ev,1 + (const void *)&gInstructions[ 2109] // ROL Ev,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2109] // ROL Ev,1 + (const void *)&gInstructions[ 2100] // ROL Ev,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -9751,13 +9975,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2273] // SAR Bb,Eb,1 + (const void *)&gInstructions[ 2264] // SAR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2264] // SAR Bb,Eb,1 + (const void *)&gInstructions[ 2255] // SAR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -9772,13 +9996,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2255] // SAR Eb,1 + (const void *)&gInstructions[ 2246] // SAR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2246] // SAR Eb,1 + (const void *)&gInstructions[ 2237] // SAR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -9813,13 +10037,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2230] // SAL Bb,Eb,1 + (const void *)&gInstructions[ 2221] // SAL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2221] // SAL Bb,Eb,1 + (const void *)&gInstructions[ 2212] // SAL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -9834,13 +10058,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2212] // SAL Eb,1 + (const void *)&gInstructions[ 2203] // SAL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2203] // SAL Eb,1 + (const void *)&gInstructions[ 2194] // SAL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -9875,13 +10099,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2474] // SHR Bb,Eb,1 + (const void *)&gInstructions[ 2458] // SHR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2465] // SHR Bb,Eb,1 + (const void *)&gInstructions[ 2449] // SHR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -9896,13 +10120,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2456] // SHR Eb,1 + (const void *)&gInstructions[ 2440] // SHR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2447] // SHR Eb,1 + (const void *)&gInstructions[ 2431] // SHR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -9937,13 +10161,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2412] // SHL Bb,Eb,1 + (const void *)&gInstructions[ 2396] // SHL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2403] // SHL Bb,Eb,1 + (const void *)&gInstructions[ 2387] // SHL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -9958,13 +10182,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2394] // SHL Eb,1 + (const void *)&gInstructions[ 2378] // SHL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2385] // SHL Eb,1 + (const void *)&gInstructions[ 2369] // SHL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -9999,13 +10223,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2070] // RCR Bb,Eb,1 + (const void *)&gInstructions[ 2060] // RCR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2061] // RCR Bb,Eb,1 + (const void *)&gInstructions[ 2051] // RCR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -10020,13 +10244,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2052] // RCR Eb,1 + (const void *)&gInstructions[ 2042] // RCR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2043] // RCR Eb,1 + (const void *)&gInstructions[ 2033] // RCR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -10061,13 +10285,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2026] // RCL Bb,Eb,1 + (const void *)&gInstructions[ 2016] // RCL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2017] // RCL Bb,Eb,1 + (const void *)&gInstructions[ 2007] // RCL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -10082,13 +10306,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2008] // RCL Eb,1 + (const void *)&gInstructions[ 1998] // RCL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1999] // RCL Eb,1 + (const void *)&gInstructions[ 1989] // RCL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -10123,13 +10347,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2177] // ROR Bb,Eb,1 + (const void *)&gInstructions[ 2168] // ROR Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2168] // ROR Bb,Eb,1 + (const void *)&gInstructions[ 2159] // ROR Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -10144,13 +10368,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2159] // ROR Eb,1 + (const void *)&gInstructions[ 2150] // ROR Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2150] // ROR Eb,1 + (const void *)&gInstructions[ 2141] // ROR Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -10185,13 +10409,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2135] // ROL Bb,Eb,1 + (const void *)&gInstructions[ 2126] // ROL Bb,Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2126] // ROL Bb,Eb,1 + (const void *)&gInstructions[ 2117] // ROL Bb,Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -10206,13 +10430,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2117] // ROL Eb,1 + (const void *)&gInstructions[ 2108] // ROL Eb,1 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2108] // ROL Eb,1 + (const void *)&gInstructions[ 2099] // ROL Eb,1 }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -10273,13 +10497,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2272] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2263] // SAR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2263] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2254] // SAR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf = @@ -10294,13 +10518,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2254] // SAR Ev,Ib + (const void *)&gInstructions[ 2245] // SAR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2245] // SAR Ev,Ib + (const void *)&gInstructions[ 2236] // SAR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf = @@ -10335,13 +10559,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2229] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2220] // SAL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2220] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2211] // SAL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -10356,13 +10580,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2211] // SAL Ev,Ib + (const void *)&gInstructions[ 2202] // SAL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2202] // SAL Ev,Ib + (const void *)&gInstructions[ 2193] // SAL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -10397,13 +10621,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2473] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2457] // SHR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2464] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2448] // SHR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -10418,13 +10642,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2455] // SHR Ev,Ib + (const void *)&gInstructions[ 2439] // SHR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2446] // SHR Ev,Ib + (const void *)&gInstructions[ 2430] // SHR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -10459,13 +10683,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2411] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2395] // SHL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2402] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2386] // SHL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -10480,13 +10704,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2393] // SHL Ev,Ib + (const void *)&gInstructions[ 2377] // SHL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2384] // SHL Ev,Ib + (const void *)&gInstructions[ 2368] // SHL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -10521,13 +10745,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2069] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2059] // RCR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2060] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2050] // RCR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -10542,13 +10766,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2051] // RCR Ev,Ib + (const void *)&gInstructions[ 2041] // RCR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2042] // RCR Ev,Ib + (const void *)&gInstructions[ 2032] // RCR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -10583,13 +10807,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2025] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2015] // RCL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2016] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2006] // RCL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf = @@ -10604,13 +10828,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2007] // RCL Ev,Ib + (const void *)&gInstructions[ 1997] // RCL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1998] // RCL Ev,Ib + (const void *)&gInstructions[ 1988] // RCL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf = @@ -10645,13 +10869,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2176] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2167] // ROR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2167] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2158] // ROR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -10666,13 +10890,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2158] // ROR Ev,Ib + (const void *)&gInstructions[ 2149] // ROR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2149] // ROR Ev,Ib + (const void *)&gInstructions[ 2140] // ROR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -10707,13 +10931,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2134] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2125] // ROL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2125] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2116] // ROL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf = @@ -10728,13 +10952,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2116] // ROL Ev,Ib + (const void *)&gInstructions[ 2107] // ROL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2107] // ROL Ev,Ib + (const void *)&gInstructions[ 2098] // ROL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf = @@ -10784,13 +11008,13 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2271] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2262] // SAR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2262] // SAR Bv,Ev,Ib + (const void *)&gInstructions[ 2253] // SAR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -10805,13 +11029,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2253] // SAR Ev,Ib + (const void *)&gInstructions[ 2244] // SAR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2244] // SAR Ev,Ib + (const void *)&gInstructions[ 2235] // SAR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -10846,13 +11070,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2228] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2219] // SAL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2219] // SAL Bv,Ev,Ib + (const void *)&gInstructions[ 2210] // SAL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -10867,13 +11091,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2210] // SAL Ev,Ib + (const void *)&gInstructions[ 2201] // SAL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2201] // SAL Ev,Ib + (const void *)&gInstructions[ 2192] // SAL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -10908,13 +11132,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2472] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2456] // SHR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2463] // SHR Bv,Ev,Ib + (const void *)&gInstructions[ 2447] // SHR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -10929,13 +11153,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2454] // SHR Ev,Ib + (const void *)&gInstructions[ 2438] // SHR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2445] // SHR Ev,Ib + (const void *)&gInstructions[ 2429] // SHR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -10970,13 +11194,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2410] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2394] // SHL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2401] // SHL Bv,Ev,Ib + (const void *)&gInstructions[ 2385] // SHL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -10991,13 +11215,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2392] // SHL Ev,Ib + (const void *)&gInstructions[ 2376] // SHL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2383] // SHL Ev,Ib + (const void *)&gInstructions[ 2367] // SHL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -11032,13 +11256,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2068] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2058] // RCR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2059] // RCR Bv,Ev,Ib + (const void *)&gInstructions[ 2049] // RCR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -11053,13 +11277,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2050] // RCR Ev,Ib + (const void *)&gInstructions[ 2040] // RCR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2041] // RCR Ev,Ib + (const void *)&gInstructions[ 2031] // RCR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -11094,13 +11318,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2024] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2014] // RCL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2015] // RCL Bv,Ev,Ib + (const void *)&gInstructions[ 2005] // RCL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -11115,13 +11339,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2006] // RCL Ev,Ib + (const void *)&gInstructions[ 1996] // RCL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1997] // RCL Ev,Ib + (const void *)&gInstructions[ 1987] // RCL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -11156,13 +11380,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2175] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2166] // ROR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2166] // ROR Bv,Ev,Ib + (const void *)&gInstructions[ 2157] // ROR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -11177,13 +11401,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2157] // ROR Ev,Ib + (const void *)&gInstructions[ 2148] // ROR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2148] // ROR Ev,Ib + (const void *)&gInstructions[ 2139] // ROR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -11218,13 +11442,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2133] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2124] // ROL Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2124] // ROL Bv,Ev,Ib + (const void *)&gInstructions[ 2115] // ROL Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -11239,13 +11463,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2115] // ROL Ev,Ib + (const void *)&gInstructions[ 2106] // ROL Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2106] // ROL Ev,Ib + (const void *)&gInstructions[ 2097] // ROL Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -11306,13 +11530,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2270] // SAR Bb,Eb,Ib + (const void *)&gInstructions[ 2261] // SAR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2261] // SAR Bb,Eb,Ib + (const void *)&gInstructions[ 2252] // SAR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf = @@ -11327,13 +11551,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2252] // SAR Eb,Ib + (const void *)&gInstructions[ 2243] // SAR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2243] // SAR Eb,Ib + (const void *)&gInstructions[ 2234] // SAR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf = @@ -11368,13 +11592,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2227] // SAL Bb,Eb,Ib + (const void *)&gInstructions[ 2218] // SAL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2218] // SAL Bb,Eb,Ib + (const void *)&gInstructions[ 2209] // SAL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -11389,13 +11613,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2209] // SAL Eb,Ib + (const void *)&gInstructions[ 2200] // SAL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2200] // SAL Eb,Ib + (const void *)&gInstructions[ 2191] // SAL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -11430,13 +11654,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2471] // SHR Bb,Eb,Ib + (const void *)&gInstructions[ 2455] // SHR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2462] // SHR Bb,Eb,Ib + (const void *)&gInstructions[ 2446] // SHR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -11451,13 +11675,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2453] // SHR Eb,Ib + (const void *)&gInstructions[ 2437] // SHR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2444] // SHR Eb,Ib + (const void *)&gInstructions[ 2428] // SHR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -11492,13 +11716,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2409] // SHL Bb,Eb,Ib + (const void *)&gInstructions[ 2393] // SHL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2400] // SHL Bb,Eb,Ib + (const void *)&gInstructions[ 2384] // SHL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -11513,13 +11737,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2391] // SHL Eb,Ib + (const void *)&gInstructions[ 2375] // SHL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2382] // SHL Eb,Ib + (const void *)&gInstructions[ 2366] // SHL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -11554,13 +11778,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2067] // RCR Bb,Eb,Ib + (const void *)&gInstructions[ 2057] // RCR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2058] // RCR Bb,Eb,Ib + (const void *)&gInstructions[ 2048] // RCR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -11575,13 +11799,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2049] // RCR Eb,Ib + (const void *)&gInstructions[ 2039] // RCR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2040] // RCR Eb,Ib + (const void *)&gInstructions[ 2030] // RCR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -11616,13 +11840,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2023] // RCL Bb,Eb,Ib + (const void *)&gInstructions[ 2013] // RCL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2014] // RCL Bb,Eb,Ib + (const void *)&gInstructions[ 2004] // RCL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf = @@ -11637,13 +11861,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2005] // RCL Eb,Ib + (const void *)&gInstructions[ 1995] // RCL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1996] // RCL Eb,Ib + (const void *)&gInstructions[ 1986] // RCL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf = @@ -11678,13 +11902,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2174] // ROR Bb,Eb,Ib + (const void *)&gInstructions[ 2165] // ROR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2165] // ROR Bb,Eb,Ib + (const void *)&gInstructions[ 2156] // ROR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -11699,13 +11923,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2156] // ROR Eb,Ib + (const void *)&gInstructions[ 2147] // ROR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2147] // ROR Eb,Ib + (const void *)&gInstructions[ 2138] // ROR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -11740,13 +11964,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2132] // ROL Bb,Eb,Ib + (const void *)&gInstructions[ 2123] // ROL Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2123] // ROL Bb,Eb,Ib + (const void *)&gInstructions[ 2114] // ROL Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf = @@ -11761,13 +11985,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2114] // ROL Eb,Ib + (const void *)&gInstructions[ 2105] // ROL Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2105] // ROL Eb,Ib + (const void *)&gInstructions[ 2096] // ROL Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf = @@ -11828,13 +12052,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1116] // IMUL Bv,Gv,Ev + (const void *)&gInstructions[ 1106] // IMUL Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1114] // IMUL Bv,Gv,Ev + (const void *)&gInstructions[ 1104] // IMUL Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf = @@ -11849,13 +12073,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1109] // IMUL Gv,Ev + (const void *)&gInstructions[ 1099] // IMUL Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1104] // IMUL Gv,Ev + (const void *)&gInstructions[ 1094] // IMUL Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf = @@ -11890,13 +12114,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_af_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1115] // IMUL Bv,Gv,Ev + (const void *)&gInstructions[ 1105] // IMUL Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1113] // IMUL Bv,Gv,Ev + (const void *)&gInstructions[ 1103] // IMUL Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf = @@ -11911,13 +12135,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1108] // IMUL Gv,Ev + (const void *)&gInstructions[ 1098] // IMUL Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1103] // IMUL Gv,Ev + (const void *)&gInstructions[ 1093] // IMUL Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf = @@ -11963,13 +12187,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_af_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2501] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2485] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2497] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2481] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf = @@ -11984,13 +12208,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2493] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2477] // SHRD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2489] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2473] // SHRD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf = @@ -12025,13 +12249,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ad_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2499] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2483] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2495] // SHRD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2479] // SHRD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf = @@ -12046,13 +12270,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2491] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2475] // SHRD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2487] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2471] // SHRD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf = @@ -12098,13 +12322,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ad_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2439] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2423] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2435] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2419] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf = @@ -12119,13 +12343,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2431] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2415] // SHLD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2427] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2411] // SHLD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf = @@ -12160,13 +12384,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_a5_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2437] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2421] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2433] // SHLD Bv,Ev,Gv,CL + (const void *)&gInstructions[ 2417] // SHLD Bv,Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf = @@ -12181,13 +12405,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2429] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2413] // SHLD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2425] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2409] // SHLD Ev,Gv,CL }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf = @@ -12233,7 +12457,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_a5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1840] // POP2P Bv,Rv + (const void *)&gInstructions[ 1830] // POP2P Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf = @@ -12257,7 +12481,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1839] // POP2 Bv,Rv + (const void *)&gInstructions[ 1829] // POP2 Bv,Rv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf = @@ -12336,13 +12560,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_8f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1846] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1836] // POPCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1844] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1834] // POPCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf = @@ -12377,13 +12601,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_88_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1845] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1835] // POPCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1843] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1833] // POPCNT Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf = @@ -12429,97 +12653,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_88_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 764] // CTESTNLE Ev,Gv,dfv + (const void *)&gInstructions[ 756] // CTESTNLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 728] // CTESTLE Ev,Gv,dfv + (const void *)&gInstructions[ 720] // CTESTLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 755] // CTESTNL Ev,Gv,dfv + (const void *)&gInstructions[ 747] // CTESTNL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 719] // CTESTL Ev,Gv,dfv + (const void *)&gInstructions[ 711] // CTESTL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 710] // CTESTF Ev,Gv,dfv + (const void *)&gInstructions[ 702] // CTESTF Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 818] // CTESTT Ev,Gv,dfv + (const void *)&gInstructions[ 810] // CTESTT Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 782] // CTESTNS Ev,Gv,dfv + (const void *)&gInstructions[ 774] // CTESTNS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 809] // CTESTS Ev,Gv,dfv + (const void *)&gInstructions[ 801] // CTESTS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 737] // CTESTNBE Ev,Gv,dfv + (const void *)&gInstructions[ 729] // CTESTNBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 692] // CTESTBE Ev,Gv,dfv + (const void *)&gInstructions[ 684] // CTESTBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 791] // CTESTNZ Ev,Gv,dfv + (const void *)&gInstructions[ 783] // CTESTNZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 827] // CTESTZ Ev,Gv,dfv + (const void *)&gInstructions[ 819] // CTESTZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 746] // CTESTNC Ev,Gv,dfv + (const void *)&gInstructions[ 738] // CTESTNC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 701] // CTESTC Ev,Gv,dfv + (const void *)&gInstructions[ 693] // CTESTC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 773] // CTESTNO Ev,Gv,dfv + (const void *)&gInstructions[ 765] // CTESTNO Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 800] // CTESTO Ev,Gv,dfv + (const void *)&gInstructions[ 792] // CTESTO Ev,Gv,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc = @@ -12568,97 +12792,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_85_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 763] // CTESTNLE Ev,Gv,dfv + (const void *)&gInstructions[ 755] // CTESTNLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 727] // CTESTLE Ev,Gv,dfv + (const void *)&gInstructions[ 719] // CTESTLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 754] // CTESTNL Ev,Gv,dfv + (const void *)&gInstructions[ 746] // CTESTNL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 718] // CTESTL Ev,Gv,dfv + (const void *)&gInstructions[ 710] // CTESTL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 709] // CTESTF Ev,Gv,dfv + (const void *)&gInstructions[ 701] // CTESTF Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 817] // CTESTT Ev,Gv,dfv + (const void *)&gInstructions[ 809] // CTESTT Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 781] // CTESTNS Ev,Gv,dfv + (const void *)&gInstructions[ 773] // CTESTNS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 808] // CTESTS Ev,Gv,dfv + (const void *)&gInstructions[ 800] // CTESTS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 736] // CTESTNBE Ev,Gv,dfv + (const void *)&gInstructions[ 728] // CTESTNBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 691] // CTESTBE Ev,Gv,dfv + (const void *)&gInstructions[ 683] // CTESTBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 790] // CTESTNZ Ev,Gv,dfv + (const void *)&gInstructions[ 782] // CTESTNZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 826] // CTESTZ Ev,Gv,dfv + (const void *)&gInstructions[ 818] // CTESTZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 745] // CTESTNC Ev,Gv,dfv + (const void *)&gInstructions[ 737] // CTESTNC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 700] // CTESTC Ev,Gv,dfv + (const void *)&gInstructions[ 692] // CTESTC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 772] // CTESTNO Ev,Gv,dfv + (const void *)&gInstructions[ 764] // CTESTNO Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 799] // CTESTO Ev,Gv,dfv + (const void *)&gInstructions[ 791] // CTESTO Ev,Gv,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc = @@ -12718,97 +12942,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_85_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 762] // CTESTNLE Eb,Gb,dfv + (const void *)&gInstructions[ 754] // CTESTNLE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 726] // CTESTLE Eb,Gb,dfv + (const void *)&gInstructions[ 718] // CTESTLE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 753] // CTESTNL Eb,Gb,dfv + (const void *)&gInstructions[ 745] // CTESTNL Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 717] // CTESTL Eb,Gb,dfv + (const void *)&gInstructions[ 709] // CTESTL Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 708] // CTESTF Eb,Gb,dfv + (const void *)&gInstructions[ 700] // CTESTF Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 816] // CTESTT Eb,Gb,dfv + (const void *)&gInstructions[ 808] // CTESTT Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 780] // CTESTNS Eb,Gb,dfv + (const void *)&gInstructions[ 772] // CTESTNS Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 807] // CTESTS Eb,Gb,dfv + (const void *)&gInstructions[ 799] // CTESTS Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 735] // CTESTNBE Eb,Gb,dfv + (const void *)&gInstructions[ 727] // CTESTNBE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 690] // CTESTBE Eb,Gb,dfv + (const void *)&gInstructions[ 682] // CTESTBE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 789] // CTESTNZ Eb,Gb,dfv + (const void *)&gInstructions[ 781] // CTESTNZ Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 825] // CTESTZ Eb,Gb,dfv + (const void *)&gInstructions[ 817] // CTESTZ Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 744] // CTESTNC Eb,Gb,dfv + (const void *)&gInstructions[ 736] // CTESTNC Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 699] // CTESTC Eb,Gb,dfv + (const void *)&gInstructions[ 691] // CTESTC Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 771] // CTESTNO Eb,Gb,dfv + (const void *)&gInstructions[ 763] // CTESTNO Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 798] // CTESTO Eb,Gb,dfv + (const void *)&gInstructions[ 790] // CTESTO Eb,Gb,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc = @@ -12868,97 +13092,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_84_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 351] // CCMPNLE Ev,Ib,dfv + (const void *)&gInstructions[ 343] // CCMPNLE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 307] // CCMPLE Ev,Ib,dfv + (const void *)&gInstructions[ 299] // CCMPLE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 340] // CCMPNL Ev,Ib,dfv + (const void *)&gInstructions[ 332] // CCMPNL Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 296] // CCMPL Ev,Ib,dfv + (const void *)&gInstructions[ 288] // CCMPL Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 285] // CCMPF Ev,Ib,dfv + (const void *)&gInstructions[ 277] // CCMPF Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 417] // CCMPT Ev,Ib,dfv + (const void *)&gInstructions[ 409] // CCMPT Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 373] // CCMPNS Ev,Ib,dfv + (const void *)&gInstructions[ 365] // CCMPNS Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 406] // CCMPS Ev,Ib,dfv + (const void *)&gInstructions[ 398] // CCMPS Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 318] // CCMPNBE Ev,Ib,dfv + (const void *)&gInstructions[ 310] // CCMPNBE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 263] // CCMPBE Ev,Ib,dfv + (const void *)&gInstructions[ 255] // CCMPBE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 384] // CCMPNZ Ev,Ib,dfv + (const void *)&gInstructions[ 376] // CCMPNZ Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 428] // CCMPZ Ev,Ib,dfv + (const void *)&gInstructions[ 420] // CCMPZ Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 329] // CCMPNC Ev,Ib,dfv + (const void *)&gInstructions[ 321] // CCMPNC Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 274] // CCMPC Ev,Ib,dfv + (const void *)&gInstructions[ 266] // CCMPC Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 362] // CCMPNO Ev,Ib,dfv + (const void *)&gInstructions[ 354] // CCMPNO Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 395] // CCMPO Ev,Ib,dfv + (const void *)&gInstructions[ 387] // CCMPO Ev,Ib,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc = @@ -13007,13 +13231,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4046] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4128] // XOR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4035] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4117] // XOR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -13028,13 +13252,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4024] // XOR Ev,Ib + (const void *)&gInstructions[ 4106] // XOR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4013] // XOR Ev,Ib + (const void *)&gInstructions[ 4095] // XOR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -13069,13 +13293,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2582] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2566] // SUB Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2571] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2555] // SUB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -13090,13 +13314,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2560] // SUB Ev,Ib + (const void *)&gInstructions[ 2544] // SUB Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2549] // SUB Ev,Ib + (const void *)&gInstructions[ 2533] // SUB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -13131,13 +13355,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 171] // AND Bv,Ev,Ib + (const void *)&gInstructions[ 163] // AND Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 160] // AND Bv,Ev,Ib + (const void *)&gInstructions[ 152] // AND Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -13152,13 +13376,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 149] // AND Ev,Ib + (const void *)&gInstructions[ 141] // AND Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 138] // AND Ev,Ib + (const void *)&gInstructions[ 130] // AND Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -13193,7 +13417,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2309] // SBB Bv,Ev,Ib + (const void *)&gInstructions[ 2300] // SBB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -13208,7 +13432,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2298] // SBB Ev,Ib + (const void *)&gInstructions[ 2289] // SBB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -13293,13 +13517,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1633] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1623] // OR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1622] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1612] // OR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -13314,13 +13538,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1611] // OR Ev,Ib + (const void *)&gInstructions[ 1601] // OR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1600] // OR Ev,Ib + (const void *)&gInstructions[ 1590] // OR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -13432,97 +13656,97 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 350] // CCMPNLE Ev,Ib,dfv + (const void *)&gInstructions[ 342] // CCMPNLE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 306] // CCMPLE Ev,Ib,dfv + (const void *)&gInstructions[ 298] // CCMPLE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 339] // CCMPNL Ev,Ib,dfv + (const void *)&gInstructions[ 331] // CCMPNL Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 295] // CCMPL Ev,Ib,dfv + (const void *)&gInstructions[ 287] // CCMPL Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 284] // CCMPF Ev,Ib,dfv + (const void *)&gInstructions[ 276] // CCMPF Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 416] // CCMPT Ev,Ib,dfv + (const void *)&gInstructions[ 408] // CCMPT Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 372] // CCMPNS Ev,Ib,dfv + (const void *)&gInstructions[ 364] // CCMPNS Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 405] // CCMPS Ev,Ib,dfv + (const void *)&gInstructions[ 397] // CCMPS Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 317] // CCMPNBE Ev,Ib,dfv + (const void *)&gInstructions[ 309] // CCMPNBE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 262] // CCMPBE Ev,Ib,dfv + (const void *)&gInstructions[ 254] // CCMPBE Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 383] // CCMPNZ Ev,Ib,dfv + (const void *)&gInstructions[ 375] // CCMPNZ Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 427] // CCMPZ Ev,Ib,dfv + (const void *)&gInstructions[ 419] // CCMPZ Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 328] // CCMPNC Ev,Ib,dfv + (const void *)&gInstructions[ 320] // CCMPNC Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 273] // CCMPC Ev,Ib,dfv + (const void *)&gInstructions[ 265] // CCMPC Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 361] // CCMPNO Ev,Ib,dfv + (const void *)&gInstructions[ 353] // CCMPNO Ev,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 394] // CCMPO Ev,Ib,dfv + (const void *)&gInstructions[ 386] // CCMPO Ev,Ib,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc = @@ -13571,13 +13795,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4045] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4127] // XOR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4034] // XOR Bv,Ev,Ib + (const void *)&gInstructions[ 4116] // XOR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -13592,13 +13816,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4023] // XOR Ev,Ib + (const void *)&gInstructions[ 4105] // XOR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4012] // XOR Ev,Ib + (const void *)&gInstructions[ 4094] // XOR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -13633,13 +13857,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2581] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2565] // SUB Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2570] // SUB Bv,Ev,Ib + (const void *)&gInstructions[ 2554] // SUB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -13654,13 +13878,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2559] // SUB Ev,Ib + (const void *)&gInstructions[ 2543] // SUB Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2548] // SUB Ev,Ib + (const void *)&gInstructions[ 2532] // SUB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -13695,13 +13919,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 170] // AND Bv,Ev,Ib + (const void *)&gInstructions[ 162] // AND Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 159] // AND Bv,Ev,Ib + (const void *)&gInstructions[ 151] // AND Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -13716,13 +13940,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 148] // AND Ev,Ib + (const void *)&gInstructions[ 140] // AND Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 137] // AND Ev,Ib + (const void *)&gInstructions[ 129] // AND Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -13757,7 +13981,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2308] // SBB Bv,Ev,Ib + (const void *)&gInstructions[ 2299] // SBB Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -13772,7 +13996,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2297] // SBB Ev,Ib + (const void *)&gInstructions[ 2288] // SBB Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -13857,13 +14081,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1632] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1622] // OR Bv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1621] // OR Bv,Ev,Ib + (const void *)&gInstructions[ 1611] // OR Bv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -13878,13 +14102,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1610] // OR Ev,Ib + (const void *)&gInstructions[ 1600] // OR Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1599] // OR Ev,Ib + (const void *)&gInstructions[ 1589] // OR Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -14007,97 +14231,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_83_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 349] // CCMPNLE Ev,Iz,dfv + (const void *)&gInstructions[ 341] // CCMPNLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 305] // CCMPLE Ev,Iz,dfv + (const void *)&gInstructions[ 297] // CCMPLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 338] // CCMPNL Ev,Iz,dfv + (const void *)&gInstructions[ 330] // CCMPNL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 294] // CCMPL Ev,Iz,dfv + (const void *)&gInstructions[ 286] // CCMPL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 283] // CCMPF Ev,Iz,dfv + (const void *)&gInstructions[ 275] // CCMPF Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 415] // CCMPT Ev,Iz,dfv + (const void *)&gInstructions[ 407] // CCMPT Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 371] // CCMPNS Ev,Iz,dfv + (const void *)&gInstructions[ 363] // CCMPNS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 404] // CCMPS Ev,Iz,dfv + (const void *)&gInstructions[ 396] // CCMPS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 316] // CCMPNBE Ev,Iz,dfv + (const void *)&gInstructions[ 308] // CCMPNBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 261] // CCMPBE Ev,Iz,dfv + (const void *)&gInstructions[ 253] // CCMPBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 382] // CCMPNZ Ev,Iz,dfv + (const void *)&gInstructions[ 374] // CCMPNZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 426] // CCMPZ Ev,Iz,dfv + (const void *)&gInstructions[ 418] // CCMPZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 327] // CCMPNC Ev,Iz,dfv + (const void *)&gInstructions[ 319] // CCMPNC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 272] // CCMPC Ev,Iz,dfv + (const void *)&gInstructions[ 264] // CCMPC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 360] // CCMPNO Ev,Iz,dfv + (const void *)&gInstructions[ 352] // CCMPNO Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 393] // CCMPO Ev,Iz,dfv + (const void *)&gInstructions[ 385] // CCMPO Ev,Iz,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc = @@ -14146,13 +14370,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4044] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4126] // XOR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4033] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4115] // XOR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf = @@ -14167,13 +14391,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4022] // XOR Ev,Iz + (const void *)&gInstructions[ 4104] // XOR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4011] // XOR Ev,Iz + (const void *)&gInstructions[ 4093] // XOR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf = @@ -14208,13 +14432,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2580] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2564] // SUB Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2569] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2553] // SUB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf = @@ -14229,13 +14453,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2558] // SUB Ev,Iz + (const void *)&gInstructions[ 2542] // SUB Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2547] // SUB Ev,Iz + (const void *)&gInstructions[ 2531] // SUB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf = @@ -14270,13 +14494,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 169] // AND Bv,Ev,Iz + (const void *)&gInstructions[ 161] // AND Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 158] // AND Bv,Ev,Iz + (const void *)&gInstructions[ 150] // AND Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf = @@ -14291,13 +14515,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 147] // AND Ev,Iz + (const void *)&gInstructions[ 139] // AND Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 136] // AND Ev,Iz + (const void *)&gInstructions[ 128] // AND Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf = @@ -14332,7 +14556,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2307] // SBB Bv,Ev,Iz + (const void *)&gInstructions[ 2298] // SBB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf = @@ -14347,7 +14571,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2296] // SBB Ev,Iz + (const void *)&gInstructions[ 2287] // SBB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf = @@ -14432,13 +14656,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1631] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1621] // OR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1620] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1610] // OR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf = @@ -14453,13 +14677,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1609] // OR Ev,Iz + (const void *)&gInstructions[ 1599] // OR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1598] // OR Ev,Iz + (const void *)&gInstructions[ 1588] // OR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf = @@ -14571,97 +14795,97 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 348] // CCMPNLE Ev,Iz,dfv + (const void *)&gInstructions[ 340] // CCMPNLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 304] // CCMPLE Ev,Iz,dfv + (const void *)&gInstructions[ 296] // CCMPLE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 337] // CCMPNL Ev,Iz,dfv + (const void *)&gInstructions[ 329] // CCMPNL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 293] // CCMPL Ev,Iz,dfv + (const void *)&gInstructions[ 285] // CCMPL Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 282] // CCMPF Ev,Iz,dfv + (const void *)&gInstructions[ 274] // CCMPF Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 414] // CCMPT Ev,Iz,dfv + (const void *)&gInstructions[ 406] // CCMPT Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 370] // CCMPNS Ev,Iz,dfv + (const void *)&gInstructions[ 362] // CCMPNS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 403] // CCMPS Ev,Iz,dfv + (const void *)&gInstructions[ 395] // CCMPS Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 315] // CCMPNBE Ev,Iz,dfv + (const void *)&gInstructions[ 307] // CCMPNBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 260] // CCMPBE Ev,Iz,dfv + (const void *)&gInstructions[ 252] // CCMPBE Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 381] // CCMPNZ Ev,Iz,dfv + (const void *)&gInstructions[ 373] // CCMPNZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 425] // CCMPZ Ev,Iz,dfv + (const void *)&gInstructions[ 417] // CCMPZ Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 326] // CCMPNC Ev,Iz,dfv + (const void *)&gInstructions[ 318] // CCMPNC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 271] // CCMPC Ev,Iz,dfv + (const void *)&gInstructions[ 263] // CCMPC Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 359] // CCMPNO Ev,Iz,dfv + (const void *)&gInstructions[ 351] // CCMPNO Ev,Iz,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 392] // CCMPO Ev,Iz,dfv + (const void *)&gInstructions[ 384] // CCMPO Ev,Iz,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc = @@ -14710,13 +14934,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4043] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4125] // XOR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4032] // XOR Bv,Ev,Iz + (const void *)&gInstructions[ 4114] // XOR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -14731,13 +14955,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4021] // XOR Ev,Iz + (const void *)&gInstructions[ 4103] // XOR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4010] // XOR Ev,Iz + (const void *)&gInstructions[ 4092] // XOR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -14772,13 +14996,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2579] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2563] // SUB Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2568] // SUB Bv,Ev,Iz + (const void *)&gInstructions[ 2552] // SUB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -14793,13 +15017,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2557] // SUB Ev,Iz + (const void *)&gInstructions[ 2541] // SUB Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2546] // SUB Ev,Iz + (const void *)&gInstructions[ 2530] // SUB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -14834,13 +15058,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 168] // AND Bv,Ev,Iz + (const void *)&gInstructions[ 160] // AND Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 157] // AND Bv,Ev,Iz + (const void *)&gInstructions[ 149] // AND Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -14855,13 +15079,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 146] // AND Ev,Iz + (const void *)&gInstructions[ 138] // AND Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 135] // AND Ev,Iz + (const void *)&gInstructions[ 127] // AND Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -14896,7 +15120,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2306] // SBB Bv,Ev,Iz + (const void *)&gInstructions[ 2297] // SBB Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -14911,7 +15135,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2295] // SBB Ev,Iz + (const void *)&gInstructions[ 2286] // SBB Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -14996,13 +15220,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1630] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1620] // OR Bv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1619] // OR Bv,Ev,Iz + (const void *)&gInstructions[ 1609] // OR Bv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -15017,13 +15241,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1608] // OR Ev,Iz + (const void *)&gInstructions[ 1598] // OR Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1597] // OR Ev,Iz + (const void *)&gInstructions[ 1587] // OR Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -15146,97 +15370,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_81_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 347] // CCMPNLE Eb,Ib,dfv + (const void *)&gInstructions[ 339] // CCMPNLE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 303] // CCMPLE Eb,Ib,dfv + (const void *)&gInstructions[ 295] // CCMPLE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 336] // CCMPNL Eb,Ib,dfv + (const void *)&gInstructions[ 328] // CCMPNL Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 292] // CCMPL Eb,Ib,dfv + (const void *)&gInstructions[ 284] // CCMPL Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 281] // CCMPF Eb,Ib,dfv + (const void *)&gInstructions[ 273] // CCMPF Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 413] // CCMPT Eb,Ib,dfv + (const void *)&gInstructions[ 405] // CCMPT Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 369] // CCMPNS Eb,Ib,dfv + (const void *)&gInstructions[ 361] // CCMPNS Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 402] // CCMPS Eb,Ib,dfv + (const void *)&gInstructions[ 394] // CCMPS Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 314] // CCMPNBE Eb,Ib,dfv + (const void *)&gInstructions[ 306] // CCMPNBE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 259] // CCMPBE Eb,Ib,dfv + (const void *)&gInstructions[ 251] // CCMPBE Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 380] // CCMPNZ Eb,Ib,dfv + (const void *)&gInstructions[ 372] // CCMPNZ Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 424] // CCMPZ Eb,Ib,dfv + (const void *)&gInstructions[ 416] // CCMPZ Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 325] // CCMPNC Eb,Ib,dfv + (const void *)&gInstructions[ 317] // CCMPNC Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 270] // CCMPC Eb,Ib,dfv + (const void *)&gInstructions[ 262] // CCMPC Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 358] // CCMPNO Eb,Ib,dfv + (const void *)&gInstructions[ 350] // CCMPNO Eb,Ib,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 391] // CCMPO Eb,Ib,dfv + (const void *)&gInstructions[ 383] // CCMPO Eb,Ib,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc = @@ -15285,13 +15509,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4042] // XOR Bb,Eb,Ib + (const void *)&gInstructions[ 4124] // XOR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4031] // XOR Bb,Eb,Ib + (const void *)&gInstructions[ 4113] // XOR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf = @@ -15306,13 +15530,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4020] // XOR Eb,Ib + (const void *)&gInstructions[ 4102] // XOR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4009] // XOR Eb,Ib + (const void *)&gInstructions[ 4091] // XOR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf = @@ -15347,13 +15571,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2578] // SUB Bb,Eb,Ib + (const void *)&gInstructions[ 2562] // SUB Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2567] // SUB Bb,Eb,Ib + (const void *)&gInstructions[ 2551] // SUB Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf = @@ -15368,13 +15592,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2556] // SUB Eb,Ib + (const void *)&gInstructions[ 2540] // SUB Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2545] // SUB Eb,Ib + (const void *)&gInstructions[ 2529] // SUB Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf = @@ -15409,13 +15633,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 167] // AND Bb,Eb,Ib + (const void *)&gInstructions[ 159] // AND Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 156] // AND Bb,Eb,Ib + (const void *)&gInstructions[ 148] // AND Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf = @@ -15430,13 +15654,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 145] // AND Eb,Ib + (const void *)&gInstructions[ 137] // AND Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 134] // AND Eb,Ib + (const void *)&gInstructions[ 126] // AND Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf = @@ -15471,7 +15695,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2305] // SBB Bb,Eb,Ib + (const void *)&gInstructions[ 2296] // SBB Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf = @@ -15486,7 +15710,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2294] // SBB Eb,Ib + (const void *)&gInstructions[ 2285] // SBB Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf = @@ -15571,13 +15795,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1629] // OR Bb,Eb,Ib + (const void *)&gInstructions[ 1619] // OR Bb,Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1618] // OR Bb,Eb,Ib + (const void *)&gInstructions[ 1608] // OR Bb,Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf = @@ -15592,13 +15816,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1607] // OR Eb,Ib + (const void *)&gInstructions[ 1597] // OR Eb,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1596] // OR Eb,Ib + (const void *)&gInstructions[ 1586] // OR Eb,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf = @@ -15721,13 +15945,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_80_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1102] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1092] // IMUL Gv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1098] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1088] // IMUL Gv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf = @@ -15742,13 +15966,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1094] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1084] // IMUL Gv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1090] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1080] // IMUL Gv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf = @@ -15783,13 +16007,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_6b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1101] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1091] // IMUL Gv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1097] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1087] // IMUL Gv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf = @@ -15804,13 +16028,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1093] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1083] // IMUL Gv,Ev,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1089] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1079] // IMUL Gv,Ev,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf = @@ -15856,13 +16080,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_6b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1100] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1090] // IMUL Gv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1096] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1086] // IMUL Gv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf = @@ -15877,13 +16101,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1092] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1082] // IMUL Gv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1088] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1078] // IMUL Gv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf = @@ -15918,13 +16142,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_69_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1099] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1089] // IMUL Gv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1095] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1085] // IMUL Gv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf = @@ -15939,13 +16163,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1091] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1081] // IMUL Gv,Ev,Iz }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1087] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1077] // IMUL Gv,Ev,Iz }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf = @@ -16091,7 +16315,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3980] // WRSSQ My,Gy + (const void *)&gInstructions[ 4062] // WRSSQ My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf = @@ -16115,7 +16339,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3978] // WRSSD My,Gy + (const void *)&gInstructions[ 4060] // WRSSD My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf = @@ -16179,7 +16403,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3984] // WRUSSQ My,Gy + (const void *)&gInstructions[ 4066] // WRUSSQ My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf = @@ -16203,7 +16427,7 @@ const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3982] // WRUSSD My,Gy + (const void *)&gInstructions[ 4064] // WRUSSD My,Gy }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf = @@ -16267,7 +16491,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_65_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1410] // MOVBE Ev,Gv + (const void *)&gInstructions[ 1400] // MOVBE Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf = @@ -16302,7 +16526,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_61_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1409] // MOVBE Ev,Gv + (const void *)&gInstructions[ 1399] // MOVBE Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf = @@ -16348,7 +16572,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_61_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1408] // MOVBE Gv,Ev + (const void *)&gInstructions[ 1398] // MOVBE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf = @@ -16383,7 +16607,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_60_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1407] // MOVBE Gv,Ev + (const void *)&gInstructions[ 1397] // MOVBE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf = @@ -16429,7 +16653,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_60_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2347] // SETNLE Eb + (const void *)&gInstructions[ 2338] // SETNLE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf = @@ -16455,13 +16679,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 494] // CFCMOVNLE Bv,Gv,Ev + (const void *)&gInstructions[ 486] // CFCMOVNLE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 597] // CMOVNLE Bv,Gv,Ev + (const void *)&gInstructions[ 589] // CMOVNLE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf = @@ -16476,13 +16700,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 491] // CFCMOVNLE Rv,Gv + (const void *)&gInstructions[ 483] // CFCMOVNLE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 492] // CFCMOVNLE Mv,Gv + (const void *)&gInstructions[ 484] // CFCMOVNLE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -16497,7 +16721,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 490] // CFCMOVNLE Gv,Ev + (const void *)&gInstructions[ 482] // CFCMOVNLE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf = @@ -16532,13 +16756,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 493] // CFCMOVNLE Bv,Gv,Ev + (const void *)&gInstructions[ 485] // CFCMOVNLE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 596] // CMOVNLE Bv,Gv,Ev + (const void *)&gInstructions[ 588] // CMOVNLE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf = @@ -16553,13 +16777,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 488] // CFCMOVNLE Rv,Gv + (const void *)&gInstructions[ 480] // CFCMOVNLE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 489] // CFCMOVNLE Mv,Gv + (const void *)&gInstructions[ 481] // CFCMOVNLE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -16574,7 +16798,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 487] // CFCMOVNLE Gv,Ev + (const void *)&gInstructions[ 479] // CFCMOVNLE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf = @@ -16620,7 +16844,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2339] // SETLE Eb + (const void *)&gInstructions[ 2330] // SETLE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf = @@ -16646,13 +16870,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 462] // CFCMOVLE Bv,Gv,Ev + (const void *)&gInstructions[ 454] // CFCMOVLE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 585] // CMOVLE Bv,Gv,Ev + (const void *)&gInstructions[ 577] // CMOVLE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf = @@ -16667,13 +16891,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 459] // CFCMOVLE Rv,Gv + (const void *)&gInstructions[ 451] // CFCMOVLE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 460] // CFCMOVLE Mv,Gv + (const void *)&gInstructions[ 452] // CFCMOVLE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -16688,7 +16912,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 458] // CFCMOVLE Gv,Ev + (const void *)&gInstructions[ 450] // CFCMOVLE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf = @@ -16723,13 +16947,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 461] // CFCMOVLE Bv,Gv,Ev + (const void *)&gInstructions[ 453] // CFCMOVLE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 584] // CMOVLE Bv,Gv,Ev + (const void *)&gInstructions[ 576] // CMOVLE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf = @@ -16744,13 +16968,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 456] // CFCMOVLE Rv,Gv + (const void *)&gInstructions[ 448] // CFCMOVLE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 457] // CFCMOVLE Mv,Gv + (const void *)&gInstructions[ 449] // CFCMOVLE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -16765,7 +16989,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 455] // CFCMOVLE Gv,Ev + (const void *)&gInstructions[ 447] // CFCMOVLE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf = @@ -16811,7 +17035,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2345] // SETNL Eb + (const void *)&gInstructions[ 2336] // SETNL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf = @@ -16837,13 +17061,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 486] // CFCMOVNL Bv,Gv,Ev + (const void *)&gInstructions[ 478] // CFCMOVNL Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 594] // CMOVNL Bv,Gv,Ev + (const void *)&gInstructions[ 586] // CMOVNL Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf = @@ -16858,13 +17082,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 483] // CFCMOVNL Rv,Gv + (const void *)&gInstructions[ 475] // CFCMOVNL Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 484] // CFCMOVNL Mv,Gv + (const void *)&gInstructions[ 476] // CFCMOVNL Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -16879,7 +17103,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 482] // CFCMOVNL Gv,Ev + (const void *)&gInstructions[ 474] // CFCMOVNL Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf = @@ -16914,13 +17138,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 485] // CFCMOVNL Bv,Gv,Ev + (const void *)&gInstructions[ 477] // CFCMOVNL Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 593] // CMOVNL Bv,Gv,Ev + (const void *)&gInstructions[ 585] // CMOVNL Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf = @@ -16935,13 +17159,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 480] // CFCMOVNL Rv,Gv + (const void *)&gInstructions[ 472] // CFCMOVNL Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 481] // CFCMOVNL Mv,Gv + (const void *)&gInstructions[ 473] // CFCMOVNL Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -16956,7 +17180,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 479] // CFCMOVNL Gv,Ev + (const void *)&gInstructions[ 471] // CFCMOVNL Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf = @@ -17002,7 +17226,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2337] // SETL Eb + (const void *)&gInstructions[ 2328] // SETL Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf = @@ -17028,13 +17252,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 454] // CFCMOVL Bv,Gv,Ev + (const void *)&gInstructions[ 446] // CFCMOVL Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 582] // CMOVL Bv,Gv,Ev + (const void *)&gInstructions[ 574] // CMOVL Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf = @@ -17049,13 +17273,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 451] // CFCMOVL Rv,Gv + (const void *)&gInstructions[ 443] // CFCMOVL Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 452] // CFCMOVL Mv,Gv + (const void *)&gInstructions[ 444] // CFCMOVL Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -17070,7 +17294,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 450] // CFCMOVL Gv,Ev + (const void *)&gInstructions[ 442] // CFCMOVL Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf = @@ -17105,13 +17329,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 453] // CFCMOVL Bv,Gv,Ev + (const void *)&gInstructions[ 445] // CFCMOVL Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 581] // CMOVL Bv,Gv,Ev + (const void *)&gInstructions[ 573] // CMOVL Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf = @@ -17126,13 +17350,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 448] // CFCMOVL Rv,Gv + (const void *)&gInstructions[ 440] // CFCMOVL Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 449] // CFCMOVL Mv,Gv + (const void *)&gInstructions[ 441] // CFCMOVL Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -17147,7 +17371,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 447] // CFCMOVL Gv,Ev + (const void *)&gInstructions[ 439] // CFCMOVL Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf = @@ -17193,7 +17417,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2351] // SETNP Eb + (const void *)&gInstructions[ 2342] // SETNP Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf = @@ -17219,13 +17443,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 510] // CFCMOVNP Bv,Gv,Ev + (const void *)&gInstructions[ 502] // CFCMOVNP Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 603] // CMOVNP Bv,Gv,Ev + (const void *)&gInstructions[ 595] // CMOVNP Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf = @@ -17240,13 +17464,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 507] // CFCMOVNP Rv,Gv + (const void *)&gInstructions[ 499] // CFCMOVNP Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 508] // CFCMOVNP Mv,Gv + (const void *)&gInstructions[ 500] // CFCMOVNP Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -17261,7 +17485,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 506] // CFCMOVNP Gv,Ev + (const void *)&gInstructions[ 498] // CFCMOVNP Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf = @@ -17296,13 +17520,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 509] // CFCMOVNP Bv,Gv,Ev + (const void *)&gInstructions[ 501] // CFCMOVNP Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 602] // CMOVNP Bv,Gv,Ev + (const void *)&gInstructions[ 594] // CMOVNP Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf = @@ -17317,13 +17541,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 504] // CFCMOVNP Rv,Gv + (const void *)&gInstructions[ 496] // CFCMOVNP Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 505] // CFCMOVNP Mv,Gv + (const void *)&gInstructions[ 497] // CFCMOVNP Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -17338,7 +17562,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 503] // CFCMOVNP Gv,Ev + (const void *)&gInstructions[ 495] // CFCMOVNP Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf = @@ -17384,7 +17608,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2359] // SETP Eb + (const void *)&gInstructions[ 2350] // SETP Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf = @@ -17410,13 +17634,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 542] // CFCMOVP Bv,Gv,Ev + (const void *)&gInstructions[ 534] // CFCMOVP Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 615] // CMOVP Bv,Gv,Ev + (const void *)&gInstructions[ 607] // CMOVP Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf = @@ -17431,13 +17655,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 539] // CFCMOVP Rv,Gv + (const void *)&gInstructions[ 531] // CFCMOVP Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 540] // CFCMOVP Mv,Gv + (const void *)&gInstructions[ 532] // CFCMOVP Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -17452,7 +17676,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 538] // CFCMOVP Gv,Ev + (const void *)&gInstructions[ 530] // CFCMOVP Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf = @@ -17487,13 +17711,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 541] // CFCMOVP Bv,Gv,Ev + (const void *)&gInstructions[ 533] // CFCMOVP Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 614] // CMOVP Bv,Gv,Ev + (const void *)&gInstructions[ 606] // CMOVP Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf = @@ -17508,13 +17732,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 536] // CFCMOVP Rv,Gv + (const void *)&gInstructions[ 528] // CFCMOVP Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 537] // CFCMOVP Mv,Gv + (const void *)&gInstructions[ 529] // CFCMOVP Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -17529,7 +17753,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 535] // CFCMOVP Gv,Ev + (const void *)&gInstructions[ 527] // CFCMOVP Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf = @@ -17575,7 +17799,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2353] // SETNS Eb + (const void *)&gInstructions[ 2344] // SETNS Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf = @@ -17601,13 +17825,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 518] // CFCMOVNS Bv,Gv,Ev + (const void *)&gInstructions[ 510] // CFCMOVNS Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 606] // CMOVNS Bv,Gv,Ev + (const void *)&gInstructions[ 598] // CMOVNS Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf = @@ -17622,13 +17846,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 515] // CFCMOVNS Rv,Gv + (const void *)&gInstructions[ 507] // CFCMOVNS Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 516] // CFCMOVNS Mv,Gv + (const void *)&gInstructions[ 508] // CFCMOVNS Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -17643,7 +17867,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 514] // CFCMOVNS Gv,Ev + (const void *)&gInstructions[ 506] // CFCMOVNS Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf = @@ -17678,13 +17902,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 517] // CFCMOVNS Bv,Gv,Ev + (const void *)&gInstructions[ 509] // CFCMOVNS Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 605] // CMOVNS Bv,Gv,Ev + (const void *)&gInstructions[ 597] // CMOVNS Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf = @@ -17699,13 +17923,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 512] // CFCMOVNS Rv,Gv + (const void *)&gInstructions[ 504] // CFCMOVNS Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 513] // CFCMOVNS Mv,Gv + (const void *)&gInstructions[ 505] // CFCMOVNS Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -17720,7 +17944,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 511] // CFCMOVNS Gv,Ev + (const void *)&gInstructions[ 503] // CFCMOVNS Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf = @@ -17766,7 +17990,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_49_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2361] // SETS Eb + (const void *)&gInstructions[ 2352] // SETS Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf = @@ -17792,13 +18016,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 550] // CFCMOVS Bv,Gv,Ev + (const void *)&gInstructions[ 542] // CFCMOVS Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 618] // CMOVS Bv,Gv,Ev + (const void *)&gInstructions[ 610] // CMOVS Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf = @@ -17813,13 +18037,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 547] // CFCMOVS Rv,Gv + (const void *)&gInstructions[ 539] // CFCMOVS Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 548] // CFCMOVS Mv,Gv + (const void *)&gInstructions[ 540] // CFCMOVS Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -17834,7 +18058,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 546] // CFCMOVS Gv,Ev + (const void *)&gInstructions[ 538] // CFCMOVS Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf = @@ -17869,13 +18093,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 549] // CFCMOVS Bv,Gv,Ev + (const void *)&gInstructions[ 541] // CFCMOVS Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 617] // CMOVS Bv,Gv,Ev + (const void *)&gInstructions[ 609] // CMOVS Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf = @@ -17890,13 +18114,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 544] // CFCMOVS Rv,Gv + (const void *)&gInstructions[ 536] // CFCMOVS Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 545] // CFCMOVS Mv,Gv + (const void *)&gInstructions[ 537] // CFCMOVS Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -17911,7 +18135,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 543] // CFCMOVS Gv,Ev + (const void *)&gInstructions[ 535] // CFCMOVS Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf = @@ -17957,7 +18181,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_48_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2341] // SETNBE Eb + (const void *)&gInstructions[ 2332] // SETNBE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf = @@ -17983,13 +18207,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 470] // CFCMOVNBE Bv,Gv,Ev + (const void *)&gInstructions[ 462] // CFCMOVNBE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 588] // CMOVNBE Bv,Gv,Ev + (const void *)&gInstructions[ 580] // CMOVNBE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf = @@ -18004,13 +18228,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 467] // CFCMOVNBE Rv,Gv + (const void *)&gInstructions[ 459] // CFCMOVNBE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 468] // CFCMOVNBE Mv,Gv + (const void *)&gInstructions[ 460] // CFCMOVNBE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -18025,7 +18249,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 466] // CFCMOVNBE Gv,Ev + (const void *)&gInstructions[ 458] // CFCMOVNBE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf = @@ -18060,13 +18284,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 469] // CFCMOVNBE Bv,Gv,Ev + (const void *)&gInstructions[ 461] // CFCMOVNBE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 587] // CMOVNBE Bv,Gv,Ev + (const void *)&gInstructions[ 579] // CMOVNBE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf = @@ -18081,13 +18305,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 464] // CFCMOVNBE Rv,Gv + (const void *)&gInstructions[ 456] // CFCMOVNBE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 465] // CFCMOVNBE Mv,Gv + (const void *)&gInstructions[ 457] // CFCMOVNBE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -18102,7 +18326,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 463] // CFCMOVNBE Gv,Ev + (const void *)&gInstructions[ 455] // CFCMOVNBE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf = @@ -18148,7 +18372,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_47_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2333] // SETBE Eb + (const void *)&gInstructions[ 2324] // SETBE Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf = @@ -18174,13 +18398,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 438] // CFCMOVBE Bv,Gv,Ev + (const void *)&gInstructions[ 430] // CFCMOVBE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 576] // CMOVBE Bv,Gv,Ev + (const void *)&gInstructions[ 568] // CMOVBE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf = @@ -18195,13 +18419,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 435] // CFCMOVBE Rv,Gv + (const void *)&gInstructions[ 427] // CFCMOVBE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 436] // CFCMOVBE Mv,Gv + (const void *)&gInstructions[ 428] // CFCMOVBE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -18216,7 +18440,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 434] // CFCMOVBE Gv,Ev + (const void *)&gInstructions[ 426] // CFCMOVBE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf = @@ -18251,13 +18475,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 437] // CFCMOVBE Bv,Gv,Ev + (const void *)&gInstructions[ 429] // CFCMOVBE Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 575] // CMOVBE Bv,Gv,Ev + (const void *)&gInstructions[ 567] // CMOVBE Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf = @@ -18272,13 +18496,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 432] // CFCMOVBE Rv,Gv + (const void *)&gInstructions[ 424] // CFCMOVBE Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 433] // CFCMOVBE Mv,Gv + (const void *)&gInstructions[ 425] // CFCMOVBE Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -18293,7 +18517,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 431] // CFCMOVBE Gv,Ev + (const void *)&gInstructions[ 423] // CFCMOVBE Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf = @@ -18339,7 +18563,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_46_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2355] // SETNZ Eb + (const void *)&gInstructions[ 2346] // SETNZ Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf = @@ -18365,13 +18589,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 526] // CFCMOVNZ Bv,Gv,Ev + (const void *)&gInstructions[ 518] // CFCMOVNZ Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 609] // CMOVNZ Bv,Gv,Ev + (const void *)&gInstructions[ 601] // CMOVNZ Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf = @@ -18386,13 +18610,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 523] // CFCMOVNZ Rv,Gv + (const void *)&gInstructions[ 515] // CFCMOVNZ Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 524] // CFCMOVNZ Mv,Gv + (const void *)&gInstructions[ 516] // CFCMOVNZ Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -18407,7 +18631,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 522] // CFCMOVNZ Gv,Ev + (const void *)&gInstructions[ 514] // CFCMOVNZ Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf = @@ -18442,13 +18666,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 525] // CFCMOVNZ Bv,Gv,Ev + (const void *)&gInstructions[ 517] // CFCMOVNZ Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 608] // CMOVNZ Bv,Gv,Ev + (const void *)&gInstructions[ 600] // CMOVNZ Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf = @@ -18463,13 +18687,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 520] // CFCMOVNZ Rv,Gv + (const void *)&gInstructions[ 512] // CFCMOVNZ Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 521] // CFCMOVNZ Mv,Gv + (const void *)&gInstructions[ 513] // CFCMOVNZ Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -18484,7 +18708,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 519] // CFCMOVNZ Gv,Ev + (const void *)&gInstructions[ 511] // CFCMOVNZ Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf = @@ -18530,7 +18754,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_45_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2364] // SETZ Eb + (const void *)&gInstructions[ 2355] // SETZ Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf = @@ -18556,13 +18780,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 558] // CFCMOVZ Bv,Gv,Ev + (const void *)&gInstructions[ 550] // CFCMOVZ Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 621] // CMOVZ Bv,Gv,Ev + (const void *)&gInstructions[ 613] // CMOVZ Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf = @@ -18577,13 +18801,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 555] // CFCMOVZ Rv,Gv + (const void *)&gInstructions[ 547] // CFCMOVZ Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 556] // CFCMOVZ Mv,Gv + (const void *)&gInstructions[ 548] // CFCMOVZ Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -18598,7 +18822,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 554] // CFCMOVZ Gv,Ev + (const void *)&gInstructions[ 546] // CFCMOVZ Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf = @@ -18633,13 +18857,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 557] // CFCMOVZ Bv,Gv,Ev + (const void *)&gInstructions[ 549] // CFCMOVZ Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 620] // CMOVZ Bv,Gv,Ev + (const void *)&gInstructions[ 612] // CMOVZ Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf = @@ -18654,13 +18878,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 552] // CFCMOVZ Rv,Gv + (const void *)&gInstructions[ 544] // CFCMOVZ Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 553] // CFCMOVZ Mv,Gv + (const void *)&gInstructions[ 545] // CFCMOVZ Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -18675,7 +18899,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 551] // CFCMOVZ Gv,Ev + (const void *)&gInstructions[ 543] // CFCMOVZ Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf = @@ -18721,7 +18945,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_44_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2343] // SETNC Eb + (const void *)&gInstructions[ 2334] // SETNC Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf = @@ -18747,13 +18971,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 478] // CFCMOVNC Bv,Gv,Ev + (const void *)&gInstructions[ 470] // CFCMOVNC Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 591] // CMOVNC Bv,Gv,Ev + (const void *)&gInstructions[ 583] // CMOVNC Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf = @@ -18768,13 +18992,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 475] // CFCMOVNC Rv,Gv + (const void *)&gInstructions[ 467] // CFCMOVNC Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 476] // CFCMOVNC Mv,Gv + (const void *)&gInstructions[ 468] // CFCMOVNC Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -18789,7 +19013,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 474] // CFCMOVNC Gv,Ev + (const void *)&gInstructions[ 466] // CFCMOVNC Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf = @@ -18824,13 +19048,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 477] // CFCMOVNC Bv,Gv,Ev + (const void *)&gInstructions[ 469] // CFCMOVNC Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 590] // CMOVNC Bv,Gv,Ev + (const void *)&gInstructions[ 582] // CMOVNC Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf = @@ -18845,13 +19069,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 472] // CFCMOVNC Rv,Gv + (const void *)&gInstructions[ 464] // CFCMOVNC Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 473] // CFCMOVNC Mv,Gv + (const void *)&gInstructions[ 465] // CFCMOVNC Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -18866,7 +19090,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 471] // CFCMOVNC Gv,Ev + (const void *)&gInstructions[ 463] // CFCMOVNC Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf = @@ -18912,7 +19136,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2335] // SETC Eb + (const void *)&gInstructions[ 2326] // SETC Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf = @@ -18938,13 +19162,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 446] // CFCMOVC Bv,Gv,Ev + (const void *)&gInstructions[ 438] // CFCMOVC Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 579] // CMOVC Bv,Gv,Ev + (const void *)&gInstructions[ 571] // CMOVC Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf = @@ -18959,13 +19183,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 443] // CFCMOVC Rv,Gv + (const void *)&gInstructions[ 435] // CFCMOVC Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 444] // CFCMOVC Mv,Gv + (const void *)&gInstructions[ 436] // CFCMOVC Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -18980,7 +19204,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 442] // CFCMOVC Gv,Ev + (const void *)&gInstructions[ 434] // CFCMOVC Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf = @@ -19015,13 +19239,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 445] // CFCMOVC Bv,Gv,Ev + (const void *)&gInstructions[ 437] // CFCMOVC Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 578] // CMOVC Bv,Gv,Ev + (const void *)&gInstructions[ 570] // CMOVC Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf = @@ -19036,13 +19260,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 440] // CFCMOVC Rv,Gv + (const void *)&gInstructions[ 432] // CFCMOVC Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 441] // CFCMOVC Mv,Gv + (const void *)&gInstructions[ 433] // CFCMOVC Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -19057,7 +19281,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 439] // CFCMOVC Gv,Ev + (const void *)&gInstructions[ 431] // CFCMOVC Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf = @@ -19103,7 +19327,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2349] // SETNO Eb + (const void *)&gInstructions[ 2340] // SETNO Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf = @@ -19129,13 +19353,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 502] // CFCMOVNO Bv,Gv,Ev + (const void *)&gInstructions[ 494] // CFCMOVNO Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 600] // CMOVNO Bv,Gv,Ev + (const void *)&gInstructions[ 592] // CMOVNO Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf = @@ -19150,13 +19374,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 499] // CFCMOVNO Rv,Gv + (const void *)&gInstructions[ 491] // CFCMOVNO Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 500] // CFCMOVNO Mv,Gv + (const void *)&gInstructions[ 492] // CFCMOVNO Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -19171,7 +19395,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 498] // CFCMOVNO Gv,Ev + (const void *)&gInstructions[ 490] // CFCMOVNO Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf = @@ -19206,13 +19430,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 501] // CFCMOVNO Bv,Gv,Ev + (const void *)&gInstructions[ 493] // CFCMOVNO Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 599] // CMOVNO Bv,Gv,Ev + (const void *)&gInstructions[ 591] // CMOVNO Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf = @@ -19227,13 +19451,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 496] // CFCMOVNO Rv,Gv + (const void *)&gInstructions[ 488] // CFCMOVNO Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 497] // CFCMOVNO Mv,Gv + (const void *)&gInstructions[ 489] // CFCMOVNO Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -19248,7 +19472,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 495] // CFCMOVNO Gv,Ev + (const void *)&gInstructions[ 487] // CFCMOVNO Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf = @@ -19294,7 +19518,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_41_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2357] // SETO Eb + (const void *)&gInstructions[ 2348] // SETO Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf = @@ -19320,13 +19544,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 534] // CFCMOVO Bv,Gv,Ev + (const void *)&gInstructions[ 526] // CFCMOVO Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 612] // CMOVO Bv,Gv,Ev + (const void *)&gInstructions[ 604] // CMOVO Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf = @@ -19341,13 +19565,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 531] // CFCMOVO Rv,Gv + (const void *)&gInstructions[ 523] // CFCMOVO Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 532] // CFCMOVO Mv,Gv + (const void *)&gInstructions[ 524] // CFCMOVO Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod = @@ -19362,7 +19586,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 530] // CFCMOVO Gv,Ev + (const void *)&gInstructions[ 522] // CFCMOVO Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf = @@ -19397,13 +19621,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 533] // CFCMOVO Bv,Gv,Ev + (const void *)&gInstructions[ 525] // CFCMOVO Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 611] // CMOVO Bv,Gv,Ev + (const void *)&gInstructions[ 603] // CMOVO Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf = @@ -19418,13 +19642,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 528] // CFCMOVO Rv,Gv + (const void *)&gInstructions[ 520] // CFCMOVO Rv,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 529] // CFCMOVO Mv,Gv + (const void *)&gInstructions[ 521] // CFCMOVO Mv,Gv }; const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod = @@ -19439,7 +19663,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modr const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 527] // CFCMOVO Gv,Ev + (const void *)&gInstructions[ 519] // CFCMOVO Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf = @@ -19485,97 +19709,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_40_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 346] // CCMPNLE Gv,Ev,dfv + (const void *)&gInstructions[ 338] // CCMPNLE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 302] // CCMPLE Gv,Ev,dfv + (const void *)&gInstructions[ 294] // CCMPLE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 335] // CCMPNL Gv,Ev,dfv + (const void *)&gInstructions[ 327] // CCMPNL Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 291] // CCMPL Gv,Ev,dfv + (const void *)&gInstructions[ 283] // CCMPL Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 280] // CCMPF Gv,Ev,dfv + (const void *)&gInstructions[ 272] // CCMPF Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 412] // CCMPT Gv,Ev,dfv + (const void *)&gInstructions[ 404] // CCMPT Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 368] // CCMPNS Gv,Ev,dfv + (const void *)&gInstructions[ 360] // CCMPNS Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 401] // CCMPS Gv,Ev,dfv + (const void *)&gInstructions[ 393] // CCMPS Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 313] // CCMPNBE Gv,Ev,dfv + (const void *)&gInstructions[ 305] // CCMPNBE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 258] // CCMPBE Gv,Ev,dfv + (const void *)&gInstructions[ 250] // CCMPBE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 379] // CCMPNZ Gv,Ev,dfv + (const void *)&gInstructions[ 371] // CCMPNZ Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 423] // CCMPZ Gv,Ev,dfv + (const void *)&gInstructions[ 415] // CCMPZ Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 324] // CCMPNC Gv,Ev,dfv + (const void *)&gInstructions[ 316] // CCMPNC Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 269] // CCMPC Gv,Ev,dfv + (const void *)&gInstructions[ 261] // CCMPC Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 357] // CCMPNO Gv,Ev,dfv + (const void *)&gInstructions[ 349] // CCMPNO Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 390] // CCMPO Gv,Ev,dfv + (const void *)&gInstructions[ 382] // CCMPO Gv,Ev,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc = @@ -19624,97 +19848,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 345] // CCMPNLE Gv,Ev,dfv + (const void *)&gInstructions[ 337] // CCMPNLE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 301] // CCMPLE Gv,Ev,dfv + (const void *)&gInstructions[ 293] // CCMPLE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 334] // CCMPNL Gv,Ev,dfv + (const void *)&gInstructions[ 326] // CCMPNL Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 290] // CCMPL Gv,Ev,dfv + (const void *)&gInstructions[ 282] // CCMPL Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 279] // CCMPF Gv,Ev,dfv + (const void *)&gInstructions[ 271] // CCMPF Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 411] // CCMPT Gv,Ev,dfv + (const void *)&gInstructions[ 403] // CCMPT Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 367] // CCMPNS Gv,Ev,dfv + (const void *)&gInstructions[ 359] // CCMPNS Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 400] // CCMPS Gv,Ev,dfv + (const void *)&gInstructions[ 392] // CCMPS Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 312] // CCMPNBE Gv,Ev,dfv + (const void *)&gInstructions[ 304] // CCMPNBE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 257] // CCMPBE Gv,Ev,dfv + (const void *)&gInstructions[ 249] // CCMPBE Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 378] // CCMPNZ Gv,Ev,dfv + (const void *)&gInstructions[ 370] // CCMPNZ Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 422] // CCMPZ Gv,Ev,dfv + (const void *)&gInstructions[ 414] // CCMPZ Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 323] // CCMPNC Gv,Ev,dfv + (const void *)&gInstructions[ 315] // CCMPNC Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 268] // CCMPC Gv,Ev,dfv + (const void *)&gInstructions[ 260] // CCMPC Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 356] // CCMPNO Gv,Ev,dfv + (const void *)&gInstructions[ 348] // CCMPNO Gv,Ev,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 389] // CCMPO Gv,Ev,dfv + (const void *)&gInstructions[ 381] // CCMPO Gv,Ev,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc = @@ -19774,97 +19998,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_3b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 344] // CCMPNLE Gb,Eb,dfv + (const void *)&gInstructions[ 336] // CCMPNLE Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 300] // CCMPLE Gb,Eb,dfv + (const void *)&gInstructions[ 292] // CCMPLE Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 333] // CCMPNL Gb,Eb,dfv + (const void *)&gInstructions[ 325] // CCMPNL Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 289] // CCMPL Gb,Eb,dfv + (const void *)&gInstructions[ 281] // CCMPL Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 278] // CCMPF Gb,Eb,dfv + (const void *)&gInstructions[ 270] // CCMPF Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 410] // CCMPT Gb,Eb,dfv + (const void *)&gInstructions[ 402] // CCMPT Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 366] // CCMPNS Gb,Eb,dfv + (const void *)&gInstructions[ 358] // CCMPNS Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 399] // CCMPS Gb,Eb,dfv + (const void *)&gInstructions[ 391] // CCMPS Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 311] // CCMPNBE Gb,Eb,dfv + (const void *)&gInstructions[ 303] // CCMPNBE Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 256] // CCMPBE Gb,Eb,dfv + (const void *)&gInstructions[ 248] // CCMPBE Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 377] // CCMPNZ Gb,Eb,dfv + (const void *)&gInstructions[ 369] // CCMPNZ Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 421] // CCMPZ Gb,Eb,dfv + (const void *)&gInstructions[ 413] // CCMPZ Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 322] // CCMPNC Gb,Eb,dfv + (const void *)&gInstructions[ 314] // CCMPNC Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 267] // CCMPC Gb,Eb,dfv + (const void *)&gInstructions[ 259] // CCMPC Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 355] // CCMPNO Gb,Eb,dfv + (const void *)&gInstructions[ 347] // CCMPNO Gb,Eb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 388] // CCMPO Gb,Eb,dfv + (const void *)&gInstructions[ 380] // CCMPO Gb,Eb,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc = @@ -19924,97 +20148,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_3a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 343] // CCMPNLE Ev,Gv,dfv + (const void *)&gInstructions[ 335] // CCMPNLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 299] // CCMPLE Ev,Gv,dfv + (const void *)&gInstructions[ 291] // CCMPLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 332] // CCMPNL Ev,Gv,dfv + (const void *)&gInstructions[ 324] // CCMPNL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 288] // CCMPL Ev,Gv,dfv + (const void *)&gInstructions[ 280] // CCMPL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 277] // CCMPF Ev,Gv,dfv + (const void *)&gInstructions[ 269] // CCMPF Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 409] // CCMPT Ev,Gv,dfv + (const void *)&gInstructions[ 401] // CCMPT Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 365] // CCMPNS Ev,Gv,dfv + (const void *)&gInstructions[ 357] // CCMPNS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 398] // CCMPS Ev,Gv,dfv + (const void *)&gInstructions[ 390] // CCMPS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 310] // CCMPNBE Ev,Gv,dfv + (const void *)&gInstructions[ 302] // CCMPNBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 255] // CCMPBE Ev,Gv,dfv + (const void *)&gInstructions[ 247] // CCMPBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 376] // CCMPNZ Ev,Gv,dfv + (const void *)&gInstructions[ 368] // CCMPNZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 420] // CCMPZ Ev,Gv,dfv + (const void *)&gInstructions[ 412] // CCMPZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 321] // CCMPNC Ev,Gv,dfv + (const void *)&gInstructions[ 313] // CCMPNC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 266] // CCMPC Ev,Gv,dfv + (const void *)&gInstructions[ 258] // CCMPC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 354] // CCMPNO Ev,Gv,dfv + (const void *)&gInstructions[ 346] // CCMPNO Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 387] // CCMPO Ev,Gv,dfv + (const void *)&gInstructions[ 379] // CCMPO Ev,Gv,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc = @@ -20063,97 +20287,97 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_39_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 342] // CCMPNLE Ev,Gv,dfv + (const void *)&gInstructions[ 334] // CCMPNLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 298] // CCMPLE Ev,Gv,dfv + (const void *)&gInstructions[ 290] // CCMPLE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 331] // CCMPNL Ev,Gv,dfv + (const void *)&gInstructions[ 323] // CCMPNL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 287] // CCMPL Ev,Gv,dfv + (const void *)&gInstructions[ 279] // CCMPL Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 276] // CCMPF Ev,Gv,dfv + (const void *)&gInstructions[ 268] // CCMPF Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 408] // CCMPT Ev,Gv,dfv + (const void *)&gInstructions[ 400] // CCMPT Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 364] // CCMPNS Ev,Gv,dfv + (const void *)&gInstructions[ 356] // CCMPNS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 397] // CCMPS Ev,Gv,dfv + (const void *)&gInstructions[ 389] // CCMPS Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 309] // CCMPNBE Ev,Gv,dfv + (const void *)&gInstructions[ 301] // CCMPNBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 254] // CCMPBE Ev,Gv,dfv + (const void *)&gInstructions[ 246] // CCMPBE Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 375] // CCMPNZ Ev,Gv,dfv + (const void *)&gInstructions[ 367] // CCMPNZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 419] // CCMPZ Ev,Gv,dfv + (const void *)&gInstructions[ 411] // CCMPZ Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 320] // CCMPNC Ev,Gv,dfv + (const void *)&gInstructions[ 312] // CCMPNC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 265] // CCMPC Ev,Gv,dfv + (const void *)&gInstructions[ 257] // CCMPC Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 353] // CCMPNO Ev,Gv,dfv + (const void *)&gInstructions[ 345] // CCMPNO Ev,Gv,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 386] // CCMPO Ev,Gv,dfv + (const void *)&gInstructions[ 378] // CCMPO Ev,Gv,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc = @@ -20213,97 +20437,97 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_39_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 341] // CCMPNLE Eb,Gb,dfv + (const void *)&gInstructions[ 333] // CCMPNLE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 297] // CCMPLE Eb,Gb,dfv + (const void *)&gInstructions[ 289] // CCMPLE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 330] // CCMPNL Eb,Gb,dfv + (const void *)&gInstructions[ 322] // CCMPNL Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 286] // CCMPL Eb,Gb,dfv + (const void *)&gInstructions[ 278] // CCMPL Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 275] // CCMPF Eb,Gb,dfv + (const void *)&gInstructions[ 267] // CCMPF Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 407] // CCMPT Eb,Gb,dfv + (const void *)&gInstructions[ 399] // CCMPT Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 363] // CCMPNS Eb,Gb,dfv + (const void *)&gInstructions[ 355] // CCMPNS Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 396] // CCMPS Eb,Gb,dfv + (const void *)&gInstructions[ 388] // CCMPS Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 308] // CCMPNBE Eb,Gb,dfv + (const void *)&gInstructions[ 300] // CCMPNBE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 253] // CCMPBE Eb,Gb,dfv + (const void *)&gInstructions[ 245] // CCMPBE Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 374] // CCMPNZ Eb,Gb,dfv + (const void *)&gInstructions[ 366] // CCMPNZ Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 418] // CCMPZ Eb,Gb,dfv + (const void *)&gInstructions[ 410] // CCMPZ Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 319] // CCMPNC Eb,Gb,dfv + (const void *)&gInstructions[ 311] // CCMPNC Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 264] // CCMPC Eb,Gb,dfv + (const void *)&gInstructions[ 256] // CCMPC Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 352] // CCMPNO Eb,Gb,dfv + (const void *)&gInstructions[ 344] // CCMPNO Eb,Gb,dfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 385] // CCMPO Eb,Gb,dfv + (const void *)&gInstructions[ 377] // CCMPO Eb,Gb,dfv }; const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc = @@ -20363,13 +20587,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_38_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4041] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4123] // XOR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4030] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4112] // XOR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf = @@ -20384,13 +20608,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4019] // XOR Gv,Ev + (const void *)&gInstructions[ 4101] // XOR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4008] // XOR Gv,Ev + (const void *)&gInstructions[ 4090] // XOR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf = @@ -20425,13 +20649,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_33_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4040] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4122] // XOR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4029] // XOR Bv,Gv,Ev + (const void *)&gInstructions[ 4111] // XOR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf = @@ -20446,13 +20670,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4018] // XOR Gv,Ev + (const void *)&gInstructions[ 4100] // XOR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4007] // XOR Gv,Ev + (const void *)&gInstructions[ 4089] // XOR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf = @@ -20498,13 +20722,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_33_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4039] // XOR Bb,Gb,Eb + (const void *)&gInstructions[ 4121] // XOR Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4028] // XOR Bb,Gb,Eb + (const void *)&gInstructions[ 4110] // XOR Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf = @@ -20519,13 +20743,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4017] // XOR Gb,Eb + (const void *)&gInstructions[ 4099] // XOR Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4006] // XOR Gb,Eb + (const void *)&gInstructions[ 4088] // XOR Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf = @@ -20571,13 +20795,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_32_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4038] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4120] // XOR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4027] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4109] // XOR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf = @@ -20592,13 +20816,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4016] // XOR Ev,Gv + (const void *)&gInstructions[ 4098] // XOR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4005] // XOR Ev,Gv + (const void *)&gInstructions[ 4087] // XOR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf = @@ -20633,13 +20857,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_31_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4037] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4119] // XOR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4026] // XOR Bv,Ev,Gv + (const void *)&gInstructions[ 4108] // XOR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf = @@ -20654,13 +20878,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4015] // XOR Ev,Gv + (const void *)&gInstructions[ 4097] // XOR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4004] // XOR Ev,Gv + (const void *)&gInstructions[ 4086] // XOR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf = @@ -20706,13 +20930,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_31_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4036] // XOR Bb,Eb,Gb + (const void *)&gInstructions[ 4118] // XOR Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4025] // XOR Bb,Eb,Gb + (const void *)&gInstructions[ 4107] // XOR Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf = @@ -20727,13 +20951,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4014] // XOR Eb,Gb + (const void *)&gInstructions[ 4096] // XOR Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4003] // XOR Eb,Gb + (const void *)&gInstructions[ 4085] // XOR Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf = @@ -20779,13 +21003,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_30_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2500] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2484] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2496] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2480] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf = @@ -20800,13 +21024,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2492] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2476] // SHRD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2488] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2472] // SHRD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf = @@ -20841,13 +21065,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2c_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2498] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2482] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2494] // SHRD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2478] // SHRD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf = @@ -20862,13 +21086,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2490] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2474] // SHRD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2486] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2470] // SHRD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf = @@ -20914,13 +21138,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2577] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2561] // SUB Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2566] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2550] // SUB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf = @@ -20935,13 +21159,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2555] // SUB Gv,Ev + (const void *)&gInstructions[ 2539] // SUB Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2544] // SUB Gv,Ev + (const void *)&gInstructions[ 2528] // SUB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf = @@ -20976,13 +21200,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2576] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2560] // SUB Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2565] // SUB Bv,Gv,Ev + (const void *)&gInstructions[ 2549] // SUB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf = @@ -20997,13 +21221,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2554] // SUB Gv,Ev + (const void *)&gInstructions[ 2538] // SUB Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2543] // SUB Gv,Ev + (const void *)&gInstructions[ 2527] // SUB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf = @@ -21049,13 +21273,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2575] // SUB Bb,Gb,Eb + (const void *)&gInstructions[ 2559] // SUB Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2564] // SUB Bb,Gb,Eb + (const void *)&gInstructions[ 2548] // SUB Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf = @@ -21070,13 +21294,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2553] // SUB Gb,Eb + (const void *)&gInstructions[ 2537] // SUB Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2542] // SUB Gb,Eb + (const void *)&gInstructions[ 2526] // SUB Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf = @@ -21122,13 +21346,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2574] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2558] // SUB Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2563] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2547] // SUB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf = @@ -21143,13 +21367,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2552] // SUB Ev,Gv + (const void *)&gInstructions[ 2536] // SUB Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2541] // SUB Ev,Gv + (const void *)&gInstructions[ 2525] // SUB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf = @@ -21184,13 +21408,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_29_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2573] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2557] // SUB Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2562] // SUB Bv,Ev,Gv + (const void *)&gInstructions[ 2546] // SUB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf = @@ -21205,13 +21429,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2551] // SUB Ev,Gv + (const void *)&gInstructions[ 2535] // SUB Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2540] // SUB Ev,Gv + (const void *)&gInstructions[ 2524] // SUB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf = @@ -21257,13 +21481,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_29_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2572] // SUB Bb,Eb,Gb + (const void *)&gInstructions[ 2556] // SUB Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2561] // SUB Bb,Eb,Gb + (const void *)&gInstructions[ 2545] // SUB Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf = @@ -21278,13 +21502,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2550] // SUB Eb,Gb + (const void *)&gInstructions[ 2534] // SUB Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2539] // SUB Eb,Gb + (const void *)&gInstructions[ 2523] // SUB Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf = @@ -21330,13 +21554,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_28_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2438] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2422] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2434] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2418] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf = @@ -21351,13 +21575,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2430] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2414] // SHLD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2426] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2410] // SHLD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf = @@ -21392,13 +21616,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_24_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2436] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2420] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2432] // SHLD Bv,Ev,Gv,Ib + (const void *)&gInstructions[ 2416] // SHLD Bv,Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf = @@ -21413,13 +21637,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2428] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2412] // SHLD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2424] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2408] // SHLD Ev,Gv,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf = @@ -21465,13 +21689,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_24_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 166] // AND Bv,Gv,Ev + (const void *)&gInstructions[ 158] // AND Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 155] // AND Bv,Gv,Ev + (const void *)&gInstructions[ 147] // AND Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf = @@ -21486,13 +21710,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 144] // AND Gv,Ev + (const void *)&gInstructions[ 136] // AND Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 133] // AND Gv,Ev + (const void *)&gInstructions[ 125] // AND Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf = @@ -21527,13 +21751,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_23_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 165] // AND Bv,Gv,Ev + (const void *)&gInstructions[ 157] // AND Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 154] // AND Bv,Gv,Ev + (const void *)&gInstructions[ 146] // AND Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf = @@ -21548,13 +21772,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 143] // AND Gv,Ev + (const void *)&gInstructions[ 135] // AND Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 132] // AND Gv,Ev + (const void *)&gInstructions[ 124] // AND Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf = @@ -21600,13 +21824,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_23_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 164] // AND Bb,Gb,Eb + (const void *)&gInstructions[ 156] // AND Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 153] // AND Bb,Gb,Eb + (const void *)&gInstructions[ 145] // AND Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf = @@ -21621,13 +21845,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 142] // AND Gb,Eb + (const void *)&gInstructions[ 134] // AND Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 131] // AND Gb,Eb + (const void *)&gInstructions[ 123] // AND Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf = @@ -21673,13 +21897,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_22_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 163] // AND Bv,Ev,Gv + (const void *)&gInstructions[ 155] // AND Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 152] // AND Bv,Ev,Gv + (const void *)&gInstructions[ 144] // AND Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf = @@ -21694,13 +21918,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 141] // AND Ev,Gv + (const void *)&gInstructions[ 133] // AND Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 130] // AND Ev,Gv + (const void *)&gInstructions[ 122] // AND Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf = @@ -21735,13 +21959,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_21_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 162] // AND Bv,Ev,Gv + (const void *)&gInstructions[ 154] // AND Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 151] // AND Bv,Ev,Gv + (const void *)&gInstructions[ 143] // AND Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf = @@ -21756,13 +21980,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 140] // AND Ev,Gv + (const void *)&gInstructions[ 132] // AND Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 129] // AND Ev,Gv + (const void *)&gInstructions[ 121] // AND Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf = @@ -21808,13 +22032,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_21_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 161] // AND Bb,Eb,Gb + (const void *)&gInstructions[ 153] // AND Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 150] // AND Bb,Eb,Gb + (const void *)&gInstructions[ 142] // AND Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf = @@ -21829,13 +22053,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 139] // AND Eb,Gb + (const void *)&gInstructions[ 131] // AND Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 128] // AND Eb,Gb + (const void *)&gInstructions[ 120] // AND Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf = @@ -21881,7 +22105,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_20_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2304] // SBB Bv,Gv,Ev + (const void *)&gInstructions[ 2295] // SBB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf = @@ -21896,7 +22120,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2293] // SBB Gv,Ev + (const void *)&gInstructions[ 2284] // SBB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf = @@ -21931,7 +22155,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2303] // SBB Bv,Gv,Ev + (const void *)&gInstructions[ 2294] // SBB Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf = @@ -21946,7 +22170,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2292] // SBB Gv,Ev + (const void *)&gInstructions[ 2283] // SBB Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf = @@ -21992,7 +22216,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2302] // SBB Bb,Gb,Eb + (const void *)&gInstructions[ 2293] // SBB Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf = @@ -22007,7 +22231,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2291] // SBB Gb,Eb + (const void *)&gInstructions[ 2282] // SBB Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf = @@ -22053,7 +22277,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2301] // SBB Bv,Ev,Gv + (const void *)&gInstructions[ 2292] // SBB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf = @@ -22068,7 +22292,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2290] // SBB Ev,Gv + (const void *)&gInstructions[ 2281] // SBB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf = @@ -22103,7 +22327,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_19_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2300] // SBB Bv,Ev,Gv + (const void *)&gInstructions[ 2291] // SBB Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf = @@ -22118,7 +22342,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2289] // SBB Ev,Gv + (const void *)&gInstructions[ 2280] // SBB Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf = @@ -22164,7 +22388,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_19_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2299] // SBB Bb,Eb,Gb + (const void *)&gInstructions[ 2290] // SBB Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf = @@ -22179,7 +22403,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2288] // SBB Eb,Gb + (const void *)&gInstructions[ 2279] // SBB Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf = @@ -22569,13 +22793,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_10_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1628] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1618] // OR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1617] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1607] // OR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf = @@ -22590,13 +22814,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1606] // OR Gv,Ev + (const void *)&gInstructions[ 1596] // OR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1595] // OR Gv,Ev + (const void *)&gInstructions[ 1585] // OR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf = @@ -22631,13 +22855,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0b_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1627] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1617] // OR Bv,Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1616] // OR Bv,Gv,Ev + (const void *)&gInstructions[ 1606] // OR Bv,Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf = @@ -22652,13 +22876,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1605] // OR Gv,Ev + (const void *)&gInstructions[ 1595] // OR Gv,Ev }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1594] // OR Gv,Ev + (const void *)&gInstructions[ 1584] // OR Gv,Ev }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf = @@ -22704,13 +22928,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1626] // OR Bb,Gb,Eb + (const void *)&gInstructions[ 1616] // OR Bb,Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1615] // OR Bb,Gb,Eb + (const void *)&gInstructions[ 1605] // OR Bb,Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf = @@ -22725,13 +22949,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1604] // OR Gb,Eb + (const void *)&gInstructions[ 1594] // OR Gb,Eb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1593] // OR Gb,Eb + (const void *)&gInstructions[ 1583] // OR Gb,Eb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf = @@ -22777,13 +23001,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1625] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1615] // OR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1614] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1604] // OR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf = @@ -22798,13 +23022,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1603] // OR Ev,Gv + (const void *)&gInstructions[ 1593] // OR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1592] // OR Ev,Gv + (const void *)&gInstructions[ 1582] // OR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf = @@ -22839,13 +23063,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_09_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1624] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1614] // OR Bv,Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1613] // OR Bv,Ev,Gv + (const void *)&gInstructions[ 1603] // OR Bv,Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf = @@ -22860,13 +23084,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1602] // OR Ev,Gv + (const void *)&gInstructions[ 1592] // OR Ev,Gv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1591] // OR Ev,Gv + (const void *)&gInstructions[ 1581] // OR Ev,Gv }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf = @@ -22912,13 +23136,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_09_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1623] // OR Bb,Eb,Gb + (const void *)&gInstructions[ 1613] // OR Bb,Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1612] // OR Bb,Eb,Gb + (const void *)&gInstructions[ 1602] // OR Bb,Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf = @@ -22933,13 +23157,13 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1601] // OR Eb,Gb + (const void *)&gInstructions[ 1591] // OR Eb,Gb }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1590] // OR Eb,Gb + (const void *)&gInstructions[ 1580] // OR Eb,Gb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf = @@ -23614,18 +23838,18 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_04_opcode = /* d1 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp, /* d2 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp, /* d3 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp, - /* d4 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp, + /* d4 */ (const void *)ND_NULL, /* d5 */ (const void *)ND_NULL, /* d6 */ (const void *)ND_NULL, /* d7 */ (const void *)ND_NULL, - /* d8 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp, - /* d9 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp, - /* da */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp, - /* db */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp, - /* dc */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp, - /* dd */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp, - /* de */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp, - /* df */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, /* e0 */ (const void *)ND_NULL, /* e1 */ (const void *)ND_NULL, /* e2 */ (const void *)ND_NULL, @@ -23664,7 +23888,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_04_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2189] // RORX Gy,Ey,Ib + (const void *)&gInstructions[ 2180] // RORX Gy,Ey,Ib }; const ND_TABLE_EX_NF gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf = @@ -23710,7 +23934,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_f0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3114] // VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3159] // VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_cf_pp_01_w = @@ -23736,7 +23960,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_cf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3116] // VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3161] // VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_ce_pp_01_w = @@ -23759,10 +23983,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_ce_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2702] // VCMPPBF16 rK{K},aKq,Hfv,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2724] // VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib + (const void *)&gInstructions[ 2710] // VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_02_w = @@ -23777,7 +24016,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2719] // VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 2705] // VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_00_w = @@ -23796,20 +24035,20 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_c2_pp = /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_00_w, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_02_w, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3734] // VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3806] // VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3733] // VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3805] // VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_73_pp_01_w = @@ -23835,7 +24074,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_73_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_72_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3738] // VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3810] // VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_72_pp_01_w = @@ -23861,13 +24100,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_72_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3725] // VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3797] // VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3724] // VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3796] // VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_71_pp_01_w = @@ -23893,7 +24132,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_71_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_70_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3729] // VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3801] // VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_70_pp_01_w = @@ -23919,13 +24158,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_70_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3079] // VFPCLASSSD rKq{K},aKq,Wsd,Ib + (const void *)&gInstructions[ 3122] // VFPCLASSSD rKq{K},aKq,Wsd,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3081] // VFPCLASSSS rKq{K},aKq,Wss,Ib + (const void *)&gInstructions[ 3124] // VFPCLASSSS rKq{K},aKq,Wss,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_01_w = @@ -23940,7 +24179,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3080] // VFPCLASSSH rKq{K},aKq,Wsh,Ib + (const void *)&gInstructions[ 3123] // VFPCLASSSH rKq{K},aKq,Wsh,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_00_w = @@ -23963,16 +24202,31 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_67_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3118] // VFPCLASSPBF16 rKq{K},aKq,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3076] // VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3119] // VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3078] // VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3121] // VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_01_w = @@ -23987,7 +24241,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3077] // VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib + (const void *)&gInstructions[ 3120] // VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_00_w = @@ -24006,20 +24260,20 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_66_pp = /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3868] // VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3942] // VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3870] // VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3944] // VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_01_w = @@ -24034,7 +24288,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3869] // VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3943] // VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_00_w = @@ -24057,16 +24311,31 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_57_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3938] // VREDUCENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3865] // VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3939] // VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3867] // VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3941] // VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_01_w = @@ -24081,7 +24350,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3866] // VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3940] // VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_00_w = @@ -24100,20 +24369,20 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_56_pp = /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2880] // VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 2910] // VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2881] // VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 2911] // VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_55_pp_01_w = @@ -24139,13 +24408,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_55_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2878] // VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 2908] // VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2879] // VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 2909] // VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_54_pp_01_w = @@ -24168,16 +24437,125 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_54_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3210] // VMINMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3212] // VMINMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_53_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3211] // VMINMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_53_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_53_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3206] // VMINMAXNEPBF16 Vfv{K}{z},aKq,Hfv,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3207] // VMINMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3209] // VMINMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_52_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3208] // VMINMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_52_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_52_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp_03_w, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3851] // VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3923] // VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3852] // VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3924] // VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_51_pp_01_w = @@ -24203,13 +24581,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_51_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3849] // VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3921] // VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3850] // VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3922] // VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_50_pp_01_w = @@ -24235,7 +24613,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_50_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_44_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3373] // VPCLMULQDQ Vfv,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3433] // VPCLMULQDQ Vfv,Hfv,Wfv,Ib }; const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_44_pp = @@ -24252,13 +24630,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_44_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3917] // VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib + (const void *)&gInstructions[ 3994] // VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3916] // VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib + (const void *)&gInstructions[ 3993] // VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_43_pp_01_w = @@ -24281,10 +24659,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_43_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3339] // VMPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2840] // VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 2868] // VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_01_w = @@ -24302,7 +24695,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_42_pp = { /* 00 */ (const void *)ND_NULL, /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_01_w, - /* 02 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_02_w, /* 03 */ (const void *)ND_NULL, } }; @@ -24310,13 +24703,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3404] // VPCMPW rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3464] // VPCMPW rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3377] // VPCMPB rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3437] // VPCMPB rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3f_pp_01_w = @@ -24342,13 +24735,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3403] // VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3463] // VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3400] // VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3460] // VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3e_pp_01_w = @@ -24374,13 +24767,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2869] // VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2899] // VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2867] // VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2897] // VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w = @@ -24417,13 +24810,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3133] // VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3178] // VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3131] // VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3176] // VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w = @@ -24460,13 +24853,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2868] // VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2898] // VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2866] // VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2896] // VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_39_pp_01_w = @@ -24492,13 +24885,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_39_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3132] // VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3177] // VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3130] // VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3175] // VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_38_pp_01_w = @@ -24524,13 +24917,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_38_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3111] // VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3156] // VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3113] // VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3158] // VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_01_w = @@ -24545,7 +24938,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3112] // VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3157] // VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_00_w = @@ -24568,16 +24961,31 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_27_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3152] // VGETMANTPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3108] // VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3153] // VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3110] // VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3155] // VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_01_w = @@ -24592,7 +25000,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3109] // VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3154] // VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_00_w = @@ -24611,20 +25019,20 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_26_pp = /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3820] // VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3892] // VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3819] // VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3891] // VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_25_pp_01_w = @@ -24650,13 +25058,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_25_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3915] // VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib + (const void *)&gInstructions[ 3992] // VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3914] // VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib + (const void *)&gInstructions[ 3991] // VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_23_pp_01_w = @@ -24682,13 +25090,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_23_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3537] // VPINSRQ Vdq,Hdq,Eq,Ib + (const void *)&gInstructions[ 3609] // VPINSRQ Vdq,Hdq,Eq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3535] // VPINSRD Vdq,Hdq,Ed,Ib + (const void *)&gInstructions[ 3607] // VPINSRD Vdq,Hdq,Ed,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = @@ -24725,7 +25133,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_22_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3135] // VINSERTPS Vdq,Hdq,Udq,Ib + (const void *)&gInstructions[ 3180] // VINSERTPS Vdq,Hdq,Udq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = @@ -24742,7 +25150,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3134] // VINSERTPS Vdq,Hdq,Md,Ib + (const void *)&gInstructions[ 3179] // VINSERTPS Vdq,Hdq,Md,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = @@ -24779,7 +25187,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_21_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3532] // VPINSRB Vdq,Hdq,Rd,Ib + (const void *)&gInstructions[ 3604] // VPINSRB Vdq,Hdq,Rd,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = @@ -24796,7 +25204,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3531] // VPINSRB Vdq,Hdq,Mb,Ib + (const void *)&gInstructions[ 3603] // VPINSRB Vdq,Hdq,Mb,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = @@ -24833,13 +25241,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_20_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3399] // VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3459] // VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3378] // VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3438] // VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1f_pp_01_w = @@ -24865,13 +25273,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3402] // VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3462] // VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3401] // VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3461] // VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1e_pp_01_w = @@ -24897,7 +25305,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2772] // VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib + (const void *)&gInstructions[ 2782] // VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1d_pp_01_w = @@ -24923,13 +25331,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2864] // VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2894] // VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2862] // VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib + (const void *)&gInstructions[ 2892] // VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w = @@ -24966,13 +25374,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3128] // VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3173] // VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3126] // VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib + (const void *)&gInstructions[ 3171] // VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w = @@ -25009,13 +25417,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2863] // VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2893] // VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2861] // VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib + (const void *)&gInstructions[ 2891] // VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_19_pp_01_w = @@ -25041,13 +25449,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_19_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3127] // VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3172] // VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3125] // VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib + (const void *)&gInstructions[ 3170] // VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_18_pp_01_w = @@ -25073,7 +25481,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_18_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2871] // VEXTRACTPS Ry,Vdq,Ib + (const void *)&gInstructions[ 2901] // VEXTRACTPS Ry,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = @@ -25090,7 +25498,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2870] // VEXTRACTPS Md,Vdq,Ib + (const void *)&gInstructions[ 2900] // VEXTRACTPS Md,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = @@ -25127,13 +25535,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_17_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3492] // VPEXTRQ Ry,Vdq,Ib + (const void *)&gInstructions[ 3564] // VPEXTRQ Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3488] // VPEXTRD Ry,Vdq,Ib + (const void *)&gInstructions[ 3560] // VPEXTRD Ry,Vdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = @@ -25159,13 +25567,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3491] // VPEXTRQ Mq,Vdq,Ib + (const void *)&gInstructions[ 3563] // VPEXTRQ Mq,Vdq,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3487] // VPEXTRD Md,Vdq,Ib + (const void *)&gInstructions[ 3559] // VPEXTRD Md,Vdq,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = @@ -25211,7 +25619,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_16_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3497] // VPEXTRW Ry,Vdq,Ib + (const void *)&gInstructions[ 3569] // VPEXTRW Ry,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = @@ -25228,7 +25636,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3496] // VPEXTRW Mw,Vdq,Ib + (const void *)&gInstructions[ 3568] // VPEXTRW Mw,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = @@ -25265,7 +25673,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_15_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3484] // VPEXTRB Ry,Vdq,Ib + (const void *)&gInstructions[ 3556] // VPEXTRB Ry,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = @@ -25282,7 +25690,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3483] // VPEXTRB Mb,Vdq,Ib + (const void *)&gInstructions[ 3555] // VPEXTRB Mb,Vdq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = @@ -25319,7 +25727,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_14_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3340] // VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib + (const void *)&gInstructions[ 3400] // VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib }; const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0f_pp = @@ -25336,7 +25744,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3874] // VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 3949] // VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0b_pp_01_w = @@ -25362,7 +25770,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3876] // VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 3951] // VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_01_w = @@ -25377,7 +25785,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3875] // VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib + (const void *)&gInstructions[ 3950] // VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_00_w = @@ -25403,7 +25811,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_09_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3871] // VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 3946] // VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_09_pp_01_w = @@ -25426,10 +25834,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_09_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3945] // VRNDSCALENEPBF16 Vfv{K}{z},aKq,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3873] // VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 3948] // VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_01_w = @@ -25444,7 +25867,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3872] // VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib + (const void *)&gInstructions[ 3947] // VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_00_w = @@ -25463,14 +25886,14 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_08_pp = /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_01_w, /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_05_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3455] // VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3527] // VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_05_pp_01_w = @@ -25496,7 +25919,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_05_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3459] // VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3531] // VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_04_pp_01_w = @@ -25522,13 +25945,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_04_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2684] // VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 2669] // VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2683] // VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 2668] // VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_03_pp_01_w = @@ -25554,7 +25977,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_03_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_01_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3464] // VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib + (const void *)&gInstructions[ 3536] // VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_01_pp_01_w = @@ -25580,7 +26003,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_01_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_00_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3470] // VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib + (const void *)&gInstructions[ 3542] // VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_00_pp_01_w = @@ -25689,8 +26112,8 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode = /* 4f */ (const void *)ND_NULL, /* 50 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp, /* 51 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp, - /* 52 */ (const void *)ND_NULL, - /* 53 */ (const void *)ND_NULL, + /* 52 */ (const void *)&gEvexMap_mmmmm_03_opcode_52_pp, + /* 53 */ (const void *)&gEvexMap_mmmmm_03_opcode_53_pp, /* 54 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp, /* 55 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp, /* 56 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp, @@ -25869,7 +26292,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2504] // SHRX Gy,Ey,By + (const void *)&gInstructions[ 2488] // SHRX Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf = @@ -25895,7 +26318,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2285] // SARX Gy,Ey,By + (const void *)&gInstructions[ 2276] // SARX Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf = @@ -25921,7 +26344,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2442] // SHLX Gy,Ey,By + (const void *)&gInstructions[ 2426] // SHLX Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf = @@ -25947,13 +26370,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 195] // BEXTR Gy,Ey,By + (const void *)&gInstructions[ 187] // BEXTR Gy,Ey,By }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 194] // BEXTR Gy,Ey,By + (const void *)&gInstructions[ 186] // BEXTR Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf = @@ -25990,7 +26413,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1493] // MULX Gy,By,Ey + (const void *)&gInstructions[ 1483] // MULX Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf = @@ -26027,7 +26450,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1720] // PDEP Gy,By,Ey + (const void *)&gInstructions[ 1710] // PDEP Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf = @@ -26053,7 +26476,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1722] // PEXT Gy,By,Ey + (const void *)&gInstructions[ 1712] // PEXT Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf = @@ -26079,13 +26502,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 246] // BZHI Gy,Ey,By + (const void *)&gInstructions[ 238] // BZHI Gy,Ey,By }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 245] // BZHI Gy,Ey,By + (const void *)&gInstructions[ 237] // BZHI Gy,Ey,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf = @@ -26122,13 +26545,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 209] // BLSI By,Ey + (const void *)&gInstructions[ 201] // BLSI By,Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 208] // BLSI By,Ey + (const void *)&gInstructions[ 200] // BLSI By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf = @@ -26154,13 +26577,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 213] // BLSMSK By,Ey + (const void *)&gInstructions[ 205] // BLSMSK By,Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 212] // BLSMSK By,Ey + (const void *)&gInstructions[ 204] // BLSMSK By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf = @@ -26186,13 +26609,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 216] // BLSR By,Ey + (const void *)&gInstructions[ 208] // BLSR By,Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 215] // BLSR By,Ey + (const void *)&gInstructions[ 207] // BLSR By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf = @@ -26244,13 +26667,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 183] // ANDN Gy,By,Ey + (const void *)&gInstructions[ 175] // ANDN Gy,By,Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 182] // ANDN Gy,By,Ey + (const void *)&gInstructions[ 174] // ANDN Gy,By,Ey }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf = @@ -26287,7 +26710,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 645] // CMPNLEXADD My,Gy,By + (const void *)&gInstructions[ 637] // CMPNLEXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf = @@ -26333,7 +26756,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ef_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 637] // CMPLEXADD My,Gy,By + (const void *)&gInstructions[ 629] // CMPLEXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf = @@ -26379,7 +26802,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ee_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 647] // CMPNLXADD My,Gy,By + (const void *)&gInstructions[ 639] // CMPNLXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf = @@ -26425,7 +26848,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ed_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 639] // CMPLXADD My,Gy,By + (const void *)&gInstructions[ 631] // CMPLXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf = @@ -26471,7 +26894,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ec_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 651] // CMPNPXADD My,Gy,By + (const void *)&gInstructions[ 643] // CMPNPXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf = @@ -26517,7 +26940,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_eb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 661] // CMPPXADD My,Gy,By + (const void *)&gInstructions[ 653] // CMPPXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf = @@ -26563,7 +26986,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ea_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 653] // CMPNSXADD My,Gy,By + (const void *)&gInstructions[ 645] // CMPNSXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf = @@ -26609,7 +27032,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 673] // CMPSXADD My,Gy,By + (const void *)&gInstructions[ 665] // CMPSXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf = @@ -26655,7 +27078,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 641] // CMPNBEXADD My,Gy,By + (const void *)&gInstructions[ 633] // CMPNBEXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf = @@ -26701,7 +27124,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 633] // CMPBEXADD My,Gy,By + (const void *)&gInstructions[ 625] // CMPBEXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf = @@ -26747,7 +27170,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 655] // CMPNZXADD My,Gy,By + (const void *)&gInstructions[ 647] // CMPNZXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf = @@ -26793,7 +27216,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 679] // CMPZXADD My,Gy,By + (const void *)&gInstructions[ 671] // CMPZXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf = @@ -26839,7 +27262,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 643] // CMPNCXADD My,Gy,By + (const void *)&gInstructions[ 635] // CMPNCXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf = @@ -26885,7 +27308,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 635] // CMPCXADD My,Gy,By + (const void *)&gInstructions[ 627] // CMPCXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf = @@ -26931,7 +27354,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 649] // CMPNOXADD My,Gy,By + (const void *)&gInstructions[ 641] // CMPNOXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf = @@ -26977,7 +27400,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 657] // CMPOXADD My,Gy,By + (const void *)&gInstructions[ 649] // CMPOXADD My,Gy,By }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf = @@ -27023,7 +27446,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_df_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2675] // VAESDECLAST Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2660] // VAESDECLAST Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_df_pp = @@ -27040,7 +27463,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_df_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2673] // VAESDEC Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2658] // VAESDEC Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_de_pp = @@ -27057,7 +27480,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_de_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2679] // VAESENCLAST Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2664] // VAESENCLAST Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dd_pp = @@ -27074,7 +27497,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2677] // VAESENC Vfv,Hfv,Wfv + (const void *)&gInstructions[ 2662] // VAESENC Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dc_pp = @@ -27088,10 +27511,122 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dc_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3501] // VPDPWSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3505] // VPDPWUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3509] // VPDPWUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d3_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_d3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3499] // VPDPWSUD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3503] // VPDPWUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3507] // VPDPWUUD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_d2_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_d2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3118] // VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3163] // VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cf_pp_01_w = @@ -27117,13 +27652,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3887] // VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3962] // VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3888] // VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3963] // VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cd_pp_01_w = @@ -27149,13 +27684,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3885] // VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae} + (const void *)&gInstructions[ 3960] // VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3886] // VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae} + (const void *)&gInstructions[ 3961] // VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w = @@ -27192,13 +27727,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3859] // VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3931] // VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3860] // VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3932] // VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cb_pp_01_w = @@ -27224,13 +27759,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3857] // VRCP28PD Voq{K}{z},aKq,Woq|B64{sae} + (const void *)&gInstructions[ 3929] // VRCP28PD Voq{K}{z},aKq,Woq|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3858] // VRCP28PS Voq{K}{z},aKq,Woq|B32{sae} + (const void *)&gInstructions[ 3930] // VRCP28PS Voq{K}{z},aKq,Woq|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w = @@ -27267,13 +27802,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ca_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2856] // VEXP2PD Voq{K}{z},aKq,Woq|B64{sae} + (const void *)&gInstructions[ 2886] // VEXP2PD Voq{K}{z},aKq,Woq|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2857] // VEXP2PS Voq{K}{z},aKq,Woq|B32{sae} + (const void *)&gInstructions[ 2887] // VEXP2PS Voq{K}{z},aKq,Woq|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w = @@ -27310,13 +27845,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3907] // VSCATTERPF1QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 3984] // VSCATTERPF1QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3908] // VSCATTERPF1QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 3985] // VSCATTERPF1QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w = @@ -27351,13 +27886,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3903] // VSCATTERPF0QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 3980] // VSCATTERPF0QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3904] // VSCATTERPF0QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 3981] // VSCATTERPF0QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w = @@ -27392,13 +27927,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3096] // VGATHERPF1QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 3139] // VGATHERPF1QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3097] // VGATHERPF1QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 3140] // VGATHERPF1QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w = @@ -27433,13 +27968,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3092] // VGATHERPF0QPD Mvm64n{K},aKq + (const void *)&gInstructions[ 3135] // VGATHERPF0QPD Mvm64n{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3093] // VGATHERPF0QPS Mvm64n{K},aKq + (const void *)&gInstructions[ 3136] // VGATHERPF0QPS Mvm64n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w = @@ -27500,13 +28035,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3905] // VSCATTERPF1DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 3982] // VSCATTERPF1DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3906] // VSCATTERPF1DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 3983] // VSCATTERPF1DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w = @@ -27541,13 +28076,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3901] // VSCATTERPF0DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 3978] // VSCATTERPF0DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3902] // VSCATTERPF0DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 3979] // VSCATTERPF0DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w = @@ -27582,13 +28117,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3094] // VGATHERPF1DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 3137] // VGATHERPF1DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3095] // VGATHERPF1DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 3138] // VGATHERPF1DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w = @@ -27623,13 +28158,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3090] // VGATHERPF0DPD Mvm32h{K},aKq + (const void *)&gInstructions[ 3133] // VGATHERPF0DPD Mvm32h{K},aKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3091] // VGATHERPF0DPS Mvm32n{K},aKq + (const void *)&gInstructions[ 3134] // VGATHERPF0DPS Mvm32n{K},aKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w = @@ -27690,13 +28225,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3418] // VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3478] // VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3417] // VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3477] // VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c4_pp_01_w = @@ -27722,13 +28257,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3063] // VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3105] // VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3066] // VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3108] // VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bf_pp_01_w = @@ -27754,13 +28289,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bf_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3058] // VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3100] // VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3061] // VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3103] // VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_be_pp_01_w = @@ -27786,13 +28321,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_be_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3025] // VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3064] // VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3028] // VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3067] // VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bd_pp_01_w = @@ -27818,13 +28353,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3020] // VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3059] // VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3023] // VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3062] // VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bc_pp_01_w = @@ -27850,13 +28385,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2966] // VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3002] // VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2969] // VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3005] // VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bb_pp_01_w = @@ -27882,13 +28417,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2961] // VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2997] // VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2964] // VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3000] // VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ba_pp_01_w = @@ -27914,13 +28449,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ba_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2907] // VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2940] // VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2910] // VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2943] // VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b9_pp_01_w = @@ -27946,13 +28481,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2902] // VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2935] // VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2905] // VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2938] // VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b8_pp_01_w = @@ -27978,13 +28513,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2981] // VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3017] // VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2984] // VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3020] // VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b7_pp_01_w = @@ -28010,13 +28545,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2932] // VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2965] // VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2935] // VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2968] // VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b6_pp_01_w = @@ -28042,7 +28577,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3557] // VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3629] // VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b5_pp_01_w = @@ -28068,7 +28603,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3559] // VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3631] // VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b4_pp_01_w = @@ -28094,13 +28629,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3053] // VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3094] // VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3056] // VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3097] // VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_af_pp_01_w = @@ -28126,13 +28661,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_af_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3048] // VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3089] // VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3051] // VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3092] // VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ae_pp_01_w = @@ -28158,13 +28693,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ae_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3015] // VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3053] // VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3018] // VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3056] // VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ad_pp_01_w = @@ -28190,13 +28725,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ad_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3010] // VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3048] // VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3013] // VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3051] // VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ac_pp_01_w = @@ -28222,7 +28757,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ac_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2660] // V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq + (const void *)&gInstructions[ 2644] // V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w = @@ -28246,13 +28781,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2956] // VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2991] // VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2959] // VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2994] // VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_01_w = @@ -28278,7 +28813,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ab_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2659] // V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 2643] // V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w = @@ -28313,13 +28848,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2951] // VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2986] // VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2954] // VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2989] // VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_01_w = @@ -28345,13 +28880,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_aa_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2897] // VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2929] // VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2900] // VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2932] // VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a9_pp_01_w = @@ -28377,13 +28912,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2892] // VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2924] // VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2895] // VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2927] // VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a8_pp_01_w = @@ -28409,13 +28944,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2976] // VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3012] // VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2979] // VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3015] // VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a7_pp_01_w = @@ -28441,13 +28976,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2927] // VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2960] // VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2930] // VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2963] // VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a6_pp_01_w = @@ -28473,13 +29008,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3909] // VSCATTERQPD Mvm64n{K},aKq,Vfv + (const void *)&gInstructions[ 3986] // VSCATTERQPD Mvm64n{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3910] // VSCATTERQPS Mvm64n{K},aKq,Vhv + (const void *)&gInstructions[ 3987] // VSCATTERQPS Mvm64n{K},aKq,Vhv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w = @@ -28514,13 +29049,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3899] // VSCATTERDPD Mvm32h{K},aKq,Vfv + (const void *)&gInstructions[ 3976] // VSCATTERDPD Mvm32h{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3900] // VSCATTERDPS Mvm32n{K},aKq,Vfv + (const void *)&gInstructions[ 3977] // VSCATTERDPS Mvm32n{K},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w = @@ -28555,13 +29090,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3710] // VPSCATTERQQ Mvm64n{K},aKq,Vfv + (const void *)&gInstructions[ 3782] // VPSCATTERQQ Mvm64n{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3709] // VPSCATTERQD Mvm64n{K},aKq,Vhv + (const void *)&gInstructions[ 3781] // VPSCATTERQD Mvm64n{K},aKq,Vhv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w = @@ -28596,13 +29131,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3708] // VPSCATTERDQ Mvm32h{K},aKq,Vfv + (const void *)&gInstructions[ 3780] // VPSCATTERDQ Mvm32h{K},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3707] // VPSCATTERDD Mvm32n{K},aKq,Vfv + (const void *)&gInstructions[ 3779] // VPSCATTERDD Mvm32n{K},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w = @@ -28637,13 +29172,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3043] // VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3083] // VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3046] // VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3086] // VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9f_pp_01_w = @@ -28669,13 +29204,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3038] // VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3078] // VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3041] // VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3081] // VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9e_pp_01_w = @@ -28701,13 +29236,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3005] // VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3042] // VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3008] // VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3045] // VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9d_pp_01_w = @@ -28733,13 +29268,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3000] // VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3037] // VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3003] // VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3040] // VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9c_pp_01_w = @@ -28765,7 +29300,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2658] // V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq + (const void *)&gInstructions[ 2642] // V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w = @@ -28789,13 +29324,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2946] // VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2980] // VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2949] // VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2983] // VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_01_w = @@ -28821,7 +29356,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2657] // V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 2641] // V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w = @@ -28856,13 +29391,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2941] // VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2975] // VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2944] // VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2978] // VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_01_w = @@ -28888,13 +29423,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2887] // VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2918] // VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2890] // VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2921] // VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_99_pp_01_w = @@ -28920,13 +29455,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_99_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2882] // VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2913] // VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2885] // VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2916] // VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_98_pp_01_w = @@ -28952,13 +29487,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_98_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2971] // VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3007] // VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2974] // VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3010] // VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_97_pp_01_w = @@ -28984,13 +29519,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_97_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2922] // VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2955] // VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2925] // VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2958] // VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_96_pp_01_w = @@ -29016,13 +29551,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_96_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3098] // VGATHERQPD Vfv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3141] // VGATHERQPD Vfv{K},aKq,Mvm64n }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3100] // VGATHERQPS Vhv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3143] // VGATHERQPS Vhv{K},aKq,Mvm64n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = @@ -29057,13 +29592,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_93_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3086] // VGATHERDPD Vfv{K},aKq,Mvm32h + (const void *)&gInstructions[ 3129] // VGATHERDPD Vfv{K},aKq,Mvm32h }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3088] // VGATHERDPS Vfv{K},aKq,Mvm32n + (const void *)&gInstructions[ 3131] // VGATHERDPS Vfv{K},aKq,Mvm32n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = @@ -29098,13 +29633,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_92_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3507] // VPGATHERQQ Vfv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3579] // VPGATHERQQ Vfv{K},aKq,Mvm64n }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3505] // VPGATHERQD Vhv{K},aKq,Mvm64n + (const void *)&gInstructions[ 3577] // VPGATHERQD Vhv{K},aKq,Mvm64n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = @@ -29139,13 +29674,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_91_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3503] // VPGATHERDQ Vfv{K},aKq,Mvm32h + (const void *)&gInstructions[ 3575] // VPGATHERDQ Vfv{K},aKq,Mvm32h }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3501] // VPGATHERDD Vfv{K},aKq,Mvm32n + (const void *)&gInstructions[ 3573] // VPGATHERDD Vfv{K},aKq,Mvm32n }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = @@ -29180,7 +29715,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_90_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3741] // VPSHUFBITQMB rK{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3813] // VPSHUFBITQMB rK{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8f_pp_01_w = @@ -29206,13 +29741,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3478] // VPERMW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3550] // VPERMW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3441] // VPERMB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3513] // VPERMB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8d_pp_01_w = @@ -29238,13 +29773,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3409] // VPCOMPRESSQ Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3469] // VPCOMPRESSQ Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3408] // VPCOMPRESSD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3468] // VPCOMPRESSD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8b_pp_01_w = @@ -29270,13 +29805,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2732] // VCOMPRESSPD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 2718] // VCOMPRESSPD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2733] // VCOMPRESSPS Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 2719] // VCOMPRESSPS Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8a_pp_01_w = @@ -29302,13 +29837,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3481] // VPEXPANDQ Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3553] // VPEXPANDQ Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3480] // VPEXPANDD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3552] // VPEXPANDD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_89_pp_01_w = @@ -29334,13 +29869,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_89_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2858] // VEXPANDPD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 2888] // VEXPANDPD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2859] // VEXPANDPS Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 2889] // VEXPANDPS Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_88_pp_01_w = @@ -29366,7 +29901,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_88_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_83_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3673] // VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3745] // VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_83_pp_01_w = @@ -29392,13 +29927,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_83_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3474] // VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3546] // VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3475] // VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3547] // VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7f_pp_01_w = @@ -29424,13 +29959,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3476] // VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3548] // VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3473] // VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3545] // VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7e_pp_01_w = @@ -29456,13 +29991,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3477] // VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3549] // VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3472] // VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3544] // VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7d_pp_01_w = @@ -29488,13 +30023,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3368] // VPBROADCASTQ Vfv{K}{z},aKq,Rq + (const void *)&gInstructions[ 3428] // VPBROADCASTQ Vfv{K}{z},aKq,Rq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3363] // VPBROADCASTD Vfv{K}{z},aKq,Rd + (const void *)&gInstructions[ 3423] // VPBROADCASTD Vfv{K}{z},aKq,Rd }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi = @@ -29529,7 +30064,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3371] // VPBROADCASTW Vfv{K}{z},aKq,Rw + (const void *)&gInstructions[ 3431] // VPBROADCASTW Vfv{K}{z},aKq,Rw }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w = @@ -29564,7 +30099,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3360] // VPBROADCASTB Vfv{K}{z},aKq,Rb + (const void *)&gInstructions[ 3420] // VPBROADCASTB Vfv{K}{z},aKq,Rb }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w = @@ -29599,7 +30134,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3370] // VPBROADCASTW Vfv{K}{z},aKq,Ww + (const void *)&gInstructions[ 3430] // VPBROADCASTW Vfv{K}{z},aKq,Ww }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_79_pp_01_w = @@ -29625,7 +30160,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_79_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3359] // VPBROADCASTB Vfv{K}{z},aKq,Wb + (const void *)&gInstructions[ 3419] // VPBROADCASTB Vfv{K}{z},aKq,Wb }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_78_pp_01_w = @@ -29651,13 +30186,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_78_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3446] // VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3518] // VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3447] // VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3519] // VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_77_pp_01_w = @@ -29683,13 +30218,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_77_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3448] // VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3520] // VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3445] // VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3517] // VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_76_pp_01_w = @@ -29715,13 +30250,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_76_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3449] // VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3521] // VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3444] // VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3516] // VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_75_pp_01_w = @@ -29744,16 +30279,42 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_75_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_74_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2725] // VCVTBIASPH2BF8 Vhv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_74_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_74_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3736] // VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3808] // VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3735] // VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3807] // VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_73_pp_01_w = @@ -29794,7 +30355,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2745] // VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 2751] // VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_02_w = @@ -29809,7 +30370,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3737] // VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3809] // VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_01_w = @@ -29835,13 +30396,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_72_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3727] // VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3799] // VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3726] // VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3798] // VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_71_pp_01_w = @@ -29867,7 +30428,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_71_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_70_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3728] // VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3800] // VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_70_pp_01_w = @@ -29893,13 +30454,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_70_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3306] // VP2INTERSECTQ rKq+1,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3366] // VP2INTERSECTQ rKq+1,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3305] // VP2INTERSECTD rKq+1,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3365] // VP2INTERSECTD rKq+1,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_68_pp_03_w = @@ -29922,16 +30483,42 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_68_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_67_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2724] // VCVT2PS2PHX Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_67_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_67_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_67_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_67_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3356] // VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3416] // VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3353] // VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3413] // VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_66_pp_01_w = @@ -29957,13 +30544,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2695] // VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 2680] // VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2696] // VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2681] // VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_65_pp_01_w = @@ -29989,13 +30576,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_65_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3355] // VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3415] // VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3354] // VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3414] // VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_64_pp_01_w = @@ -30021,13 +30608,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_64_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3410] // VPCOMPRESSW Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3470] // VPCOMPRESSW Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3407] // VPCOMPRESSB Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3467] // VPCOMPRESSB Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_63_pp_01_w = @@ -30053,13 +30640,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_63_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3482] // VPEXPANDW Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3554] // VPEXPANDW Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3479] // VPEXPANDB Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3551] // VPEXPANDB Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_62_pp_01_w = @@ -30085,13 +30672,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_62_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2712] // VBROADCASTI64X4 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2697] // VBROADCASTI64X4 Voq{K}{z},aKq,Mqq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2710] // VBROADCASTI32X8 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2695] // VBROADCASTI32X8 Voq{K}{z},aKq,Mqq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w = @@ -30137,13 +30724,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2711] // VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2696] // VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2709] // VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2694] // VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w = @@ -30178,13 +30765,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3367] // VPBROADCASTQ Vfv{K}{z},aKq,Wq + (const void *)&gInstructions[ 3427] // VPBROADCASTQ Vfv{K}{z},aKq,Wq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2708] // VBROADCASTI32X2 Vfv{K}{z},aKq,Wq + (const void *)&gInstructions[ 2693] // VBROADCASTI32X2 Vfv{K}{z},aKq,Wq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_59_pp_01_w = @@ -30210,7 +30797,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_59_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3362] // VPBROADCASTD Vfv{K}{z},aKq,Wd + (const void *)&gInstructions[ 3422] // VPBROADCASTD Vfv{K}{z},aKq,Wd }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_58_pp_01_w = @@ -30236,13 +30823,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_58_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3678] // VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3750] // VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3677] // VPOPCNTD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3749] // VPOPCNTD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_55_pp_01_w = @@ -30268,13 +30855,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_55_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3679] // VPOPCNTW Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3751] // VPOPCNTW Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3676] // VPOPCNTB Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3748] // VPOPCNTB Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_54_pp_01_w = @@ -30300,7 +30887,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_54_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3308] // VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 3368] // VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w = @@ -30335,7 +30922,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3431] // VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3497] // VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_01_w = @@ -30361,7 +30948,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_53_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3307] // VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq + (const void *)&gInstructions[ 3367] // VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w = @@ -30396,7 +30983,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2851] // VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2880] // VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_02_w = @@ -30411,7 +30998,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3429] // VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3495] // VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_01_w = @@ -30423,21 +31010,66 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2882] // VDPPHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_52_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_01_w, /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_02_w, /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod, } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3481] // VPDPBSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3485] // VPDPBSUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3425] // VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3489] // VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_01_w = @@ -30449,21 +31081,66 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3493] // VPDPBUUDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_51_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3479] // VPDPBSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3483] // VPDPBSUD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3423] // VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3487] // VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_01_w = @@ -30475,27 +31152,42 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_01_w = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3491] // VPDPBUUD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_50_pp = { ND_ILUT_EX_PP, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3883] // VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd + (const void *)&gInstructions[ 3958] // VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3884] // VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss + (const void *)&gInstructions[ 3959] // VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4f_pp_01_w = @@ -30521,13 +31213,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3881] // VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3956] // VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3882] // VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3957] // VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4e_pp_01_w = @@ -30553,13 +31245,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3855] // VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd + (const void *)&gInstructions[ 3927] // VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3856] // VRCP14SS Vdq{K}{z},aKq,Hdq,Wss + (const void *)&gInstructions[ 3928] // VRCP14SS Vdq{K}{z},aKq,Hdq,Wss }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4d_pp_01_w = @@ -30585,13 +31277,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3853] // VRCP14PD Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3925] // VRCP14PD Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3854] // VRCP14PS Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3926] // VRCP14PS Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4c_pp_01_w = @@ -30617,7 +31309,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2621] // TILELOADD rTt,Mt + (const void *)&gInstructions[ 2605] // TILELOADD rTt,Mt }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf = @@ -30676,7 +31368,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2626] // TILESTORED Mt,rTt + (const void *)&gInstructions[ 2610] // TILESTORED Mt,rTt }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf = @@ -30735,7 +31427,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2623] // TILELOADDT1 rTt,Mt + (const void *)&gInstructions[ 2607] // TILELOADDT1 rTt,Mt }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf = @@ -30805,7 +31497,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2536] // STTILECFG Moq + (const void *)&gInstructions[ 2520] // STTILECFG Moq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf = @@ -30864,7 +31556,7 @@ const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1315] // LDTILECFG Moq + (const void *)&gInstructions[ 1305] // LDTILECFG Moq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf = @@ -30934,13 +31626,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_49_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3763] // VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3835] // VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3761] // VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3833] // VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_47_pp_01_w = @@ -30966,13 +31658,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_47_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3778] // VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3850] // VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3776] // VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3848] // VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_46_pp_01_w = @@ -30998,13 +31690,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_46_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3796] // VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3868] // VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3794] // VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3866] // VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_45_pp_01_w = @@ -31030,13 +31722,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_45_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3544] // VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3616] // VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3543] // VPLZCNTD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3615] // VPLZCNTD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_44_pp_01_w = @@ -31062,13 +31754,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_44_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3105] // VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3149] // VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3107] // VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3151] // VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_43_pp_01_w = @@ -31094,13 +31786,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_43_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3102] // VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 3146] // VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3104] // VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 3148] // VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_42_pp_01_w = @@ -31126,13 +31818,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_42_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3670] // VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3742] // VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3668] // VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3740] // VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_40_pp_01_w = @@ -31158,13 +31850,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_40_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3580] // VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3652] // VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3578] // VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3650] // VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3f_pp_01_w = @@ -31190,7 +31882,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3581] // VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3653] // VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3e_pp = @@ -31207,13 +31899,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3573] // VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3645] // VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3571] // VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3643] // VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3d_pp_01_w = @@ -31239,7 +31931,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3569] // VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3641] // VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3c_pp = @@ -31256,13 +31948,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3594] // VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3666] // VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3592] // VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3664] // VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3b_pp_01_w = @@ -31288,7 +31980,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3366] // VPBROADCASTMW2D Vfv,mKq + (const void *)&gInstructions[ 3426] // VPBROADCASTMW2D Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w = @@ -31312,7 +32004,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3595] // VPMINUW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3667] // VPMINUW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3a_pp = @@ -31329,13 +32021,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3606] // VPMOVQ2M rKq,Ufv + (const void *)&gInstructions[ 3678] // VPMOVQ2M rKq,Ufv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3598] // VPMOVD2M rKq,Ufv + (const void *)&gInstructions[ 3670] // VPMOVD2M rKq,Ufv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w = @@ -31359,13 +32051,13 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3587] // VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3659] // VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3585] // VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3657] // VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_01_w = @@ -31391,13 +32083,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_39_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3603] // VPMOVM2Q Vfv,mKq + (const void *)&gInstructions[ 3675] // VPMOVM2Q Vfv,mKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3602] // VPMOVM2D Vfv,mKq + (const void *)&gInstructions[ 3674] // VPMOVM2D Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w = @@ -31421,7 +32113,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3583] // VPMINSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3655] // VPMINSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_38_pp = @@ -31438,7 +32130,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_38_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_37_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3393] // VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3453] // VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_37_pp_01_w = @@ -31464,13 +32156,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_37_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3469] // VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64 + (const void *)&gInstructions[ 3541] // VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3442] // VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32 + (const void *)&gInstructions[ 3514] // VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_36_pp_01_w = @@ -31496,7 +32188,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_36_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3608] // VPMOVQD Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3680] // VPMOVQD Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_02_w = @@ -31511,7 +32203,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3651] // VPMOVZXDQ Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3723] // VPMOVZXDQ Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_01_w = @@ -31537,7 +32229,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_35_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3609] // VPMOVQW Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3681] // VPMOVQW Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_34_pp_02_w = @@ -31552,7 +32244,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_34_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3657] // VPMOVZXWQ Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3729] // VPMOVZXWQ Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_34_pp = @@ -31569,7 +32261,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_34_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3600] // VPMOVDW Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3672] // VPMOVDW Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_33_pp_02_w = @@ -31584,7 +32276,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_33_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3654] // VPMOVZXWD Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3726] // VPMOVZXWD Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_33_pp = @@ -31601,7 +32293,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_33_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3607] // VPMOVQB Wev{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3679] // VPMOVQB Wev{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_32_pp_02_w = @@ -31616,7 +32308,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_32_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3645] // VPMOVZXBQ Vfv{K}{z},aKq,Wev + (const void *)&gInstructions[ 3717] // VPMOVZXBQ Vfv{K}{z},aKq,Wev }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_32_pp = @@ -31633,7 +32325,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_32_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3599] // VPMOVDB Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3671] // VPMOVDB Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_31_pp_02_w = @@ -31648,7 +32340,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_31_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3642] // VPMOVZXBD Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3714] // VPMOVZXBD Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_31_pp = @@ -31665,7 +32357,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_31_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3641] // VPMOVWB Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3713] // VPMOVWB Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_30_pp_02_w = @@ -31680,7 +32372,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_30_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3648] // VPMOVZXBW Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3720] // VPMOVZXBW Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_30_pp = @@ -31697,13 +32389,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_30_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3896] // VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er} + (const void *)&gInstructions[ 3973] // VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3898] // VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er} + (const void *)&gInstructions[ 3975] // VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2d_pp_01_w = @@ -31729,13 +32421,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3893] // VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3970] // VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3895] // VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3972] // VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2c_pp_01_w = @@ -31761,7 +32453,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3320] // VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3380] // VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2b_pp_01_w = @@ -31787,7 +32479,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3365] // VPBROADCASTMB2Q Vfv,mKq + (const void *)&gInstructions[ 3425] // VPBROADCASTMB2Q Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w = @@ -31811,7 +32503,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3231] // VMOVNTDQA Vfv,Mfv + (const void *)&gInstructions[ 3287] // VMOVNTDQA Vfv,Mfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w = @@ -31846,13 +32538,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3640] // VPMOVW2M rKq,Ufv + (const void *)&gInstructions[ 3712] // VPMOVW2M rKq,Ufv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3597] // VPMOVB2M rKq,Ufv + (const void *)&gInstructions[ 3669] // VPMOVB2M rKq,Ufv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w = @@ -31876,7 +32568,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3383] // VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3443] // VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_01_w = @@ -31902,13 +32594,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_29_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3604] // VPMOVM2W Vfv,mKq + (const void *)&gInstructions[ 3676] // VPMOVM2W Vfv,mKq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3601] // VPMOVM2B Vfv,mKq + (const void *)&gInstructions[ 3673] // VPMOVM2B Vfv,mKq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w = @@ -31932,7 +32624,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3660] // VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3732] // VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_01_w = @@ -31958,13 +32650,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_28_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3828] // VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3900] // VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3827] // VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3899] // VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_02_w = @@ -31979,13 +32671,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3824] // VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3896] // VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3823] // VPTESTMD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3895] // VPTESTMD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_01_w = @@ -32011,13 +32703,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_27_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3829] // VPTESTNMW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3901] // VPTESTNMW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3826] // VPTESTNMB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3898] // VPTESTNMB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_02_w = @@ -32032,13 +32724,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3825] // VPTESTMW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3897] // VPTESTMW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3822] // VPTESTMB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3894] // VPTESTMB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_01_w = @@ -32064,7 +32756,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_26_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3613] // VPMOVSQD Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3685] // VPMOVSQD Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_02_w = @@ -32079,7 +32771,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3625] // VPMOVSXDQ Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3697] // VPMOVSXDQ Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_01_w = @@ -32105,7 +32797,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_25_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3614] // VPMOVSQW Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3686] // VPMOVSQW Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_24_pp_02_w = @@ -32120,7 +32812,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_24_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3631] // VPMOVSXWQ Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3703] // VPMOVSXWQ Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_24_pp = @@ -32137,7 +32829,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_24_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3611] // VPMOVSDW Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3683] // VPMOVSDW Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_23_pp_02_w = @@ -32152,7 +32844,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_23_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3628] // VPMOVSXWD Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3700] // VPMOVSXWD Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_23_pp = @@ -32169,7 +32861,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_23_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3612] // VPMOVSQB Wev{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3684] // VPMOVSQB Wev{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_22_pp_02_w = @@ -32184,7 +32876,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_22_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3619] // VPMOVSXBQ Vfv{K}{z},aKq,Wev + (const void *)&gInstructions[ 3691] // VPMOVSXBQ Vfv{K}{z},aKq,Wev }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_22_pp = @@ -32201,7 +32893,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_22_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3610] // VPMOVSDB Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3682] // VPMOVSDB Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_21_pp_02_w = @@ -32216,7 +32908,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_21_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3616] // VPMOVSXBD Vfv{K}{z},aKq,Wqv + (const void *)&gInstructions[ 3688] // VPMOVSXBD Vfv{K}{z},aKq,Wqv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_21_pp = @@ -32233,7 +32925,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_21_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3615] // VPMOVSWB Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3687] // VPMOVSWB Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_20_pp_02_w = @@ -32248,7 +32940,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_20_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3622] // VPMOVSXBW Vfv{K}{z},aKq,Whv + (const void *)&gInstructions[ 3694] // VPMOVSXBW Vfv{K}{z},aKq,Whv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_20_pp = @@ -32265,7 +32957,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_20_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3313] // VPABSQ Vfv{K}{z},aKq,Wfv|B64 + (const void *)&gInstructions[ 3373] // VPABSQ Vfv{K}{z},aKq,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1f_pp_01_w = @@ -32291,7 +32983,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3311] // VPABSD Vfv{K}{z},aKq,Wfv|B32 + (const void *)&gInstructions[ 3371] // VPABSD Vfv{K}{z},aKq,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1e_pp_01_w = @@ -32317,7 +33009,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3314] // VPABSW Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3374] // VPABSW Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1d_pp = @@ -32334,7 +33026,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3309] // VPABSB Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3369] // VPABSB Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1c_pp = @@ -32351,13 +33043,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2706] // VBROADCASTF64X4 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2691] // VBROADCASTF64X4 Voq{K}{z},aKq,Mqq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2704] // VBROADCASTF32X8 Voq{K}{z},aKq,Mqq + (const void *)&gInstructions[ 2689] // VBROADCASTF32X8 Voq{K}{z},aKq,Mqq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w = @@ -32403,13 +33095,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2705] // VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2690] // VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2703] // VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq + (const void *)&gInstructions[ 2688] // VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w = @@ -32444,13 +33136,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2713] // VBROADCASTSD Vuv{K}{z},aKq,Wsd + (const void *)&gInstructions[ 2698] // VBROADCASTSD Vuv{K}{z},aKq,Wsd }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2702] // VBROADCASTF32X2 Vuv{K}{z},aKq,Wq + (const void *)&gInstructions[ 2687] // VBROADCASTF32X2 Vuv{K}{z},aKq,Wq }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_19_pp_01_w = @@ -32476,7 +33168,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_19_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2715] // VBROADCASTSS Vfv{K}{z},aKq,Wss + (const void *)&gInstructions[ 2700] // VBROADCASTSS Vfv{K}{z},aKq,Wss }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_18_pp_01_w = @@ -32502,13 +33194,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_18_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3463] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 + (const void *)&gInstructions[ 3535] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3467] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 + (const void *)&gInstructions[ 3539] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w = @@ -32523,13 +33215,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3462] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 + (const void *)&gInstructions[ 3534] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3466] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 + (const void *)&gInstructions[ 3538] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w = @@ -32566,7 +33258,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_16_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3637] // VPMOVUSQD Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3709] // VPMOVUSQD Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_02_w = @@ -32581,13 +33273,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3688] // VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3760] // VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3687] // VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3759] // VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_01_w = @@ -32613,7 +33305,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_15_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3638] // VPMOVUSQW Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3710] // VPMOVUSQW Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_02_w = @@ -32628,13 +33320,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3692] // VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3764] // VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3691] // VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3763] // VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_01_w = @@ -32660,7 +33352,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_14_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3635] // VPMOVUSDW Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3707] // VPMOVUSDW Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_02_w = @@ -32675,7 +33367,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2758] // VCVTPH2PS Vfv{K}{z},aKq,Whv{sae} + (const void *)&gInstructions[ 2766] // VCVTPH2PS Vfv{K}{z},aKq,Whv{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_01_w = @@ -32701,7 +33393,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_13_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3636] // VPMOVUSQB Wev{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3708] // VPMOVUSQB Wev{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_02_w = @@ -32716,7 +33408,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3765] // VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3837] // VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_01_w = @@ -32742,7 +33434,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_12_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3634] // VPMOVUSDB Wqv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3706] // VPMOVUSDB Wqv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_02_w = @@ -32757,7 +33449,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3779] // VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3851] // VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_01_w = @@ -32783,7 +33475,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_11_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3639] // VPMOVUSWB Whv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3711] // VPMOVUSWB Whv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_02_w = @@ -32798,7 +33490,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3798] // VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3870] // VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_01_w = @@ -32824,7 +33516,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_10_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3454] // VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3526] // VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0d_pp_01_w = @@ -32850,7 +33542,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3458] // VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3530] // VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0c_pp_01_w = @@ -32876,7 +33568,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3662] // VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3734] // VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0b_pp = @@ -32893,7 +33585,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_04_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3561] // VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3633] // VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_04_pp = @@ -32910,7 +33602,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_04_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_00_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3739] // VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3811] // VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_00_pp = @@ -33031,7 +33723,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = /* 64 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp, /* 65 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp, /* 66 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp, - /* 67 */ (const void *)ND_NULL, + /* 67 */ (const void *)&gEvexMap_mmmmm_02_opcode_67_pp, /* 68 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp, /* 69 */ (const void *)ND_NULL, /* 6a */ (const void *)ND_NULL, @@ -33044,7 +33736,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = /* 71 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp, /* 72 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp, /* 73 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp, - /* 74 */ (const void *)ND_NULL, + /* 74 */ (const void *)&gEvexMap_mmmmm_02_opcode_74_pp, /* 75 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp, /* 76 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp, /* 77 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp, @@ -33138,8 +33830,8 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = /* cf */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp, /* d0 */ (const void *)ND_NULL, /* d1 */ (const void *)ND_NULL, - /* d2 */ (const void *)ND_NULL, - /* d3 */ (const void *)ND_NULL, + /* d2 */ (const void *)&gEvexMap_mmmmm_02_opcode_d2_pp, + /* d3 */ (const void *)&gEvexMap_mmmmm_02_opcode_d3_pp, /* d4 */ (const void *)ND_NULL, /* d5 */ (const void *)ND_NULL, /* d6 */ (const void *)ND_NULL, @@ -33190,7 +33882,7 @@ const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fe_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3326] // VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3386] // VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fe_pp_01_w = @@ -33216,7 +33908,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fe_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3338] // VPADDW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3398] // VPADDW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fd_pp = @@ -33233,7 +33925,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3324] // VPADDB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3384] // VPADDB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fc_pp = @@ -33250,7 +33942,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3807] // VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3879] // VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fb_pp_01_w = @@ -33276,7 +33968,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3805] // VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3877] // VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fa_pp_01_w = @@ -33302,7 +33994,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fa_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3817] // VPSUBW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3889] // VPSUBW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f9_pp = @@ -33319,7 +34011,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3803] // VPSUBB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3875] // VPSUBB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f8_pp = @@ -33336,7 +34028,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3705] // VPSADBW Vfv,Hfv,Wfv + (const void *)&gInstructions[ 3777] // VPSADBW Vfv,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f6_pp = @@ -33353,7 +34045,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3563] // VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3635] // VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f5_pp = @@ -33370,7 +34062,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3674] // VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3746] // VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f4_pp_01_w = @@ -33396,7 +34088,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f3_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3758] // VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3830] // VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f3_pp_01_w = @@ -33422,7 +34114,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3752] // VPSLLD Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3824] // VPSLLD Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f2_pp_01_w = @@ -33448,7 +34140,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3767] // VPSLLW Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3839] // VPSLLW Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f1_pp = @@ -33465,13 +34157,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3848] // VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3920] // VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3847] // VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3919] // VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_ef_pp_01_w = @@ -33497,7 +34189,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ef_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ee_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3574] // VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3646] // VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ee_pp = @@ -33514,7 +34206,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ee_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ed_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3332] // VPADDSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3392] // VPADDSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ed_pp = @@ -33531,7 +34223,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ed_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ec_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3330] // VPADDSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3390] // VPADDSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ec_pp = @@ -33548,13 +34240,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ec_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3682] // VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3754] // VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3681] // VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3753] // VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_eb_pp_01_w = @@ -33580,7 +34272,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_eb_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ea_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3588] // VPMINSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3660] // VPMINSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ea_pp = @@ -33597,7 +34289,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ea_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3811] // VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3883] // VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e9_pp = @@ -33614,7 +34306,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3809] // VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3881] // VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e8_pp = @@ -33631,7 +34323,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3229] // VMOVNTDQ Mfv,Vfv + (const void *)&gInstructions[ 3285] // VMOVNTDQ Mfv,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w = @@ -33666,7 +34358,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e7_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2747] // VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2753] // VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_03_w = @@ -33681,13 +34373,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2779] // VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2789] // VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2734] // VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32 + (const void *)&gInstructions[ 2729] // VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_02_w = @@ -33702,7 +34394,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2804] // VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2816] // VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_01_w = @@ -33728,7 +34420,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3666] // VPMULHW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3738] // VPMULHW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e5_pp = @@ -33745,7 +34437,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3664] // VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3736] // VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e4_pp = @@ -33762,7 +34454,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3350] // VPAVGW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3410] // VPAVGW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e3_pp = @@ -33779,13 +34471,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3775] // VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3847] // VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3771] // VPSRAD Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3843] // VPSRAD Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e2_pp_01_w = @@ -33811,7 +34503,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3781] // VPSRAW Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3853] // VPSRAW Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e1_pp = @@ -33828,7 +34520,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e0_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3348] // VPAVGB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3408] // VPAVGB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e0_pp = @@ -33845,13 +34537,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e0_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3346] // VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3406] // VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3345] // VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3405] // VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_df_pp_01_w = @@ -33877,7 +34569,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_df_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3576] // VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3648] // VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_de_pp = @@ -33894,7 +34586,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_de_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3336] // VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3396] // VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dd_pp = @@ -33911,7 +34603,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dd_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3334] // VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3394] // VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dc_pp = @@ -33928,13 +34620,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dc_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3347] // VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3407] // VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3343] // VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3403] // VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_db_pp_01_w = @@ -33960,7 +34652,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_db_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_da_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3590] // VPMINUB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3662] // VPMINUB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_da_pp = @@ -33977,7 +34669,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_da_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3815] // VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3887] // VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d9_pp = @@ -33994,7 +34686,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d9_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3813] // VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3885] // VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d8_pp = @@ -34011,14 +34703,20 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d8_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3240] // VMOVQ Wq,Vdq + (const void *)&gInstructions[ 3296] // VMOVQ Wq,Vdq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3239] // VMOVD Wd,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_00_leaf, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf, } }; @@ -34048,7 +34746,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3671] // VPMULLW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3743] // VPMULLW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d5_pp = @@ -34065,7 +34763,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3328] // VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3388] // VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d4_pp_01_w = @@ -34091,7 +34789,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d3_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3791] // VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3863] // VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d3_pp_01_w = @@ -34117,7 +34815,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d3_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3785] // VPSRLD Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3857] // VPSRLD Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d2_pp_01_w = @@ -34143,7 +34841,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3800] // VPSRLW Vfv{K}{z},aKq,Hfv,Wdq + (const void *)&gInstructions[ 3872] // VPSRLW Vfv{K}{z},aKq,Hfv,Wdq }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d1_pp = @@ -34160,7 +34858,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d1_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3918] // VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib + (const void *)&gInstructions[ 3995] // VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_01_w = @@ -34175,7 +34873,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3920] // VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib + (const void *)&gInstructions[ 3997] // VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_00_w = @@ -34201,7 +34899,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c6_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3495] // VPEXTRW Gy,Udq,Ib + (const void *)&gInstructions[ 3567] // VPEXTRW Gy,Udq,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l = @@ -34238,7 +34936,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c5_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3540] // VPINSRW Vdq,Hdq,Rv,Ib + (const void *)&gInstructions[ 3612] // VPINSRW Vdq,Hdq,Rv,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = @@ -34255,7 +34953,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3539] // VPINSRW Vdq,Hdq,Mw,Ib + (const void *)&gInstructions[ 3611] // VPINSRW Vdq,Hdq,Mw,Ib }; const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l = @@ -34292,7 +34990,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c4_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2722] // VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib + (const void *)&gInstructions[ 2708] // VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_03_w = @@ -34307,7 +35005,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2725] // VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib + (const void *)&gInstructions[ 2711] // VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_02_w = @@ -34322,7 +35020,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2717] // VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib + (const void *)&gInstructions[ 2703] // VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_01_w = @@ -34337,7 +35035,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2720] // VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib + (const void *)&gInstructions[ 2706] // VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_00_w = @@ -34363,7 +35061,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c2_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1258] // KMOVQ Gy,mKq + (const void *)&gInstructions[ 1248] // KMOVQ Gy,mKq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf = @@ -34378,7 +35076,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1248] // KMOVD Gy,mKd + (const void *)&gInstructions[ 1238] // KMOVD Gy,mKd }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf = @@ -34422,7 +35120,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1238] // KMOVB Gy,mKb + (const void *)&gInstructions[ 1228] // KMOVB Gy,mKb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf = @@ -34466,7 +35164,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1268] // KMOVW Gy,mKw + (const void *)&gInstructions[ 1258] // KMOVW Gy,mKw }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf = @@ -34521,7 +35219,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_93_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1257] // KMOVQ rKq,Ry + (const void *)&gInstructions[ 1247] // KMOVQ rKq,Ry }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf = @@ -34536,7 +35234,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1247] // KMOVD rKd,Ry + (const void *)&gInstructions[ 1237] // KMOVD rKd,Ry }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf = @@ -34580,7 +35278,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1237] // KMOVB rKb,Ry + (const void *)&gInstructions[ 1227] // KMOVB rKb,Ry }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf = @@ -34624,7 +35322,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1267] // KMOVW rKw,Ry + (const void *)&gInstructions[ 1257] // KMOVW rKw,Ry }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf = @@ -34679,7 +35377,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_92_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1246] // KMOVD Md,rKd + (const void *)&gInstructions[ 1236] // KMOVD Md,rKd }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf = @@ -34694,7 +35392,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1236] // KMOVB Mb,rKb + (const void *)&gInstructions[ 1226] // KMOVB Mb,rKb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf = @@ -34738,7 +35436,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1256] // KMOVQ Mq,rKq + (const void *)&gInstructions[ 1246] // KMOVQ Mq,rKq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf = @@ -34753,7 +35451,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1266] // KMOVW Mw,rKw + (const void *)&gInstructions[ 1256] // KMOVW Mw,rKw }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf = @@ -34808,7 +35506,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_91_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1245] // KMOVD rKd,mKd + (const void *)&gInstructions[ 1235] // KMOVD rKd,mKd }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf = @@ -34823,7 +35521,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1235] // KMOVB rKb,mKb + (const void *)&gInstructions[ 1225] // KMOVB rKb,mKb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf = @@ -34858,7 +35556,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1244] // KMOVD rKd,Md + (const void *)&gInstructions[ 1234] // KMOVD rKd,Md }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf = @@ -34873,7 +35571,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1234] // KMOVB rKb,Mb + (const void *)&gInstructions[ 1224] // KMOVB rKb,Mb }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf = @@ -34917,7 +35615,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1255] // KMOVQ rKq,mKq + (const void *)&gInstructions[ 1245] // KMOVQ rKq,mKq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf = @@ -34932,7 +35630,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1265] // KMOVW rKw,mKw + (const void *)&gInstructions[ 1255] // KMOVW rKw,mKw }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf = @@ -34967,7 +35665,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1254] // KMOVQ rKq,Mq + (const void *)&gInstructions[ 1244] // KMOVQ rKq,Mq }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf = @@ -34982,7 +35680,7 @@ const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1264] // KMOVW rKw,Mw + (const void *)&gInstructions[ 1254] // KMOVW rKw,Mw }; const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf = @@ -35037,13 +35735,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_90_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3200] // VMOVDQU16 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3256] // VMOVDQU16 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3206] // VMOVDQU8 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3262] // VMOVDQU8 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_03_w = @@ -35058,13 +35756,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3204] // VMOVDQU64 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3260] // VMOVDQU64 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3202] // VMOVDQU32 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3258] // VMOVDQU32 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_02_w = @@ -35079,13 +35777,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3196] // VMOVDQA64 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3252] // VMOVDQA64 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3194] // VMOVDQA32 Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3250] // VMOVDQA32 Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_01_w = @@ -35111,14 +35809,20 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3239] // VMOVQ Vdq,Wq + (const void *)&gInstructions[ 3295] // VMOVQ Vdq,Wq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3238] // VMOVD Vdq,Wd }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w = { ND_ILUT_EX_W, { - /* 00 */ (const void *)ND_NULL, + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_00_leaf, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf, } }; @@ -35137,13 +35841,13 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_7e_pp_02_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3238] // VMOVQ Ey,Vdq + (const void *)&gInstructions[ 3294] // VMOVQ Ey,Vdq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3183] // VMOVD Ey,Vdq + (const void *)&gInstructions[ 3237] // VMOVD Ey,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi = @@ -35180,13 +35884,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2835] // VCVTUSI2SD Vdq,Hdq{er},Ey + (const void *)&gInstructions[ 2863] // VCVTUSI2SD Vdq,Hdq{er},Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2834] // VCVTUSI2SD Vdq,Hdq,Ey + (const void *)&gInstructions[ 2862] // VCVTUSI2SD Vdq,Hdq,Ey }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_03_wi = @@ -35201,19 +35905,19 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_03_wi = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2837] // VCVTUSI2SS Vss,Hss{er},Ey + (const void *)&gInstructions[ 2865] // VCVTUSI2SS Vss,Hss{er},Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2753] // VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2759] // VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2776] // VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er} + (const void *)&gInstructions[ 2786] // VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_01_w = @@ -35239,13 +35943,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2833] // VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2861] // VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2830] // VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2858] // VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_03_w = @@ -35260,13 +35964,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2831] // VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2859] // VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2828] // VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32 + (const void *)&gInstructions[ 2856] // VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_02_w = @@ -35281,13 +35985,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2806] // VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2819] // VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2817] // VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2838] // VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_01_w = @@ -35313,25 +36017,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2787] // VCVTSD2USI Gy,Wsd{er} + (const void *)&gInstructions[ 2797] // VCVTSD2USI Gy,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2803] // VCVTSS2USI Gy,Wss{er} + (const void *)&gInstructions[ 2813] // VCVTSS2USI Gy,Wss{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2755] // VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2761] // VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2778] // VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er} + (const void *)&gInstructions[ 2788] // VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_01_w = @@ -35346,13 +36050,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2754] // VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2760] // VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2777] // VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2787] // VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_00_w = @@ -35378,25 +36082,25 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_79_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2822] // VCVTTSD2USI Gy,Wsd{sae} + (const void *)&gInstructions[ 2847] // VCVTTSD2USI Gy,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2827] // VCVTTSS2USI Gy,Wss{sae} + (const void *)&gInstructions[ 2854] // VCVTTSS2USI Gy,Wss{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2808] // VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2823] // VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2819] // VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2842] // VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_01_w = @@ -35411,13 +36115,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2807] // VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae} + (const void *)&gInstructions[ 2821] // VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2818] // VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2840] // VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_00_w = @@ -35443,7 +36147,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_78_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_76_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3381] // VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3441] // VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_76_pp = @@ -35460,7 +36164,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_76_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_75_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3385] // VPCMPEQW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3445] // VPCMPEQW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_75_pp = @@ -35474,10 +36178,40 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_75_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2736] // VCVTNE2PH2BF8 Vfv{K}{z},aKq,Hfv,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_74_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2747] // VCVTNEPH2BF8 Vhv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_74_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3379] // VPCMPEQB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3439] // VPCMPEQB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_74_pp = @@ -35486,21 +36220,21 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_74_pp = { /* 00 */ (const void *)ND_NULL, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_01_leaf, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_03_w, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3755] // VPSLLDQ Hfv,Wfv,Ib + (const void *)&gInstructions[ 3827] // VPSLLDQ Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3757] // VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3829] // VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w = @@ -35515,13 +36249,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3788] // VPSRLDQ Hfv,Wfv,Ib + (const void *)&gInstructions[ 3860] // VPSRLDQ Hfv,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3790] // VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3862] // VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w = @@ -35562,7 +36296,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_73_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3751] // VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3823] // VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w = @@ -35577,13 +36311,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3774] // VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3846] // VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3770] // VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3842] // VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w = @@ -35598,7 +36332,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3784] // VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3856] // VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w = @@ -35613,13 +36347,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3686] // VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3758] // VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3685] // VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3757] // VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w = @@ -35634,13 +36368,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3690] // VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib + (const void *)&gInstructions[ 3762] // VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3689] // VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3761] // VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w = @@ -35681,19 +36415,19 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_72_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3766] // VPSLLW Hfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3838] // VPSLLW Hfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3780] // VPSRAW Hfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3852] // VPSRAW Hfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3799] // VPSRLW Hfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3871] // VPSRLW Hfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg = @@ -35725,19 +36459,19 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_71_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3746] // VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3818] // VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3744] // VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib + (const void *)&gInstructions[ 3816] // VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3742] // VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib + (const void *)&gInstructions[ 3814] // VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_70_pp_01_w = @@ -35763,13 +36497,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_70_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3199] // VMOVDQU16 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3255] // VMOVDQU16 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3205] // VMOVDQU8 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3261] // VMOVDQU8 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_03_w = @@ -35784,13 +36518,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3203] // VMOVDQU64 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3259] // VMOVDQU64 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3201] // VMOVDQU32 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3257] // VMOVDQU32 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_02_w = @@ -35805,13 +36539,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3195] // VMOVDQA64 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3251] // VMOVDQA64 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3193] // VMOVDQA32 Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3249] // VMOVDQA32 Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_01_w = @@ -35837,13 +36571,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3237] // VMOVQ Vdq,Eq + (const void *)&gInstructions[ 3293] // VMOVQ Vdq,Eq }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3182] // VMOVD Vdq,Ed + (const void *)&gInstructions[ 3236] // VMOVD Vdq,Ed }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi = @@ -35880,7 +36614,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3834] // VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3906] // VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6d_pp_01_w = @@ -35906,7 +36640,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3842] // VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3914] // VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6c_pp_01_w = @@ -35932,7 +36666,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3316] // VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3376] // VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6b_pp_01_w = @@ -35958,7 +36692,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3832] // VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3904] // VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6a_pp_01_w = @@ -35984,7 +36718,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_69_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3836] // VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3908] // VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_69_pp = @@ -36001,7 +36735,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_69_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_68_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3830] // VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3902] // VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_68_pp = @@ -36018,7 +36752,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_68_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_67_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3322] // VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3382] // VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_67_pp = @@ -36035,7 +36769,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_67_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_66_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3391] // VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3451] // VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_66_pp_01_w = @@ -36061,7 +36795,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_66_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_65_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3395] // VPCMPGTW rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3455] // VPCMPGTW rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_65_pp = @@ -36078,7 +36812,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_65_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_64_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3389] // VPCMPGTB rKq{K},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3449] // VPCMPGTB rKq{K},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_64_pp = @@ -36095,7 +36829,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_64_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_63_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3318] // VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3378] // VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_63_pp = @@ -36112,7 +36846,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_63_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_62_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3840] // VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3912] // VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_62_pp_01_w = @@ -36138,7 +36872,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_62_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_61_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3844] // VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3916] // VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_61_pp = @@ -36155,7 +36889,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_61_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_60_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3838] // VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv + (const void *)&gInstructions[ 3910] // VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_60_pp = @@ -36172,7 +36906,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_60_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3150] // VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3196] // VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_03_w = @@ -36187,7 +36921,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3153] // VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3199] // VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_02_w = @@ -36202,7 +36936,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3145] // VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} + (const void *)&gInstructions[ 3191] // VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_01_w = @@ -36217,7 +36951,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3148] // VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} + (const void *)&gInstructions[ 3194] // VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_00_w = @@ -36243,7 +36977,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2846] // VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2875] // VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_03_w = @@ -36258,7 +36992,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2849] // VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2878] // VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_02_w = @@ -36273,7 +37007,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2841] // VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2870] // VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_01_w = @@ -36288,7 +37022,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2844] // VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2873] // VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_00_w = @@ -36314,7 +37048,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5e_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3165] // VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae} + (const void *)&gInstructions[ 3219] // VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_03_w = @@ -36329,7 +37063,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3168] // VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 3222] // VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_02_w = @@ -36344,7 +37078,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3160] // VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} + (const void *)&gInstructions[ 3214] // VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_01_w = @@ -36359,7 +37093,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3163] // VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} + (const void *)&gInstructions[ 3217] // VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_00_w = @@ -36385,7 +37119,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3943] // VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 4022] // VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_03_w = @@ -36400,7 +37134,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3946] // VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 4025] // VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_02_w = @@ -36415,7 +37149,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3938] // VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 4017] // VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_01_w = @@ -36430,7 +37164,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3941] // VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 4020] // VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_00_w = @@ -36456,7 +37190,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2815] // VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae} + (const void *)&gInstructions[ 2833] // VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_02_w = @@ -36471,7 +37205,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2767] // VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2775] // VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_01_w = @@ -36486,13 +37220,13 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2781] // VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2791] // VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2738] // VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 2733] // VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_00_w = @@ -36518,7 +37252,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2785] // VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2795] // VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_03_w = @@ -36533,7 +37267,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2798] // VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae} + (const void *)&gInstructions[ 2808] // VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_02_w = @@ -36548,7 +37282,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2750] // VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 2756] // VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_01_w = @@ -36563,7 +37297,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2769] // VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae} + (const void *)&gInstructions[ 2779] // VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_00_w = @@ -36589,7 +37323,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3293] // VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 3353] // VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_03_w = @@ -36604,7 +37338,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3296] // VMULSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 3356] // VMULSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_02_w = @@ -36619,7 +37353,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3288] // VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 3348] // VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_01_w = @@ -36634,7 +37368,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3291] // VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 3351] // VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_00_w = @@ -36660,7 +37394,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_59_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2666] // VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 2651] // VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_03_w = @@ -36675,7 +37409,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2669] // VADDSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 2654] // VADDSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_02_w = @@ -36690,7 +37424,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2661] // VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} + (const void *)&gInstructions[ 2646] // VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_01_w = @@ -36705,7 +37439,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2664] // VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} + (const void *)&gInstructions[ 2649] // VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_00_w = @@ -36731,7 +37465,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_58_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3963] // VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 4045] // VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_01_w = @@ -36746,7 +37480,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3965] // VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 4047] // VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_00_w = @@ -36772,7 +37506,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_57_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3301] // VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 3361] // VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_01_w = @@ -36787,7 +37521,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3303] // VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 3363] // VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_00_w = @@ -36813,7 +37547,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_56_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2685] // VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 2670] // VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_01_w = @@ -36828,7 +37562,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2687] // VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2672] // VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_00_w = @@ -36854,7 +37588,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_55_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2689] // VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 2674] // VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_01_w = @@ -36869,7 +37603,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2691] // VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 2676] // VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_00_w = @@ -36895,7 +37629,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_54_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_03_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3932] // VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er} + (const void *)&gInstructions[ 4010] // VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_03_w = @@ -36910,7 +37644,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_03_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3935] // VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er} + (const void *)&gInstructions[ 4013] // VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_02_w = @@ -36925,7 +37659,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3927] // VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er} + (const void *)&gInstructions[ 4005] // VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_01_w = @@ -36940,7 +37674,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3930] // VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er} + (const void *)&gInstructions[ 4008] // VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_00_w = @@ -36963,10 +37697,62 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_51_pp = } }; +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2723] // VCOMXSS Vdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2f_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2721] // VCOMXSD Vdq,Wsd{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2f_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2727] // VCOMISD Vdq,Wsd{sae} + (const void *)&gInstructions[ 2713] // VCOMISD Vdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_01_w = @@ -36981,7 +37767,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2730] // VCOMISS Vdq,Wss{sae} + (const void *)&gInstructions[ 2716] // VCOMISS Vdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_00_w = @@ -36999,6 +37785,58 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2f_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4036] // VUCOMXSS Vdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2e_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4034] // VUCOMXSD Vdq,Wsd{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_2e_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_l_00_w, + /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)ND_NULL, /* 03 */ (const void *)ND_NULL, } @@ -37007,7 +37845,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2f_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3950] // VUCOMISD Vdq,Wsd{sae} + (const void *)&gInstructions[ 4029] // VUCOMISD Vdq,Wsd{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_01_w = @@ -37022,7 +37860,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3953] // VUCOMISS Vdq,Wss{sae} + (const void *)&gInstructions[ 4032] // VUCOMISS Vdq,Wss{sae} }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_00_w = @@ -37040,21 +37878,21 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2e_pp = { /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_00_w, /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_01_w, - /* 02 */ (const void *)ND_NULL, - /* 03 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_03_l, } }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2783] // VCVTSD2SI Gy,Wsd{er} + (const void *)&gInstructions[ 2793] // VCVTSD2SI Gy,Wsd{er} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2801] // VCVTSS2SI Gy,Wss{er} + (const void *)&gInstructions[ 2811] // VCVTSS2SI Gy,Wss{er} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2d_pp = @@ -37071,13 +37909,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2d_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2820] // VCVTTSD2SI Gy,Wsd{sae} + (const void *)&gInstructions[ 2844] // VCVTTSD2SI Gy,Wsd{sae} }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2825] // VCVTTSS2SI Gy,Wss{sae} + (const void *)&gInstructions[ 2851] // VCVTTSS2SI Gy,Wss{sae} }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2c_pp = @@ -37094,7 +37932,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2c_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3233] // VMOVNTPD Mfv,Vfv + (const void *)&gInstructions[ 3289] // VMOVNTPD Mfv,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w = @@ -37118,7 +37956,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3235] // VMOVNTPS Mfv,Vfv + (const void *)&gInstructions[ 3291] // VMOVNTPS Mfv,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w = @@ -37153,13 +37991,13 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2b_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2793] // VCVTSI2SD Vdq,Hdq{er},Ey + (const void *)&gInstructions[ 2803] // VCVTSI2SD Vdq,Hdq{er},Ey }; const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2792] // VCVTSI2SD Vdq,Hdq,Ey + (const void *)&gInstructions[ 2802] // VCVTSI2SD Vdq,Hdq,Ey }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2a_pp_03_wi = @@ -37174,7 +38012,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2a_pp_03_wi = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2796] // VCVTSI2SS Vdq,Hdq{er},Ey + (const void *)&gInstructions[ 2806] // VCVTSI2SS Vdq,Hdq{er},Ey }; const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2a_pp = @@ -37191,7 +38029,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2a_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3175] // VMOVAPD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3229] // VMOVAPD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_01_w = @@ -37206,7 +38044,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3179] // VMOVAPS Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3233] // VMOVAPS Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_00_w = @@ -37232,7 +38070,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_29_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3174] // VMOVAPD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3228] // VMOVAPD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_01_w = @@ -37247,7 +38085,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3178] // VMOVAPS Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3232] // VMOVAPS Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_00_w = @@ -37273,7 +38111,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_28_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3210] // VMOVHPD Mq,Vdq + (const void *)&gInstructions[ 3266] // VMOVHPD Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w = @@ -37308,7 +38146,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3214] // VMOVHPS Mq,Vdq + (const void *)&gInstructions[ 3270] // VMOVHPS Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w = @@ -37354,7 +38192,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_17_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3257] // VMOVSHDUP Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3313] // VMOVSHDUP Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_02_w = @@ -37369,7 +38207,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3209] // VMOVHPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3265] // VMOVHPD Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w = @@ -37404,7 +38242,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3217] // VMOVLHPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3273] // VMOVLHPS Vdq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w = @@ -37430,7 +38268,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3213] // VMOVHPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3269] // VMOVHPS Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w = @@ -37476,7 +38314,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_16_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3955] // VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 4037] // VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_01_w = @@ -37491,7 +38329,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3957] // VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 4039] // VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_00_w = @@ -37517,7 +38355,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_15_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3959] // VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64 + (const void *)&gInstructions[ 4041] // VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_01_w = @@ -37532,7 +38370,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3961] // VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32 + (const void *)&gInstructions[ 4043] // VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32 }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_00_w = @@ -37558,7 +38396,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_14_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3220] // VMOVLPD Mq,Vdq + (const void *)&gInstructions[ 3276] // VMOVLPD Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w = @@ -37593,7 +38431,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3224] // VMOVLPS Mq,Vdq + (const void *)&gInstructions[ 3280] // VMOVLPS Mq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w = @@ -37639,7 +38477,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_13_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3188] // VMOVDDUP Voq{K}{z},aKq,Woq + (const void *)&gInstructions[ 3244] // VMOVDDUP Voq{K}{z},aKq,Woq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w = @@ -37654,7 +38492,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3187] // VMOVDDUP Vqq{K}{z},aKq,Wqq + (const void *)&gInstructions[ 3243] // VMOVDDUP Vqq{K}{z},aKq,Wqq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w = @@ -37669,7 +38507,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3186] // VMOVDDUP Vdq{K}{z},aKq,Wq + (const void *)&gInstructions[ 3242] // VMOVDDUP Vdq{K}{z},aKq,Wq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w = @@ -37695,7 +38533,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_03_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3259] // VMOVSLDUP Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3315] // VMOVSLDUP Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_02_w = @@ -37710,7 +38548,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_02_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3219] // VMOVLPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3275] // VMOVLPD Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w = @@ -37745,7 +38583,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3207] // VMOVHLPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3263] // VMOVHLPS Vdq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w = @@ -37771,7 +38609,7 @@ const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3223] // VMOVLPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3279] // VMOVLPS Vdq,Hdq,Mq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w = @@ -37817,7 +38655,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_12_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3248] // VMOVSD Udq{K}{z},aKq,Hdq,Vdq + (const void *)&gInstructions[ 3304] // VMOVSD Udq{K}{z},aKq,Hdq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w = @@ -37832,7 +38670,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3247] // VMOVSD Msd{K},aKq,Vdq + (const void *)&gInstructions[ 3303] // VMOVSD Msd{K},aKq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w = @@ -37856,7 +38694,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3264] // VMOVSS Udq{K}{z},aKq,Hdq,Vdq + (const void *)&gInstructions[ 3320] // VMOVSS Udq{K}{z},aKq,Hdq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w = @@ -37871,7 +38709,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3263] // VMOVSS Mss{K},aKq,Vdq + (const void *)&gInstructions[ 3319] // VMOVSS Mss{K},aKq,Vdq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w = @@ -37895,7 +38733,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3270] // VMOVUPD Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3326] // VMOVUPD Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_01_w = @@ -37910,7 +38748,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3274] // VMOVUPS Wfv{K}{z},aKq,Vfv + (const void *)&gInstructions[ 3330] // VMOVUPS Wfv{K}{z},aKq,Vfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_00_w = @@ -37936,7 +38774,7 @@ const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_11_pp = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3246] // VMOVSD Vdq{K}{z},aKq,Hdq,Udq + (const void *)&gInstructions[ 3302] // VMOVSD Vdq{K}{z},aKq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w = @@ -37951,7 +38789,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3245] // VMOVSD Vdq{K}{z},aKq,Msd + (const void *)&gInstructions[ 3301] // VMOVSD Vdq{K}{z},aKq,Msd }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w = @@ -37975,7 +38813,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3262] // VMOVSS Vdq{K}{z},aKq,Hdq,Udq + (const void *)&gInstructions[ 3318] // VMOVSS Vdq{K}{z},aKq,Hdq,Udq }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w = @@ -37990,7 +38828,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3261] // VMOVSS Vdq{K}{z},aKq,Mss + (const void *)&gInstructions[ 3317] // VMOVSS Vdq{K}{z},aKq,Mss }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w = @@ -38014,7 +38852,7 @@ const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3269] // VMOVUPD Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3325] // VMOVUPD Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_01_w = @@ -38029,7 +38867,7 @@ const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_01_w = const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3273] // VMOVUPS Vfv{K}{z},aKq,Wfv + (const void *)&gInstructions[ 3329] // VMOVUPS Vfv{K}{z},aKq,Wfv }; const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_00_w = diff --git a/bddisasm/include/bdx86_table_root.h b/bddisasm/include/bdx86_table_root.h index 79f2bfa..2c356a9 100644 --- a/bddisasm/include/bdx86_table_root.h +++ b/bddisasm/include/bdx86_table_root.h @@ -13,13 +13,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1975] // PUSH Ev + (const void *)&gInstructions[ 1965] // PUSH Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1194] // JMPF Mp + (const void *)&gInstructions[ 1184] // JMPF Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_05_modrmmod = @@ -34,13 +34,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1189] // JMP Ev + (const void *)&gInstructions[ 1179] // JMP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 251] // CALLF Mp + (const void *)&gInstructions[ 243] // CALLF Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_03_modrmmod = @@ -55,19 +55,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 249] // CALL Ev + (const void *)&gInstructions[ 241] // CALL Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 881] // DEC Ev + (const void *)&gInstructions[ 873] // DEC Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1147] // INC Ev + (const void *)&gInstructions[ 1137] // INC Ev }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_ff_modrmreg = @@ -88,13 +88,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_ff_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fe_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 880] // DEC Eb + (const void *)&gInstructions[ 872] // DEC Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fe_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1146] // INC Eb + (const void *)&gInstructions[ 1136] // INC Eb }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_fe_modrmreg = @@ -115,85 +115,85 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_fe_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2522] // STD + (const void *)&gInstructions[ 2506] // STD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 561] // CLD + (const void *)&gInstructions[ 553] // CLD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2524] // STI + (const void *)&gInstructions[ 2508] // STI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 568] // CLI + (const void *)&gInstructions[ 560] // CLI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2521] // STC + (const void *)&gInstructions[ 2505] // STC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 560] // CLC + (const void *)&gInstructions[ 552] // CLC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1086] // IDIV Ev + (const void *)&gInstructions[ 1076] // IDIV Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 890] // DIV Ev + (const void *)&gInstructions[ 882] // DIV Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1120] // IMUL Ev + (const void *)&gInstructions[ 1110] // IMUL Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1488] // MUL Ev + (const void *)&gInstructions[ 1478] // MUL Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1510] // NEG Ev + (const void *)&gInstructions[ 1500] // NEG Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1589] // NOT Ev + (const void *)&gInstructions[ 1579] // NOT Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2619] // TEST Ev,Iz + (const void *)&gInstructions[ 2603] // TEST Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2618] // TEST Ev,Iz + (const void *)&gInstructions[ 2602] // TEST Ev,Iz }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_f7_modrmreg = @@ -214,49 +214,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_f7_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1085] // IDIV Eb + (const void *)&gInstructions[ 1075] // IDIV Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 889] // DIV Eb + (const void *)&gInstructions[ 881] // DIV Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1119] // IMUL Eb + (const void *)&gInstructions[ 1109] // IMUL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1487] // MUL Eb + (const void *)&gInstructions[ 1477] // MUL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1509] // NEG Eb + (const void *)&gInstructions[ 1499] // NEG Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1588] // NOT Eb + (const void *)&gInstructions[ 1578] // NOT Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2617] // TEST Eb,Ib + (const void *)&gInstructions[ 2601] // TEST Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2616] // TEST Eb,Ib + (const void *)&gInstructions[ 2600] // TEST Eb,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_f6_modrmreg = @@ -277,109 +277,109 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_f6_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 574] // CMC + (const void *)&gInstructions[ 566] // CMC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1075] // HLT + (const void *)&gInstructions[ 1065] // HLT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1161] // INT1 + (const void *)&gInstructions[ 1151] // INT1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1649] // OUT DX,eAX + (const void *)&gInstructions[ 1639] // OUT DX,eAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1648] // OUT DX,AL + (const void *)&gInstructions[ 1638] // OUT DX,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1125] // IN eAX,DX + (const void *)&gInstructions[ 1115] // IN eAX,DX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1124] // IN AL,DX + (const void *)&gInstructions[ 1114] // IN AL,DX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_eb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1188] // JMP Jb + (const void *)&gInstructions[ 1178] // JMP Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ea_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1193] // JMPF Ap + (const void *)&gInstructions[ 1183] // JMPF Ap }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1187] // JMP Jz + (const void *)&gInstructions[ 1177] // JMP Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 248] // CALL Jz + (const void *)&gInstructions[ 240] // CALL Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1647] // OUT Ib,eAX + (const void *)&gInstructions[ 1637] // OUT Ib,eAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1646] // OUT Ib,AL + (const void *)&gInstructions[ 1636] // OUT Ib,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1123] // IN eAX,Ib + (const void *)&gInstructions[ 1113] // IN eAX,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1122] // IN AL,Ib + (const void *)&gInstructions[ 1112] // IN AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1215] // JRCXZ Jb + (const void *)&gInstructions[ 1205] // JRCXZ Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1182] // JECXZ Jb + (const void *)&gInstructions[ 1172] // JECXZ Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1181] // JCXZ Jb + (const void *)&gInstructions[ 1171] // JCXZ Jb }; const ND_TABLE_ASIZE gLegacyMap_opcode_e3_asize = @@ -396,25 +396,25 @@ const ND_TABLE_ASIZE gLegacyMap_opcode_e3_asize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1339] // LOOP Jb + (const void *)&gInstructions[ 1329] // LOOP Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1341] // LOOPZ Jb + (const void *)&gInstructions[ 1331] // LOOPZ Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1340] // LOOPNZ Jb + (const void *)&gInstructions[ 1330] // LOOPNZ Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1023] // FRINEAR + (const void *)&gInstructions[ 1013] // FRINEAR }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm = @@ -435,7 +435,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 982] // FISTP Mq,ST(0) + (const void *)&gInstructions[ 972] // FISTP Mq,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_07_modrmmod = @@ -450,13 +450,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 940] // FCOMIP ST(0),ST(i) + (const void *)&gInstructions[ 930] // FCOMIP ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 925] // FBSTP Mfa,ST(0) + (const void *)&gInstructions[ 915] // FBSTP Mfa,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_06_modrmmod = @@ -471,13 +471,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1055] // FUCOMIP ST(0),ST(i) + (const void *)&gInstructions[ 1045] // FUCOMIP ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 974] // FILD ST(0),Mq + (const void *)&gInstructions[ 964] // FILD ST(0),Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_05_modrmmod = @@ -492,19 +492,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1041] // FSTSG AX + (const void *)&gInstructions[ 1031] // FSTSG AX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1033] // FSTDW AX + (const void *)&gInstructions[ 1023] // FSTDW AX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1018] // FNSTSW AX + (const void *)&gInstructions[ 1008] // FNSTSW AX }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm = @@ -525,7 +525,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 924] // FBLD ST(0),Mfa + (const void *)&gInstructions[ 914] // FBLD ST(0),Mfa }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_04_modrmmod = @@ -540,13 +540,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1039] // FSTP ST(i),ST(0) + (const void *)&gInstructions[ 1029] // FSTP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 981] // FISTP Mw,ST(0) + (const void *)&gInstructions[ 971] // FISTP Mw,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_03_modrmmod = @@ -561,13 +561,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1038] // FSTP ST(i),ST(0) + (const void *)&gInstructions[ 1028] // FSTP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 979] // FIST Mw,ST(0) + (const void *)&gInstructions[ 969] // FIST Mw,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_02_modrmmod = @@ -582,13 +582,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1061] // FXCH ST(0),ST(i) + (const void *)&gInstructions[ 1051] // FXCH ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 985] // FISTTP Mw,ST(0) + (const void *)&gInstructions[ 975] // FISTTP Mw,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_01_modrmmod = @@ -603,13 +603,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 961] // FFREEP ST(i) + (const void *)&gInstructions[ 951] // FFREEP ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 973] // FILD ST(0),Mw + (const void *)&gInstructions[ 963] // FILD ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_00_modrmmod = @@ -639,13 +639,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_df_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 953] // FDIVP ST(i),ST(0) + (const void *)&gInstructions[ 943] // FDIVP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 971] // FIDIVR ST(0),Mw + (const void *)&gInstructions[ 961] // FIDIVR ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_07_modrmmod = @@ -660,13 +660,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 958] // FDIVRP ST(i),ST(0) + (const void *)&gInstructions[ 948] // FDIVRP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 969] // FIDIV ST(0),Mw + (const void *)&gInstructions[ 959] // FIDIV ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_06_modrmmod = @@ -681,13 +681,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1046] // FSUBP ST(i),ST(0) + (const void *)&gInstructions[ 1036] // FSUBP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 989] // FISUBR ST(0),Mw + (const void *)&gInstructions[ 979] // FISUBR ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_05_modrmmod = @@ -702,13 +702,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1051] // FSUBRP ST(i),ST(0) + (const void *)&gInstructions[ 1041] // FSUBRP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 987] // FISUB ST(0),Mw + (const void *)&gInstructions[ 977] // FISUB ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_04_modrmmod = @@ -723,7 +723,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 946] // FCOMPP + (const void *)&gInstructions[ 936] // FCOMPP }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm = @@ -744,7 +744,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 967] // FICOMP ST(0),Mw + (const void *)&gInstructions[ 957] // FICOMP ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_03_modrmmod = @@ -759,13 +759,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 945] // FCOMP ST(0),ST(i) + (const void *)&gInstructions[ 935] // FCOMP ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 965] // FICOM ST(0),Mw + (const void *)&gInstructions[ 955] // FICOM ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_02_modrmmod = @@ -780,13 +780,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1007] // FMULP ST(i),ST(0) + (const void *)&gInstructions[ 997] // FMULP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 976] // FIMUL ST(0),Mw + (const void *)&gInstructions[ 966] // FIMUL ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_01_modrmmod = @@ -801,13 +801,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 923] // FADDP ST(i),ST(0) + (const void *)&gInstructions[ 913] // FADDP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 963] // FIADD ST(0),Mw + (const void *)&gInstructions[ 953] // FIADD ST(0),Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_00_modrmmod = @@ -837,7 +837,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_de_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1017] // FNSTSW Mw + (const void *)&gInstructions[ 1007] // FNSTSW Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_07_modrmmod = @@ -852,7 +852,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1014] // FNSAVE Mfs + (const void *)&gInstructions[ 1004] // FNSAVE Mfs }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_06_modrmmod = @@ -867,7 +867,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1056] // FUCOMP ST(0),ST(i) + (const void *)&gInstructions[ 1046] // FUCOMP ST(0),ST(i) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_05_modrmmod = @@ -882,13 +882,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1053] // FUCOM ST(0),ST(i) + (const void *)&gInstructions[ 1043] // FUCOM ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1025] // FRSTOR Mfs + (const void *)&gInstructions[ 1015] // FRSTOR Mfs }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_04_modrmmod = @@ -903,13 +903,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1037] // FSTP ST(i),ST(0) + (const void *)&gInstructions[ 1027] // FSTP ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1036] // FSTP Mfq,ST(0) + (const void *)&gInstructions[ 1026] // FSTP Mfq,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_03_modrmmod = @@ -924,13 +924,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1032] // FST ST(i),ST(0) + (const void *)&gInstructions[ 1022] // FST ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1031] // FST Mfq,ST(0) + (const void *)&gInstructions[ 1021] // FST Mfq,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_02_modrmmod = @@ -945,13 +945,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1060] // FXCH ST(0),ST(i) + (const void *)&gInstructions[ 1050] // FXCH ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 984] // FISTTP Mq,ST(0) + (const void *)&gInstructions[ 974] // FISTTP Mq,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_01_modrmmod = @@ -966,13 +966,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 960] // FFREE ST(i) + (const void *)&gInstructions[ 950] // FFREE ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 993] // FLD ST(0),Mfq + (const void *)&gInstructions[ 983] // FLD ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_00_modrmmod = @@ -1002,13 +1002,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_dd_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 952] // FDIV ST(i),ST(0) + (const void *)&gInstructions[ 942] // FDIV ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 956] // FDIVR ST(0),Mfq + (const void *)&gInstructions[ 946] // FDIVR ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_07_modrmmod = @@ -1023,13 +1023,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 957] // FDIVR ST(i),ST(0) + (const void *)&gInstructions[ 947] // FDIVR ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 951] // FDIV ST(0),Mfq + (const void *)&gInstructions[ 941] // FDIV ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_06_modrmmod = @@ -1044,13 +1044,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1045] // FSUB ST(i),ST(0) + (const void *)&gInstructions[ 1035] // FSUB ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1049] // FSUBR ST(0),Mfq + (const void *)&gInstructions[ 1039] // FSUBR ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_05_modrmmod = @@ -1065,13 +1065,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1050] // FSUBR ST(i),ST(0) + (const void *)&gInstructions[ 1040] // FSUBR ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1044] // FSUB ST(0),Mfq + (const void *)&gInstructions[ 1034] // FSUB ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_04_modrmmod = @@ -1086,13 +1086,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 944] // FCOMP ST(0),ST(i) + (const void *)&gInstructions[ 934] // FCOMP ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 943] // FCOMP ST(0),Mfq + (const void *)&gInstructions[ 933] // FCOMP ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_03_modrmmod = @@ -1107,13 +1107,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 938] // FCOM ST(0),ST(i) + (const void *)&gInstructions[ 928] // FCOM ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 937] // FCOM ST(0),Mfq + (const void *)&gInstructions[ 927] // FCOM ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_02_modrmmod = @@ -1128,13 +1128,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1006] // FMUL ST(i),ST(0) + (const void *)&gInstructions[ 996] // FMUL ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1005] // FMUL ST(0),Mfq + (const void *)&gInstructions[ 995] // FMUL ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_01_modrmmod = @@ -1149,13 +1149,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 922] // FADD ST(i),ST(0) + (const void *)&gInstructions[ 912] // FADD ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 921] // FADD ST(0),Mfq + (const void *)&gInstructions[ 911] // FADD ST(0),Mfq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_00_modrmmod = @@ -1185,7 +1185,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_dc_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1035] // FSTP Mft,ST(0) + (const void *)&gInstructions[ 1025] // FSTP Mft,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_07_modrmmod = @@ -1200,7 +1200,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 939] // FCOMI ST(0),ST(i) + (const void *)&gInstructions[ 929] // FCOMI ST(0),ST(i) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_06_modrmmod = @@ -1215,13 +1215,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1054] // FUCOMI ST(0),ST(i) + (const void *)&gInstructions[ 1044] // FUCOMI ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 992] // FLD ST(0),Mft + (const void *)&gInstructions[ 982] // FLD ST(0),Mft }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_05_modrmmod = @@ -1236,31 +1236,31 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1013] // FNOP + (const void *)&gInstructions[ 1003] // FNOP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1010] // FNINIT + (const void *)&gInstructions[ 1000] // FNINIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1008] // FNCLEX + (const void *)&gInstructions[ 998] // FNCLEX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1009] // FNDISI + (const void *)&gInstructions[ 999] // FNDISI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1012] // FNOP + (const void *)&gInstructions[ 1002] // FNOP }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm = @@ -1290,13 +1290,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 933] // FCMOVNU ST(0),ST(i) + (const void *)&gInstructions[ 923] // FCMOVNU ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 980] // FISTP Md,ST(0) + (const void *)&gInstructions[ 970] // FISTP Md,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_03_modrmmod = @@ -1311,13 +1311,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 931] // FCMOVNBE ST(0),ST(i) + (const void *)&gInstructions[ 921] // FCMOVNBE ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 978] // FIST Md,ST(0) + (const void *)&gInstructions[ 968] // FIST Md,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_02_modrmmod = @@ -1332,13 +1332,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 932] // FCMOVNE ST(0),ST(i) + (const void *)&gInstructions[ 922] // FCMOVNE ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 983] // FISTTP Md,ST(0) + (const void *)&gInstructions[ 973] // FISTTP Md,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_01_modrmmod = @@ -1353,13 +1353,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 930] // FCMOVNB ST(0),ST(i) + (const void *)&gInstructions[ 920] // FCMOVNB ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 972] // FILD ST(0),Md + (const void *)&gInstructions[ 962] // FILD ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_00_modrmmod = @@ -1389,7 +1389,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_db_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 970] // FIDIVR ST(0),Md + (const void *)&gInstructions[ 960] // FIDIVR ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_07_modrmmod = @@ -1404,7 +1404,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 968] // FIDIV ST(0),Md + (const void *)&gInstructions[ 958] // FIDIV ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_06_modrmmod = @@ -1419,7 +1419,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1057] // FUCOMPP + (const void *)&gInstructions[ 1047] // FUCOMPP }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm = @@ -1440,7 +1440,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 988] // FISUBR ST(0),Md + (const void *)&gInstructions[ 978] // FISUBR ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_05_modrmmod = @@ -1455,7 +1455,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 986] // FISUB ST(0),Md + (const void *)&gInstructions[ 976] // FISUB ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_04_modrmmod = @@ -1470,13 +1470,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 934] // FCMOVU ST(0),ST(i) + (const void *)&gInstructions[ 924] // FCMOVU ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 966] // FICOMP ST(0),Md + (const void *)&gInstructions[ 956] // FICOMP ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_03_modrmmod = @@ -1491,13 +1491,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 928] // FCMOVBE ST(0),ST(i) + (const void *)&gInstructions[ 918] // FCMOVBE ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 964] // FICOM ST(0),Md + (const void *)&gInstructions[ 954] // FICOM ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_02_modrmmod = @@ -1512,13 +1512,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 929] // FCMOVE ST(0),ST(i) + (const void *)&gInstructions[ 919] // FCMOVE ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 975] // FIMUL ST(0),Md + (const void *)&gInstructions[ 965] // FIMUL ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_01_modrmmod = @@ -1533,13 +1533,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 927] // FCMOVB ST(0),ST(i) + (const void *)&gInstructions[ 917] // FCMOVB ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 962] // FIADD ST(0),Md + (const void *)&gInstructions[ 952] // FIADD ST(0),Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_00_modrmmod = @@ -1569,49 +1569,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_da_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 947] // FCOS + (const void *)&gInstructions[ 937] // FCOS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1027] // FSIN + (const void *)&gInstructions[ 1017] // FSIN }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1026] // FSCALE + (const void *)&gInstructions[ 1016] // FSCALE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1024] // FRNDINT + (const void *)&gInstructions[ 1014] // FRNDINT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1028] // FSINCOS + (const void *)&gInstructions[ 1018] // FSINCOS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1029] // FSQRT + (const void *)&gInstructions[ 1019] // FSQRT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1068] // FYL2XP1 + (const void *)&gInstructions[ 1058] // FYL2XP1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1020] // FPREM + (const void *)&gInstructions[ 1010] // FPREM }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm = @@ -1632,7 +1632,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1015] // FNSTCW Mw + (const void *)&gInstructions[ 1005] // FNSTCW Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_07_modrmmod = @@ -1647,49 +1647,49 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 977] // FINCSTP + (const void *)&gInstructions[ 967] // FINCSTP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 948] // FDECSTP + (const void *)&gInstructions[ 938] // FDECSTP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1021] // FPREM1 + (const void *)&gInstructions[ 1011] // FPREM1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1066] // FXTRACT + (const void *)&gInstructions[ 1056] // FXTRACT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1019] // FPATAN + (const void *)&gInstructions[ 1009] // FPATAN }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1022] // FPTAN + (const void *)&gInstructions[ 1012] // FPTAN }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1067] // FYL2X + (const void *)&gInstructions[ 1057] // FYL2X }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 917] // F2XM1 + (const void *)&gInstructions[ 907] // F2XM1 }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm = @@ -1710,7 +1710,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1016] // FNSTENV Mfe + (const void *)&gInstructions[ 1006] // FNSTENV Mfe }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_06_modrmmod = @@ -1725,43 +1725,43 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1002] // FLDZ + (const void *)&gInstructions[ 992] // FLDZ }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1000] // FLDLN2 + (const void *)&gInstructions[ 990] // FLDLN2 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 999] // FLDLG2 + (const void *)&gInstructions[ 989] // FLDLG2 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1001] // FLDPI + (const void *)&gInstructions[ 991] // FLDPI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 997] // FLDL2E + (const void *)&gInstructions[ 987] // FLDL2E }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 998] // FLDL2T + (const void *)&gInstructions[ 988] // FLDL2T }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 994] // FLD1 + (const void *)&gInstructions[ 984] // FLD1 }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm = @@ -1782,7 +1782,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 995] // FLDCW Mw + (const void *)&gInstructions[ 985] // FLDCW Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_05_modrmmod = @@ -1797,25 +1797,25 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1058] // FXAM + (const void *)&gInstructions[ 1048] // FXAM }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1052] // FTST + (const void *)&gInstructions[ 1042] // FTST }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 918] // FABS + (const void *)&gInstructions[ 908] // FABS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 926] // FCHS + (const void *)&gInstructions[ 916] // FCHS }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm = @@ -1836,7 +1836,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 996] // FLDENV Mfe + (const void *)&gInstructions[ 986] // FLDENV Mfe }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_04_modrmmod = @@ -1851,13 +1851,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1040] // FSTPNCE ST(i),ST(0) + (const void *)&gInstructions[ 1030] // FSTPNCE ST(i),ST(0) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1034] // FSTP Mfd,ST(0) + (const void *)&gInstructions[ 1024] // FSTP Mfd,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_03_modrmmod = @@ -1872,7 +1872,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1011] // FNOP + (const void *)&gInstructions[ 1001] // FNOP }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm = @@ -1893,7 +1893,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1030] // FST Mfd,ST(0) + (const void *)&gInstructions[ 1020] // FST Mfd,ST(0) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_02_modrmmod = @@ -1908,7 +1908,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1059] // FXCH ST(0),ST(i) + (const void *)&gInstructions[ 1049] // FXCH ST(0),ST(i) }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_01_modrmmod = @@ -1923,13 +1923,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 991] // FLD ST(0),ST(i) + (const void *)&gInstructions[ 981] // FLD ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 990] // FLD ST(0),Mfd + (const void *)&gInstructions[ 980] // FLD ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_00_modrmmod = @@ -1959,13 +1959,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d9_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 955] // FDIVR ST(0),ST(i) + (const void *)&gInstructions[ 945] // FDIVR ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 954] // FDIVR ST(0),Mfd + (const void *)&gInstructions[ 944] // FDIVR ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_07_modrmmod = @@ -1980,13 +1980,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 950] // FDIV ST(0),ST(i) + (const void *)&gInstructions[ 940] // FDIV ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 949] // FDIV ST(0),Mfd + (const void *)&gInstructions[ 939] // FDIV ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_06_modrmmod = @@ -2001,13 +2001,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1048] // FSUBR ST(0),ST(i) + (const void *)&gInstructions[ 1038] // FSUBR ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1047] // FSUBR ST(0),Mfd + (const void *)&gInstructions[ 1037] // FSUBR ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_05_modrmmod = @@ -2022,13 +2022,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1043] // FSUB ST(0),ST(i) + (const void *)&gInstructions[ 1033] // FSUB ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1042] // FSUB ST(0),Mfd + (const void *)&gInstructions[ 1032] // FSUB ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_04_modrmmod = @@ -2043,13 +2043,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 942] // FCOMP ST(0),ST(i) + (const void *)&gInstructions[ 932] // FCOMP ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 941] // FCOMP ST(0),Mfd + (const void *)&gInstructions[ 931] // FCOMP ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_03_modrmmod = @@ -2064,13 +2064,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 936] // FCOM ST(0),ST(i) + (const void *)&gInstructions[ 926] // FCOM ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 935] // FCOM ST(0),Mfd + (const void *)&gInstructions[ 925] // FCOM ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_02_modrmmod = @@ -2085,13 +2085,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1004] // FMUL ST(0),ST(i) + (const void *)&gInstructions[ 994] // FMUL ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1003] // FMUL ST(0),Mfd + (const void *)&gInstructions[ 993] // FMUL ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_01_modrmmod = @@ -2106,13 +2106,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 920] // FADD ST(0),ST(i) + (const void *)&gInstructions[ 910] // FADD ST(0),ST(i) }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 919] // FADD ST(0),Mfd + (const void *)&gInstructions[ 909] // FADD ST(0),Mfd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_00_modrmmod = @@ -2142,13 +2142,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d8_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4002] // XLATB + (const void *)&gInstructions[ 4084] // XLATB }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2242] // SALC + (const void *)&gInstructions[ 2233] // SALC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d5_leaf = @@ -2166,49 +2166,49 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d4_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2284] // SAR Ev,CL + (const void *)&gInstructions[ 2275] // SAR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2241] // SAL Ev,CL + (const void *)&gInstructions[ 2232] // SAL Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2485] // SHR Ev,CL + (const void *)&gInstructions[ 2469] // SHR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2423] // SHL Ev,CL + (const void *)&gInstructions[ 2407] // SHL Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2081] // RCR Ev,CL + (const void *)&gInstructions[ 2071] // RCR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2037] // RCL Ev,CL + (const void *)&gInstructions[ 2027] // RCL Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2188] // ROR Ev,CL + (const void *)&gInstructions[ 2179] // ROR Ev,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2146] // ROL Ev,CL + (const void *)&gInstructions[ 2137] // ROL Ev,CL }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d3_modrmreg = @@ -2229,49 +2229,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d3_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2283] // SAR Eb,CL + (const void *)&gInstructions[ 2274] // SAR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2240] // SAL Eb,CL + (const void *)&gInstructions[ 2231] // SAL Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2484] // SHR Eb,CL + (const void *)&gInstructions[ 2468] // SHR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2422] // SHL Eb,CL + (const void *)&gInstructions[ 2406] // SHL Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2080] // RCR Eb,CL + (const void *)&gInstructions[ 2070] // RCR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2036] // RCL Eb,CL + (const void *)&gInstructions[ 2026] // RCL Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2187] // ROR Eb,CL + (const void *)&gInstructions[ 2178] // ROR Eb,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2145] // ROL Eb,CL + (const void *)&gInstructions[ 2136] // ROL Eb,CL }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d2_modrmreg = @@ -2292,49 +2292,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d2_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2282] // SAR Ev,1 + (const void *)&gInstructions[ 2273] // SAR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2239] // SAL Ev,1 + (const void *)&gInstructions[ 2230] // SAL Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2483] // SHR Ev,1 + (const void *)&gInstructions[ 2467] // SHR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2421] // SHL Ev,1 + (const void *)&gInstructions[ 2405] // SHL Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2079] // RCR Ev,1 + (const void *)&gInstructions[ 2069] // RCR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2035] // RCL Ev,1 + (const void *)&gInstructions[ 2025] // RCL Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2186] // ROR Ev,1 + (const void *)&gInstructions[ 2177] // ROR Ev,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2144] // ROL Ev,1 + (const void *)&gInstructions[ 2135] // ROL Ev,1 }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d1_modrmreg = @@ -2355,49 +2355,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d1_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2281] // SAR Eb,1 + (const void *)&gInstructions[ 2272] // SAR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2238] // SAL Eb,1 + (const void *)&gInstructions[ 2229] // SAL Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2482] // SHR Eb,1 + (const void *)&gInstructions[ 2466] // SHR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2420] // SHL Eb,1 + (const void *)&gInstructions[ 2404] // SHL Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2078] // RCR Eb,1 + (const void *)&gInstructions[ 2068] // RCR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2034] // RCL Eb,1 + (const void *)&gInstructions[ 2024] // RCL Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2185] // ROR Eb,1 + (const void *)&gInstructions[ 2176] // ROR Eb,1 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2143] // ROL Eb,1 + (const void *)&gInstructions[ 2134] // ROL Eb,1 }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_d0_modrmreg = @@ -2418,19 +2418,19 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_d0_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1175] // IRETQ + (const void *)&gInstructions[ 1165] // IRETQ }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1174] // IRETD + (const void *)&gInstructions[ 1164] // IRETD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1176] // IRETW + (const void *)&gInstructions[ 1166] // IRETW }; const ND_TABLE_DSIZE gLegacyMap_opcode_cf_dsize = @@ -2449,49 +2449,49 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_cf_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1163] // INTO + (const void *)&gInstructions[ 1153] // INTO }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1160] // INT Ib + (const void *)&gInstructions[ 1150] // INT Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1162] // INT3 + (const void *)&gInstructions[ 1152] // INT3 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2099] // RETF + (const void *)&gInstructions[ 2089] // RETF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ca_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2098] // RETF Iw + (const void *)&gInstructions[ 2088] // RETF Iw }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1318] // LEAVE + (const void *)&gInstructions[ 1308] // LEAVE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 911] // ENTER Iw,Ib + (const void *)&gInstructions[ 901] // ENTER Iw,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3989] // XBEGIN Jz + (const void *)&gInstructions[ 4071] // XBEGIN Jz }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm = @@ -2521,7 +2521,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c7_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1396] // MOV Ev,Iz + (const void *)&gInstructions[ 1386] // MOV Ev,Iz }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_c7_modrmreg = @@ -2542,7 +2542,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_c7_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3986] // XABORT Ib + (const void *)&gInstructions[ 4068] // XABORT Ib }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm = @@ -2572,7 +2572,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c6_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1395] // MOV Eb,Ib + (const void *)&gInstructions[ 1385] // MOV Eb,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_c6_modrmreg = @@ -2593,7 +2593,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_c6_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c5_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1314] // LDS Gz,Mp + (const void *)&gInstructions[ 1304] // LDS Gz,Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c5_modrmmod = @@ -2608,7 +2608,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c5_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c4_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1319] // LES Gz,Mp + (const void *)&gInstructions[ 1309] // LES Gz,Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c4_modrmmod = @@ -2623,61 +2623,61 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c4_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2101] // RETN + (const void *)&gInstructions[ 2091] // RETN }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2100] // RETN Iw + (const void *)&gInstructions[ 2090] // RETN Iw }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2280] // SAR Ev,Ib + (const void *)&gInstructions[ 2271] // SAR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2237] // SAL Ev,Ib + (const void *)&gInstructions[ 2228] // SAL Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2481] // SHR Ev,Ib + (const void *)&gInstructions[ 2465] // SHR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2419] // SHL Ev,Ib + (const void *)&gInstructions[ 2403] // SHL Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2077] // RCR Ev,Ib + (const void *)&gInstructions[ 2067] // RCR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2033] // RCL Ev,Ib + (const void *)&gInstructions[ 2023] // RCL Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2184] // ROR Ev,Ib + (const void *)&gInstructions[ 2175] // ROR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2142] // ROL Ev,Ib + (const void *)&gInstructions[ 2133] // ROL Ev,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_c1_modrmreg = @@ -2698,49 +2698,49 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_c1_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2279] // SAR Eb,Ib + (const void *)&gInstructions[ 2270] // SAR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2236] // SAL Eb,Ib + (const void *)&gInstructions[ 2227] // SAL Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2480] // SHR Eb,Ib + (const void *)&gInstructions[ 2464] // SHR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2418] // SHL Eb,Ib + (const void *)&gInstructions[ 2402] // SHL Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2076] // RCR Eb,Ib + (const void *)&gInstructions[ 2066] // RCR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2032] // RCL Eb,Ib + (const void *)&gInstructions[ 2022] // RCL Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2183] // ROR Eb,Ib + (const void *)&gInstructions[ 2174] // ROR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2141] // ROL Eb,Ib + (const void *)&gInstructions[ 2132] // ROL Eb,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_c0_modrmreg = @@ -2761,109 +2761,109 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_c0_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1394] // MOV Zv,Iv + (const void *)&gInstructions[ 1384] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1393] // MOV Zv,Iv + (const void *)&gInstructions[ 1383] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1392] // MOV Zv,Iv + (const void *)&gInstructions[ 1382] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1391] // MOV Zv,Iv + (const void *)&gInstructions[ 1381] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1390] // MOV Zv,Iv + (const void *)&gInstructions[ 1380] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ba_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1389] // MOV Zv,Iv + (const void *)&gInstructions[ 1379] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1388] // MOV Zv,Iv + (const void *)&gInstructions[ 1378] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1387] // MOV Zv,Iv + (const void *)&gInstructions[ 1377] // MOV Zv,Iv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1386] // MOV Zb,Ib + (const void *)&gInstructions[ 1376] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1385] // MOV Zb,Ib + (const void *)&gInstructions[ 1375] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1384] // MOV Zb,Ib + (const void *)&gInstructions[ 1374] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1383] // MOV Zb,Ib + (const void *)&gInstructions[ 1373] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1382] // MOV Zb,Ib + (const void *)&gInstructions[ 1372] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1381] // MOV Zb,Ib + (const void *)&gInstructions[ 1371] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1380] // MOV Zb,Ib + (const void *)&gInstructions[ 1370] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1379] // MOV Zb,Ib + (const void *)&gInstructions[ 1369] // MOV Zb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2325] // SCASQ RAX,Yv + (const void *)&gInstructions[ 2316] // SCASQ RAX,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2324] // SCASQ RAX,Yv + (const void *)&gInstructions[ 2315] // SCASQ RAX,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_03_auxiliary = @@ -2886,13 +2886,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2323] // SCASD EAX,Yv + (const void *)&gInstructions[ 2314] // SCASD EAX,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2322] // SCASD EAX,Yv + (const void *)&gInstructions[ 2313] // SCASD EAX,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_02_auxiliary = @@ -2915,13 +2915,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2327] // SCASW AX,Yv + (const void *)&gInstructions[ 2318] // SCASW AX,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2326] // SCASW AX,Yv + (const void *)&gInstructions[ 2317] // SCASW AX,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_01_auxiliary = @@ -2957,13 +2957,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_af_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2321] // SCASB AL,Yb + (const void *)&gInstructions[ 2312] // SCASB AL,Yb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2320] // SCASB AL,Yb + (const void *)&gInstructions[ 2311] // SCASB AL,Yb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ae_auxiliary = @@ -2986,13 +2986,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ae_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1336] // LODSQ RAX,Xv + (const void *)&gInstructions[ 1326] // LODSQ RAX,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1335] // LODSQ RAX,Xv + (const void *)&gInstructions[ 1325] // LODSQ RAX,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_03_auxiliary = @@ -3015,13 +3015,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1334] // LODSD EAX,Xv + (const void *)&gInstructions[ 1324] // LODSD EAX,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1333] // LODSD EAX,Xv + (const void *)&gInstructions[ 1323] // LODSD EAX,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_02_auxiliary = @@ -3044,13 +3044,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1338] // LODSW AX,Xv + (const void *)&gInstructions[ 1328] // LODSW AX,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1337] // LODSW AX,Xv + (const void *)&gInstructions[ 1327] // LODSW AX,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_01_auxiliary = @@ -3086,13 +3086,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_ad_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ac_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1332] // LODSB AL,Xb + (const void *)&gInstructions[ 1322] // LODSB AL,Xb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ac_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1331] // LODSB AL,Xb + (const void *)&gInstructions[ 1321] // LODSB AL,Xb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ac_auxiliary = @@ -3115,13 +3115,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ac_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2531] // STOSQ Yv,RAX + (const void *)&gInstructions[ 2515] // STOSQ Yv,RAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2530] // STOSQ Yv,RAX + (const void *)&gInstructions[ 2514] // STOSQ Yv,RAX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_03_auxiliary = @@ -3144,13 +3144,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2529] // STOSD Yv,EAX + (const void *)&gInstructions[ 2513] // STOSD Yv,EAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2528] // STOSD Yv,EAX + (const void *)&gInstructions[ 2512] // STOSD Yv,EAX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_02_auxiliary = @@ -3173,13 +3173,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2533] // STOSW Yv,AX + (const void *)&gInstructions[ 2517] // STOSW Yv,AX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2532] // STOSW Yv,AX + (const void *)&gInstructions[ 2516] // STOSW Yv,AX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_01_auxiliary = @@ -3215,13 +3215,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_ab_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2527] // STOSB Yb,AL + (const void *)&gInstructions[ 2511] // STOSB Yb,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2526] // STOSB Yb,AL + (const void *)&gInstructions[ 2510] // STOSB Yb,AL }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_aa_auxiliary = @@ -3244,25 +3244,25 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_aa_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2615] // TEST rAX,Iz + (const void *)&gInstructions[ 2599] // TEST rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2614] // TEST AL,Ib + (const void *)&gInstructions[ 2598] // TEST AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 669] // CMPSQ Xv,Yv + (const void *)&gInstructions[ 661] // CMPSQ Xv,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 668] // CMPSQ Xv,Yv + (const void *)&gInstructions[ 660] // CMPSQ Xv,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_03_auxiliary = @@ -3285,13 +3285,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 666] // CMPSD Xv,Yv + (const void *)&gInstructions[ 658] // CMPSD Xv,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 665] // CMPSD Xv,Yv + (const void *)&gInstructions[ 657] // CMPSD Xv,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_02_auxiliary = @@ -3314,13 +3314,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 672] // CMPSW Xv,Yv + (const void *)&gInstructions[ 664] // CMPSW Xv,Yv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 671] // CMPSW Xv,Yv + (const void *)&gInstructions[ 663] // CMPSW Xv,Yv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_01_auxiliary = @@ -3356,13 +3356,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_a7_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a6_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 664] // CMPSB Xb,Yb + (const void *)&gInstructions[ 656] // CMPSB Xb,Yb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a6_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 663] // CMPSB Xb,Yb + (const void *)&gInstructions[ 655] // CMPSB Xb,Yb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a6_auxiliary = @@ -3385,13 +3385,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a6_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1466] // MOVSQ Yv,Xv + (const void *)&gInstructions[ 1456] // MOVSQ Yv,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1465] // MOVSQ Yv,Xv + (const void *)&gInstructions[ 1455] // MOVSQ Yv,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_03_auxiliary = @@ -3414,13 +3414,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_03_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1460] // MOVSD Yv,Xv + (const void *)&gInstructions[ 1450] // MOVSD Yv,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1459] // MOVSD Yv,Xv + (const void *)&gInstructions[ 1449] // MOVSD Yv,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_02_auxiliary = @@ -3443,13 +3443,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_02_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1470] // MOVSW Yv,Xv + (const void *)&gInstructions[ 1460] // MOVSW Yv,Xv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1469] // MOVSW Yv,Xv + (const void *)&gInstructions[ 1459] // MOVSW Yv,Xv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_01_auxiliary = @@ -3485,13 +3485,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_a5_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1458] // MOVSB Yb,Xb + (const void *)&gInstructions[ 1448] // MOVSB Yb,Xb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1457] // MOVSB Yb,Xb + (const void *)&gInstructions[ 1447] // MOVSB Yb,Xb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a4_auxiliary = @@ -3514,19 +3514,19 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a4_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1378] // MOV Ov,rAX + (const void *)&gInstructions[ 1368] // MOV Ov,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1377] // MOV Ob,AL + (const void *)&gInstructions[ 1367] // MOV Ob,AL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a1_auxiliary_07_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1190] // JMPABS Aq + (const void *)&gInstructions[ 1180] // JMPABS Aq }; const ND_TABLE_EX_W gLegacyMap_opcode_a1_auxiliary_07_w = @@ -3541,7 +3541,7 @@ const ND_TABLE_EX_W gLegacyMap_opcode_a1_auxiliary_07_w = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a1_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1376] // MOV rAX,Ov + (const void *)&gInstructions[ 1366] // MOV rAX,Ov }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_a1_auxiliary = @@ -3564,37 +3564,37 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_a1_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1375] // MOV AL,Ob + (const void *)&gInstructions[ 1365] // MOV AL,Ob }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1309] // LAHF + (const void *)&gInstructions[ 1299] // LAHF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2199] // SAHF + (const void *)&gInstructions[ 2190] // SAHF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1849] // POPFQ Fv + (const void *)&gInstructions[ 1839] // POPFQ Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1848] // POPFD Fv + (const void *)&gInstructions[ 1838] // POPFD Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1850] // POPFW Fv + (const void *)&gInstructions[ 1840] // POPFW Fv }; const ND_TABLE_DSIZE gLegacyMap_opcode_9d_dsize = @@ -3613,19 +3613,19 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_9d_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1983] // PUSHFQ Fv + (const void *)&gInstructions[ 1973] // PUSHFQ Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1982] // PUSHFD Fv + (const void *)&gInstructions[ 1972] // PUSHFD Fv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1984] // PUSHFW Fv + (const void *)&gInstructions[ 1974] // PUSHFW Fv }; const ND_TABLE_DSIZE gLegacyMap_opcode_9c_dsize = @@ -3644,31 +3644,31 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_9c_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3969] // WAIT + (const void *)&gInstructions[ 4051] // WAIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 250] // CALLF Ap + (const void *)&gInstructions[ 242] // CALLF Ap }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 684] // CQO + (const void *)&gInstructions[ 676] // CQO }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 429] // CDQ + (const void *)&gInstructions[ 421] // CDQ }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 856] // CWD + (const void *)&gInstructions[ 848] // CWD }; const ND_TABLE_DSIZE gLegacyMap_opcode_99_dsize = @@ -3687,19 +3687,19 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_99_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 430] // CDQE + (const void *)&gInstructions[ 422] // CDQE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 857] // CWDE + (const void *)&gInstructions[ 849] // CWDE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 252] // CBW + (const void *)&gInstructions[ 244] // CBW }; const ND_TABLE_DSIZE gLegacyMap_opcode_98_dsize = @@ -3718,61 +3718,61 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_98_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3999] // XCHG Zv,rAX + (const void *)&gInstructions[ 4081] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3998] // XCHG Zv,rAX + (const void *)&gInstructions[ 4080] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3997] // XCHG Zv,rAX + (const void *)&gInstructions[ 4079] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3996] // XCHG Zv,rAX + (const void *)&gInstructions[ 4078] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3995] // XCHG Zv,rAX + (const void *)&gInstructions[ 4077] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3994] // XCHG Zv,rAX + (const void *)&gInstructions[ 4076] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3993] // XCHG Zv,rAX + (const void *)&gInstructions[ 4075] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1691] // PAUSE + (const void *)&gInstructions[ 1681] // PAUSE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3992] // XCHG Zv,rAX + (const void *)&gInstructions[ 4074] // XCHG Zv,rAX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1511] // NOP + (const void *)&gInstructions[ 1501] // NOP }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_90_auxiliary = @@ -3795,7 +3795,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_90_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8f_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1836] // POP Ev + (const void *)&gInstructions[ 1826] // POP Ev }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_8f_modrmreg = @@ -3816,13 +3816,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_8f_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8e_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1374] // MOV Sw,Rv + (const void *)&gInstructions[ 1364] // MOV Sw,Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8e_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1373] // MOV Sw,Mw + (const void *)&gInstructions[ 1363] // MOV Sw,Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8e_modrmmod = @@ -3837,7 +3837,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8e_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8d_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1317] // LEA Gv,M0 + (const void *)&gInstructions[ 1307] // LEA Gv,M0 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8d_modrmmod = @@ -3852,13 +3852,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8d_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8c_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1372] // MOV Rv,Sw + (const void *)&gInstructions[ 1362] // MOV Rv,Sw }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8c_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1371] // MOV Mw,Sw + (const void *)&gInstructions[ 1361] // MOV Mw,Sw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8c_modrmmod = @@ -3873,79 +3873,79 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8c_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1370] // MOV Gv,Ev + (const void *)&gInstructions[ 1360] // MOV Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1369] // MOV Gb,Eb + (const void *)&gInstructions[ 1359] // MOV Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_89_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1368] // MOV Ev,Gv + (const void *)&gInstructions[ 1358] // MOV Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_88_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1367] // MOV Eb,Gb + (const void *)&gInstructions[ 1357] // MOV Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3991] // XCHG Ev,Gv + (const void *)&gInstructions[ 4073] // XCHG Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3990] // XCHG Eb,Gb + (const void *)&gInstructions[ 4072] // XCHG Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2613] // TEST Ev,Gv + (const void *)&gInstructions[ 2597] // TEST Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2612] // TEST Eb,Gb + (const void *)&gInstructions[ 2596] // TEST Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 632] // CMP Ev,Ib + (const void *)&gInstructions[ 624] // CMP Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4056] // XOR Ev,Ib + (const void *)&gInstructions[ 4138] // XOR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2592] // SUB Ev,Ib + (const void *)&gInstructions[ 2576] // SUB Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 181] // AND Ev,Ib + (const void *)&gInstructions[ 173] // AND Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2319] // SBB Ev,Ib + (const void *)&gInstructions[ 2310] // SBB Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_02_leaf = @@ -3957,7 +3957,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1643] // OR Ev,Ib + (const void *)&gInstructions[ 1633] // OR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_00_leaf = @@ -3984,31 +3984,31 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_83_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 631] // CMP Eb,Ib + (const void *)&gInstructions[ 623] // CMP Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4055] // XOR Eb,Ib + (const void *)&gInstructions[ 4137] // XOR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2591] // SUB Eb,Ib + (const void *)&gInstructions[ 2575] // SUB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 180] // AND Eb,Ib + (const void *)&gInstructions[ 172] // AND Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2318] // SBB Eb,Ib + (const void *)&gInstructions[ 2309] // SBB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_02_leaf = @@ -4020,7 +4020,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1642] // OR Eb,Ib + (const void *)&gInstructions[ 1632] // OR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_00_leaf = @@ -4047,31 +4047,31 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_82_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 630] // CMP Ev,Iz + (const void *)&gInstructions[ 622] // CMP Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4054] // XOR Ev,Iz + (const void *)&gInstructions[ 4136] // XOR Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2590] // SUB Ev,Iz + (const void *)&gInstructions[ 2574] // SUB Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 179] // AND Ev,Iz + (const void *)&gInstructions[ 171] // AND Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2317] // SBB Ev,Iz + (const void *)&gInstructions[ 2308] // SBB Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_02_leaf = @@ -4083,7 +4083,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1641] // OR Ev,Iz + (const void *)&gInstructions[ 1631] // OR Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_00_leaf = @@ -4110,31 +4110,31 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_81_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 629] // CMP Eb,Ib + (const void *)&gInstructions[ 621] // CMP Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4053] // XOR Eb,Ib + (const void *)&gInstructions[ 4135] // XOR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2589] // SUB Eb,Ib + (const void *)&gInstructions[ 2573] // SUB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 178] // AND Eb,Ib + (const void *)&gInstructions[ 170] // AND Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2316] // SBB Eb,Ib + (const void *)&gInstructions[ 2307] // SBB Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_02_leaf = @@ -4146,7 +4146,7 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_02_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1640] // OR Eb,Ib + (const void *)&gInstructions[ 1630] // OR Eb,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_00_leaf = @@ -4173,109 +4173,109 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_80_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1201] // JNLE Jb + (const void *)&gInstructions[ 1191] // JNLE Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1185] // JLE Jb + (const void *)&gInstructions[ 1175] // JLE Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1199] // JNL Jb + (const void *)&gInstructions[ 1189] // JNL Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1183] // JL Jb + (const void *)&gInstructions[ 1173] // JL Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1205] // JNP Jb + (const void *)&gInstructions[ 1195] // JNP Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1213] // JP Jb + (const void *)&gInstructions[ 1203] // JP Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_79_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1207] // JNS Jb + (const void *)&gInstructions[ 1197] // JNS Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_78_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1216] // JS Jb + (const void *)&gInstructions[ 1206] // JS Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_77_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1195] // JNBE Jb + (const void *)&gInstructions[ 1185] // JNBE Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_76_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1177] // JBE Jb + (const void *)&gInstructions[ 1167] // JBE Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_75_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1209] // JNZ Jb + (const void *)&gInstructions[ 1199] // JNZ Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_74_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1218] // JZ Jb + (const void *)&gInstructions[ 1208] // JZ Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_73_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1197] // JNC Jb + (const void *)&gInstructions[ 1187] // JNC Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_72_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1179] // JC Jb + (const void *)&gInstructions[ 1169] // JC Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_71_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1203] // JNO Jb + (const void *)&gInstructions[ 1193] // JNO Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_70_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1211] // JO Jb + (const void *)&gInstructions[ 1201] // JO Jb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1655] // OUTSW DX,Xz + (const void *)&gInstructions[ 1645] // OUTSW DX,Xz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1654] // OUTSW DX,Xz + (const void *)&gInstructions[ 1644] // OUTSW DX,Xz }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_01_auxiliary = @@ -4298,13 +4298,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_01_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1653] // OUTSD DX,Xz + (const void *)&gInstructions[ 1643] // OUTSD DX,Xz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1652] // OUTSD DX,Xz + (const void *)&gInstructions[ 1642] // OUTSD DX,Xz }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_00_auxiliary = @@ -4340,13 +4340,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_6f_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1651] // OUTSB DX,Xb + (const void *)&gInstructions[ 1641] // OUTSB DX,Xb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1650] // OUTSB DX,Xb + (const void *)&gInstructions[ 1640] // OUTSB DX,Xb }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6e_auxiliary = @@ -4369,13 +4369,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_6e_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_01_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1159] // INSW Yz,DX + (const void *)&gInstructions[ 1149] // INSW Yz,DX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1158] // INSW Yz,DX + (const void *)&gInstructions[ 1148] // INSW Yz,DX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_01_auxiliary = @@ -4398,13 +4398,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_01_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_00_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1153] // INSD Yz,DX + (const void *)&gInstructions[ 1143] // INSD Yz,DX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1152] // INSD Yz,DX + (const void *)&gInstructions[ 1142] // INSD Yz,DX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_00_auxiliary = @@ -4440,13 +4440,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_6d_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6c_auxiliary_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1151] // INSB Yb,DX + (const void *)&gInstructions[ 1141] // INSB Yb,DX }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6c_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1150] // INSB Yb,DX + (const void *)&gInstructions[ 1140] // INSB Yb,DX }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_6c_auxiliary = @@ -4469,37 +4469,37 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_6c_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1118] // IMUL Gv,Ev,Ib + (const void *)&gInstructions[ 1108] // IMUL Gv,Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1974] // PUSH Ib + (const void *)&gInstructions[ 1964] // PUSH Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_69_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1117] // IMUL Gv,Ev,Iz + (const void *)&gInstructions[ 1107] // IMUL Gv,Ev,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_68_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1973] // PUSH Iz + (const void *)&gInstructions[ 1963] // PUSH Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1473] // MOVSXD Gv,Ez + (const void *)&gInstructions[ 1463] // MOVSXD Gv,Ez }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 191] // ARPL Ew,Gw + (const void *)&gInstructions[ 183] // ARPL Ew,Gw }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_63_auxiliary = @@ -4522,7 +4522,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_63_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_62_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 226] // BOUND Gv,Ma + (const void *)&gInstructions[ 218] // BOUND Gv,Ma }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_62_modrmmod = @@ -4537,13 +4537,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_62_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1842] // POPAD + (const void *)&gInstructions[ 1832] // POPAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1841] // POPA + (const void *)&gInstructions[ 1831] // POPA }; const ND_TABLE_DSIZE gLegacyMap_opcode_61_dsize = @@ -4562,13 +4562,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_61_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1981] // PUSHAD + (const void *)&gInstructions[ 1971] // PUSHAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1980] // PUSHA + (const void *)&gInstructions[ 1970] // PUSHA }; const ND_TABLE_DSIZE gLegacyMap_opcode_60_dsize = @@ -4587,13 +4587,13 @@ const ND_TABLE_DSIZE gLegacyMap_opcode_60_dsize = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1858] // POPP Zv + (const void *)&gInstructions[ 1848] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1835] // POP Zv + (const void *)&gInstructions[ 1825] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5f_auxiliary = @@ -4616,13 +4616,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5f_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1857] // POPP Zv + (const void *)&gInstructions[ 1847] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1834] // POP Zv + (const void *)&gInstructions[ 1824] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5e_auxiliary = @@ -4645,13 +4645,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5e_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1856] // POPP Zv + (const void *)&gInstructions[ 1846] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1833] // POP Zv + (const void *)&gInstructions[ 1823] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5d_auxiliary = @@ -4674,13 +4674,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5d_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1855] // POPP Zv + (const void *)&gInstructions[ 1845] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1832] // POP Zv + (const void *)&gInstructions[ 1822] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5c_auxiliary = @@ -4703,13 +4703,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5c_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1854] // POPP Zv + (const void *)&gInstructions[ 1844] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1831] // POP Zv + (const void *)&gInstructions[ 1821] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5b_auxiliary = @@ -4732,13 +4732,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5b_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1853] // POPP Zv + (const void *)&gInstructions[ 1843] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1830] // POP Zv + (const void *)&gInstructions[ 1820] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_5a_auxiliary = @@ -4761,13 +4761,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_5a_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1852] // POPP Zv + (const void *)&gInstructions[ 1842] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1829] // POP Zv + (const void *)&gInstructions[ 1819] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_59_auxiliary = @@ -4790,13 +4790,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_59_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1851] // POPP Zv + (const void *)&gInstructions[ 1841] // POPP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1828] // POP Zv + (const void *)&gInstructions[ 1818] // POP Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_58_auxiliary = @@ -4819,13 +4819,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_58_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1992] // PUSHP Zv + (const void *)&gInstructions[ 1982] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1972] // PUSH Zv + (const void *)&gInstructions[ 1962] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_57_auxiliary = @@ -4848,13 +4848,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_57_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1991] // PUSHP Zv + (const void *)&gInstructions[ 1981] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1971] // PUSH Zv + (const void *)&gInstructions[ 1961] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_56_auxiliary = @@ -4877,13 +4877,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_56_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1990] // PUSHP Zv + (const void *)&gInstructions[ 1980] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1970] // PUSH Zv + (const void *)&gInstructions[ 1960] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_55_auxiliary = @@ -4906,13 +4906,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_55_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1989] // PUSHP Zv + (const void *)&gInstructions[ 1979] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1969] // PUSH Zv + (const void *)&gInstructions[ 1959] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_54_auxiliary = @@ -4935,13 +4935,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_54_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1988] // PUSHP Zv + (const void *)&gInstructions[ 1978] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1968] // PUSH Zv + (const void *)&gInstructions[ 1958] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_53_auxiliary = @@ -4964,13 +4964,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_53_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1987] // PUSHP Zv + (const void *)&gInstructions[ 1977] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1967] // PUSH Zv + (const void *)&gInstructions[ 1957] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_52_auxiliary = @@ -4993,13 +4993,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_52_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1986] // PUSHP Zv + (const void *)&gInstructions[ 1976] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1966] // PUSH Zv + (const void *)&gInstructions[ 1956] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_51_auxiliary = @@ -5022,13 +5022,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_51_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1985] // PUSHP Zv + (const void *)&gInstructions[ 1975] // PUSHP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1965] // PUSH Zv + (const void *)&gInstructions[ 1955] // PUSH Zv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_50_auxiliary = @@ -5051,97 +5051,97 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_50_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 879] // DEC Zv + (const void *)&gInstructions[ 871] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 878] // DEC Zv + (const void *)&gInstructions[ 870] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 877] // DEC Zv + (const void *)&gInstructions[ 869] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 876] // DEC Zv + (const void *)&gInstructions[ 868] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 875] // DEC Zv + (const void *)&gInstructions[ 867] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 874] // DEC Zv + (const void *)&gInstructions[ 866] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_49_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 873] // DEC Zv + (const void *)&gInstructions[ 865] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_48_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 872] // DEC Zv + (const void *)&gInstructions[ 864] // DEC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_47_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1145] // INC Zv + (const void *)&gInstructions[ 1135] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_46_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1144] // INC Zv + (const void *)&gInstructions[ 1134] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_45_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1143] // INC Zv + (const void *)&gInstructions[ 1133] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_44_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1142] // INC Zv + (const void *)&gInstructions[ 1132] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_43_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1141] // INC Zv + (const void *)&gInstructions[ 1131] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_42_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1140] // INC Zv + (const void *)&gInstructions[ 1130] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_41_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1139] // INC Zv + (const void *)&gInstructions[ 1129] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_40_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1138] // INC Zv + (const void *)&gInstructions[ 1128] // INC Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3f_leaf = @@ -5153,37 +5153,37 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3f_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 628] // CMP rAX,Iz + (const void *)&gInstructions[ 620] // CMP rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 627] // CMP AL,Ib + (const void *)&gInstructions[ 619] // CMP AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 626] // CMP Gv,Ev + (const void *)&gInstructions[ 618] // CMP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 625] // CMP Gb,Eb + (const void *)&gInstructions[ 617] // CMP Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_39_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 624] // CMP Ev,Gv + (const void *)&gInstructions[ 616] // CMP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_38_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 623] // CMP Eb,Gb + (const void *)&gInstructions[ 615] // CMP Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_37_leaf = @@ -5195,181 +5195,181 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_37_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4052] // XOR rAX,Iz + (const void *)&gInstructions[ 4134] // XOR rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4051] // XOR AL,Ib + (const void *)&gInstructions[ 4133] // XOR AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4050] // XOR Gv,Ev + (const void *)&gInstructions[ 4132] // XOR Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4049] // XOR Gb,Eb + (const void *)&gInstructions[ 4131] // XOR Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4048] // XOR Ev,Gv + (const void *)&gInstructions[ 4130] // XOR Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4047] // XOR Eb,Gb + (const void *)&gInstructions[ 4129] // XOR Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 859] // DAS + (const void *)&gInstructions[ 851] // DAS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2588] // SUB rAX,Iz + (const void *)&gInstructions[ 2572] // SUB rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2587] // SUB AL,Ib + (const void *)&gInstructions[ 2571] // SUB AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2586] // SUB Gv,Ev + (const void *)&gInstructions[ 2570] // SUB Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2585] // SUB Gb,Eb + (const void *)&gInstructions[ 2569] // SUB Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_29_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2584] // SUB Ev,Gv + (const void *)&gInstructions[ 2568] // SUB Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_28_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2583] // SUB Eb,Gb + (const void *)&gInstructions[ 2567] // SUB Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_27_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 858] // DAA + (const void *)&gInstructions[ 850] // DAA }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_25_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 177] // AND rAX,Iz + (const void *)&gInstructions[ 169] // AND rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_24_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 176] // AND AL,Ib + (const void *)&gInstructions[ 168] // AND AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_23_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 175] // AND Gv,Ev + (const void *)&gInstructions[ 167] // AND Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_22_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 174] // AND Gb,Eb + (const void *)&gInstructions[ 166] // AND Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_21_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 173] // AND Ev,Gv + (const void *)&gInstructions[ 165] // AND Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_20_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 172] // AND Eb,Gb + (const void *)&gInstructions[ 164] // AND Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1827] // POP DS + (const void *)&gInstructions[ 1817] // POP DS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1964] // PUSH DS + (const void *)&gInstructions[ 1954] // PUSH DS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2315] // SBB rAX,Iz + (const void *)&gInstructions[ 2306] // SBB rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2314] // SBB AL,Ib + (const void *)&gInstructions[ 2305] // SBB AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2313] // SBB Gv,Ev + (const void *)&gInstructions[ 2304] // SBB Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2312] // SBB Gb,Eb + (const void *)&gInstructions[ 2303] // SBB Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2311] // SBB Ev,Gv + (const void *)&gInstructions[ 2302] // SBB Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_18_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2310] // SBB Eb,Gb + (const void *)&gInstructions[ 2301] // SBB Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_17_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1826] // POP SS + (const void *)&gInstructions[ 1816] // POP SS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_16_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1963] // PUSH SS + (const void *)&gInstructions[ 1953] // PUSH SS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_15_leaf = @@ -5411,19 +5411,19 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_10_leaf = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ff_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2639] // UD0 Gd,Ed + (const void *)&gInstructions[ 2623] // UD0 Gd,Ed }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1672] // PADDD Vx,Wx + (const void *)&gInstructions[ 1662] // PADDD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1671] // PADDD Pq,Qq + (const void *)&gInstructions[ 1661] // PADDD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fe_prefix = @@ -5440,13 +5440,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fe_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1684] // PADDW Vx,Wx + (const void *)&gInstructions[ 1674] // PADDW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1683] // PADDW Pq,Qq + (const void *)&gInstructions[ 1673] // PADDW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fd_prefix = @@ -5463,13 +5463,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1670] // PADDB Vx,Wx + (const void *)&gInstructions[ 1660] // PADDB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1669] // PADDB Pq,Qq + (const void *)&gInstructions[ 1659] // PADDB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fc_prefix = @@ -5486,13 +5486,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1933] // PSUBQ Vx,Wx + (const void *)&gInstructions[ 1923] // PSUBQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1932] // PSUBQ Pq,Qq + (const void *)&gInstructions[ 1922] // PSUBQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fb_prefix = @@ -5509,13 +5509,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1931] // PSUBD Vx,Wx + (const void *)&gInstructions[ 1921] // PSUBD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1930] // PSUBD Pq,Qq + (const void *)&gInstructions[ 1920] // PSUBD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fa_prefix = @@ -5532,13 +5532,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fa_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1943] // PSUBW Vx,Wx + (const void *)&gInstructions[ 1933] // PSUBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1942] // PSUBW Pq,Qq + (const void *)&gInstructions[ 1932] // PSUBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f9_prefix = @@ -5555,13 +5555,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1929] // PSUBB Vx,Wx + (const void *)&gInstructions[ 1919] // PSUBB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1928] // PSUBB Pq,Qq + (const void *)&gInstructions[ 1918] // PSUBB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f8_prefix = @@ -5578,7 +5578,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f8_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1353] // MASKMOVDQU Vdq,Udq + (const void *)&gInstructions[ 1343] // MASKMOVDQU Vdq,Udq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod = @@ -5593,7 +5593,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1354] // MASKMOVQ Pq,Nq + (const void *)&gInstructions[ 1344] // MASKMOVQ Pq,Nq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod = @@ -5619,13 +5619,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f7_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1880] // PSADBW Vx,Wx + (const void *)&gInstructions[ 1870] // PSADBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1879] // PSADBW Pq,Qq + (const void *)&gInstructions[ 1869] // PSADBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f6_prefix = @@ -5642,13 +5642,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1781] // PMADDWD Vx,Wx + (const void *)&gInstructions[ 1771] // PMADDWD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1780] // PMADDWD Pq,Qq + (const void *)&gInstructions[ 1770] // PMADDWD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f5_prefix = @@ -5665,13 +5665,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1824] // PMULUDQ Vx,Wx + (const void *)&gInstructions[ 1814] // PMULUDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1823] // PMULUDQ Pq,Qq + (const void *)&gInstructions[ 1813] // PMULUDQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f4_prefix = @@ -5688,13 +5688,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1901] // PSLLQ Vx,Wx + (const void *)&gInstructions[ 1891] // PSLLQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1900] // PSLLQ Pq,Qq + (const void *)&gInstructions[ 1890] // PSLLQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f3_prefix = @@ -5711,13 +5711,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1896] // PSLLD Vx,Wx + (const void *)&gInstructions[ 1886] // PSLLD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1895] // PSLLD Pq,Qq + (const void *)&gInstructions[ 1885] // PSLLD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f2_prefix = @@ -5734,13 +5734,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1905] // PSLLW Vx,Wx + (const void *)&gInstructions[ 1895] // PSLLW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1904] // PSLLW Pq,Qq + (const void *)&gInstructions[ 1894] // PSLLW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f1_prefix = @@ -5757,7 +5757,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f1_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1312] // LDDQU Vx,Mx + (const void *)&gInstructions[ 1302] // LDDQU Vx,Mx }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod = @@ -5783,13 +5783,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1995] // PXOR Vx,Wx + (const void *)&gInstructions[ 1985] // PXOR Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1994] // PXOR Pq,Qq + (const void *)&gInstructions[ 1984] // PXOR Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ef_prefix = @@ -5806,13 +5806,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ef_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1785] // PMAXSW Vx,Wx + (const void *)&gInstructions[ 1775] // PMAXSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1784] // PMAXSW Pq,Qq + (const void *)&gInstructions[ 1774] // PMAXSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ee_prefix = @@ -5829,13 +5829,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ee_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1678] // PADDSW Vx,Wx + (const void *)&gInstructions[ 1668] // PADDSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1677] // PADDSW Pq,Qq + (const void *)&gInstructions[ 1667] // PADDSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ed_prefix = @@ -5852,13 +5852,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ed_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1676] // PADDSB Vx,Wx + (const void *)&gInstructions[ 1666] // PADDSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1675] // PADDSB Pq,Qq + (const void *)&gInstructions[ 1665] // PADDSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ec_prefix = @@ -5875,13 +5875,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ec_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1860] // POR Vx,Wx + (const void *)&gInstructions[ 1850] // POR Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1859] // POR Pq,Qq + (const void *)&gInstructions[ 1849] // POR Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_eb_prefix = @@ -5898,13 +5898,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_eb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1793] // PMINSW Vx,Wx + (const void *)&gInstructions[ 1783] // PMINSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1792] // PMINSW Pq,Qq + (const void *)&gInstructions[ 1782] // PMINSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ea_prefix = @@ -5921,13 +5921,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ea_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1937] // PSUBSW Vx,Wx + (const void *)&gInstructions[ 1927] // PSUBSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1936] // PSUBSW Pq,Qq + (const void *)&gInstructions[ 1926] // PSUBSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e9_prefix = @@ -5944,13 +5944,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1935] // PSUBSB Vx,Wx + (const void *)&gInstructions[ 1925] // PSUBSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1934] // PSUBSB Pq,Qq + (const void *)&gInstructions[ 1924] // PSUBSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e8_prefix = @@ -5967,7 +5967,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e8_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1440] // MOVNTDQ Mx,Vx + (const void *)&gInstructions[ 1430] // MOVNTDQ Mx,Vx }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod = @@ -5982,7 +5982,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1445] // MOVNTQ Mq,Pq + (const void *)&gInstructions[ 1435] // MOVNTQ Mq,Pq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod = @@ -6008,19 +6008,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e7_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 836] // CVTPD2DQ Vx,Wpd + (const void *)&gInstructions[ 828] // CVTPD2DQ Vx,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 834] // CVTDQ2PD Vx,Wq + (const void *)&gInstructions[ 826] // CVTDQ2PD Vx,Wq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 850] // CVTTPD2DQ Vx,Wpd + (const void *)&gInstructions[ 842] // CVTTPD2DQ Vx,Wpd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e6_prefix = @@ -6037,13 +6037,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1819] // PMULHW Vx,Wx + (const void *)&gInstructions[ 1809] // PMULHW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1818] // PMULHW Pq,Qq + (const void *)&gInstructions[ 1808] // PMULHW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e5_prefix = @@ -6060,13 +6060,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1817] // PMULHUW Vx,Wx + (const void *)&gInstructions[ 1807] // PMULHUW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1816] // PMULHUW Pq,Qq + (const void *)&gInstructions[ 1806] // PMULHUW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e4_prefix = @@ -6083,13 +6083,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1696] // PAVGW Vx,Wx + (const void *)&gInstructions[ 1686] // PAVGW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1695] // PAVGW Pq,Qq + (const void *)&gInstructions[ 1685] // PAVGW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e3_prefix = @@ -6106,13 +6106,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1910] // PSRAD Vx,Wx + (const void *)&gInstructions[ 1900] // PSRAD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1909] // PSRAD Pq,Qq + (const void *)&gInstructions[ 1899] // PSRAD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e2_prefix = @@ -6129,13 +6129,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1914] // PSRAW Vx,Wx + (const void *)&gInstructions[ 1904] // PSRAW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1913] // PSRAW Pq,Qq + (const void *)&gInstructions[ 1903] // PSRAW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e1_prefix = @@ -6152,13 +6152,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e1_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1693] // PAVGB Vx,Wx + (const void *)&gInstructions[ 1683] // PAVGB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1692] // PAVGB Pq,Qq + (const void *)&gInstructions[ 1682] // PAVGB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e0_prefix = @@ -6175,13 +6175,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1690] // PANDN Vx,Wx + (const void *)&gInstructions[ 1680] // PANDN Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1689] // PANDN Pq,Qq + (const void *)&gInstructions[ 1679] // PANDN Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_df_prefix = @@ -6198,13 +6198,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_df_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1787] // PMAXUB Vx,Wx + (const void *)&gInstructions[ 1777] // PMAXUB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1786] // PMAXUB Pq,Qq + (const void *)&gInstructions[ 1776] // PMAXUB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_de_prefix = @@ -6221,13 +6221,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_de_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1682] // PADDUSW Vx,Wx + (const void *)&gInstructions[ 1672] // PADDUSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1681] // PADDUSW Pq,Qq + (const void *)&gInstructions[ 1671] // PADDUSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dd_prefix = @@ -6244,13 +6244,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1680] // PADDUSB Vx,Wx + (const void *)&gInstructions[ 1670] // PADDUSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1679] // PADDUSB Pq,Qq + (const void *)&gInstructions[ 1669] // PADDUSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dc_prefix = @@ -6267,13 +6267,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1688] // PAND Vx,Wx + (const void *)&gInstructions[ 1678] // PAND Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1687] // PAND Pq,Qq + (const void *)&gInstructions[ 1677] // PAND Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_db_prefix = @@ -6290,13 +6290,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_db_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1795] // PMINUB Vx,Wx + (const void *)&gInstructions[ 1785] // PMINUB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1794] // PMINUB Pq,Qq + (const void *)&gInstructions[ 1784] // PMINUB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_da_prefix = @@ -6313,13 +6313,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_da_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1941] // PSUBUSW Vx,Wx + (const void *)&gInstructions[ 1931] // PSUBUSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1940] // PSUBUSW Pq,Qq + (const void *)&gInstructions[ 1930] // PSUBUSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d9_prefix = @@ -6336,13 +6336,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1939] // PSUBUSB Vx,Wx + (const void *)&gInstructions[ 1929] // PSUBUSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1938] // PSUBUSB Pq,Qq + (const void *)&gInstructions[ 1928] // PSUBUSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d8_prefix = @@ -6359,7 +6359,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d8_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1799] // PMOVMSKB Gy,Ux + (const void *)&gInstructions[ 1789] // PMOVMSKB Gy,Ux }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod = @@ -6374,7 +6374,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1798] // PMOVMSKB Gy,Nq + (const void *)&gInstructions[ 1788] // PMOVMSKB Gy,Nq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod = @@ -6400,7 +6400,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d7_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1424] // MOVDQ2Q Pq,Uq + (const void *)&gInstructions[ 1414] // MOVDQ2Q Pq,Uq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod = @@ -6415,7 +6415,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1456] // MOVQ2DQ Vdq,Nq + (const void *)&gInstructions[ 1446] // MOVQ2DQ Vdq,Nq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod = @@ -6430,7 +6430,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1455] // MOVQ Wq,Vq + (const void *)&gInstructions[ 1445] // MOVQ Wq,Vq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d6_prefix = @@ -6447,13 +6447,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1822] // PMULLW Vx,Wx + (const void *)&gInstructions[ 1812] // PMULLW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1821] // PMULLW Pq,Qq + (const void *)&gInstructions[ 1811] // PMULLW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d5_prefix = @@ -6470,13 +6470,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1674] // PADDQ Vx,Wx + (const void *)&gInstructions[ 1664] // PADDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1673] // PADDQ Pq,Qq + (const void *)&gInstructions[ 1663] // PADDQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d4_prefix = @@ -6493,13 +6493,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1923] // PSRLQ Vx,Wx + (const void *)&gInstructions[ 1913] // PSRLQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1922] // PSRLQ Pq,Qq + (const void *)&gInstructions[ 1912] // PSRLQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d3_prefix = @@ -6516,13 +6516,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1918] // PSRLD Vx,Wx + (const void *)&gInstructions[ 1908] // PSRLD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1917] // PSRLD Pq,Qq + (const void *)&gInstructions[ 1907] // PSRLD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d2_prefix = @@ -6539,13 +6539,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1927] // PSRLW Vx,Wx + (const void *)&gInstructions[ 1917] // PSRLW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1926] // PSRLW Pq,Qq + (const void *)&gInstructions[ 1916] // PSRLW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d1_prefix = @@ -6585,55 +6585,55 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 236] // BSWAP Zv + (const void *)&gInstructions[ 228] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 235] // BSWAP Zv + (const void *)&gInstructions[ 227] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 234] // BSWAP Zv + (const void *)&gInstructions[ 226] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 233] // BSWAP Zv + (const void *)&gInstructions[ 225] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 232] // BSWAP Zv + (const void *)&gInstructions[ 224] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ca_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 231] // BSWAP Zv + (const void *)&gInstructions[ 223] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 230] // BSWAP Zv + (const void *)&gInstructions[ 222] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 229] // BSWAP Zv + (const void *)&gInstructions[ 221] // BSWAP Zv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2086] // RDPID Ryf + (const void *)&gInstructions[ 2076] // RDPID Ryf }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod = @@ -6648,7 +6648,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2093] // RDSEED Rv + (const void *)&gInstructions[ 2083] // RDSEED Rv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod = @@ -6663,13 +6663,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2092] // RDSEED Rv + (const void *)&gInstructions[ 2082] // RDSEED Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3283] // VMPTRST Mq + (const void *)&gInstructions[ 3342] // VMPTRST Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod = @@ -6695,13 +6695,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2331] // SENDUIPI Rq + (const void *)&gInstructions[ 2322] // SENDUIPI Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3300] // VMXON Mq + (const void *)&gInstructions[ 3360] // VMXON Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod = @@ -6716,13 +6716,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2091] // RDRAND Rv + (const void *)&gInstructions[ 2081] // RDRAND Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3156] // VMCLEAR Mq + (const void *)&gInstructions[ 3202] // VMCLEAR Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod = @@ -6737,13 +6737,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2090] // RDRAND Rv + (const void *)&gInstructions[ 2080] // RDRAND Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3282] // VMPTRLD Mq + (const void *)&gInstructions[ 3341] // VMPTRLD Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod = @@ -6769,13 +6769,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4071] // XSAVES64 M? + (const void *)&gInstructions[ 4153] // XSAVES64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4070] // XSAVES M? + (const void *)&gInstructions[ 4152] // XSAVES M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary = @@ -6818,13 +6818,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4067] // XSAVEC64 M? + (const void *)&gInstructions[ 4149] // XSAVEC64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4066] // XSAVEC M? + (const void *)&gInstructions[ 4148] // XSAVEC M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary = @@ -6867,13 +6867,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4063] // XRSTORS64 M? + (const void *)&gInstructions[ 4145] // XRSTORS64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4062] // XRSTORS M? + (const void *)&gInstructions[ 4144] // XRSTORS M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary = @@ -6916,13 +6916,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 677] // CMPXCHG16B Mdq + (const void *)&gInstructions[ 669] // CMPXCHG16B Mdq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 678] // CMPXCHG8B Mq + (const void *)&gInstructions[ 670] // CMPXCHG8B Mq }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary = @@ -6969,13 +6969,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_c7_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2506] // SHUFPD Vpd,Wpd,Ib + (const void *)&gInstructions[ 2490] // SHUFPD Vpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2507] // SHUFPS Vps,Wps,Ib + (const void *)&gInstructions[ 2491] // SHUFPS Vps,Wps,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c6_prefix = @@ -6992,7 +6992,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1731] // PEXTRW Gy,Udq,Ib + (const void *)&gInstructions[ 1721] // PEXTRW Gy,Udq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod = @@ -7007,7 +7007,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1730] // PEXTRW Gy,Nq,Ib + (const void *)&gInstructions[ 1720] // PEXTRW Gy,Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod = @@ -7033,13 +7033,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1776] // PINSRW Vdq,Rd,Ib + (const void *)&gInstructions[ 1766] // PINSRW Vdq,Rd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1777] // PINSRW Vdq,Mw,Ib + (const void *)&gInstructions[ 1767] // PINSRW Vdq,Mw,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod = @@ -7054,13 +7054,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1774] // PINSRW Pq,Rd,Ib + (const void *)&gInstructions[ 1764] // PINSRW Pq,Rd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1775] // PINSRW Pq,Mw,Ib + (const void *)&gInstructions[ 1765] // PINSRW Pq,Mw,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod = @@ -7086,7 +7086,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c4_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1442] // MOVNTI My,Gy + (const void *)&gInstructions[ 1432] // MOVNTI My,Gy }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod = @@ -7112,25 +7112,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c3_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 667] // CMPSD Vsd,Wsd,Ib + (const void *)&gInstructions[ 659] // CMPSD Vsd,Wsd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 670] // CMPSS Vss,Wss,Ib + (const void *)&gInstructions[ 662] // CMPSS Vss,Wss,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 659] // CMPPD Vpd,Wpd,Ib + (const void *)&gInstructions[ 651] // CMPPD Vpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 660] // CMPPS Vps,Wps,Ib + (const void *)&gInstructions[ 652] // CMPPS Vps,Wps,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c2_prefix = @@ -7147,37 +7147,37 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c2_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3988] // XADD Ev,Gv + (const void *)&gInstructions[ 4070] // XADD Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3987] // XADD Eb,Gb + (const void *)&gInstructions[ 4069] // XADD Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1472] // MOVSX Gv,Ew + (const void *)&gInstructions[ 1462] // MOVSX Gv,Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_be_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1471] // MOVSX Gv,Eb + (const void *)&gInstructions[ 1461] // MOVSX Gv,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1352] // LZCNT Gv,Ev + (const void *)&gInstructions[ 1342] // LZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 228] // BSR Gv,Ev + (const void *)&gInstructions[ 220] // BSR Gv,Ev }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bd_auxiliary = @@ -7200,13 +7200,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bd_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2635] // TZCNT Gv,Ev + (const void *)&gInstructions[ 2619] // TZCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 227] // BSF Gv,Ev + (const void *)&gInstructions[ 219] // BSF Gv,Ev }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bc_auxiliary = @@ -7229,31 +7229,31 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bc_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 240] // BTC Ev,Gv + (const void *)&gInstructions[ 232] // BTC Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 239] // BTC Ev,Ib + (const void *)&gInstructions[ 231] // BTC Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 242] // BTR Ev,Ib + (const void *)&gInstructions[ 234] // BTR Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 244] // BTS Ev,Ib + (const void *)&gInstructions[ 236] // BTS Ev,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 238] // BT Ev,Ib + (const void *)&gInstructions[ 230] // BT Ev,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ba_modrmreg = @@ -7274,19 +7274,19 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ba_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2640] // UD1 Gd,Ed + (const void *)&gInstructions[ 2624] // UD1 Gd,Ed }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1847] // POPCNT Gv,Ev + (const void *)&gInstructions[ 1837] // POPCNT Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1192] // JMPE Jz + (const void *)&gInstructions[ 1182] // JMPE Jz }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_b8_auxiliary = @@ -7309,19 +7309,19 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_b8_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1479] // MOVZX Gv,Ew + (const void *)&gInstructions[ 1469] // MOVZX Gv,Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1478] // MOVZX Gv,Eb + (const void *)&gInstructions[ 1468] // MOVZX Gv,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b5_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1323] // LGS Gv,Mp + (const void *)&gInstructions[ 1313] // LGS Gv,Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b5_modrmmod = @@ -7336,7 +7336,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b5_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b4_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1321] // LFS Gv,Mp + (const void *)&gInstructions[ 1311] // LFS Gv,Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b4_modrmmod = @@ -7351,13 +7351,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b4_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 241] // BTR Ev,Gv + (const void *)&gInstructions[ 233] // BTR Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b2_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1344] // LSS Gv,Mp + (const void *)&gInstructions[ 1334] // LSS Gv,Mp }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b2_modrmmod = @@ -7372,25 +7372,25 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b2_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 676] // CMPXCHG Ev,Gv + (const void *)&gInstructions[ 668] // CMPXCHG Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 675] // CMPXCHG Eb,Gb + (const void *)&gInstructions[ 667] // CMPXCHG Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_af_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1121] // IMUL Gv,Ev + (const void *)&gInstructions[ 1111] // IMUL Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2644] // UMWAIT Ry + (const void *)&gInstructions[ 2628] // UMWAIT Ry }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod = @@ -7420,13 +7420,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2643] // UMONITOR mMb + (const void *)&gInstructions[ 2627] // UMONITOR mMb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 569] // CLRSSBSY Mq + (const void *)&gInstructions[ 561] // CLRSSBSY Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod = @@ -7441,13 +7441,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1149] // INCSSPQ Rq + (const void *)&gInstructions[ 1139] // INCSSPQ Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1148] // INCSSPD Rd + (const void *)&gInstructions[ 1138] // INCSSPD Rd }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary = @@ -7479,13 +7479,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1946] // PTWRITE Ey + (const void *)&gInstructions[ 1936] // PTWRITE Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3973] // WRGSBASE Ry + (const void *)&gInstructions[ 4055] // WRGSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary = @@ -7517,7 +7517,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3972] // WRFSBASE Ry + (const void *)&gInstructions[ 4054] // WRFSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary = @@ -7549,7 +7549,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2083] // RDGSBASE Ry + (const void *)&gInstructions[ 2073] // RDGSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary = @@ -7581,7 +7581,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2082] // RDFSBASE Ry + (const void *)&gInstructions[ 2072] // RDFSBASE Ry }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary = @@ -7628,7 +7628,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 566] // CLFLUSHOPT Mb + (const void *)&gInstructions[ 558] // CLFLUSHOPT Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod = @@ -7643,13 +7643,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2630] // TPAUSE Ry + (const void *)&gInstructions[ 2614] // TPAUSE Ry }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 572] // CLWB Mb + (const void *)&gInstructions[ 564] // CLWB Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod = @@ -7679,13 +7679,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2366] // SFENCE + (const void *)&gInstructions[ 2357] // SFENCE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 565] // CLFLUSH Mb + (const void *)&gInstructions[ 557] // CLFLUSH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod = @@ -7700,19 +7700,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1360] // MFENCE + (const void *)&gInstructions[ 1350] // MFENCE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4069] // XSAVEOPT64 M? + (const void *)&gInstructions[ 4151] // XSAVEOPT64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4068] // XSAVEOPT M? + (const void *)&gInstructions[ 4150] // XSAVEOPT M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary = @@ -7744,19 +7744,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1320] // LFENCE + (const void *)&gInstructions[ 1310] // LFENCE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4061] // XRSTOR64 M? + (const void *)&gInstructions[ 4143] // XRSTOR64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4060] // XRSTOR M? + (const void *)&gInstructions[ 4142] // XRSTOR M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary = @@ -7788,13 +7788,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4065] // XSAVE64 M? + (const void *)&gInstructions[ 4147] // XSAVE64 M? }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4064] // XSAVE M? + (const void *)&gInstructions[ 4146] // XSAVE M? }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary = @@ -7826,7 +7826,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2525] // STMXCSR Md + (const void *)&gInstructions[ 2509] // STMXCSR Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod = @@ -7841,7 +7841,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1313] // LDMXCSR Md + (const void *)&gInstructions[ 1303] // LDMXCSR Md }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod = @@ -7856,13 +7856,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1063] // FXRSTOR64 Mrx + (const void *)&gInstructions[ 1053] // FXRSTOR64 Mrx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1062] // FXRSTOR Mrx + (const void *)&gInstructions[ 1052] // FXRSTOR Mrx }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary = @@ -7894,13 +7894,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1065] // FXSAVE64 Mrx + (const void *)&gInstructions[ 1055] // FXSAVE64 Mrx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1064] // FXSAVE Mrx + (const void *)&gInstructions[ 1054] // FXSAVE Mrx }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary = @@ -7958,283 +7958,283 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ae_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ad_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2503] // SHRD Ev,Gv,CL + (const void *)&gInstructions[ 2487] // SHRD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ac_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2502] // SHRD Ev,Gv,Ib + (const void *)&gInstructions[ 2486] // SHRD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ab_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 243] // BTS Ev,Gv + (const void *)&gInstructions[ 235] // BTS Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2195] // RSM + (const void *)&gInstructions[ 2186] // RSM }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a9_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1838] // POP GS + (const void *)&gInstructions[ 1828] // POP GS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a8_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1977] // PUSH GS + (const void *)&gInstructions[ 1967] // PUSH GS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a5_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2441] // SHLD Ev,Gv,CL + (const void *)&gInstructions[ 2425] // SHLD Ev,Gv,CL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2440] // SHLD Ev,Gv,Ib + (const void *)&gInstructions[ 2424] // SHLD Ev,Gv,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 237] // BT Ev,Gv + (const void *)&gInstructions[ 229] // BT Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 683] // CPUID + (const void *)&gInstructions[ 675] // CPUID }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1837] // POP FS + (const void *)&gInstructions[ 1827] // POP FS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1976] // PUSH FS + (const void *)&gInstructions[ 1966] // PUSH FS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2348] // SETNLE Eb + (const void *)&gInstructions[ 2339] // SETNLE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2340] // SETLE Eb + (const void *)&gInstructions[ 2331] // SETLE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2346] // SETNL Eb + (const void *)&gInstructions[ 2337] // SETNL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2338] // SETL Eb + (const void *)&gInstructions[ 2329] // SETL Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2352] // SETNP Eb + (const void *)&gInstructions[ 2343] // SETNP Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2360] // SETP Eb + (const void *)&gInstructions[ 2351] // SETP Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_99_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2354] // SETNS Eb + (const void *)&gInstructions[ 2345] // SETNS Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_98_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2362] // SETS Eb + (const void *)&gInstructions[ 2353] // SETS Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2342] // SETNBE Eb + (const void *)&gInstructions[ 2333] // SETNBE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2334] // SETBE Eb + (const void *)&gInstructions[ 2325] // SETBE Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2356] // SETNZ Eb + (const void *)&gInstructions[ 2347] // SETNZ Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2365] // SETZ Eb + (const void *)&gInstructions[ 2356] // SETZ Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_93_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2344] // SETNC Eb + (const void *)&gInstructions[ 2335] // SETNC Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_92_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2336] // SETC Eb + (const void *)&gInstructions[ 2327] // SETC Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_91_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2350] // SETNO Eb + (const void *)&gInstructions[ 2341] // SETNO Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2358] // SETO Eb + (const void *)&gInstructions[ 2349] // SETO Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1202] // JNLE Jz + (const void *)&gInstructions[ 1192] // JNLE Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1186] // JLE Jz + (const void *)&gInstructions[ 1176] // JLE Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1200] // JNL Jz + (const void *)&gInstructions[ 1190] // JNL Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1184] // JL Jz + (const void *)&gInstructions[ 1174] // JL Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1206] // JNP Jz + (const void *)&gInstructions[ 1196] // JNP Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1214] // JP Jz + (const void *)&gInstructions[ 1204] // JP Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_89_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1208] // JNS Jz + (const void *)&gInstructions[ 1198] // JNS Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_88_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1217] // JS Jz + (const void *)&gInstructions[ 1207] // JS Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1196] // JNBE Jz + (const void *)&gInstructions[ 1186] // JNBE Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1178] // JBE Jz + (const void *)&gInstructions[ 1168] // JBE Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1210] // JNZ Jz + (const void *)&gInstructions[ 1200] // JNZ Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_84_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1219] // JZ Jz + (const void *)&gInstructions[ 1209] // JZ Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1198] // JNC Jz + (const void *)&gInstructions[ 1188] // JNC Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1180] // JC Jz + (const void *)&gInstructions[ 1170] // JC Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1204] // JNO Jz + (const void *)&gInstructions[ 1194] // JNO Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1212] // JO Jz + (const void *)&gInstructions[ 1202] // JO Jz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1428] // MOVDQU Wx,Vx + (const void *)&gInstructions[ 1418] // MOVDQU Wx,Vx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1426] // MOVDQA Wx,Vx + (const void *)&gInstructions[ 1416] // MOVDQA Wx,Vx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1454] // MOVQ Qq,Pq + (const void *)&gInstructions[ 1444] // MOVQ Qq,Pq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7f_prefix = @@ -8251,19 +8251,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1453] // MOVQ Vdq,Wq + (const void *)&gInstructions[ 1443] // MOVQ Vdq,Wq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1452] // MOVQ Ey,Vdq + (const void *)&gInstructions[ 1442] // MOVQ Ey,Vdq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1418] // MOVD Ey,Vdq + (const void *)&gInstructions[ 1408] // MOVD Ey,Vdq }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary = @@ -8286,13 +8286,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1451] // MOVQ Ey,Pq + (const void *)&gInstructions[ 1441] // MOVQ Ey,Pq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1417] // MOVD Ey,Pd + (const void *)&gInstructions[ 1407] // MOVD Ey,Pd }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary = @@ -8326,13 +8326,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7d_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1078] // HSUBPS Vps,Wps + (const void *)&gInstructions[ 1068] // HSUBPS Vps,Wps }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1077] // HSUBPD Vpd,Wpd + (const void *)&gInstructions[ 1067] // HSUBPD Vpd,Wpd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7d_prefix = @@ -8349,13 +8349,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7c_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1074] // HADDPS Vps,Wps + (const void *)&gInstructions[ 1064] // HADDPS Vps,Wps }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1073] // HADDPD Vpd,Wpd + (const void *)&gInstructions[ 1063] // HADDPD Vpd,Wpd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7c_prefix = @@ -8372,7 +8372,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1157] // INSERTQ Vdq,Udq + (const void *)&gInstructions[ 1147] // INSERTQ Vdq,Udq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod = @@ -8387,7 +8387,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 916] // EXTRQ Vdq,Uq + (const void *)&gInstructions[ 906] // EXTRQ Vdq,Uq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod = @@ -8402,7 +8402,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3298] // VMWRITE Gy,Ey + (const void *)&gInstructions[ 3358] // VMWRITE Gy,Ey }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_79_prefix = @@ -8419,13 +8419,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_79_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1156] // INSERTQ Vdq,Udq,Ib,Ib + (const void *)&gInstructions[ 1146] // INSERTQ Vdq,Udq,Ib,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 915] // EXTRQ Uq,Ib,Ib + (const void *)&gInstructions[ 905] // EXTRQ Uq,Ib,Ib }; const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg = @@ -8446,7 +8446,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3284] // VMREAD Ey,Gy + (const void *)&gInstructions[ 3343] // VMREAD Ey,Gy }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_78_prefix = @@ -8463,7 +8463,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_78_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_77_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 897] // EMMS + (const void *)&gInstructions[ 889] // EMMS }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_77_prefix = @@ -8480,13 +8480,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_77_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1704] // PCMPEQD Vx,Wx + (const void *)&gInstructions[ 1694] // PCMPEQD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1703] // PCMPEQD Pq,Qq + (const void *)&gInstructions[ 1693] // PCMPEQD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_76_prefix = @@ -8503,13 +8503,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_76_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1707] // PCMPEQW Vx,Wx + (const void *)&gInstructions[ 1697] // PCMPEQW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1706] // PCMPEQW Pq,Qq + (const void *)&gInstructions[ 1696] // PCMPEQW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_75_prefix = @@ -8526,13 +8526,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_75_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1702] // PCMPEQB Vx,Wx + (const void *)&gInstructions[ 1692] // PCMPEQB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1701] // PCMPEQB Pq,Qq + (const void *)&gInstructions[ 1691] // PCMPEQB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_74_prefix = @@ -8549,7 +8549,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_74_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1897] // PSLLDQ Ux,Ib + (const void *)&gInstructions[ 1887] // PSLLDQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod = @@ -8564,7 +8564,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1899] // PSLLQ Ux,Ib + (const void *)&gInstructions[ 1889] // PSLLQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod = @@ -8579,7 +8579,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1919] // PSRLDQ Ux,Ib + (const void *)&gInstructions[ 1909] // PSRLDQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod = @@ -8594,7 +8594,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1921] // PSRLQ Ux,Ib + (const void *)&gInstructions[ 1911] // PSRLQ Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod = @@ -8624,7 +8624,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1898] // PSLLQ Nq,Ib + (const void *)&gInstructions[ 1888] // PSLLQ Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod = @@ -8639,7 +8639,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1920] // PSRLQ Nq,Ib + (const void *)&gInstructions[ 1910] // PSRLQ Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod = @@ -8680,7 +8680,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_73_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1894] // PSLLD Ux,Ib + (const void *)&gInstructions[ 1884] // PSLLD Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod = @@ -8695,7 +8695,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1908] // PSRAD Ux,Ib + (const void *)&gInstructions[ 1898] // PSRAD Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod = @@ -8710,7 +8710,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1916] // PSRLD Ux,Ib + (const void *)&gInstructions[ 1906] // PSRLD Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod = @@ -8740,7 +8740,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1893] // PSLLD Nq,Ib + (const void *)&gInstructions[ 1883] // PSLLD Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod = @@ -8755,7 +8755,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1907] // PSRAD Nq,Ib + (const void *)&gInstructions[ 1897] // PSRAD Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod = @@ -8770,7 +8770,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1915] // PSRLD Nq,Ib + (const void *)&gInstructions[ 1905] // PSRLD Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod = @@ -8811,7 +8811,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_72_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1903] // PSLLW Ux,Ib + (const void *)&gInstructions[ 1893] // PSLLW Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod = @@ -8826,7 +8826,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1912] // PSRAW Ux,Ib + (const void *)&gInstructions[ 1902] // PSRAW Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod = @@ -8841,7 +8841,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1925] // PSRLW Ux,Ib + (const void *)&gInstructions[ 1915] // PSRLW Ux,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod = @@ -8871,7 +8871,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1902] // PSLLW Nq,Ib + (const void *)&gInstructions[ 1892] // PSLLW Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod = @@ -8886,7 +8886,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1911] // PSRAW Nq,Ib + (const void *)&gInstructions[ 1901] // PSRAW Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod = @@ -8901,7 +8901,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1924] // PSRLW Nq,Ib + (const void *)&gInstructions[ 1914] // PSRLW Nq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod = @@ -8942,25 +8942,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_71_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1885] // PSHUFLW Vx,Wx,Ib + (const void *)&gInstructions[ 1875] // PSHUFLW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1884] // PSHUFHW Vx,Wx,Ib + (const void *)&gInstructions[ 1874] // PSHUFHW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1883] // PSHUFD Vx,Wx,Ib + (const void *)&gInstructions[ 1873] // PSHUFD Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1886] // PSHUFW Pq,Qq,Ib + (const void *)&gInstructions[ 1876] // PSHUFW Pq,Qq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_70_prefix = @@ -8977,19 +8977,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_70_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1427] // MOVDQU Vx,Wx + (const void *)&gInstructions[ 1417] // MOVDQU Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1425] // MOVDQA Vx,Wx + (const void *)&gInstructions[ 1415] // MOVDQA Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1450] // MOVQ Pq,Qq + (const void *)&gInstructions[ 1440] // MOVQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6f_prefix = @@ -9006,13 +9006,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1449] // MOVQ Vdq,Ey + (const void *)&gInstructions[ 1439] // MOVQ Vdq,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1416] // MOVD Vdq,Ey + (const void *)&gInstructions[ 1406] // MOVD Vdq,Ey }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary = @@ -9035,13 +9035,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1448] // MOVQ Pq,Ey + (const void *)&gInstructions[ 1438] // MOVQ Pq,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1415] // MOVD Pq,Ey + (const void *)&gInstructions[ 1405] // MOVD Pq,Ey }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary = @@ -9075,7 +9075,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1951] // PUNPCKHQDQ Vx,Wx + (const void *)&gInstructions[ 1941] // PUNPCKHQDQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6d_prefix = @@ -9092,7 +9092,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1958] // PUNPCKLQDQ Vx,Wx + (const void *)&gInstructions[ 1948] // PUNPCKLQDQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6c_prefix = @@ -9109,13 +9109,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1663] // PACKSSDW Vx,Wx + (const void *)&gInstructions[ 1653] // PACKSSDW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1662] // PACKSSDW Pq,Qq + (const void *)&gInstructions[ 1652] // PACKSSDW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6b_prefix = @@ -9132,13 +9132,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1950] // PUNPCKHDQ Vx,Wx + (const void *)&gInstructions[ 1940] // PUNPCKHDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1949] // PUNPCKHDQ Pq,Qq + (const void *)&gInstructions[ 1939] // PUNPCKHDQ Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6a_prefix = @@ -9155,13 +9155,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1953] // PUNPCKHWD Vx,Wx + (const void *)&gInstructions[ 1943] // PUNPCKHWD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1952] // PUNPCKHWD Pq,Qq + (const void *)&gInstructions[ 1942] // PUNPCKHWD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_69_prefix = @@ -9178,13 +9178,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_69_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1948] // PUNPCKHBW Vx,Wx + (const void *)&gInstructions[ 1938] // PUNPCKHBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1947] // PUNPCKHBW Pq,Qq + (const void *)&gInstructions[ 1937] // PUNPCKHBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_68_prefix = @@ -9201,13 +9201,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_68_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1668] // PACKUSWB Vx,Wx + (const void *)&gInstructions[ 1658] // PACKUSWB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1667] // PACKUSWB Pq,Qq + (const void *)&gInstructions[ 1657] // PACKUSWB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_67_prefix = @@ -9224,13 +9224,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_67_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1713] // PCMPGTD Vx,Wx + (const void *)&gInstructions[ 1703] // PCMPGTD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1712] // PCMPGTD Pq,Qq + (const void *)&gInstructions[ 1702] // PCMPGTD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_66_prefix = @@ -9247,13 +9247,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_66_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1716] // PCMPGTW Vx,Wx + (const void *)&gInstructions[ 1706] // PCMPGTW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1715] // PCMPGTW Pq,Qq + (const void *)&gInstructions[ 1705] // PCMPGTW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_65_prefix = @@ -9270,13 +9270,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_65_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1711] // PCMPGTB Vx,Wx + (const void *)&gInstructions[ 1701] // PCMPGTB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1710] // PCMPGTB Pq,Qq + (const void *)&gInstructions[ 1700] // PCMPGTB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_64_prefix = @@ -9293,13 +9293,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_64_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1665] // PACKSSWB Vx,Wx + (const void *)&gInstructions[ 1655] // PACKSSWB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1664] // PACKSSWB Pq,Qq + (const void *)&gInstructions[ 1654] // PACKSSWB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_63_prefix = @@ -9316,13 +9316,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_63_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1957] // PUNPCKLDQ Vx,Wx + (const void *)&gInstructions[ 1947] // PUNPCKLDQ Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1956] // PUNPCKLDQ Pq,Qd + (const void *)&gInstructions[ 1946] // PUNPCKLDQ Pq,Qd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_62_prefix = @@ -9339,13 +9339,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_62_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1960] // PUNPCKLWD Vx,Wx + (const void *)&gInstructions[ 1950] // PUNPCKLWD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1959] // PUNPCKLWD Pq,Qd + (const void *)&gInstructions[ 1949] // PUNPCKLWD Pq,Qd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_61_prefix = @@ -9362,13 +9362,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_61_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1955] // PUNPCKLBW Vx,Wx + (const void *)&gInstructions[ 1945] // PUNPCKLBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1954] // PUNPCKLBW Pq,Qd + (const void *)&gInstructions[ 1944] // PUNPCKLBW Pq,Qd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_60_prefix = @@ -9385,25 +9385,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_60_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1357] // MAXSD Vsd,Wsd + (const void *)&gInstructions[ 1347] // MAXSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1358] // MAXSS Vss,Wss + (const void *)&gInstructions[ 1348] // MAXSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1355] // MAXPD Vpd,Wpd + (const void *)&gInstructions[ 1345] // MAXPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1356] // MAXPS Vps,Wps + (const void *)&gInstructions[ 1346] // MAXPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5f_prefix = @@ -9420,25 +9420,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 893] // DIVSD Vsd,Wsd + (const void *)&gInstructions[ 885] // DIVSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 894] // DIVSS Vss,Wss + (const void *)&gInstructions[ 886] // DIVSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 891] // DIVPD Vpd,Wpd + (const void *)&gInstructions[ 883] // DIVPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 892] // DIVPS Vps,Wps + (const void *)&gInstructions[ 884] // DIVPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5e_prefix = @@ -9455,25 +9455,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1363] // MINSD Vsd,Wsd + (const void *)&gInstructions[ 1353] // MINSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1364] // MINSS Vss,Wss + (const void *)&gInstructions[ 1354] // MINSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1361] // MINPD Vpd,Wpd + (const void *)&gInstructions[ 1351] // MINPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1362] // MINPS Vps,Wps + (const void *)&gInstructions[ 1352] // MINPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5d_prefix = @@ -9490,25 +9490,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2595] // SUBSD Vsd,Wsd + (const void *)&gInstructions[ 2579] // SUBSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2596] // SUBSS Vss,Wss + (const void *)&gInstructions[ 2580] // SUBSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2593] // SUBPD Vpd,Wpd + (const void *)&gInstructions[ 2577] // SUBPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2594] // SUBPS Vps,Wps + (const void *)&gInstructions[ 2578] // SUBPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5c_prefix = @@ -9525,19 +9525,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 852] // CVTTPS2DQ Vdq,Wps + (const void *)&gInstructions[ 844] // CVTTPS2DQ Vdq,Wps }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 841] // CVTPS2DQ Vdq,Wps + (const void *)&gInstructions[ 833] // CVTPS2DQ Vdq,Wps }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 835] // CVTDQ2PS Vps,Wdq + (const void *)&gInstructions[ 827] // CVTDQ2PS Vps,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5b_prefix = @@ -9554,25 +9554,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 845] // CVTSD2SS Vss,Wsd + (const void *)&gInstructions[ 837] // CVTSD2SS Vss,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 848] // CVTSS2SD Vsd,Wss + (const void *)&gInstructions[ 840] // CVTSS2SD Vsd,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 838] // CVTPD2PS Vps,Wpd + (const void *)&gInstructions[ 830] // CVTPD2PS Vps,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 842] // CVTPS2PD Vpd,Wq + (const void *)&gInstructions[ 834] // CVTPS2PD Vpd,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5a_prefix = @@ -9589,25 +9589,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1491] // MULSD Vsd,Wsd + (const void *)&gInstructions[ 1481] // MULSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1492] // MULSS Vss,Wss + (const void *)&gInstructions[ 1482] // MULSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1489] // MULPD Vpd,Wpd + (const void *)&gInstructions[ 1479] // MULPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1490] // MULPS Vps,Wps + (const void *)&gInstructions[ 1480] // MULPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_59_prefix = @@ -9659,13 +9659,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_58_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4057] // XORPD Vpd,Wpd + (const void *)&gInstructions[ 4139] // XORPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4058] // XORPS Vps,Wps + (const void *)&gInstructions[ 4140] // XORPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_57_prefix = @@ -9682,13 +9682,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_57_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1644] // ORPD Vpd,Wpd + (const void *)&gInstructions[ 1634] // ORPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1645] // ORPS Vps,Wps + (const void *)&gInstructions[ 1635] // ORPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_56_prefix = @@ -9705,13 +9705,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_56_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_55_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 185] // ANDNPD Vpd,Wpd + (const void *)&gInstructions[ 177] // ANDNPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_55_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 186] // ANDNPS Vps,Wps + (const void *)&gInstructions[ 178] // ANDNPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_55_prefix = @@ -9728,13 +9728,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_55_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_54_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 187] // ANDPD Vpd,Wpd + (const void *)&gInstructions[ 179] // ANDPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_54_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 188] // ANDPS Vps,Wps + (const void *)&gInstructions[ 180] // ANDPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_54_prefix = @@ -9751,13 +9751,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_54_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2039] // RCPSS Vss,Wss + (const void *)&gInstructions[ 2029] // RCPSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2038] // RCPPS Vps,Wps + (const void *)&gInstructions[ 2028] // RCPPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_53_prefix = @@ -9774,13 +9774,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_53_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2197] // RSQRTSS Vss,Wss + (const void *)&gInstructions[ 2188] // RSQRTSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2196] // RSQRTPS Vps,Wps + (const void *)&gInstructions[ 2187] // RSQRTPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_52_prefix = @@ -9797,25 +9797,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_52_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2518] // SQRTSD Vsd,Wsd + (const void *)&gInstructions[ 2502] // SQRTSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2519] // SQRTSS Vss,Wss + (const void *)&gInstructions[ 2503] // SQRTSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2516] // SQRTPD Vpd,Wpd + (const void *)&gInstructions[ 2500] // SQRTPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2517] // SQRTPS Vps,Wps + (const void *)&gInstructions[ 2501] // SQRTPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_51_prefix = @@ -9832,7 +9832,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_51_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1438] // MOVMSKPD Gy,Upd + (const void *)&gInstructions[ 1428] // MOVMSKPD Gy,Upd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod = @@ -9847,7 +9847,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1439] // MOVMSKPS Gy,Ups + (const void *)&gInstructions[ 1429] // MOVMSKPS Gy,Ups }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod = @@ -9873,103 +9873,103 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_50_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 598] // CMOVNLE Gv,Ev + (const void *)&gInstructions[ 590] // CMOVNLE Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 586] // CMOVLE Gv,Ev + (const void *)&gInstructions[ 578] // CMOVLE Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 595] // CMOVNL Gv,Ev + (const void *)&gInstructions[ 587] // CMOVNL Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 583] // CMOVL Gv,Ev + (const void *)&gInstructions[ 575] // CMOVL Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 604] // CMOVNP Gv,Ev + (const void *)&gInstructions[ 596] // CMOVNP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 616] // CMOVP Gv,Ev + (const void *)&gInstructions[ 608] // CMOVP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_49_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 607] // CMOVNS Gv,Ev + (const void *)&gInstructions[ 599] // CMOVNS Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_48_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 619] // CMOVS Gv,Ev + (const void *)&gInstructions[ 611] // CMOVS Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_47_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 589] // CMOVNBE Gv,Ev + (const void *)&gInstructions[ 581] // CMOVNBE Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_46_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 577] // CMOVBE Gv,Ev + (const void *)&gInstructions[ 569] // CMOVBE Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_45_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 610] // CMOVNZ Gv,Ev + (const void *)&gInstructions[ 602] // CMOVNZ Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_44_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 622] // CMOVZ Gv,Ev + (const void *)&gInstructions[ 614] // CMOVZ Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_43_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 592] // CMOVNC Gv,Ev + (const void *)&gInstructions[ 584] // CMOVNC Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_42_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 580] // CMOVC Gv,Ev + (const void *)&gInstructions[ 572] // CMOVC Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_41_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 601] // CMOVNO Gv,Ev + (const void *)&gInstructions[ 593] // CMOVNO Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_40_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 613] // CMOVO Gv,Ev + (const void *)&gInstructions[ 605] // CMOVO Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1076] // HRESET Ib + (const void *)&gInstructions[ 1066] // HRESET Ib }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm = @@ -10025,7 +10025,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 127] // AESKEYGENASSIST Vdq,Wdq,Ib + (const void *)&gInstructions[ 119] // AESKEYGENASSIST Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix = @@ -10042,7 +10042,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1070] // GF2P8AFFINEINVQB Vdq,Wdq,Ib + (const void *)&gInstructions[ 1060] // GF2P8AFFINEINVQB Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix = @@ -10059,7 +10059,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1071] // GF2P8AFFINEQB Vdq,Wdq,Ib + (const void *)&gInstructions[ 1061] // GF2P8AFFINEQB Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix = @@ -10076,7 +10076,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2375] // SHA1RNDS4 Vdq,Wdq,Ib + (const void *)&gInstructions[ 2362] // SHA1RNDS4 Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix = @@ -10093,7 +10093,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1717] // PCMPISTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 1707] // PCMPISTRI Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix = @@ -10110,7 +10110,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1718] // PCMPISTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 1708] // PCMPISTRM Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix = @@ -10127,7 +10127,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1708] // PCMPESTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 1698] // PCMPESTRI Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix = @@ -10144,7 +10144,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1709] // PCMPESTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 1699] // PCMPESTRM Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix = @@ -10161,7 +10161,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1700] // PCLMULQDQ Vdq,Wdq,Ib + (const void *)&gInstructions[ 1690] // PCLMULQDQ Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix = @@ -10178,7 +10178,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1480] // MPSADBW Vdq,Wdq,Ib + (const void *)&gInstructions[ 1470] // MPSADBW Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix = @@ -10195,7 +10195,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 895] // DPPD Vdq,Wdq,Ib + (const void *)&gInstructions[ 887] // DPPD Vdq,Wdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix = @@ -10212,7 +10212,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 896] // DPPS Vx,Wx,Ib + (const void *)&gInstructions[ 888] // DPPS Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix = @@ -10229,13 +10229,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1773] // PINSRQ Vdq,Eq,Ib + (const void *)&gInstructions[ 1763] // PINSRQ Vdq,Eq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1772] // PINSRD Vdq,Ed,Ib + (const void *)&gInstructions[ 1762] // PINSRD Vdq,Ed,Ib }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary = @@ -10269,13 +10269,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1155] // INSERTPS Vdq,Udq,Ib + (const void *)&gInstructions[ 1145] // INSERTPS Vdq,Udq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1154] // INSERTPS Vdq,Md,Ib + (const void *)&gInstructions[ 1144] // INSERTPS Vdq,Md,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod = @@ -10301,13 +10301,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1771] // PINSRB Vdq,Ry,Ib + (const void *)&gInstructions[ 1761] // PINSRB Vdq,Ry,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1770] // PINSRB Vdq,Mb,Ib + (const void *)&gInstructions[ 1760] // PINSRB Vdq,Mb,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod = @@ -10333,7 +10333,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 914] // EXTRACTPS Ed,Vdq,Ib + (const void *)&gInstructions[ 904] // EXTRACTPS Ed,Vdq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix = @@ -10350,13 +10350,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1729] // PEXTRQ Ry,Vdq,Ib + (const void *)&gInstructions[ 1719] // PEXTRQ Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1727] // PEXTRD Ry,Vdq,Ib + (const void *)&gInstructions[ 1717] // PEXTRD Ry,Vdq,Ib }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary = @@ -10379,13 +10379,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1728] // PEXTRQ Mq,Vdq,Ib + (const void *)&gInstructions[ 1718] // PEXTRQ Mq,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1726] // PEXTRD Md,Vdq,Ib + (const void *)&gInstructions[ 1716] // PEXTRD Md,Vdq,Ib }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary = @@ -10428,13 +10428,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1733] // PEXTRW Ry,Vdq,Ib + (const void *)&gInstructions[ 1723] // PEXTRW Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1732] // PEXTRW Mw,Vdq,Ib + (const void *)&gInstructions[ 1722] // PEXTRW Mw,Vdq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod = @@ -10460,13 +10460,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1725] // PEXTRB Ry,Vdq,Ib + (const void *)&gInstructions[ 1715] // PEXTRB Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1724] // PEXTRB Mb,Vdq,Ib + (const void *)&gInstructions[ 1714] // PEXTRB Mb,Vdq,Ib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod = @@ -10492,13 +10492,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1686] // PALIGNR Vx,Wx,Ib + (const void *)&gInstructions[ 1676] // PALIGNR Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1685] // PALIGNR Pq,Qq,Ib + (const void *)&gInstructions[ 1675] // PALIGNR Pq,Qq,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix = @@ -10515,7 +10515,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1698] // PBLENDW Vx,Wx,Ib + (const void *)&gInstructions[ 1688] // PBLENDW Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix = @@ -10532,7 +10532,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 203] // BLENDPD Vx,Wx,Ib + (const void *)&gInstructions[ 195] // BLENDPD Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix = @@ -10549,7 +10549,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 204] // BLENDPS Vx,Wx,Ib + (const void *)&gInstructions[ 196] // BLENDPS Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix = @@ -10566,7 +10566,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2193] // ROUNDSD Vsd,Wsd,Ib + (const void *)&gInstructions[ 2184] // ROUNDSD Vsd,Wsd,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix = @@ -10583,7 +10583,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2194] // ROUNDSS Vss,Wss,Ib + (const void *)&gInstructions[ 2185] // ROUNDSS Vss,Wss,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix = @@ -10600,7 +10600,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2191] // ROUNDPD Vx,Wx,Ib + (const void *)&gInstructions[ 2182] // ROUNDPD Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix = @@ -10617,7 +10617,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2192] // ROUNDPS Vx,Wx,Ib + (const void *)&gInstructions[ 2183] // ROUNDPS Vx,Wx,Ib }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix = @@ -10897,7 +10897,7 @@ const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_3a_opcode = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 190] // AOR My,Gy + (const void *)&gInstructions[ 182] // AOR My,Gy }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod = @@ -10912,7 +10912,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 193] // AXOR My,Gy + (const void *)&gInstructions[ 185] // AXOR My,Gy }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod = @@ -10968,7 +10968,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 904] // ENCODEKEY256 Gd,Rd + (const void *)&gInstructions[ 894] // ENCODEKEY256 Gd,Rd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod = @@ -10994,7 +10994,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 902] // ENCODEKEY128 Gd,Rd + (const void *)&gInstructions[ 893] // ENCODEKEY128 Gd,Rd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod = @@ -11020,7 +11020,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1423] // MOVDIRI My,Gy + (const void *)&gInstructions[ 1413] // MOVDIRI My,Gy }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod = @@ -11046,13 +11046,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2651] // URDMSR Rq,Gq + (const void *)&gInstructions[ 2635] // URDMSR Rq,Gq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 908] // ENQCMD rM?,Moq + (const void *)&gInstructions[ 898] // ENQCMD rM?,Moq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod = @@ -11067,13 +11067,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2655] // UWRMSR Gq,Rq + (const void *)&gInstructions[ 2639] // UWRMSR Gq,Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 910] // ENQCMDS rM?,Moq + (const void *)&gInstructions[ 900] // ENQCMDS rM?,Moq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod = @@ -11088,7 +11088,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1421] // MOVDIR64B rMoq,Moq + (const void *)&gInstructions[ 1411] // MOVDIR64B rMoq,Moq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod = @@ -11126,13 +11126,13 @@ const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_01_le const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3981] // WRSSQ My,Gy + (const void *)&gInstructions[ 4063] // WRSSQ My,Gy }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3979] // WRSSD My,Gy + (const void *)&gInstructions[ 4061] // WRSSD My,Gy }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary = @@ -11175,13 +11175,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3985] // WRUSSQ My,Gy + (const void *)&gInstructions[ 4067] // WRUSSQ My,Gy }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3983] // WRUSSD My,Gy + (const void *)&gInstructions[ 4065] // WRUSSD My,Gy }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary = @@ -11224,13 +11224,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 689] // CRC32 Gy,Ev + (const void *)&gInstructions[ 681] // CRC32 Gy,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1414] // MOVBE Mv,Gv + (const void *)&gInstructions[ 1404] // MOVBE Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod = @@ -11245,7 +11245,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1413] // MOVBE Mv,Gv + (const void *)&gInstructions[ 1403] // MOVBE Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod = @@ -11271,13 +11271,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 688] // CRC32 Gy,Eb + (const void *)&gInstructions[ 680] // CRC32 Gy,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1412] // MOVBE Gv,Mv + (const void *)&gInstructions[ 1402] // MOVBE Gv,Mv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod = @@ -11292,7 +11292,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1411] // MOVBE Gv,Mv + (const void *)&gInstructions[ 1401] // MOVBE Gv,Mv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod = @@ -11318,7 +11318,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 110] // AESDEC256KL Vdq,M512 + (const void *)&gInstructions[ 108] // AESDEC256KL Vdq,M512 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod = @@ -11333,7 +11333,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 111] // AESDECLAST Vdq,Wdq + (const void *)&gInstructions[ 109] // AESDECLAST Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix = @@ -11350,7 +11350,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 120] // AESENC256KL Vdq,M512 + (const void *)&gInstructions[ 114] // AESENC256KL Vdq,M512 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod = @@ -11382,7 +11382,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 108] // AESDEC128KL Vdq,M384 + (const void *)&gInstructions[ 107] // AESDEC128KL Vdq,M384 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod = @@ -11397,7 +11397,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 121] // AESENCLAST Vdq,Wdq + (const void *)&gInstructions[ 115] // AESENCLAST Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix = @@ -11414,13 +11414,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1330] // LOADIWKEY Vdq,Udq + (const void *)&gInstructions[ 1320] // LOADIWKEY Vdq,Udq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 118] // AESENC128KL Vdq,M384 + (const void *)&gInstructions[ 113] // AESENC128KL Vdq,M384 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod = @@ -11435,7 +11435,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 116] // AESENC Vdq,Wdq + (const void *)&gInstructions[ 112] // AESENC Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix = @@ -11452,7 +11452,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 126] // AESIMC Vdq,Wdq + (const void *)&gInstructions[ 118] // AESIMC Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix = @@ -11469,7 +11469,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 115] // AESDECWIDE256KL M512 + (const void *)&gInstructions[ 111] // AESDECWIDE256KL M512 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod = @@ -11484,7 +11484,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 125] // AESENCWIDE256KL M512 + (const void *)&gInstructions[ 117] // AESENCWIDE256KL M512 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod = @@ -11499,7 +11499,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 113] // AESDECWIDE128KL M384 + (const void *)&gInstructions[ 110] // AESDECWIDE128KL M384 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod = @@ -11514,7 +11514,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 123] // AESENCWIDE128KL M384 + (const void *)&gInstructions[ 116] // AESENCWIDE128KL M384 }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod = @@ -11555,7 +11555,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1072] // GF2P8MULB Vdq,Wdq + (const void *)&gInstructions[ 1062] // GF2P8MULB Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix = @@ -11572,7 +11572,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2379] // SHA256MSG2 Vdq,Wdq + (const void *)&gInstructions[ 2364] // SHA256MSG2 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix = @@ -11589,7 +11589,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2377] // SHA256MSG1 Vdq,Wdq + (const void *)&gInstructions[ 2363] // SHA256MSG1 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix = @@ -11606,7 +11606,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2381] // SHA256RNDS2 Vdq,Wdq + (const void *)&gInstructions[ 2365] // SHA256RNDS2 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix = @@ -11623,7 +11623,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2371] // SHA1MSG2 Vdq,Wdq + (const void *)&gInstructions[ 2360] // SHA1MSG2 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix = @@ -11640,7 +11640,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2369] // SHA1MSG1 Vdq,Wdq + (const void *)&gInstructions[ 2359] // SHA1MSG1 Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix = @@ -11657,7 +11657,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2373] // SHA1NEXTE Vdq,Wdq + (const void *)&gInstructions[ 2361] // SHA1NEXTE Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix = @@ -11674,7 +11674,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1171] // INVPCID Gy,Mdq + (const void *)&gInstructions[ 1161] // INVPCID Gy,Mdq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod = @@ -11700,7 +11700,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1173] // INVVPID Gy,Mdq + (const void *)&gInstructions[ 1163] // INVVPID Gy,Mdq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod = @@ -11726,7 +11726,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1166] // INVEPT Gy,Mdq + (const void *)&gInstructions[ 1156] // INVEPT Gy,Mdq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod = @@ -11752,7 +11752,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1761] // PHMINPOSUW Vdq,Wdq + (const void *)&gInstructions[ 1751] // PHMINPOSUW Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix = @@ -11769,7 +11769,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1820] // PMULLD Vx,Wx + (const void *)&gInstructions[ 1810] // PMULLD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix = @@ -11786,7 +11786,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1788] // PMAXUD Vx,Wx + (const void *)&gInstructions[ 1778] // PMAXUD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix = @@ -11803,7 +11803,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1789] // PMAXUW Vx,Wx + (const void *)&gInstructions[ 1779] // PMAXUW Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix = @@ -11820,7 +11820,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1783] // PMAXSD Vx,Wx + (const void *)&gInstructions[ 1773] // PMAXSD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix = @@ -11837,7 +11837,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1782] // PMAXSB Vx,Wx + (const void *)&gInstructions[ 1772] // PMAXSB Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix = @@ -11854,7 +11854,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1796] // PMINUD Vx,Wx + (const void *)&gInstructions[ 1786] // PMINUD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix = @@ -11871,7 +11871,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1797] // PMINUW Vx,Wx + (const void *)&gInstructions[ 1787] // PMINUW Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix = @@ -11888,7 +11888,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1791] // PMINSD Vx,Wx + (const void *)&gInstructions[ 1781] // PMINSD Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix = @@ -11905,7 +11905,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1790] // PMINSB Vx,Wx + (const void *)&gInstructions[ 1780] // PMINSB Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix = @@ -11922,7 +11922,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1714] // PCMPGTQ Vx,Wx + (const void *)&gInstructions[ 1704] // PCMPGTQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix = @@ -11939,7 +11939,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1809] // PMOVZXDQ Vdq,Wq + (const void *)&gInstructions[ 1799] // PMOVZXDQ Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix = @@ -11956,7 +11956,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1811] // PMOVZXWQ Vdq,Wd + (const void *)&gInstructions[ 1801] // PMOVZXWQ Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix = @@ -11973,7 +11973,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1810] // PMOVZXWD Vdq,Wq + (const void *)&gInstructions[ 1800] // PMOVZXWD Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix = @@ -11990,7 +11990,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1807] // PMOVZXBQ Vdq,Ww + (const void *)&gInstructions[ 1797] // PMOVZXBQ Vdq,Ww }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix = @@ -12007,7 +12007,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1806] // PMOVZXBD Vdq,Wd + (const void *)&gInstructions[ 1796] // PMOVZXBD Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix = @@ -12024,7 +12024,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1808] // PMOVZXBW Vdq,Wq + (const void *)&gInstructions[ 1798] // PMOVZXBW Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix = @@ -12041,7 +12041,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1666] // PACKUSDW Vx,Wx + (const void *)&gInstructions[ 1656] // PACKUSDW Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix = @@ -12058,7 +12058,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1441] // MOVNTDQA Vx,Mx + (const void *)&gInstructions[ 1431] // MOVNTDQA Vx,Mx }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod = @@ -12084,7 +12084,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1705] // PCMPEQQ Vx,Wx + (const void *)&gInstructions[ 1695] // PCMPEQQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix = @@ -12101,7 +12101,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1812] // PMULDQ Vx,Wx + (const void *)&gInstructions[ 1802] // PMULDQ Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix = @@ -12118,7 +12118,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1803] // PMOVSXDQ Vdq,Wq + (const void *)&gInstructions[ 1793] // PMOVSXDQ Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix = @@ -12135,7 +12135,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1805] // PMOVSXWQ Vdq,Wd + (const void *)&gInstructions[ 1795] // PMOVSXWQ Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix = @@ -12152,7 +12152,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1804] // PMOVSXWD Vdq,Wq + (const void *)&gInstructions[ 1794] // PMOVSXWD Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix = @@ -12169,7 +12169,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1801] // PMOVSXBQ Vdq,Ww + (const void *)&gInstructions[ 1791] // PMOVSXBQ Vdq,Ww }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix = @@ -12186,7 +12186,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1800] // PMOVSXBD Vdq,Wd + (const void *)&gInstructions[ 1790] // PMOVSXBD Vdq,Wd }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix = @@ -12203,7 +12203,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1802] // PMOVSXBW Vdq,Wq + (const void *)&gInstructions[ 1792] // PMOVSXBW Vdq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix = @@ -12220,13 +12220,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1659] // PABSD Vx,Wx + (const void *)&gInstructions[ 1649] // PABSD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1658] // PABSD Pq,Qq + (const void *)&gInstructions[ 1648] // PABSD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix = @@ -12243,13 +12243,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1661] // PABSW Vx,Wx + (const void *)&gInstructions[ 1651] // PABSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1660] // PABSW Pq,Qq + (const void *)&gInstructions[ 1650] // PABSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix = @@ -12266,13 +12266,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1657] // PABSB Vx,Wx + (const void *)&gInstructions[ 1647] // PABSB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1656] // PABSB Pq,Qq + (const void *)&gInstructions[ 1646] // PABSB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix = @@ -12289,7 +12289,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1945] // PTEST Vdq,Wdq + (const void *)&gInstructions[ 1935] // PTEST Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix = @@ -12306,7 +12306,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 205] // BLENDVPD Vdq,Wdq + (const void *)&gInstructions[ 197] // BLENDVPD Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix = @@ -12323,7 +12323,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 206] // BLENDVPS Vdq,Wdq + (const void *)&gInstructions[ 198] // BLENDVPS Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix = @@ -12340,7 +12340,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1697] // PBLENDVB Vdq,Wdq + (const void *)&gInstructions[ 1687] // PBLENDVB Vdq,Wdq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix = @@ -12357,13 +12357,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1814] // PMULHRSW Vx,Wx + (const void *)&gInstructions[ 1804] // PMULHRSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1813] // PMULHRSW Pq,Qq + (const void *)&gInstructions[ 1803] // PMULHRSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix = @@ -12380,13 +12380,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1890] // PSIGND Vx,Wx + (const void *)&gInstructions[ 1880] // PSIGND Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1889] // PSIGND Pq,Qq + (const void *)&gInstructions[ 1879] // PSIGND Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix = @@ -12403,13 +12403,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1892] // PSIGNW Vx,Wx + (const void *)&gInstructions[ 1882] // PSIGNW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1891] // PSIGNW Pq,Qq + (const void *)&gInstructions[ 1881] // PSIGNW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix = @@ -12426,13 +12426,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1888] // PSIGNB Vx,Wx + (const void *)&gInstructions[ 1878] // PSIGNB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1887] // PSIGNB Pq,Qq + (const void *)&gInstructions[ 1877] // PSIGNB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix = @@ -12449,13 +12449,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1765] // PHSUBSW Vx,Wx + (const void *)&gInstructions[ 1755] // PHSUBSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1764] // PHSUBSW Pq,Qq + (const void *)&gInstructions[ 1754] // PHSUBSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix = @@ -12472,13 +12472,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1763] // PHSUBD Vx,Wx + (const void *)&gInstructions[ 1753] // PHSUBD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1762] // PHSUBD Pq,Qq + (const void *)&gInstructions[ 1752] // PHSUBD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix = @@ -12495,13 +12495,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1767] // PHSUBW Vx,Wx + (const void *)&gInstructions[ 1757] // PHSUBW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1766] // PHSUBW Pq,Qq + (const void *)&gInstructions[ 1756] // PHSUBW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix = @@ -12518,13 +12518,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1779] // PMADDUBSW Vx,Wx + (const void *)&gInstructions[ 1769] // PMADDUBSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1778] // PMADDUBSW Pq,Qq + (const void *)&gInstructions[ 1768] // PMADDUBSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix = @@ -12541,13 +12541,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1758] // PHADDSW Vx,Wx + (const void *)&gInstructions[ 1748] // PHADDSW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1757] // PHADDSW Pq,Qq + (const void *)&gInstructions[ 1747] // PHADDSW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix = @@ -12564,13 +12564,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1756] // PHADDD Vx,Wx + (const void *)&gInstructions[ 1746] // PHADDD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1755] // PHADDD Pq,Qq + (const void *)&gInstructions[ 1745] // PHADDD Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix = @@ -12587,13 +12587,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1760] // PHADDW Vx,Wx + (const void *)&gInstructions[ 1750] // PHADDW Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1759] // PHADDW Pq,Qq + (const void *)&gInstructions[ 1749] // PHADDW Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix = @@ -12610,13 +12610,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1882] // PSHUFB Vx,Wx + (const void *)&gInstructions[ 1872] // PSHUFB Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1881] // PSHUFB Pq,Qq + (const void *)&gInstructions[ 1871] // PSHUFB Pq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix = @@ -12896,7 +12896,7 @@ const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_38_opcode = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_37_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1069] // GETSEC + (const void *)&gInstructions[ 1059] // GETSEC }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_37_prefix = @@ -12913,49 +12913,49 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_37_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_35_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2600] // SYSEXIT + (const void *)&gInstructions[ 2584] // SYSEXIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_34_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2599] // SYSENTER + (const void *)&gInstructions[ 2583] // SYSENTER }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_33_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2088] // RDPMC + (const void *)&gInstructions[ 2078] // RDPMC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_32_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2084] // RDMSR + (const void *)&gInstructions[ 2074] // RDMSR }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_31_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2096] // RDTSC + (const void *)&gInstructions[ 2086] // RDTSC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_30_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3974] // WRMSR + (const void *)&gInstructions[ 4056] // WRMSR }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 681] // COMISD Vsd,Wsd + (const void *)&gInstructions[ 673] // COMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 682] // COMISS Vss,Wss + (const void *)&gInstructions[ 674] // COMISS Vss,Wss }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2f_prefix = @@ -12972,13 +12972,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2f_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2637] // UCOMISD Vsd,Wsd + (const void *)&gInstructions[ 2621] // UCOMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2638] // UCOMISS Vss,Wss + (const void *)&gInstructions[ 2622] // UCOMISS Vss,Wss }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2e_prefix = @@ -12995,25 +12995,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2e_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 844] // CVTSD2SI Gy,Wsd + (const void *)&gInstructions[ 836] // CVTSD2SI Gy,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 849] // CVTSS2SI Gy,Wss + (const void *)&gInstructions[ 841] // CVTSS2SI Gy,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 837] // CVTPD2PI Pq,Wpd + (const void *)&gInstructions[ 829] // CVTPD2PI Pq,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 843] // CVTPS2PI Pq,Wq + (const void *)&gInstructions[ 835] // CVTPS2PI Pq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2d_prefix = @@ -13030,25 +13030,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2d_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 854] // CVTTSD2SI Gy,Wsd + (const void *)&gInstructions[ 846] // CVTTSD2SI Gy,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 855] // CVTTSS2SI Gy,Wss + (const void *)&gInstructions[ 847] // CVTTSS2SI Gy,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 851] // CVTTPD2PI Pq,Wpd + (const void *)&gInstructions[ 843] // CVTTPD2PI Pq,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 853] // CVTTPS2PI Pq,Wq + (const void *)&gInstructions[ 845] // CVTTPS2PI Pq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2c_prefix = @@ -13065,7 +13065,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2c_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1446] // MOVNTSD Msd,Vsd + (const void *)&gInstructions[ 1436] // MOVNTSD Msd,Vsd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod = @@ -13080,7 +13080,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1447] // MOVNTSS Mss,Vss + (const void *)&gInstructions[ 1437] // MOVNTSS Mss,Vss }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod = @@ -13095,7 +13095,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1443] // MOVNTPD Mpd,Vpd + (const void *)&gInstructions[ 1433] // MOVNTPD Mpd,Vpd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod = @@ -13110,7 +13110,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1444] // MOVNTPS Mps,Vps + (const void *)&gInstructions[ 1434] // MOVNTPS Mps,Vps }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod = @@ -13136,25 +13136,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2b_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 846] // CVTSI2SD Vsd,Ey + (const void *)&gInstructions[ 838] // CVTSI2SD Vsd,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 847] // CVTSI2SS Vss,Ey + (const void *)&gInstructions[ 839] // CVTSI2SS Vss,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 839] // CVTPI2PD Vpd,Qq + (const void *)&gInstructions[ 831] // CVTPI2PD Vpd,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 840] // CVTPI2PS Vq,Qq + (const void *)&gInstructions[ 832] // CVTPI2PS Vq,Qq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2a_prefix = @@ -13171,13 +13171,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2a_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_29_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1404] // MOVAPD Wpd,Vpd + (const void *)&gInstructions[ 1394] // MOVAPD Wpd,Vpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_29_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1406] // MOVAPS Wps,Vps + (const void *)&gInstructions[ 1396] // MOVAPS Wps,Vps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_29_prefix = @@ -13194,13 +13194,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_29_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_28_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1403] // MOVAPD Vpd,Wpd + (const void *)&gInstructions[ 1393] // MOVAPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_28_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1405] // MOVAPS Vps,Wps + (const void *)&gInstructions[ 1395] // MOVAPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_28_prefix = @@ -13217,79 +13217,79 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_28_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_26_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1402] // MOV Ty,Ry + (const void *)&gInstructions[ 1392] // MOV Ty,Ry }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_24_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1401] // MOV Ry,Ty + (const void *)&gInstructions[ 1391] // MOV Ry,Ty }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_23_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1400] // MOV Dy,Ry + (const void *)&gInstructions[ 1390] // MOV Dy,Ry }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_22_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1399] // MOV Cy,Ry + (const void *)&gInstructions[ 1389] // MOV Cy,Ry }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_21_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1398] // MOV Ry,Dy + (const void *)&gInstructions[ 1388] // MOV Ry,Dy }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_20_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1397] // MOV Ry,Cy + (const void *)&gInstructions[ 1387] // MOV Ry,Cy }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1544] // NOP Ev,Gv + (const void *)&gInstructions[ 1534] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1581] // NOP Rv,Gv + (const void *)&gInstructions[ 1571] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1580] // NOP Rv,Gv + (const void *)&gInstructions[ 1570] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1579] // NOP Rv,Gv + (const void *)&gInstructions[ 1569] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1578] // NOP Rv,Gv + (const void *)&gInstructions[ 1568] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 905] // ENDBR32 + (const void *)&gInstructions[ 895] // ENDBR32 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1577] // NOP Rv,Gv + (const void *)&gInstructions[ 1567] // NOP Rv,Gv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary = @@ -13312,13 +13312,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 906] // ENDBR64 + (const void *)&gInstructions[ 896] // ENDBR64 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1576] // NOP Rv,Gv + (const void *)&gInstructions[ 1566] // NOP Rv,Gv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary = @@ -13341,13 +13341,13 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1575] // NOP Rv,Gv + (const void *)&gInstructions[ 1565] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1574] // NOP Rv,Gv + (const void *)&gInstructions[ 1564] // NOP Rv,Gv }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm = @@ -13368,7 +13368,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1573] // NOP Mv,Gv + (const void *)&gInstructions[ 1563] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod = @@ -13383,13 +13383,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1572] // NOP Rv,Gv + (const void *)&gInstructions[ 1562] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1571] // NOP Mv,Gv + (const void *)&gInstructions[ 1561] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod = @@ -13404,13 +13404,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1570] // NOP Rv,Gv + (const void *)&gInstructions[ 1560] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1569] // NOP Mv,Gv + (const void *)&gInstructions[ 1559] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod = @@ -13425,13 +13425,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1568] // NOP Rv,Gv + (const void *)&gInstructions[ 1558] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1567] // NOP Mv,Gv + (const void *)&gInstructions[ 1557] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod = @@ -13446,13 +13446,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1566] // NOP Rv,Gv + (const void *)&gInstructions[ 1556] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1565] // NOP Mv,Gv + (const void *)&gInstructions[ 1555] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod = @@ -13467,13 +13467,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1564] // NOP Rv,Gv + (const void *)&gInstructions[ 1554] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1563] // NOP Mv,Gv + (const void *)&gInstructions[ 1553] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod = @@ -13488,13 +13488,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2095] // RDSSPQ Rq + (const void *)&gInstructions[ 2085] // RDSSPQ Rq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2094] // RDSSPD Rd + (const void *)&gInstructions[ 2084] // RDSSPD Rd }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary = @@ -13517,7 +13517,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1562] // NOP Rv,Gv + (const void *)&gInstructions[ 1552] // NOP Rv,Gv }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary = @@ -13540,7 +13540,7 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1561] // NOP Mv,Gv + (const void *)&gInstructions[ 1551] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod = @@ -13555,13 +13555,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1560] // NOP Rv,Gv + (const void *)&gInstructions[ 1550] // NOP Rv,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1559] // NOP Mv,Gv + (const void *)&gInstructions[ 1549] // NOP Mv,Gv }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod = @@ -13591,7 +13591,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1543] // NOP Ev,Gv + (const void *)&gInstructions[ 1533] // NOP Ev,Gv }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1e_feature = @@ -13612,79 +13612,79 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1e_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1542] // NOP Ev,Gv + (const void *)&gInstructions[ 1532] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1558] // NOP Ev,Gv + (const void *)&gInstructions[ 1548] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1557] // NOP Ev,Gv + (const void *)&gInstructions[ 1547] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1556] // NOP Ev,Gv + (const void *)&gInstructions[ 1546] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1555] // NOP Ev,Gv + (const void *)&gInstructions[ 1545] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1554] // NOP Ev,Gv + (const void *)&gInstructions[ 1544] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1553] // NOP Ev,Gv + (const void *)&gInstructions[ 1543] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1552] // NOP Ev,Gv + (const void *)&gInstructions[ 1542] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1551] // NOP Ev,Gv + (const void *)&gInstructions[ 1541] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1550] // NOP Ev,Gv + (const void *)&gInstructions[ 1540] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1549] // NOP Ev,Gv + (const void *)&gInstructions[ 1539] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1548] // NOP Ev,Gv + (const void *)&gInstructions[ 1538] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 562] // CLDEMOTE Mb + (const void *)&gInstructions[ 554] // CLDEMOTE Mb }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix = @@ -13725,7 +13725,7 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1541] // NOP Ev,Gv + (const void *)&gInstructions[ 1531] // NOP Ev,Gv }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1c_feature = @@ -13746,19 +13746,19 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1c_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 219] // BNDCN rBl,Ey + (const void *)&gInstructions[ 211] // BNDCN rBl,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1547] // NOP Gv,Ev + (const void *)&gInstructions[ 1537] // NOP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 222] // BNDMK rBl,My + (const void *)&gInstructions[ 214] // BNDMK rBl,My }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod = @@ -13773,19 +13773,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_mod const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 224] // BNDMOV mBl,rBl + (const void *)&gInstructions[ 216] // BNDMOV mBl,rBl }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1546] // NOP Gv,Ev + (const void *)&gInstructions[ 1536] // NOP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 225] // BNDSTX Mmib,rBl + (const void *)&gInstructions[ 217] // BNDSTX Mmib,rBl }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod = @@ -13811,7 +13811,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1540] // NOP Gv,Ev + (const void *)&gInstructions[ 1530] // NOP Gv,Ev }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1b_feature = @@ -13832,31 +13832,31 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1b_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 220] // BNDCU rBl,Ey + (const void *)&gInstructions[ 212] // BNDCU rBl,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 218] // BNDCL rBl,Ey + (const void *)&gInstructions[ 210] // BNDCL rBl,Ey }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 223] // BNDMOV rBl,mBl + (const void *)&gInstructions[ 215] // BNDMOV rBl,mBl }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1545] // NOP Gv,Ev + (const void *)&gInstructions[ 1535] // NOP Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 221] // BNDLDX rBl,Mmib + (const void *)&gInstructions[ 213] // BNDLDX rBl,Mmib }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod = @@ -13882,7 +13882,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1539] // NOP Ev,Gv + (const void *)&gInstructions[ 1529] // NOP Ev,Gv }; const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1a_feature = @@ -13903,25 +13903,25 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1a_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_19_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1528] // NOP Ev + (const void *)&gInstructions[ 1518] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1538] // NOP Ev + (const void *)&gInstructions[ 1528] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1866] // PREFETCHIT0 Mb + (const void *)&gInstructions[ 1856] // PREFETCHIT0 Mb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1537] // NOP Ev + (const void *)&gInstructions[ 1527] // NOP Ev }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary = @@ -13953,19 +13953,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1536] // NOP Ev + (const void *)&gInstructions[ 1526] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1867] // PREFETCHIT1 Mb + (const void *)&gInstructions[ 1857] // PREFETCHIT1 Mb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1535] // NOP Ev + (const void *)&gInstructions[ 1525] // NOP Ev }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary = @@ -13997,25 +13997,25 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1534] // NOP Ev + (const void *)&gInstructions[ 1524] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1533] // NOP Ev + (const void *)&gInstructions[ 1523] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1532] // NOP Ev + (const void *)&gInstructions[ 1522] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1876] // PREFETCHT2 Mb + (const void *)&gInstructions[ 1866] // PREFETCHT2 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod = @@ -14030,13 +14030,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1531] // NOP Ev + (const void *)&gInstructions[ 1521] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1874] // PREFETCHT1 Mb + (const void *)&gInstructions[ 1864] // PREFETCHT1 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod = @@ -14051,13 +14051,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1530] // NOP Ev + (const void *)&gInstructions[ 1520] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1872] // PREFETCHT0 Mb + (const void *)&gInstructions[ 1862] // PREFETCHT0 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod = @@ -14072,13 +14072,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1529] // NOP Ev + (const void *)&gInstructions[ 1519] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1870] // PREFETCHNTA Mb + (const void *)&gInstructions[ 1860] // PREFETCHNTA Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod = @@ -14108,37 +14108,37 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1527] // NOP Ev + (const void *)&gInstructions[ 1517] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1526] // NOP Ev + (const void *)&gInstructions[ 1516] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1525] // NOP Ev + (const void *)&gInstructions[ 1515] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1524] // NOP Ev + (const void *)&gInstructions[ 1514] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1523] // NOP Ev + (const void *)&gInstructions[ 1513] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1875] // PREFETCHT2 Mb + (const void *)&gInstructions[ 1865] // PREFETCHT2 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod = @@ -14153,13 +14153,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1522] // NOP Ev + (const void *)&gInstructions[ 1512] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1873] // PREFETCHT1 Mb + (const void *)&gInstructions[ 1863] // PREFETCHT1 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod = @@ -14174,13 +14174,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1521] // NOP Ev + (const void *)&gInstructions[ 1511] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1871] // PREFETCHT0 Mb + (const void *)&gInstructions[ 1861] // PREFETCHT0 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod = @@ -14195,13 +14195,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1520] // NOP Ev + (const void *)&gInstructions[ 1510] // NOP Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1869] // PREFETCHNTA Mb + (const void *)&gInstructions[ 1859] // PREFETCHNTA Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod = @@ -14246,7 +14246,7 @@ const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_18_feature = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1431] // MOVHPD Mq,Vq + (const void *)&gInstructions[ 1421] // MOVHPD Mq,Vq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod = @@ -14261,7 +14261,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1433] // MOVHPS Mq,Vq + (const void *)&gInstructions[ 1423] // MOVHPS Mq,Vq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod = @@ -14287,13 +14287,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_17_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1463] // MOVSHDUP Vx,Wx + (const void *)&gInstructions[ 1453] // MOVSHDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1430] // MOVHPD Vq,Mq + (const void *)&gInstructions[ 1420] // MOVHPD Vq,Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod = @@ -14308,13 +14308,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1434] // MOVLHPS Vq,Uq + (const void *)&gInstructions[ 1424] // MOVLHPS Vq,Uq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1432] // MOVHPS Vq,Mq + (const void *)&gInstructions[ 1422] // MOVHPS Vq,Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod = @@ -14340,13 +14340,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_16_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2645] // UNPCKHPD Vx,Wx + (const void *)&gInstructions[ 2629] // UNPCKHPD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2646] // UNPCKHPS Vx,Wx + (const void *)&gInstructions[ 2630] // UNPCKHPS Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_15_prefix = @@ -14363,13 +14363,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_15_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2647] // UNPCKLPD Vx,Wx + (const void *)&gInstructions[ 2631] // UNPCKLPD Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2648] // UNPCKLPS Vx,Wx + (const void *)&gInstructions[ 2632] // UNPCKLPS Vx,Wx }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_14_prefix = @@ -14386,7 +14386,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_14_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1436] // MOVLPD Mq,Vpd + (const void *)&gInstructions[ 1426] // MOVLPD Mq,Vpd }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod = @@ -14401,7 +14401,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1437] // MOVLPS Mq,Vps + (const void *)&gInstructions[ 1427] // MOVLPS Mq,Vps }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod = @@ -14427,19 +14427,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_13_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1419] // MOVDDUP Vdq,Wq + (const void *)&gInstructions[ 1409] // MOVDDUP Vdq,Wq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1464] // MOVSLDUP Vx,Wx + (const void *)&gInstructions[ 1454] // MOVSLDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1435] // MOVLPD Vsd,Mq + (const void *)&gInstructions[ 1425] // MOVLPD Vsd,Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod = @@ -14454,7 +14454,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1429] // MOVHLPS Vq,Wq + (const void *)&gInstructions[ 1419] // MOVHLPS Vq,Wq }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_12_prefix = @@ -14471,25 +14471,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_12_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1462] // MOVSD Wsd,Vsd + (const void *)&gInstructions[ 1452] // MOVSD Wsd,Vsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1468] // MOVSS Wss,Vss + (const void *)&gInstructions[ 1458] // MOVSS Wss,Vss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1475] // MOVUPD Wpd,Vpd + (const void *)&gInstructions[ 1465] // MOVUPD Wpd,Vpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1477] // MOVUPS Wps,Vps + (const void *)&gInstructions[ 1467] // MOVUPS Wps,Vps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_11_prefix = @@ -14506,25 +14506,25 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_11_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1461] // MOVSD Vsd,Wsd + (const void *)&gInstructions[ 1451] // MOVSD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1467] // MOVSS Vss,Wss + (const void *)&gInstructions[ 1457] // MOVSS Vss,Wss }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1474] // MOVUPD Vpd,Wpd + (const void *)&gInstructions[ 1464] // MOVUPD Vpd,Wpd }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1476] // MOVUPS Vps,Wps + (const void *)&gInstructions[ 1466] // MOVUPS Vps,Wps }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_10_prefix = @@ -14541,157 +14541,157 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_10_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1694] // PAVGUSB Pq,Qq + (const void *)&gInstructions[ 1684] // PAVGUSB Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1944] // PSWAPD Pq,Qq + (const void *)&gInstructions[ 1934] // PSWAPD Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1815] // PMULHRW Pq,Qq + (const void *)&gInstructions[ 1805] // PMULHRW Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1748] // PFRCPIT2 Pq,Qq + (const void *)&gInstructions[ 1738] // PFRCPIT2 Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1743] // PFMUL Pq,Qq + (const void *)&gInstructions[ 1733] // PFMUL Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1738] // PFCMPEQ Pq,Qq + (const void *)&gInstructions[ 1728] // PFCMPEQ Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_ae_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1736] // PFACC Pq,Qq + (const void *)&gInstructions[ 1726] // PFACC Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_aa_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1754] // PFSUBR Pq,Qq + (const void *)&gInstructions[ 1744] // PFSUBR Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1750] // PFRSQIT1 Pq,Qq + (const void *)&gInstructions[ 1740] // PFRSQIT1 Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1747] // PFRCPIT1 Pq,Qq + (const void *)&gInstructions[ 1737] // PFRCPIT1 Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a4_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1741] // PFMAX Pq,Qq + (const void *)&gInstructions[ 1731] // PFMAX Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1740] // PFCMPGT Pq,Qq + (const void *)&gInstructions[ 1730] // PFCMPGT Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1737] // PFADD Pq,Qq + (const void *)&gInstructions[ 1727] // PFADD Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1753] // PFSUB Pq,Qq + (const void *)&gInstructions[ 1743] // PFSUB Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1751] // PFRSQRT Pq,Qq + (const void *)&gInstructions[ 1741] // PFRSQRT Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1746] // PFRCP Pq,Qq + (const void *)&gInstructions[ 1736] // PFRCP Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_94_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1742] // PFMIN Pq,Qq + (const void *)&gInstructions[ 1732] // PFMIN Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_90_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1739] // PFCMPGE Pq,Qq + (const void *)&gInstructions[ 1729] // PFCMPGE Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1745] // PFPNACC Pq,Qq + (const void *)&gInstructions[ 1735] // PFPNACC Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1744] // PFNACC Pq,Qq + (const void *)&gInstructions[ 1734] // PFNACC Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1752] // PFRSQRTV Pq,Qq + (const void *)&gInstructions[ 1742] // PFRSQRTV Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1749] // PFRCPV Pq,Qq + (const void *)&gInstructions[ 1739] // PFRCPV Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1734] // PF2ID Pq,Qq + (const void *)&gInstructions[ 1724] // PF2ID Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1735] // PF2IW Pq,Qq + (const void *)&gInstructions[ 1725] // PF2IW Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1768] // PI2FD Pq,Qq + (const void *)&gInstructions[ 1758] // PI2FD Pq,Qq }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1769] // PI2FW Pq,Qq + (const void *)&gInstructions[ 1759] // PI2FW Pq,Qq }; const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_0f_opcode_last = @@ -14960,19 +14960,19 @@ const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_0f_opcode_last = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 959] // FEMMS + (const void *)&gInstructions[ 949] // FEMMS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1519] // NOP Ev,Gv + (const void *)&gInstructions[ 1509] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1864] // PREFETCH Mb + (const void *)&gInstructions[ 1854] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod = @@ -14987,13 +14987,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1518] // NOP Ev,Gv + (const void *)&gInstructions[ 1508] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1863] // PREFETCH Mb + (const void *)&gInstructions[ 1853] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod = @@ -15008,13 +15008,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1517] // NOP Ev,Gv + (const void *)&gInstructions[ 1507] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1862] // PREFETCH Mb + (const void *)&gInstructions[ 1852] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod = @@ -15029,13 +15029,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1516] // NOP Ev,Gv + (const void *)&gInstructions[ 1506] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1861] // PREFETCH Mb + (const void *)&gInstructions[ 1851] // PREFETCH Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod = @@ -15050,13 +15050,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1515] // NOP Ev,Gv + (const void *)&gInstructions[ 1505] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1868] // PREFETCHM Mb + (const void *)&gInstructions[ 1858] // PREFETCHM Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod = @@ -15071,13 +15071,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1514] // NOP Ev,Gv + (const void *)&gInstructions[ 1504] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1878] // PREFETCHWT1 Mb + (const void *)&gInstructions[ 1868] // PREFETCHWT1 Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod = @@ -15092,13 +15092,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1513] // NOP Ev,Gv + (const void *)&gInstructions[ 1503] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1877] // PREFETCHW Mb + (const void *)&gInstructions[ 1867] // PREFETCHW Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod = @@ -15113,13 +15113,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1512] // NOP Ev,Gv + (const void *)&gInstructions[ 1502] // NOP Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1865] // PREFETCHE Mb + (const void *)&gInstructions[ 1855] // PREFETCHE Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod = @@ -15149,19 +15149,19 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_0d_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2641] // UD2 + (const void *)&gInstructions[ 2625] // UD2 }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3971] // WBNOINVD + (const void *)&gInstructions[ 4053] // WBNOINVD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3970] // WBINVD + (const void *)&gInstructions[ 4052] // WBINVD }; const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_09_auxiliary = @@ -15184,37 +15184,37 @@ const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_09_auxiliary = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1164] // INVD + (const void *)&gInstructions[ 1154] // INVD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2601] // SYSRET + (const void *)&gInstructions[ 2585] // SYSRET }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 570] // CLTS + (const void *)&gInstructions[ 562] // CLTS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2598] // SYSCALL + (const void *)&gInstructions[ 2582] // SYSCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1343] // LSL Gv,Rz + (const void *)&gInstructions[ 1333] // LSL Gv,Rz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1342] // LSL Gv,Mw + (const void *)&gInstructions[ 1332] // LSL Gv,Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_03_modrmmod = @@ -15229,13 +15229,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1311] // LAR Gv,Rz + (const void *)&gInstructions[ 1301] // LAR Gv,Rz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1310] // LAR Gv,Mw + (const void *)&gInstructions[ 1300] // LAR Gv,Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_02_modrmmod = @@ -15250,19 +15250,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1993] // PVALIDATE + (const void *)&gInstructions[ 1983] // PVALIDATE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1906] // PSMASH + (const void *)&gInstructions[ 1896] // PSMASH }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2629] // TLBSYNC + (const void *)&gInstructions[ 2613] // TLBSYNC }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix = @@ -15279,19 +15279,19 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2104] // RMPUPDATE + (const void *)&gInstructions[ 2095] // RMPUPDATE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2102] // RMPADJUST + (const void *)&gInstructions[ 2092] // RMPADJUST }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1169] // INVLPGB + (const void *)&gInstructions[ 1159] // INVLPGB }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix = @@ -15305,16 +15305,22 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo } }; +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2094] // RMPREAD +}; + const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2103] // RMPQUERY + (const void *)&gInstructions[ 2093] // RMPQUERY }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2089] // RDPRU + (const void *)&gInstructions[ 2079] // RDPRU }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix = @@ -15324,20 +15330,20 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf, /* 01 */ (const void *)ND_NULL, /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf, - /* 03 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_03_leaf, } }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 573] // CLZERO + (const void *)&gInstructions[ 565] // CLZERO }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1496] // MWAITX + (const void *)&gInstructions[ 1486] // MWAITX }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix = @@ -15354,13 +15360,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1359] // MCOMMIT + (const void *)&gInstructions[ 1349] // MCOMMIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1366] // MONITORX + (const void *)&gInstructions[ 1356] // MONITORX }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix = @@ -15377,13 +15383,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2097] // RDTSCP + (const void *)&gInstructions[ 2087] // RDTSCP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2597] // SWAPGS + (const void *)&gInstructions[ 2581] // SWAPGS }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm = @@ -15404,7 +15410,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1167] // INVLPG Mb + (const void *)&gInstructions[ 1157] // INVLPG Mb }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod = @@ -15419,19 +15425,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1329] // LMSW Ew + (const void *)&gInstructions[ 1319] // LMSW Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4059] // XRESLDTRK + (const void *)&gInstructions[ 4141] // XRESLDTRK }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4073] // XSUSLDTRK + (const void *)&gInstructions[ 4155] // XSUSLDTRK }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm = @@ -15461,37 +15467,37 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2538] // STUI + (const void *)&gInstructions[ 2522] // STUI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 571] // CLUI + (const void *)&gInstructions[ 563] // CLUI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2620] // TESTUI + (const void *)&gInstructions[ 2604] // TESTUI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2642] // UIRET + (const void *)&gInstructions[ 2626] // UIRET }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2287] // SAVEPREVSSP + (const void *)&gInstructions[ 2278] // SAVEPREVSSP }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2363] // SETSSBSY + (const void *)&gInstructions[ 2354] // SETSSBSY }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm = @@ -15512,7 +15518,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_mod const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2198] // RSTORSSP Mq + (const void *)&gInstructions[ 2189] // RSTORSSP Mq }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod = @@ -15527,19 +15533,19 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3977] // WRPKRU + (const void *)&gInstructions[ 4059] // WRPKRU }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2087] // RDPKRU + (const void *)&gInstructions[ 2077] // RDPKRU }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2332] // SERIALIZE + (const void *)&gInstructions[ 2323] // SERIALIZE }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm = @@ -15580,13 +15586,13 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2514] // SMSW Rv + (const void *)&gInstructions[ 2498] // SMSW Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2513] // SMSW Mw + (const void *)&gInstructions[ 2497] // SMSW Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod = @@ -15601,61 +15607,61 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1168] // INVLPGA + (const void *)&gInstructions[ 1158] // INVLPGA }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2509] // SKINIT + (const void *)&gInstructions[ 2493] // SKINIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 567] // CLGI + (const void *)&gInstructions[ 559] // CLGI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2523] // STGI + (const void *)&gInstructions[ 2507] // STGI }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3287] // VMSAVE + (const void *)&gInstructions[ 3346] // VMSAVE }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3171] // VMLOAD + (const void *)&gInstructions[ 3225] // VMLOAD }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3159] // VMGEXIT + (const void *)&gInstructions[ 3205] // VMGEXIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3158] // VMGEXIT + (const void *)&gInstructions[ 3204] // VMGEXIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3173] // VMMCALL + (const void *)&gInstructions[ 3227] // VMMCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3172] // VMMCALL + (const void *)&gInstructions[ 3226] // VMMCALL }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix = @@ -15672,7 +15678,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3286] // VMRUN + (const void *)&gInstructions[ 3345] // VMRUN }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm = @@ -15693,7 +15699,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_m const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1324] // LIDT Ms + (const void *)&gInstructions[ 1314] // LIDT Ms }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod = @@ -15708,37 +15714,37 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 899] // ENCLU + (const void *)&gInstructions[ 891] // ENCLU }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4074] // XTEST + (const void *)&gInstructions[ 4156] // XTEST }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4000] // XEND + (const void *)&gInstructions[ 4082] // XEND }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3157] // VMFUNC + (const void *)&gInstructions[ 3203] // VMFUNC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4072] // XSETBV + (const void *)&gInstructions[ 4154] // XSETBV }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 4001] // XGETBV + (const void *)&gInstructions[ 4083] // XGETBV }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm = @@ -15770,7 +15776,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_pr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1322] // LGDT Ms + (const void *)&gInstructions[ 1312] // LGDT Ms }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod = @@ -15785,7 +15791,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 912] // ERETS + (const void *)&gInstructions[ 902] // ERETS }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm = @@ -15806,7 +15812,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 913] // ERETU + (const void *)&gInstructions[ 903] // ERETU }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm = @@ -15827,25 +15833,25 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2328] // SEAMCALL + (const void *)&gInstructions[ 2319] // SEAMCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2329] // SEAMOPS + (const void *)&gInstructions[ 2320] // SEAMOPS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2330] // SEAMRET + (const void *)&gInstructions[ 2321] // SEAMRET }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2605] // TDCALL + (const void *)&gInstructions[ 2589] // TDCALL }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm = @@ -15866,31 +15872,31 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 898] // ENCLS + (const void *)&gInstructions[ 890] // ENCLS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2520] // STAC + (const void *)&gInstructions[ 2504] // STAC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 559] // CLAC + (const void *)&gInstructions[ 551] // CLAC }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1495] // MWAIT + (const void *)&gInstructions[ 1485] // MWAIT }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1365] // MONITOR + (const void *)&gInstructions[ 1355] // MONITOR }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm = @@ -15922,7 +15928,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_pr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2508] // SIDT Ms + (const void *)&gInstructions[ 2492] // SIDT Ms }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod = @@ -15937,7 +15943,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2085] // RDMSRLIST + (const void *)&gInstructions[ 2075] // RDMSRLIST }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm = @@ -15958,7 +15964,7 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3975] // WRMSRLIST + (const void *)&gInstructions[ 4057] // WRMSRLIST }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm = @@ -15979,49 +15985,49 @@ const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_p const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1699] // PBNDKB + (const void *)&gInstructions[ 1689] // PBNDKB }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3976] // WRMSRNS + (const void *)&gInstructions[ 4058] // WRMSRNS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1719] // PCONFIG + (const void *)&gInstructions[ 1709] // PCONFIG }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3299] // VMXOFF + (const void *)&gInstructions[ 3359] // VMXOFF }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3285] // VMRESUME + (const void *)&gInstructions[ 3344] // VMRESUME }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3170] // VMLAUNCH + (const void *)&gInstructions[ 3224] // VMLAUNCH }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3155] // VMCALL + (const void *)&gInstructions[ 3201] // VMCALL }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 900] // ENCLV + (const void *)&gInstructions[ 892] // ENCLV }; const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm = @@ -16053,7 +16059,7 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_pr const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2367] // SGDT Ms + (const void *)&gInstructions[ 2358] // SGDT Ms }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod = @@ -16083,13 +16089,13 @@ const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_01_modrmreg = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1326] // LKGS Rv + (const void *)&gInstructions[ 1316] // LKGS Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1325] // LKGS Mw + (const void *)&gInstructions[ 1315] // LKGS Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod = @@ -16104,7 +16110,7 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_mo const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1191] // JMPE Ev + (const void *)&gInstructions[ 1181] // JMPE Ev }; const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix = @@ -16121,37 +16127,37 @@ const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2855] // VERW Ew + (const void *)&gInstructions[ 2885] // VERW Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2854] // VERR Ew + (const void *)&gInstructions[ 2884] // VERR Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1345] // LTR Ew + (const void *)&gInstructions[ 1335] // LTR Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1327] // LLDT Ew + (const void *)&gInstructions[ 1317] // LLDT Ew }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2535] // STR Rv + (const void *)&gInstructions[ 2519] // STR Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2534] // STR Mw + (const void *)&gInstructions[ 2518] // STR Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod = @@ -16166,13 +16172,13 @@ const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2511] // SLDT Rv + (const void *)&gInstructions[ 2495] // SLDT Rv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2510] // SLDT Mw + (const void *)&gInstructions[ 2494] // SLDT Mw }; const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod = @@ -16465,55 +16471,55 @@ const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode = const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1962] // PUSH CS + (const void *)&gInstructions[ 1952] // PUSH CS }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0d_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1639] // OR rAX,Iz + (const void *)&gInstructions[ 1629] // OR rAX,Iz }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0c_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1638] // OR AL,Ib + (const void *)&gInstructions[ 1628] // OR AL,Ib }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0b_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1637] // OR Gv,Ev + (const void *)&gInstructions[ 1627] // OR Gv,Ev }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0a_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1636] // OR Gb,Eb + (const void *)&gInstructions[ 1626] // OR Gb,Eb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_09_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1635] // OR Ev,Gv + (const void *)&gInstructions[ 1625] // OR Ev,Gv }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_08_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1634] // OR Eb,Gb + (const void *)&gInstructions[ 1624] // OR Eb,Gb }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1825] // POP ES + (const void *)&gInstructions[ 1815] // POP ES }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1961] // PUSH ES + (const void *)&gInstructions[ 1951] // PUSH ES }; const ND_TABLE_INSTRUCTION gLegacyMap_opcode_05_leaf = diff --git a/bddisasm/include/bdx86_table_vex.h b/bddisasm/include/bdx86_table_vex.h index 6a0261c..bd13233 100644 --- a/bddisasm/include/bdx86_table_vex.h +++ b/bddisasm/include/bdx86_table_vex.h @@ -13,7 +13,7 @@ const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2652] // URDMSR Rq,Id + (const void *)&gInstructions[ 2636] // URDMSR Rq,Id }; const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w = @@ -63,7 +63,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2656] // UWRMSR Id,Rq + (const void *)&gInstructions[ 2640] // UWRMSR Id,Rq }; const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w = @@ -387,7 +387,7 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_07_opcode = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2190] // RORX Gy,Ey,Ib + (const void *)&gInstructions[ 2181] // RORX Gy,Ey,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_f0_pp_03_l = @@ -415,7 +415,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_f0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2682] // VAESKEYGENASSIST Vdq,Wdq,Ib + (const void *)&gInstructions[ 2667] // VAESKEYGENASSIST Vdq,Wdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_df_pp_01_l = @@ -443,7 +443,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_df_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3924] // VSM3RNDS2 Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 4001] // VSM3RNDS2 Vdq,Hdq,Wdq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w = @@ -480,7 +480,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_de_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3115] // VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3160] // VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_cf_pp_01_w = @@ -506,7 +506,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_cf_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3117] // VGF2P8AFFINEQB Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3162] // VGF2P8AFFINEQB Vx,Hx,Wx,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_ce_pp_01_w = @@ -532,13 +532,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_ce_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3073] // VFNMSUBSD Vdq,Hdq,Ldq,Wsd + (const void *)&gInstructions[ 3115] // VFNMSUBSD Vdq,Hdq,Ldq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3072] // VFNMSUBSD Vdq,Hdq,Wsd,Ldq + (const void *)&gInstructions[ 3114] // VFNMSUBSD Vdq,Hdq,Wsd,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7f_pp_01_w = @@ -564,13 +564,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3075] // VFNMSUBSS Vdq,Hdq,Ldq,Wss + (const void *)&gInstructions[ 3117] // VFNMSUBSS Vdq,Hdq,Ldq,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3074] // VFNMSUBSS Vdq,Hdq,Wss,Ldq + (const void *)&gInstructions[ 3116] // VFNMSUBSS Vdq,Hdq,Wss,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7e_pp_01_w = @@ -596,13 +596,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3069] // VFNMSUBPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3111] // VFNMSUBPD Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3068] // VFNMSUBPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3110] // VFNMSUBPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7d_pp_01_w = @@ -628,13 +628,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3071] // VFNMSUBPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3113] // VFNMSUBPS Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3070] // VFNMSUBPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3112] // VFNMSUBPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7c_pp_01_w = @@ -660,13 +660,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3035] // VFNMADDSD Vdq,Hdq,Ldq,Wsd + (const void *)&gInstructions[ 3074] // VFNMADDSD Vdq,Hdq,Ldq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3034] // VFNMADDSD Vdq,Hdq,Wsd,Ldq + (const void *)&gInstructions[ 3073] // VFNMADDSD Vdq,Hdq,Wsd,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7b_pp_01_w = @@ -692,13 +692,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3037] // VFNMADDSS Vdq,Hdq,Ldq,Wss + (const void *)&gInstructions[ 3076] // VFNMADDSS Vdq,Hdq,Ldq,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3036] // VFNMADDSS Vdq,Hdq,Wss,Ldq + (const void *)&gInstructions[ 3075] // VFNMADDSS Vdq,Hdq,Wss,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7a_pp_01_w = @@ -724,13 +724,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3031] // VFNMADDPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3070] // VFNMADDPD Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3030] // VFNMADDPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3069] // VFNMADDPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_79_pp_01_w = @@ -756,13 +756,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_79_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3033] // VFNMADDPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3072] // VFNMADDPS Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3032] // VFNMADDPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3071] // VFNMADDPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_78_pp_01_w = @@ -788,13 +788,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_78_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2995] // VFMSUBSD Vdq,Hdq,Ldq,Wsd + (const void *)&gInstructions[ 3031] // VFMSUBSD Vdq,Hdq,Ldq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2994] // VFMSUBSD Vdq,Hdq,Wsd,Ldq + (const void *)&gInstructions[ 3030] // VFMSUBSD Vdq,Hdq,Wsd,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6f_pp_01_w = @@ -820,13 +820,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2997] // VFMSUBSS Vdq,Hdq,Ldq,Wss + (const void *)&gInstructions[ 3033] // VFMSUBSS Vdq,Hdq,Ldq,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2996] // VFMSUBSS Vdq,Hdq,Wss,Ldq + (const void *)&gInstructions[ 3032] // VFMSUBSS Vdq,Hdq,Wss,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6e_pp_01_w = @@ -852,13 +852,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2991] // VFMSUBPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3027] // VFMSUBPD Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2990] // VFMSUBPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3026] // VFMSUBPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6d_pp_01_w = @@ -884,13 +884,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2993] // VFMSUBPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3029] // VFMSUBPS Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2992] // VFMSUBPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3028] // VFMSUBPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6c_pp_01_w = @@ -916,13 +916,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2919] // VFMADDSD Vdq,Hdq,Ldq,Wsd + (const void *)&gInstructions[ 2952] // VFMADDSD Vdq,Hdq,Ldq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2918] // VFMADDSD Vdq,Hdq,Wsd,Ldq + (const void *)&gInstructions[ 2951] // VFMADDSD Vdq,Hdq,Wsd,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6b_pp_01_w = @@ -948,13 +948,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2921] // VFMADDSS Vdq,Hdq,Ldq,Wss + (const void *)&gInstructions[ 2954] // VFMADDSS Vdq,Hdq,Ldq,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2920] // VFMADDSS Vdq,Hdq,Wss,Ldq + (const void *)&gInstructions[ 2953] // VFMADDSS Vdq,Hdq,Wss,Ldq }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6a_pp_01_w = @@ -980,13 +980,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2915] // VFMADDPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 2948] // VFMADDPD Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2914] // VFMADDPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2947] // VFMADDPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_69_pp_01_w = @@ -1012,13 +1012,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_69_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2917] // VFMADDPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 2950] // VFMADDPS Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2916] // VFMADDPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2949] // VFMADDPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_68_pp_01_w = @@ -1044,7 +1044,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_68_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3397] // VPCMPISTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 3457] // VPCMPISTRI Vdq,Wdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_63_pp_01_l = @@ -1072,7 +1072,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_63_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3398] // VPCMPISTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 3458] // VPCMPISTRM Vdq,Wdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_62_pp_01_l = @@ -1100,7 +1100,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_62_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3387] // VPCMPESTRI Vdq,Wdq,Ib + (const void *)&gInstructions[ 3447] // VPCMPESTRI Vdq,Wdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_61_pp_01_l = @@ -1128,7 +1128,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_61_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3388] // VPCMPESTRM Vdq,Wdq,Ib + (const void *)&gInstructions[ 3448] // VPCMPESTRM Vdq,Wdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_60_pp_01_l = @@ -1156,13 +1156,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_60_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2987] // VFMSUBADDPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3023] // VFMSUBADDPD Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2986] // VFMSUBADDPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3022] // VFMSUBADDPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5f_pp_01_w = @@ -1188,13 +1188,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2989] // VFMSUBADDPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3025] // VFMSUBADDPS Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2988] // VFMSUBADDPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3024] // VFMSUBADDPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5e_pp_01_w = @@ -1220,13 +1220,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2938] // VFMADDSUBPD Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 2971] // VFMADDSUBPD Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2937] // VFMADDSUBPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2970] // VFMADDSUBPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5d_pp_01_w = @@ -1252,13 +1252,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2940] // VFMADDSUBPS Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 2973] // VFMADDSUBPS Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2939] // VFMADDSUBPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2972] // VFMADDSUBPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5c_pp_01_w = @@ -1284,7 +1284,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3357] // VPBLENDVB Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3417] // VPBLENDVB Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4c_pp_01_w = @@ -1310,7 +1310,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2699] // VBLENDVPD Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2684] // VBLENDVPD Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4b_pp_01_w = @@ -1336,7 +1336,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2700] // VBLENDVPS Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 2685] // VBLENDVPS Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4a_pp_01_w = @@ -1362,13 +1362,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3451] // VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb + (const void *)&gInstructions[ 3523] // VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3450] // VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb + (const void *)&gInstructions[ 3522] // VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_49_pp_01_w = @@ -1394,13 +1394,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_49_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3453] // VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb + (const void *)&gInstructions[ 3525] // VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3452] // VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb + (const void *)&gInstructions[ 3524] // VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_48_pp_01_w = @@ -1426,7 +1426,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_48_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3440] // VPERM2I128 Vqq,Hqq,Wqq,Ib + (const void *)&gInstructions[ 3512] // VPERM2I128 Vqq,Hqq,Wqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w = @@ -1463,7 +1463,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_46_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_44_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3374] // VPCLMULQDQ Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3434] // VPCLMULQDQ Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_44_pp = @@ -1480,7 +1480,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_44_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_42_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3281] // VMPSADBW Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3340] // VMPSADBW Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_42_pp = @@ -1497,7 +1497,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_42_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2852] // VDPPD Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 2881] // VDPPD Vdq,Hdq,Wdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_41_pp_01_l = @@ -1525,7 +1525,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_41_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_40_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2853] // VDPPS Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 2883] // VDPPS Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_40_pp = @@ -1542,7 +1542,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_40_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2865] // VEXTRACTI128 Wdq,Vqq,Ib + (const void *)&gInstructions[ 2895] // VEXTRACTI128 Wdq,Vqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w = @@ -1579,7 +1579,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_39_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3129] // VINSERTI128 Vqq,Hqq,Wdq,Ib + (const void *)&gInstructions[ 3174] // VINSERTI128 Vqq,Hqq,Wdq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w = @@ -1616,13 +1616,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_38_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1288] // KSHIFTLQ rKq,mKq,Ib + (const void *)&gInstructions[ 1278] // KSHIFTLQ rKq,mKq,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1287] // KSHIFTLD rKd,mKd,Ib + (const void *)&gInstructions[ 1277] // KSHIFTLD rKd,mKd,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w = @@ -1668,13 +1668,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_33_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1289] // KSHIFTLW rKw,mKw,Ib + (const void *)&gInstructions[ 1279] // KSHIFTLW rKw,mKw,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1286] // KSHIFTLB rKb,mKb,Ib + (const void *)&gInstructions[ 1276] // KSHIFTLB rKb,mKb,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w = @@ -1720,13 +1720,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_32_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1292] // KSHIFTRQ rKq,mKq,Ib + (const void *)&gInstructions[ 1282] // KSHIFTRQ rKq,mKq,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1291] // KSHIFTRD rKd,mKd,Ib + (const void *)&gInstructions[ 1281] // KSHIFTRD rKd,mKd,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w = @@ -1772,13 +1772,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_31_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1293] // KSHIFTRW rKw,mKw,Ib + (const void *)&gInstructions[ 1283] // KSHIFTRW rKw,mKw,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1290] // KSHIFTRB rKb,mKb,Ib + (const void *)&gInstructions[ 1280] // KSHIFTRB rKb,mKb,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w = @@ -1824,13 +1824,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_30_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3538] // VPINSRQ Vdq,Hdq,Ey,Ib + (const void *)&gInstructions[ 3610] // VPINSRQ Vdq,Hdq,Ey,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3536] // VPINSRD Vdq,Hdq,Ey,Ib + (const void *)&gInstructions[ 3608] // VPINSRD Vdq,Hdq,Ey,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = @@ -1867,7 +1867,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_22_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3137] // VINSERTPS Vdq,Hdq,Udq,Ib + (const void *)&gInstructions[ 3182] // VINSERTPS Vdq,Hdq,Udq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = @@ -1884,7 +1884,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3136] // VINSERTPS Vdq,Hdq,Md,Ib + (const void *)&gInstructions[ 3181] // VINSERTPS Vdq,Hdq,Md,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = @@ -1921,7 +1921,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_21_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3534] // VPINSRB Vdq,Hdq,Rd,Ib + (const void *)&gInstructions[ 3606] // VPINSRB Vdq,Hdq,Rd,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = @@ -1938,7 +1938,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3533] // VPINSRB Vdq,Hdq,Mb,Ib + (const void *)&gInstructions[ 3605] // VPINSRB Vdq,Hdq,Mb,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = @@ -1975,7 +1975,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_20_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2774] // VCVTPS2PH Wdq,Vqq,Ib + (const void *)&gInstructions[ 2784] // VCVTPS2PH Wdq,Vqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w = @@ -1990,7 +1990,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2773] // VCVTPS2PH Wq,Vdq,Ib + (const void *)&gInstructions[ 2783] // VCVTPS2PH Wq,Vdq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w = @@ -2027,7 +2027,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_1d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2860] // VEXTRACTF128 Wdq,Vqq,Ib + (const void *)&gInstructions[ 2890] // VEXTRACTF128 Wdq,Vqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w = @@ -2064,7 +2064,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_19_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3124] // VINSERTF128 Vqq,Hqq,Wdq,Ib + (const void *)&gInstructions[ 3169] // VINSERTF128 Vqq,Hqq,Wdq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w = @@ -2101,7 +2101,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_18_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2873] // VEXTRACTPS Ry,Vdq,Ib + (const void *)&gInstructions[ 2903] // VEXTRACTPS Ry,Vdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = @@ -2118,7 +2118,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2872] // VEXTRACTPS Md,Vdq,Ib + (const void *)&gInstructions[ 2902] // VEXTRACTPS Md,Vdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = @@ -2155,13 +2155,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_17_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3494] // VPEXTRQ Ry,Vdq,Ib + (const void *)&gInstructions[ 3566] // VPEXTRQ Ry,Vdq,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3490] // VPEXTRD Ry,Vdq,Ib + (const void *)&gInstructions[ 3562] // VPEXTRD Ry,Vdq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = @@ -2187,13 +2187,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3493] // VPEXTRQ Mq,Vdq,Ib + (const void *)&gInstructions[ 3565] // VPEXTRQ Mq,Vdq,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3489] // VPEXTRD Md,Vdq,Ib + (const void *)&gInstructions[ 3561] // VPEXTRD Md,Vdq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = @@ -2239,7 +2239,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_16_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3500] // VPEXTRW Ry,Vdq,Ib + (const void *)&gInstructions[ 3572] // VPEXTRW Ry,Vdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = @@ -2256,7 +2256,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3499] // VPEXTRW Mw,Vdq,Ib + (const void *)&gInstructions[ 3571] // VPEXTRW Mw,Vdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = @@ -2293,7 +2293,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_15_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3486] // VPEXTRB Ry,Vdq,Ib + (const void *)&gInstructions[ 3558] // VPEXTRB Ry,Vdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = @@ -2310,7 +2310,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3485] // VPEXTRB Mb,Vdq,Ib + (const void *)&gInstructions[ 3557] // VPEXTRB Mb,Vdq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = @@ -2347,7 +2347,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_14_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3341] // VPALIGNR Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3401] // VPALIGNR Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0f_pp = @@ -2364,7 +2364,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3358] // VPBLENDW Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3418] // VPBLENDW Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0e_pp = @@ -2381,7 +2381,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2697] // VBLENDPD Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 2682] // VBLENDPD Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0d_pp = @@ -2398,7 +2398,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2698] // VBLENDPS Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 2683] // VBLENDPS Vx,Hx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0c_pp = @@ -2415,7 +2415,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3879] // VROUNDSD Vsd,Hsd,Wsd,Ib + (const void *)&gInstructions[ 3954] // VROUNDSD Vsd,Hsd,Wsd,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0b_pp = @@ -2432,7 +2432,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3880] // VROUNDSS Vss,Hss,Wss,Ib + (const void *)&gInstructions[ 3955] // VROUNDSS Vss,Hss,Wss,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0a_pp = @@ -2449,7 +2449,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_09_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3877] // VROUNDPD Vx,Wx,Ib + (const void *)&gInstructions[ 3952] // VROUNDPD Vx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_09_pp = @@ -2466,7 +2466,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_09_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_08_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3878] // VROUNDPS Vx,Wx,Ib + (const void *)&gInstructions[ 3953] // VROUNDPS Vx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_08_pp = @@ -2483,7 +2483,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_08_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3439] // VPERM2F128 Vqq,Hqq,Wqq,Ib + (const void *)&gInstructions[ 3511] // VPERM2F128 Vqq,Hqq,Wqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w = @@ -2520,7 +2520,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_06_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3457] // VPERMILPD Vx,Wx,Ib + (const void *)&gInstructions[ 3529] // VPERMILPD Vx,Wx,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_05_pp_01_w = @@ -2546,7 +2546,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_05_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3461] // VPERMILPS Vx,Wx,Ib + (const void *)&gInstructions[ 3533] // VPERMILPS Vx,Wx,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_04_pp_01_w = @@ -2572,7 +2572,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_04_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3352] // VPBLENDD Vx,Hx,Wx,Ib + (const void *)&gInstructions[ 3412] // VPBLENDD Vx,Hx,Wx,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_02_pp_01_w = @@ -2598,7 +2598,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_02_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3465] // VPERMPD Vqq,Wqq,Ib + (const void *)&gInstructions[ 3537] // VPERMPD Vqq,Wqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w = @@ -2635,7 +2635,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_01_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3471] // VPERMQ Vqq,Wqq,Ib + (const void *)&gInstructions[ 3543] // VPERMQ Vqq,Wqq,Ib }; const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w = @@ -2935,7 +2935,7 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_03_opcode = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2505] // SHRX Gy,Ey,By + (const void *)&gInstructions[ 2489] // SHRX Gy,Ey,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_03_l = @@ -2952,7 +2952,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_03_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2286] // SARX Gy,Ey,By + (const void *)&gInstructions[ 2277] // SARX Gy,Ey,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_02_l = @@ -2969,7 +2969,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2443] // SHLX Gy,Ey,By + (const void *)&gInstructions[ 2427] // SHLX Gy,Ey,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_01_l = @@ -2986,7 +2986,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 196] // BEXTR Gy,Ey,By + (const void *)&gInstructions[ 188] // BEXTR Gy,Ey,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_00_l = @@ -3014,7 +3014,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1494] // MULX Gy,By,Ey + (const void *)&gInstructions[ 1484] // MULX Gy,By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f6_pp_03_l = @@ -3042,7 +3042,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1721] // PDEP Gy,By,Ey + (const void *)&gInstructions[ 1711] // PDEP Gy,By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_03_l = @@ -3059,7 +3059,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_03_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1723] // PEXT Gy,By,Ey + (const void *)&gInstructions[ 1713] // PEXT Gy,By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_02_l = @@ -3076,7 +3076,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 247] // BZHI Gy,Ey,By + (const void *)&gInstructions[ 239] // BZHI Gy,Ey,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_00_l = @@ -3104,7 +3104,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 210] // BLSI By,Ey + (const void *)&gInstructions[ 202] // BLSI By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = @@ -3121,7 +3121,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 214] // BLSMSK By,Ey + (const void *)&gInstructions[ 206] // BLSMSK By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = @@ -3138,7 +3138,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 217] // BLSR By,Ey + (const void *)&gInstructions[ 209] // BLSR By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l = @@ -3181,7 +3181,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 184] // ANDN Gy,By,Ey + (const void *)&gInstructions[ 176] // ANDN Gy,By,Ey }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f2_pp_00_l = @@ -3209,7 +3209,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 646] // CMPNLEXADD My,Gy,By + (const void *)&gInstructions[ 638] // CMPNLEXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l = @@ -3246,7 +3246,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ef_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 638] // CMPLEXADD My,Gy,By + (const void *)&gInstructions[ 630] // CMPLEXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l = @@ -3283,7 +3283,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ee_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 648] // CMPNLXADD My,Gy,By + (const void *)&gInstructions[ 640] // CMPNLXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l = @@ -3320,7 +3320,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ed_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 640] // CMPLXADD My,Gy,By + (const void *)&gInstructions[ 632] // CMPLXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l = @@ -3357,7 +3357,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ec_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 652] // CMPNPXADD My,Gy,By + (const void *)&gInstructions[ 644] // CMPNPXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l = @@ -3394,7 +3394,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_eb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 662] // CMPPXADD My,Gy,By + (const void *)&gInstructions[ 654] // CMPPXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l = @@ -3431,7 +3431,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ea_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 654] // CMPNSXADD My,Gy,By + (const void *)&gInstructions[ 646] // CMPNSXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l = @@ -3468,7 +3468,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 674] // CMPSXADD My,Gy,By + (const void *)&gInstructions[ 666] // CMPSXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l = @@ -3505,7 +3505,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 642] // CMPNBEXADD My,Gy,By + (const void *)&gInstructions[ 634] // CMPNBEXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l = @@ -3542,7 +3542,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 634] // CMPBEXADD My,Gy,By + (const void *)&gInstructions[ 626] // CMPBEXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l = @@ -3579,7 +3579,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 656] // CMPNZXADD My,Gy,By + (const void *)&gInstructions[ 648] // CMPNZXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l = @@ -3616,7 +3616,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 680] // CMPZXADD My,Gy,By + (const void *)&gInstructions[ 672] // CMPZXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l = @@ -3653,7 +3653,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 644] // CMPNCXADD My,Gy,By + (const void *)&gInstructions[ 636] // CMPNCXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l = @@ -3690,7 +3690,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 636] // CMPCXADD My,Gy,By + (const void *)&gInstructions[ 628] // CMPCXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l = @@ -3727,7 +3727,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 650] // CMPNOXADD My,Gy,By + (const void *)&gInstructions[ 642] // CMPNOXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l = @@ -3764,7 +3764,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 658] // CMPOXADD My,Gy,By + (const void *)&gInstructions[ 650] // CMPOXADD My,Gy,By }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l = @@ -3801,7 +3801,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_df_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2676] // VAESDECLAST Vx,Hx,Wx + (const void *)&gInstructions[ 2661] // VAESDECLAST Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_df_pp = @@ -3818,7 +3818,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_df_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2674] // VAESDEC Vx,Hx,Wx + (const void *)&gInstructions[ 2659] // VAESDEC Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_de_pp = @@ -3835,7 +3835,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_de_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2680] // VAESENCLAST Vx,Hx,Wx + (const void *)&gInstructions[ 2665] // VAESENCLAST Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dd_pp = @@ -3852,7 +3852,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2678] // VAESENC Vx,Hx,Wx + (const void *)&gInstructions[ 2663] // VAESENC Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dc_pp = @@ -3869,7 +3869,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2681] // VAESIMC Vdq,Wdq + (const void *)&gInstructions[ 2666] // VAESIMC Vdq,Wdq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_db_pp_01_l = @@ -3897,7 +3897,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_db_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3926] // VSM4RNDS4 Vx,Hx,Wx + (const void *)&gInstructions[ 4003] // VSM4RNDS4 Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_03_w = @@ -3912,7 +3912,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_03_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3925] // VSM4KEY4 Vx,Hx,Wx + (const void *)&gInstructions[ 4002] // VSM4KEY4 Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_02_w = @@ -3927,7 +3927,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3923] // VSM3MSG2 Vdq,Hdq,Wdq + (const void *)&gInstructions[ 4000] // VSM3MSG2 Vdq,Hdq,Wdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w = @@ -3953,7 +3953,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3922] // VSM3MSG1 Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3999] // VSM3MSG1 Vdq,Hdq,Wdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w = @@ -3990,7 +3990,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_da_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3434] // VPDPWSUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3502] // VPDPWSUDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_02_w = @@ -4005,7 +4005,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3436] // VPDPWUSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3506] // VPDPWUSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_01_w = @@ -4020,7 +4020,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3438] // VPDPWUUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3510] // VPDPWUUDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_00_w = @@ -4046,7 +4046,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3433] // VPDPWSUD Vx,Hx,Wx + (const void *)&gInstructions[ 3500] // VPDPWSUD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_02_w = @@ -4061,7 +4061,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3435] // VPDPWUSD Vx,Hx,Wx + (const void *)&gInstructions[ 3504] // VPDPWUSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_01_w = @@ -4076,7 +4076,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3437] // VPDPWUUD Vx,Hx,Wx + (const void *)&gInstructions[ 3508] // VPDPWUUD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_00_w = @@ -4102,7 +4102,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3119] // VGF2P8MULB Vx,Hx,Wx + (const void *)&gInstructions[ 3164] // VGF2P8MULB Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cf_pp_01_w = @@ -4128,7 +4128,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cf_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3912] // VSHA512MSG2 Vqq,Uqq + (const void *)&gInstructions[ 3989] // VSHA512MSG2 Vqq,Uqq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w = @@ -4174,7 +4174,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3911] // VSHA512MSG1 Vqq,Udq + (const void *)&gInstructions[ 3988] // VSHA512MSG1 Vqq,Udq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w = @@ -4220,7 +4220,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3913] // VSHA512RNDS2 Vqq,Hqq,Udq + (const void *)&gInstructions[ 3990] // VSHA512RNDS2 Vqq,Hqq,Udq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w = @@ -4266,13 +4266,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3064] // VFNMSUB231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3106] // VFNMSUB231SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3067] // VFNMSUB231SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3109] // VFNMSUB231SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bf_pp_01_w = @@ -4298,13 +4298,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bf_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3059] // VFNMSUB231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3101] // VFNMSUB231PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3062] // VFNMSUB231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3104] // VFNMSUB231PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_be_pp_01_w = @@ -4330,13 +4330,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_be_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3026] // VFNMADD231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3065] // VFNMADD231SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3029] // VFNMADD231SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3068] // VFNMADD231SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bd_pp_01_w = @@ -4362,13 +4362,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3021] // VFNMADD231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3060] // VFNMADD231PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3024] // VFNMADD231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3063] // VFNMADD231PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bc_pp_01_w = @@ -4394,13 +4394,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2967] // VFMSUB231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3003] // VFMSUB231SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2970] // VFMSUB231SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3006] // VFMSUB231SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bb_pp_01_w = @@ -4426,13 +4426,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2962] // VFMSUB231PD Vx,Hx,Wx + (const void *)&gInstructions[ 2998] // VFMSUB231PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2965] // VFMSUB231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3001] // VFMSUB231PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ba_pp_01_w = @@ -4458,13 +4458,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ba_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2908] // VFMADD231SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2941] // VFMADD231SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2911] // VFMADD231SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2944] // VFMADD231SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b9_pp_01_w = @@ -4490,13 +4490,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2903] // VFMADD231PD Vx,Hx,Wx + (const void *)&gInstructions[ 2936] // VFMADD231PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2906] // VFMADD231PS Vx,Hx,Wx + (const void *)&gInstructions[ 2939] // VFMADD231PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b8_pp_01_w = @@ -4522,13 +4522,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2982] // VFMSUBADD231PD Vx,Hx,Wx + (const void *)&gInstructions[ 3018] // VFMSUBADD231PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2985] // VFMSUBADD231PS Vx,Hx,Wx + (const void *)&gInstructions[ 3021] // VFMSUBADD231PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b7_pp_01_w = @@ -4554,13 +4554,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2933] // VFMADDSUB231PD Vx,Hx,Wx + (const void *)&gInstructions[ 2966] // VFMADDSUB231PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2936] // VFMADDSUB231PS Vx,Hx,Wx + (const void *)&gInstructions[ 2969] // VFMADDSUB231PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b6_pp_01_w = @@ -4586,7 +4586,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3558] // VPMADD52HUQ Vx,Hx,Wx + (const void *)&gInstructions[ 3630] // VPMADD52HUQ Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b5_pp_01_w = @@ -4612,7 +4612,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3560] // VPMADD52LUQ Vx,Hx,Wx + (const void *)&gInstructions[ 3632] // VPMADD52LUQ Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b4_pp_01_w = @@ -4638,7 +4638,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2693] // VBCSTNEBF162PS Vx,Mw + (const void *)&gInstructions[ 2678] // VBCSTNEBF162PS Vx,Mw }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w = @@ -4662,7 +4662,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2694] // VBCSTNESH2PS Vx,Mw + (const void *)&gInstructions[ 2679] // VBCSTNESH2PS Vx,Mw }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w = @@ -4697,7 +4697,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2743] // VCVTNEOBF162PS Vx,Mx + (const void *)&gInstructions[ 2745] // VCVTNEOBF162PS Vx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w = @@ -4721,7 +4721,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2741] // VCVTNEEBF162PS Vx,Mx + (const void *)&gInstructions[ 2743] // VCVTNEEBF162PS Vx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w = @@ -4745,7 +4745,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2742] // VCVTNEEPH2PS Vx,Mx + (const void *)&gInstructions[ 2744] // VCVTNEEPH2PS Vx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w = @@ -4769,7 +4769,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2744] // VCVTNEOPH2PS Vx,Mx + (const void *)&gInstructions[ 2746] // VCVTNEOPH2PS Vx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w = @@ -4804,13 +4804,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3054] // VFNMSUB213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3095] // VFNMSUB213SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3057] // VFNMSUB213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3098] // VFNMSUB213SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_af_pp_01_w = @@ -4836,13 +4836,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_af_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3049] // VFNMSUB213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3090] // VFNMSUB213PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3052] // VFNMSUB213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3093] // VFNMSUB213PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ae_pp_01_w = @@ -4868,13 +4868,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ae_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3016] // VFNMADD213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3054] // VFNMADD213SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3019] // VFNMADD213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3057] // VFNMADD213SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ad_pp_01_w = @@ -4900,13 +4900,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ad_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3011] // VFNMADD213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3049] // VFNMADD213PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3014] // VFNMADD213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3052] // VFNMADD213PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ac_pp_01_w = @@ -4932,13 +4932,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ac_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2957] // VFMSUB213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2992] // VFMSUB213SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2960] // VFMSUB213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2995] // VFMSUB213SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ab_pp_01_w = @@ -4964,13 +4964,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ab_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2952] // VFMSUB213PD Vx,Hx,Wx + (const void *)&gInstructions[ 2987] // VFMSUB213PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2955] // VFMSUB213PS Vx,Hx,Wx + (const void *)&gInstructions[ 2990] // VFMSUB213PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_aa_pp_01_w = @@ -4996,13 +4996,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_aa_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2898] // VFMADD213SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2930] // VFMADD213SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2901] // VFMADD213SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2933] // VFMADD213SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a9_pp_01_w = @@ -5028,13 +5028,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2893] // VFMADD213PD Vx,Hx,Wx + (const void *)&gInstructions[ 2925] // VFMADD213PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2896] // VFMADD213PS Vx,Hx,Wx + (const void *)&gInstructions[ 2928] // VFMADD213PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a8_pp_01_w = @@ -5060,13 +5060,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2977] // VFMSUBADD213PD Vx,Hx,Wx + (const void *)&gInstructions[ 3013] // VFMSUBADD213PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2980] // VFMSUBADD213PS Vx,Hx,Wx + (const void *)&gInstructions[ 3016] // VFMSUBADD213PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a7_pp_01_w = @@ -5092,13 +5092,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2928] // VFMADDSUB213PD Vx,Hx,Wx + (const void *)&gInstructions[ 2961] // VFMADDSUB213PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2931] // VFMADDSUB213PS Vx,Hx,Wx + (const void *)&gInstructions[ 2964] // VFMADDSUB213PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a6_pp_01_w = @@ -5124,13 +5124,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3044] // VFNMSUB132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3084] // VFNMSUB132SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3047] // VFNMSUB132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3087] // VFNMSUB132SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9f_pp_01_w = @@ -5156,13 +5156,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3039] // VFNMSUB132PD Vx,Hx,Wx + (const void *)&gInstructions[ 3079] // VFNMSUB132PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3042] // VFNMSUB132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3082] // VFNMSUB132PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9e_pp_01_w = @@ -5188,13 +5188,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3006] // VFNMADD132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 3043] // VFNMADD132SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3009] // VFNMADD132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 3046] // VFNMADD132SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9d_pp_01_w = @@ -5220,13 +5220,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3001] // VFNMADD132PD Vx,Hx,Wx + (const void *)&gInstructions[ 3038] // VFNMADD132PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3004] // VFNMADD132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3041] // VFNMADD132PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9c_pp_01_w = @@ -5252,13 +5252,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2947] // VFMSUB132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2981] // VFMSUB132SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2950] // VFMSUB132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2984] // VFMSUB132SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9b_pp_01_w = @@ -5284,13 +5284,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2942] // VFMSUB132PD Vx,Hx,Wx + (const void *)&gInstructions[ 2976] // VFMSUB132PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2945] // VFMSUB132PS Vx,Hx,Wx + (const void *)&gInstructions[ 2979] // VFMSUB132PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9a_pp_01_w = @@ -5316,13 +5316,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2888] // VFMADD132SD Vdq,Hdq,Wsd + (const void *)&gInstructions[ 2919] // VFMADD132SD Vdq,Hdq,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2891] // VFMADD132SS Vdq,Hdq,Wss + (const void *)&gInstructions[ 2922] // VFMADD132SS Vdq,Hdq,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_99_pp_01_w = @@ -5348,13 +5348,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_99_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2883] // VFMADD132PD Vx,Hx,Wx + (const void *)&gInstructions[ 2914] // VFMADD132PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2886] // VFMADD132PS Vx,Hx,Wx + (const void *)&gInstructions[ 2917] // VFMADD132PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_98_pp_01_w = @@ -5380,13 +5380,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_98_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2972] // VFMSUBADD132PD Vx,Hx,Wx + (const void *)&gInstructions[ 3008] // VFMSUBADD132PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2975] // VFMSUBADD132PS Vx,Hx,Wx + (const void *)&gInstructions[ 3011] // VFMSUBADD132PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_97_pp_01_w = @@ -5412,13 +5412,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_97_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2923] // VFMADDSUB132PD Vx,Hx,Wx + (const void *)&gInstructions[ 2956] // VFMADDSUB132PD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2926] // VFMADDSUB132PS Vx,Hx,Wx + (const void *)&gInstructions[ 2959] // VFMADDSUB132PS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_96_pp_01_w = @@ -5444,13 +5444,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_96_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3099] // VGATHERQPD Vx,Mvm64n,Hx + (const void *)&gInstructions[ 3142] // VGATHERQPD Vx,Mvm64n,Hx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3101] // VGATHERQPS Vdq,Mvm64n,Hdq + (const void *)&gInstructions[ 3144] // VGATHERQPS Vdq,Mvm64n,Hdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = @@ -5485,13 +5485,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_93_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3087] // VGATHERDPD Vx,Mvm32h,Hx + (const void *)&gInstructions[ 3130] // VGATHERDPD Vx,Mvm32h,Hx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3089] // VGATHERDPS Vx,Mvm32n,Hx + (const void *)&gInstructions[ 3132] // VGATHERDPS Vx,Mvm32n,Hx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = @@ -5526,13 +5526,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_92_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3508] // VPGATHERQQ Vx,Mvm64n,Hx + (const void *)&gInstructions[ 3580] // VPGATHERQQ Vx,Mvm64n,Hx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3506] // VPGATHERQD Vdq,Mvm64n,Hdq + (const void *)&gInstructions[ 3578] // VPGATHERQD Vdq,Mvm64n,Hdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = @@ -5567,13 +5567,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_91_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3504] // VPGATHERDQ Vx,Mvm32h,Hx + (const void *)&gInstructions[ 3576] // VPGATHERDQ Vx,Mvm32h,Hx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3502] // VPGATHERDD Vx,Mvm32n,Hx + (const void *)&gInstructions[ 3574] // VPGATHERDD Vx,Mvm32n,Hx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = @@ -5608,13 +5608,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_90_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3568] // VPMASKMOVQ Mx,Hx,Vx + (const void *)&gInstructions[ 3640] // VPMASKMOVQ Mx,Hx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3566] // VPMASKMOVD Mx,Hx,Vx + (const void *)&gInstructions[ 3638] // VPMASKMOVD Mx,Hx,Vx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w = @@ -5649,13 +5649,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3567] // VPMASKMOVQ Vx,Hx,Mx + (const void *)&gInstructions[ 3639] // VPMASKMOVQ Vx,Hx,Mx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3565] // VPMASKMOVD Vx,Hx,Mx + (const void *)&gInstructions[ 3637] // VPMASKMOVD Vx,Hx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w = @@ -5690,7 +5690,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3372] // VPBROADCASTW Vx,Ww + (const void *)&gInstructions[ 3432] // VPBROADCASTW Vx,Ww }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_79_pp_01_w = @@ -5716,7 +5716,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_79_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3361] // VPBROADCASTB Vx,Wb + (const void *)&gInstructions[ 3421] // VPBROADCASTB Vx,Wb }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_78_pp_01_w = @@ -5742,7 +5742,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_78_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2746] // VCVTNEPS2BF16 Vx,Wx + (const void *)&gInstructions[ 2752] // VCVTNEPS2BF16 Vx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_72_pp_02_w = @@ -5768,7 +5768,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_72_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2603] // TCMMIMFP16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2587] // TCMMIMFP16PS rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w = @@ -5803,7 +5803,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2604] // TCMMRLFP16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2588] // TCMMRLFP16PS rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w = @@ -5849,7 +5849,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2607] // TDPBSSD rTt,mTt,vTt + (const void *)&gInstructions[ 2591] // TDPBSSD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w = @@ -5884,7 +5884,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2608] // TDPBSUD rTt,mTt,vTt + (const void *)&gInstructions[ 2592] // TDPBSUD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w = @@ -5919,7 +5919,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2609] // TDPBUSD rTt,mTt,vTt + (const void *)&gInstructions[ 2593] // TDPBUSD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w = @@ -5954,7 +5954,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2610] // TDPBUUD rTt,mTt,vTt + (const void *)&gInstructions[ 2594] // TDPBUUD rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w = @@ -6000,7 +6000,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2611] // TDPFP16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2595] // TDPFP16PS rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w = @@ -6035,7 +6035,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2606] // TDPBF16PS rTt,mTt,vTt + (const void *)&gInstructions[ 2590] // TDPBF16PS rTt,mTt,vTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w = @@ -6081,7 +6081,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2707] // VBROADCASTI128 Vqq,Mdq + (const void *)&gInstructions[ 2692] // VBROADCASTI128 Vqq,Mdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w = @@ -6127,7 +6127,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3369] // VPBROADCASTQ Vx,Wq + (const void *)&gInstructions[ 3429] // VPBROADCASTQ Vx,Wq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_59_pp_01_w = @@ -6153,7 +6153,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_59_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3364] // VPBROADCASTD Vx,Wd + (const void *)&gInstructions[ 3424] // VPBROADCASTD Vx,Wd }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_58_pp_01_w = @@ -6179,7 +6179,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_58_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3432] // VPDPWSSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3498] // VPDPWSSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_53_pp_01_w = @@ -6205,7 +6205,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_53_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3430] // VPDPWSSD Vx,Hx,Wx + (const void *)&gInstructions[ 3496] // VPDPWSSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_52_pp_01_w = @@ -6231,7 +6231,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_52_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3420] // VPDPBSSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3482] // VPDPBSSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_03_w = @@ -6246,7 +6246,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_03_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3422] // VPDPBSUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3486] // VPDPBSUDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_02_w = @@ -6261,7 +6261,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3426] // VPDPBUSDS Vx,Hx,Wx + (const void *)&gInstructions[ 3490] // VPDPBUSDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_01_w = @@ -6276,7 +6276,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3428] // VPDPBUUDS Vx,Hx,Wx + (const void *)&gInstructions[ 3494] // VPDPBUUDS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_00_w = @@ -6302,7 +6302,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_51_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3419] // VPDPBSSD Vx,Hx,Wx + (const void *)&gInstructions[ 3480] // VPDPBSSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_03_w = @@ -6317,7 +6317,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_03_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3421] // VPDPBSUD Vx,Hx,Wx + (const void *)&gInstructions[ 3484] // VPDPBSUD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_02_w = @@ -6332,7 +6332,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_02_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3424] // VPDPBUSD Vx,Hx,Wx + (const void *)&gInstructions[ 3488] // VPDPBUSD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_01_w = @@ -6347,7 +6347,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3427] // VPDPBUUD Vx,Hx,Wx + (const void *)&gInstructions[ 3492] // VPDPBUUD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_00_w = @@ -6373,7 +6373,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_50_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2622] // TILELOADD rTt,Mt + (const void *)&gInstructions[ 2606] // TILELOADD rTt,Mt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w = @@ -6408,7 +6408,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2627] // TILESTORED Mt,rTt + (const void *)&gInstructions[ 2611] // TILESTORED Mt,rTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w = @@ -6443,7 +6443,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2624] // TILELOADDT1 rTt,Mt + (const void *)&gInstructions[ 2608] // TILELOADDT1 rTt,Mt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w = @@ -6489,7 +6489,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_4b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2628] // TILEZERO rTt + (const void *)&gInstructions[ 2612] // TILEZERO rTt }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w = @@ -6539,7 +6539,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2537] // STTILECFG Moq + (const void *)&gInstructions[ 2521] // STTILECFG Moq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w = @@ -6589,7 +6589,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2625] // TILERELEASE + (const void *)&gInstructions[ 2609] // TILERELEASE }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w = @@ -6630,7 +6630,7 @@ const ND_TABLE_MODRM_RM gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01 const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1316] // LDTILECFG Moq + (const void *)&gInstructions[ 1306] // LDTILECFG Moq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w = @@ -6691,13 +6691,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_49_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3764] // VPSLLVQ Vx,Hx,Wx + (const void *)&gInstructions[ 3836] // VPSLLVQ Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3762] // VPSLLVD Vx,Hx,Wx + (const void *)&gInstructions[ 3834] // VPSLLVD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_47_pp_01_w = @@ -6723,7 +6723,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_47_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3777] // VPSRAVD Vx,Hx,Wx + (const void *)&gInstructions[ 3849] // VPSRAVD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_46_pp_01_w = @@ -6749,13 +6749,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_46_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3797] // VPSRLVQ Vx,Hx,Wx + (const void *)&gInstructions[ 3869] // VPSRLVQ Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3795] // VPSRLVD Vx,Hx,Wx + (const void *)&gInstructions[ 3867] // VPSRLVD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_45_pp_01_w = @@ -6781,7 +6781,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_45_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_41_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3524] // VPHMINPOSUW Vdq,Wdq + (const void *)&gInstructions[ 3596] // VPHMINPOSUW Vdq,Wdq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_41_pp_01_l = @@ -6809,7 +6809,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_41_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_40_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3669] // VPMULLD Vx,Hx,Wx + (const void *)&gInstructions[ 3741] // VPMULLD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_40_pp = @@ -6826,7 +6826,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_40_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3579] // VPMAXUD Vx,Hx,Wx + (const void *)&gInstructions[ 3651] // VPMAXUD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3f_pp = @@ -6843,7 +6843,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3582] // VPMAXUW Vx,Hx,Wx + (const void *)&gInstructions[ 3654] // VPMAXUW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3e_pp = @@ -6860,7 +6860,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3572] // VPMAXSD Vx,Hx,Wx + (const void *)&gInstructions[ 3644] // VPMAXSD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3d_pp = @@ -6877,7 +6877,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3570] // VPMAXSB Vx,Hx,Wx + (const void *)&gInstructions[ 3642] // VPMAXSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3c_pp = @@ -6894,7 +6894,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3593] // VPMINUD Vx,Hx,Wx + (const void *)&gInstructions[ 3665] // VPMINUD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3b_pp = @@ -6911,7 +6911,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3596] // VPMINUW Vx,Hx,Wx + (const void *)&gInstructions[ 3668] // VPMINUW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3a_pp = @@ -6928,7 +6928,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_39_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3586] // VPMINSD Vx,Hx,Wx + (const void *)&gInstructions[ 3658] // VPMINSD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_39_pp = @@ -6945,7 +6945,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_39_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_38_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3584] // VPMINSB Vx,Hx,Wx + (const void *)&gInstructions[ 3656] // VPMINSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_38_pp = @@ -6962,7 +6962,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_38_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_37_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3394] // VPCMPGTQ Vx,Hx,Wx + (const void *)&gInstructions[ 3454] // VPCMPGTQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_37_pp = @@ -6979,7 +6979,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_37_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3443] // VPERMD Vqq,Hqq,Wqq + (const void *)&gInstructions[ 3515] // VPERMD Vqq,Hqq,Wqq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w = @@ -7016,13 +7016,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_36_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3653] // VPMOVZXDQ Vqq,Wdq + (const void *)&gInstructions[ 3725] // VPMOVZXDQ Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3652] // VPMOVZXDQ Vdq,Wq + (const void *)&gInstructions[ 3724] // VPMOVZXDQ Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_35_pp_01_l = @@ -7050,13 +7050,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_35_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3659] // VPMOVZXWQ Vqq,Wq + (const void *)&gInstructions[ 3731] // VPMOVZXWQ Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3658] // VPMOVZXWQ Vdq,Wd + (const void *)&gInstructions[ 3730] // VPMOVZXWQ Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_34_pp_01_l = @@ -7084,13 +7084,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_34_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3656] // VPMOVZXWD Vqq,Wdq + (const void *)&gInstructions[ 3728] // VPMOVZXWD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3655] // VPMOVZXWD Vdq,Wq + (const void *)&gInstructions[ 3727] // VPMOVZXWD Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_33_pp_01_l = @@ -7118,13 +7118,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_33_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3647] // VPMOVZXBQ Vqq,Wd + (const void *)&gInstructions[ 3719] // VPMOVZXBQ Vqq,Wd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3646] // VPMOVZXBQ Vdq,Ww + (const void *)&gInstructions[ 3718] // VPMOVZXBQ Vdq,Ww }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_32_pp_01_l = @@ -7152,13 +7152,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_32_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3644] // VPMOVZXBD Vqq,Wq + (const void *)&gInstructions[ 3716] // VPMOVZXBD Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3643] // VPMOVZXBD Vdq,Wd + (const void *)&gInstructions[ 3715] // VPMOVZXBD Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_31_pp_01_l = @@ -7186,13 +7186,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_31_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3650] // VPMOVZXBW Vqq,Wdq + (const void *)&gInstructions[ 3722] // VPMOVZXBW Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3649] // VPMOVZXBW Vdq,Wq + (const void *)&gInstructions[ 3721] // VPMOVZXBW Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_30_pp_01_l = @@ -7220,7 +7220,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_30_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3142] // VMASKMOVPD Mx,Hx,Vx + (const void *)&gInstructions[ 3187] // VMASKMOVPD Mx,Hx,Vx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w = @@ -7255,7 +7255,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3144] // VMASKMOVPS Mx,Hx,Vx + (const void *)&gInstructions[ 3189] // VMASKMOVPS Mx,Hx,Vx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w = @@ -7290,7 +7290,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3141] // VMASKMOVPD Vx,Hx,Mx + (const void *)&gInstructions[ 3186] // VMASKMOVPD Vx,Hx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w = @@ -7325,7 +7325,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3143] // VMASKMOVPS Vx,Hx,Mx + (const void *)&gInstructions[ 3188] // VMASKMOVPS Vx,Hx,Mx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w = @@ -7360,7 +7360,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3321] // VPACKUSDW Vx,Hx,Wx + (const void *)&gInstructions[ 3381] // VPACKUSDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2b_pp = @@ -7377,7 +7377,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3232] // VMOVNTDQA Vx,Mx + (const void *)&gInstructions[ 3288] // VMOVNTDQA Vx,Mx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod = @@ -7403,7 +7403,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_29_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3384] // VPCMPEQQ Vx,Hx,Wx + (const void *)&gInstructions[ 3444] // VPCMPEQQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_29_pp = @@ -7420,7 +7420,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_29_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_28_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3661] // VPMULDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3733] // VPMULDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_28_pp = @@ -7437,13 +7437,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_28_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3627] // VPMOVSXDQ Vqq,Wdq + (const void *)&gInstructions[ 3699] // VPMOVSXDQ Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3626] // VPMOVSXDQ Vdq,Wq + (const void *)&gInstructions[ 3698] // VPMOVSXDQ Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_25_pp_01_l = @@ -7471,13 +7471,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_25_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3633] // VPMOVSXWQ Vqq,Wq + (const void *)&gInstructions[ 3705] // VPMOVSXWQ Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3632] // VPMOVSXWQ Vdq,Wd + (const void *)&gInstructions[ 3704] // VPMOVSXWQ Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_24_pp_01_l = @@ -7505,13 +7505,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_24_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3630] // VPMOVSXWD Vqq,Wdq + (const void *)&gInstructions[ 3702] // VPMOVSXWD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3629] // VPMOVSXWD Vdq,Wq + (const void *)&gInstructions[ 3701] // VPMOVSXWD Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_23_pp_01_l = @@ -7539,13 +7539,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_23_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3621] // VPMOVSXBQ Vqq,Wd + (const void *)&gInstructions[ 3693] // VPMOVSXBQ Vqq,Wd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3620] // VPMOVSXBQ Vdq,Ww + (const void *)&gInstructions[ 3692] // VPMOVSXBQ Vdq,Ww }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_22_pp_01_l = @@ -7573,13 +7573,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_22_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3618] // VPMOVSXBD Vqq,Wq + (const void *)&gInstructions[ 3690] // VPMOVSXBD Vqq,Wq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3617] // VPMOVSXBD Vdq,Wd + (const void *)&gInstructions[ 3689] // VPMOVSXBD Vdq,Wd }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_21_pp_01_l = @@ -7607,13 +7607,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_21_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3624] // VPMOVSXBW Vqq,Wdq + (const void *)&gInstructions[ 3696] // VPMOVSXBW Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3623] // VPMOVSXBW Vdq,Wq + (const void *)&gInstructions[ 3695] // VPMOVSXBW Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_20_pp_01_l = @@ -7641,7 +7641,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_20_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3312] // VPABSD Vx,Wx + (const void *)&gInstructions[ 3372] // VPABSD Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1e_pp = @@ -7658,7 +7658,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3315] // VPABSW Vx,Wx + (const void *)&gInstructions[ 3375] // VPABSW Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1d_pp = @@ -7675,7 +7675,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3310] // VPABSB Vx,Wx + (const void *)&gInstructions[ 3370] // VPABSB Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1c_pp = @@ -7692,7 +7692,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2701] // VBROADCASTF128 Vqq,Mdq + (const void *)&gInstructions[ 2686] // VBROADCASTF128 Vqq,Mdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w = @@ -7738,7 +7738,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2714] // VBROADCASTSD Vqq,Wsd + (const void *)&gInstructions[ 2699] // VBROADCASTSD Vqq,Wsd }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_19_pp_01_w = @@ -7764,7 +7764,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_19_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2716] // VBROADCASTSS Vx,Wss + (const void *)&gInstructions[ 2701] // VBROADCASTSS Vx,Wss }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_18_pp_01_w = @@ -7790,7 +7790,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_18_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_17_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3821] // VPTEST Vx,Wx + (const void *)&gInstructions[ 3893] // VPTEST Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_17_pp = @@ -7807,7 +7807,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_17_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3468] // VPERMPS Vqq,Hqq,Wqq + (const void *)&gInstructions[ 3540] // VPERMPS Vqq,Hqq,Wqq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w = @@ -7844,7 +7844,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_16_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2760] // VCVTPH2PS Vqq,Wdq + (const void *)&gInstructions[ 2768] // VCVTPH2PS Vqq,Wdq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w = @@ -7859,7 +7859,7 @@ const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2759] // VCVTPH2PS Vdq,Wq + (const void *)&gInstructions[ 2767] // VCVTPH2PS Vdq,Wq }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w = @@ -7896,7 +7896,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_13_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0f_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3948] // VTESTPD Vx,Wx + (const void *)&gInstructions[ 4027] // VTESTPD Vx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0f_pp_01_w = @@ -7922,7 +7922,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0e_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3949] // VTESTPS Vx,Wx + (const void *)&gInstructions[ 4028] // VTESTPS Vx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0e_pp_01_w = @@ -7948,7 +7948,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0d_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3456] // VPERMILPD Vx,Hx,Wx + (const void *)&gInstructions[ 3528] // VPERMILPD Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0d_pp_01_w = @@ -7974,7 +7974,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3460] // VPERMILPS Vx,Hx,Wx + (const void *)&gInstructions[ 3532] // VPERMILPS Vx,Hx,Wx }; const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0c_pp_01_w = @@ -8000,7 +8000,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3663] // VPMULHRSW Vx,Hx,Wx + (const void *)&gInstructions[ 3735] // VPMULHRSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0b_pp = @@ -8017,7 +8017,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3749] // VPSIGND Vx,Hx,Wx + (const void *)&gInstructions[ 3821] // VPSIGND Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0a_pp = @@ -8034,7 +8034,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_09_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3750] // VPSIGNW Vx,Hx,Wx + (const void *)&gInstructions[ 3822] // VPSIGNW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_09_pp = @@ -8051,7 +8051,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_09_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_08_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3748] // VPSIGNB Vx,Hx,Wx + (const void *)&gInstructions[ 3820] // VPSIGNB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_08_pp = @@ -8068,7 +8068,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_08_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_07_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3528] // VPHSUBSW Vx,Hx,Wx + (const void *)&gInstructions[ 3600] // VPHSUBSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_07_pp = @@ -8085,7 +8085,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_07_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_06_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3526] // VPHSUBD Vx,Hx,Wx + (const void *)&gInstructions[ 3598] // VPHSUBD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_06_pp = @@ -8102,7 +8102,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_06_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_05_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3529] // VPHSUBW Vx,Hx,Wx + (const void *)&gInstructions[ 3601] // VPHSUBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_05_pp = @@ -8119,7 +8119,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_05_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_04_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3562] // VPMADDUBSW Vx,Hx,Wx + (const void *)&gInstructions[ 3634] // VPMADDUBSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_04_pp = @@ -8136,7 +8136,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_04_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_03_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3514] // VPHADDSW Vx,Hx,Wx + (const void *)&gInstructions[ 3586] // VPHADDSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_03_pp = @@ -8153,7 +8153,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_03_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_02_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3512] // VPHADDD Vx,Hx,Wx + (const void *)&gInstructions[ 3584] // VPHADDD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_02_pp = @@ -8170,7 +8170,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_02_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_01_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3521] // VPHADDW Vx,Hx,Wx + (const void *)&gInstructions[ 3593] // VPHADDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_01_pp = @@ -8187,7 +8187,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_01_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_00_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3740] // VPSHUFB Vx,Hx,Wx + (const void *)&gInstructions[ 3812] // VPSHUFB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_00_pp = @@ -8467,7 +8467,7 @@ const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fe_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3327] // VPADDD Vx,Hx,Wx + (const void *)&gInstructions[ 3387] // VPADDD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fe_pp = @@ -8484,7 +8484,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fe_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3339] // VPADDW Vx,Hx,Wx + (const void *)&gInstructions[ 3399] // VPADDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fd_pp = @@ -8501,7 +8501,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3325] // VPADDB Vx,Hx,Wx + (const void *)&gInstructions[ 3385] // VPADDB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fc_pp = @@ -8518,7 +8518,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fb_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3808] // VPSUBQ Vx,Hx,Wx + (const void *)&gInstructions[ 3880] // VPSUBQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fb_pp = @@ -8535,7 +8535,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fa_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3806] // VPSUBD Vx,Hx,Wx + (const void *)&gInstructions[ 3878] // VPSUBD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fa_pp = @@ -8552,7 +8552,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fa_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3818] // VPSUBW Vx,Hx,Wx + (const void *)&gInstructions[ 3890] // VPSUBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f9_pp = @@ -8569,7 +8569,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3804] // VPSUBB Vx,Hx,Wx + (const void *)&gInstructions[ 3876] // VPSUBB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f8_pp = @@ -8586,7 +8586,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3140] // VMASKMOVDQU Vdq,Udq + (const void *)&gInstructions[ 3185] // VMASKMOVDQU Vdq,Udq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l = @@ -8623,7 +8623,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3706] // VPSADBW Vx,Hx,Wx + (const void *)&gInstructions[ 3778] // VPSADBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f6_pp = @@ -8640,7 +8640,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3564] // VPMADDWD Vx,Hx,Wx + (const void *)&gInstructions[ 3636] // VPMADDWD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f5_pp = @@ -8657,7 +8657,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3675] // VPMULUDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3747] // VPMULUDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f4_pp = @@ -8674,7 +8674,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3760] // VPSLLQ Vx,Hx,Wdq + (const void *)&gInstructions[ 3832] // VPSLLQ Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f3_pp = @@ -8691,7 +8691,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3754] // VPSLLD Vx,Hx,Wdq + (const void *)&gInstructions[ 3826] // VPSLLD Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f2_pp = @@ -8708,7 +8708,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3769] // VPSLLW Vx,Hx,Wdq + (const void *)&gInstructions[ 3841] // VPSLLW Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f1_pp = @@ -8725,7 +8725,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3138] // VLDDQU Vx,Mx + (const void *)&gInstructions[ 3183] // VLDDQU Vx,Mx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod = @@ -8751,7 +8751,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ef_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3846] // VPXOR Vx,Hx,Wx + (const void *)&gInstructions[ 3918] // VPXOR Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ef_pp = @@ -8768,7 +8768,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ef_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ee_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3575] // VPMAXSW Vx,Hx,Wx + (const void *)&gInstructions[ 3647] // VPMAXSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ee_pp = @@ -8785,7 +8785,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ee_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ed_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3333] // VPADDSW Vx,Hx,Wx + (const void *)&gInstructions[ 3393] // VPADDSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ed_pp = @@ -8802,7 +8802,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ed_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ec_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3331] // VPADDSB Vx,Hx,Wx + (const void *)&gInstructions[ 3391] // VPADDSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ec_pp = @@ -8819,7 +8819,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ec_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_eb_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3680] // VPOR Vx,Hx,Wx + (const void *)&gInstructions[ 3752] // VPOR Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_eb_pp = @@ -8836,7 +8836,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_eb_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ea_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3589] // VPMINSW Vx,Hx,Wx + (const void *)&gInstructions[ 3661] // VPMINSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ea_pp = @@ -8853,7 +8853,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ea_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3812] // VPSUBSW Vx,Hx,Wx + (const void *)&gInstructions[ 3884] // VPSUBSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e9_pp = @@ -8870,7 +8870,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3810] // VPSUBSB Vx,Hx,Wx + (const void *)&gInstructions[ 3882] // VPSUBSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e8_pp = @@ -8887,7 +8887,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3230] // VMOVNTDQ Mx,Vx + (const void *)&gInstructions[ 3286] // VMOVNTDQ Mx,Vx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod = @@ -8913,19 +8913,19 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2748] // VCVTPD2DQ Vdq,Wx + (const void *)&gInstructions[ 2754] // VCVTPD2DQ Vdq,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2736] // VCVTDQ2PD Vqq,Wdq + (const void *)&gInstructions[ 2731] // VCVTDQ2PD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2735] // VCVTDQ2PD Vdq,Wq + (const void *)&gInstructions[ 2730] // VCVTDQ2PD Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_e6_pp_02_l = @@ -8942,7 +8942,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_e6_pp_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2805] // VCVTTPD2DQ Vdq,Wx + (const void *)&gInstructions[ 2817] // VCVTTPD2DQ Vdq,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e6_pp = @@ -8959,7 +8959,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3667] // VPMULHW Vx,Hx,Wx + (const void *)&gInstructions[ 3739] // VPMULHW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e5_pp = @@ -8976,7 +8976,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3665] // VPMULHUW Vx,Hx,Wx + (const void *)&gInstructions[ 3737] // VPMULHUW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e4_pp = @@ -8993,7 +8993,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3351] // VPAVGW Vx,Hx,Wx + (const void *)&gInstructions[ 3411] // VPAVGW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e3_pp = @@ -9010,7 +9010,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3773] // VPSRAD Vx,Hx,Wdq + (const void *)&gInstructions[ 3845] // VPSRAD Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e2_pp = @@ -9027,7 +9027,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3783] // VPSRAW Vx,Hx,Wdq + (const void *)&gInstructions[ 3855] // VPSRAW Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e1_pp = @@ -9044,7 +9044,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e0_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3349] // VPAVGB Vx,Hx,Wx + (const void *)&gInstructions[ 3409] // VPAVGB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e0_pp = @@ -9061,7 +9061,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_df_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3344] // VPANDN Vx,Hx,Wx + (const void *)&gInstructions[ 3404] // VPANDN Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_df_pp = @@ -9078,7 +9078,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_df_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_de_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3577] // VPMAXUB Vx,Hx,Wx + (const void *)&gInstructions[ 3649] // VPMAXUB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_de_pp = @@ -9095,7 +9095,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_de_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dd_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3337] // VPADDUSW Vx,Hx,Wx + (const void *)&gInstructions[ 3397] // VPADDUSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dd_pp = @@ -9112,7 +9112,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dd_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dc_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3335] // VPADDUSB Vx,Hx,Wx + (const void *)&gInstructions[ 3395] // VPADDUSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dc_pp = @@ -9129,7 +9129,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dc_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_db_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3342] // VPAND Vx,Hx,Wx + (const void *)&gInstructions[ 3402] // VPAND Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_db_pp = @@ -9146,7 +9146,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_db_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_da_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3591] // VPMINUB Vx,Hx,Wx + (const void *)&gInstructions[ 3663] // VPMINUB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_da_pp = @@ -9163,7 +9163,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_da_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d9_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3816] // VPSUBUSW Vx,Hx,Wx + (const void *)&gInstructions[ 3888] // VPSUBUSW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d9_pp = @@ -9180,7 +9180,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d9_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d8_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3814] // VPSUBUSB Vx,Hx,Wx + (const void *)&gInstructions[ 3886] // VPSUBUSB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d8_pp = @@ -9197,7 +9197,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d8_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3605] // VPMOVMSKB Gy,Ux + (const void *)&gInstructions[ 3677] // VPMOVMSKB Gy,Ux }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod = @@ -9223,7 +9223,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d7_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d6_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3244] // VMOVQ Wq,Vdq + (const void *)&gInstructions[ 3300] // VMOVQ Wq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_d6_pp_01_l = @@ -9251,7 +9251,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d5_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3672] // VPMULLW Vx,Hx,Wx + (const void *)&gInstructions[ 3744] // VPMULLW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d5_pp = @@ -9268,7 +9268,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d4_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3329] // VPADDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3389] // VPADDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d4_pp = @@ -9285,7 +9285,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d3_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3793] // VPSRLQ Vx,Hx,Wdq + (const void *)&gInstructions[ 3865] // VPSRLQ Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d3_pp = @@ -9302,7 +9302,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d3_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3787] // VPSRLD Vx,Hx,Wdq + (const void *)&gInstructions[ 3859] // VPSRLD Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d2_pp = @@ -9319,7 +9319,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d1_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3802] // VPSRLW Vx,Hx,Wdq + (const void *)&gInstructions[ 3874] // VPSRLW Vx,Hx,Wdq }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d1_pp = @@ -9336,13 +9336,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d1_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2672] // VADDSUBPS Vps,Hps,Wps + (const void *)&gInstructions[ 2657] // VADDSUBPS Vps,Hps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2671] // VADDSUBPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2656] // VADDSUBPD Vpd,Hpd,Wpd }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d0_pp = @@ -9359,13 +9359,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d0_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3919] // VSHUFPD Vpd,Hpd,Wpd,Ib + (const void *)&gInstructions[ 3996] // VSHUFPD Vpd,Hpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3921] // VSHUFPS Vps,Hps,Wps,Ib + (const void *)&gInstructions[ 3998] // VSHUFPS Vps,Hps,Wps,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c6_pp = @@ -9382,7 +9382,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c6_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3498] // VPEXTRW Gy,Udq,Ib + (const void *)&gInstructions[ 3570] // VPEXTRW Gy,Udq,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l = @@ -9419,7 +9419,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c5_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3542] // VPINSRW Vdq,Hdq,Rd,Ib + (const void *)&gInstructions[ 3614] // VPINSRW Vdq,Hdq,Rd,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = @@ -9436,7 +9436,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3541] // VPINSRW Vdq,Hdq,Mw,Ib + (const void *)&gInstructions[ 3613] // VPINSRW Vdq,Hdq,Mw,Ib }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l = @@ -9473,25 +9473,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c4_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2723] // VCMPSD Vsd,Hsd,Wsd,Ib + (const void *)&gInstructions[ 2709] // VCMPSD Vsd,Hsd,Wsd,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2726] // VCMPSS Vss,Hss,Wss,Ib + (const void *)&gInstructions[ 2712] // VCMPSS Vss,Hss,Wss,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2718] // VCMPPD Vpd,Hpd,Wpd,Ib + (const void *)&gInstructions[ 2704] // VCMPPD Vpd,Hpd,Wpd,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2721] // VCMPPS Vss,Hss,Wss,Ib + (const void *)&gInstructions[ 2707] // VCMPPS Vss,Hss,Wss,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c2_pp = @@ -9508,7 +9508,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c2_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 563] // CLEVICT0 M? + (const void *)&gInstructions[ 555] // CLEVICT0 M? }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod = @@ -9523,7 +9523,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2515] // SPFLT Ry + (const void *)&gInstructions[ 2499] // SPFLT Ry }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod = @@ -9553,7 +9553,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 564] // CLEVICT1 M? + (const void *)&gInstructions[ 556] // CLEVICT1 M? }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod = @@ -9568,7 +9568,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 882] // DELAY Ry + (const void *)&gInstructions[ 874] // DELAY Ry }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod = @@ -9598,7 +9598,7 @@ const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3937] // VSTMXCSR Md + (const void *)&gInstructions[ 4015] // VSTMXCSR Md }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod = @@ -9613,7 +9613,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3139] // VLDMXCSR Md + (const void *)&gInstructions[ 3184] // VLDMXCSR Md }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod = @@ -9654,13 +9654,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ae_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1295] // KTESTD rKd,mKd + (const void *)&gInstructions[ 1285] // KTESTD rKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1294] // KTESTB rKb,mKb + (const void *)&gInstructions[ 1284] // KTESTB rKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w = @@ -9695,13 +9695,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1296] // KTESTQ rKq,mKq + (const void *)&gInstructions[ 1286] // KTESTQ rKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1297] // KTESTW rKw,mKw + (const void *)&gInstructions[ 1287] // KTESTW rKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w = @@ -9747,13 +9747,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_99_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1282] // KORTESTD rKd,mKd + (const void *)&gInstructions[ 1272] // KORTESTD rKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1281] // KORTESTB rKb,mKb + (const void *)&gInstructions[ 1271] // KORTESTB rKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w = @@ -9788,13 +9788,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1283] // KORTESTQ rKq,mKq + (const void *)&gInstructions[ 1273] // KORTESTQ rKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1284] // KORTESTW rKw,mKw + (const void *)&gInstructions[ 1274] // KORTESTW rKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w = @@ -9840,13 +9840,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_98_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1263] // KMOVQ Gy,mKq + (const void *)&gInstructions[ 1253] // KMOVQ Gy,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1253] // KMOVD Gy,mKd + (const void *)&gInstructions[ 1243] // KMOVD Gy,mKd }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w = @@ -9881,7 +9881,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1243] // KMOVB Gy,mKb + (const void *)&gInstructions[ 1233] // KMOVB Gy,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w = @@ -9916,7 +9916,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1273] // KMOVW Gy,mKw + (const void *)&gInstructions[ 1263] // KMOVW Gy,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w = @@ -9962,13 +9962,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_93_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1262] // KMOVQ rKq,Ry + (const void *)&gInstructions[ 1252] // KMOVQ rKq,Ry }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1252] // KMOVD rKd,Ry + (const void *)&gInstructions[ 1242] // KMOVD rKd,Ry }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w = @@ -10003,7 +10003,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1242] // KMOVB rKb,Ry + (const void *)&gInstructions[ 1232] // KMOVB rKb,Ry }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w = @@ -10038,7 +10038,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1272] // KMOVW rKw,Ry + (const void *)&gInstructions[ 1262] // KMOVW rKw,Ry }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w = @@ -10084,13 +10084,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_92_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1251] // KMOVD Md,rKd + (const void *)&gInstructions[ 1241] // KMOVD Md,rKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1241] // KMOVB Mb,rKb + (const void *)&gInstructions[ 1231] // KMOVB Mb,rKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w = @@ -10125,13 +10125,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1261] // KMOVQ Mq,rKq + (const void *)&gInstructions[ 1251] // KMOVQ Mq,rKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1271] // KMOVW Mw,rKw + (const void *)&gInstructions[ 1261] // KMOVW Mw,rKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w = @@ -10177,13 +10177,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_91_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1250] // KMOVD rKd,mKd + (const void *)&gInstructions[ 1240] // KMOVD rKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1240] // KMOVB rKb,mKb + (const void *)&gInstructions[ 1230] // KMOVB rKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w = @@ -10209,13 +10209,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1249] // KMOVD rKd,Md + (const void *)&gInstructions[ 1239] // KMOVD rKd,Md }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1239] // KMOVB rKb,Mb + (const void *)&gInstructions[ 1229] // KMOVB rKb,Mb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w = @@ -10250,13 +10250,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1260] // KMOVQ rKq,mKq + (const void *)&gInstructions[ 1250] // KMOVQ rKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1270] // KMOVW rKw,mKw + (const void *)&gInstructions[ 1260] // KMOVW rKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w = @@ -10282,13 +10282,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1259] // KMOVQ rKq,Mq + (const void *)&gInstructions[ 1249] // KMOVQ rKq,Mq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1269] // KMOVW rKw,Mw + (const void *)&gInstructions[ 1259] // KMOVW rKw,Mw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w = @@ -10334,13 +10334,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_90_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3198] // VMOVDQU Wx,Vx + (const void *)&gInstructions[ 3254] // VMOVDQU Wx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3192] // VMOVDQA Wx,Vx + (const void *)&gInstructions[ 3248] // VMOVDQA Wx,Vx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7f_pp = @@ -10357,7 +10357,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_02_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3243] // VMOVQ Vdq,Wq + (const void *)&gInstructions[ 3299] // VMOVQ Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_02_l = @@ -10374,13 +10374,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_02_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3242] // VMOVQ Ey,Vq + (const void *)&gInstructions[ 3298] // VMOVQ Ey,Vq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3185] // VMOVD Ey,Vd + (const void *)&gInstructions[ 3241] // VMOVD Ey,Vd }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi = @@ -10417,13 +10417,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3123] // VHSUBPS Vps,Hps,Wps + (const void *)&gInstructions[ 3168] // VHSUBPS Vps,Hps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3122] // VHSUBPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3167] // VHSUBPD Vpd,Hpd,Wpd }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7d_pp = @@ -10440,13 +10440,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3121] // VHADDPS Vps,Hps,Wps + (const void *)&gInstructions[ 3166] // VHADDPS Vps,Hps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3120] // VHADDPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3165] // VHADDPD Vpd,Hpd,Wpd }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7c_pp = @@ -10463,13 +10463,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3967] // VZEROALL + (const void *)&gInstructions[ 4049] // VZEROALL }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3968] // VZEROUPPER + (const void *)&gInstructions[ 4050] // VZEROUPPER }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_77_pp_00_l = @@ -10497,7 +10497,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_77_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_76_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3382] // VPCMPEQD Vx,Hx,Wx + (const void *)&gInstructions[ 3442] // VPCMPEQD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_76_pp = @@ -10514,7 +10514,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_76_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_75_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3386] // VPCMPEQW Vx,Hx,Wx + (const void *)&gInstructions[ 3446] // VPCMPEQW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_75_pp = @@ -10531,7 +10531,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_75_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_74_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3380] // VPCMPEQB Vx,Hx,Wx + (const void *)&gInstructions[ 3440] // VPCMPEQB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_74_pp = @@ -10548,7 +10548,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_74_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3756] // VPSLLDQ Hx,Ux,Ib + (const void *)&gInstructions[ 3828] // VPSLLDQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod = @@ -10563,7 +10563,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3759] // VPSLLQ Hx,Ux,Ib + (const void *)&gInstructions[ 3831] // VPSLLQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod = @@ -10578,7 +10578,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3789] // VPSRLDQ Hx,Ux,Ib + (const void *)&gInstructions[ 3861] // VPSRLDQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod = @@ -10593,7 +10593,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3792] // VPSRLQ Hx,Ux,Ib + (const void *)&gInstructions[ 3864] // VPSRLQ Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod = @@ -10634,7 +10634,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_73_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3753] // VPSLLD Hx,Ux,Ib + (const void *)&gInstructions[ 3825] // VPSLLD Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod = @@ -10649,7 +10649,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3772] // VPSRAD Hx,Ux,Ib + (const void *)&gInstructions[ 3844] // VPSRAD Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod = @@ -10664,7 +10664,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3786] // VPSRLD Hx,Ux,Ib + (const void *)&gInstructions[ 3858] // VPSRLD Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod = @@ -10705,7 +10705,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_72_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3768] // VPSLLW Hx,Ux,Ib + (const void *)&gInstructions[ 3840] // VPSLLW Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod = @@ -10720,7 +10720,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3782] // VPSRAW Hx,Ux,Ib + (const void *)&gInstructions[ 3854] // VPSRAW Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod = @@ -10735,7 +10735,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3801] // VPSRLW Hx,Ux,Ib + (const void *)&gInstructions[ 3873] // VPSRLW Hx,Ux,Ib }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod = @@ -10776,19 +10776,19 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_71_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3747] // VPSHUFLW Vx,Wx,Ib + (const void *)&gInstructions[ 3819] // VPSHUFLW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3745] // VPSHUFHW Vx,Wx,Ib + (const void *)&gInstructions[ 3817] // VPSHUFHW Vx,Wx,Ib }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3743] // VPSHUFD Vx,Wx,Ib + (const void *)&gInstructions[ 3815] // VPSHUFD Vx,Wx,Ib }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_70_pp = @@ -10805,13 +10805,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_70_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3197] // VMOVDQU Vx,Wx + (const void *)&gInstructions[ 3253] // VMOVDQU Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3191] // VMOVDQA Vx,Wx + (const void *)&gInstructions[ 3247] // VMOVDQA Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6f_pp = @@ -10828,13 +10828,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3241] // VMOVQ Vdq,Ey + (const void *)&gInstructions[ 3297] // VMOVQ Vdq,Ey }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3184] // VMOVD Vdq,Ey + (const void *)&gInstructions[ 3240] // VMOVD Vdq,Ey }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi = @@ -10871,7 +10871,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3835] // VPUNPCKHQDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3907] // VPUNPCKHQDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6d_pp = @@ -10888,7 +10888,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3843] // VPUNPCKLQDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3915] // VPUNPCKLQDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6c_pp = @@ -10905,7 +10905,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3317] // VPACKSSDW Vx,Hx,Wx + (const void *)&gInstructions[ 3377] // VPACKSSDW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6b_pp = @@ -10922,7 +10922,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6a_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3833] // VPUNPCKHDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3905] // VPUNPCKHDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6a_pp = @@ -10939,7 +10939,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_69_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3837] // VPUNPCKHWD Vx,Hx,Wx + (const void *)&gInstructions[ 3909] // VPUNPCKHWD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_69_pp = @@ -10956,7 +10956,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_69_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_68_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3831] // VPUNPCKHBW Vx,Hx,Wx + (const void *)&gInstructions[ 3903] // VPUNPCKHBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_68_pp = @@ -10973,7 +10973,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_68_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_67_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3323] // VPACKUSWB Vx,Hx,Wx + (const void *)&gInstructions[ 3383] // VPACKUSWB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_67_pp = @@ -10990,7 +10990,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_67_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_66_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3392] // VPCMPGTD Vx,Hx,Wx + (const void *)&gInstructions[ 3452] // VPCMPGTD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_66_pp = @@ -11007,7 +11007,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_66_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_65_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3396] // VPCMPGTW Vx,Hx,Wx + (const void *)&gInstructions[ 3456] // VPCMPGTW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_65_pp = @@ -11024,7 +11024,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_65_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_64_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3390] // VPCMPGTB Vx,Hx,Wx + (const void *)&gInstructions[ 3450] // VPCMPGTB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_64_pp = @@ -11041,7 +11041,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_64_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_63_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3319] // VPACKSSWB Vx,Hx,Wx + (const void *)&gInstructions[ 3379] // VPACKSSWB Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_63_pp = @@ -11058,7 +11058,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_63_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_62_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3841] // VPUNPCKLDQ Vx,Hx,Wx + (const void *)&gInstructions[ 3913] // VPUNPCKLDQ Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_62_pp = @@ -11075,7 +11075,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_62_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_61_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3845] // VPUNPCKLWD Vx,Hx,Wx + (const void *)&gInstructions[ 3917] // VPUNPCKLWD Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_61_pp = @@ -11092,7 +11092,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_61_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_60_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3839] // VPUNPCKLBW Vx,Hx,Wx + (const void *)&gInstructions[ 3911] // VPUNPCKLBW Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_60_pp = @@ -11109,25 +11109,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_60_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3151] // VMAXSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 3197] // VMAXSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3154] // VMAXSS Vss,Hss,Wss + (const void *)&gInstructions[ 3200] // VMAXSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3146] // VMAXPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3192] // VMAXPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3149] // VMAXPS Vps,Hps,Wps + (const void *)&gInstructions[ 3195] // VMAXPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5f_pp = @@ -11144,25 +11144,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2847] // VDIVSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 2876] // VDIVSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2850] // VDIVSS Vss,Hss,Wss + (const void *)&gInstructions[ 2879] // VDIVSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2842] // VDIVPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2871] // VDIVPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2845] // VDIVPS Vps,Hps,Wps + (const void *)&gInstructions[ 2874] // VDIVPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5e_pp = @@ -11179,25 +11179,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3166] // VMINSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 3220] // VMINSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3169] // VMINSS Vss,Hss,Wss + (const void *)&gInstructions[ 3223] // VMINSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3161] // VMINPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3215] // VMINPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3164] // VMINPS Vps,Hps,Wps + (const void *)&gInstructions[ 3218] // VMINPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5d_pp = @@ -11214,25 +11214,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3944] // VSUBSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 4023] // VSUBSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3947] // VSUBSS Vss,Hss,Wss + (const void *)&gInstructions[ 4026] // VSUBSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3939] // VSUBPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 4018] // VSUBPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3942] // VSUBPS Vps,Hps,Wps + (const void *)&gInstructions[ 4021] // VSUBPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5c_pp = @@ -11249,19 +11249,19 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2816] // VCVTTPS2DQ Vps,Wps + (const void *)&gInstructions[ 2834] // VCVTTPS2DQ Vps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2768] // VCVTPS2DQ Vps,Wps + (const void *)&gInstructions[ 2776] // VCVTPS2DQ Vps,Wps }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2739] // VCVTDQ2PS Vps,Wps + (const void *)&gInstructions[ 2734] // VCVTDQ2PS Vps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5b_pp = @@ -11278,25 +11278,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2786] // VCVTSD2SS Vss,Hx,Wsd + (const void *)&gInstructions[ 2796] // VCVTSD2SS Vss,Hx,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2799] // VCVTSS2SD Vsd,Hx,Wss + (const void *)&gInstructions[ 2809] // VCVTSS2SD Vsd,Hx,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2752] // VCVTPD2PS Vdq,Wqq + (const void *)&gInstructions[ 2758] // VCVTPD2PS Vdq,Wqq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2751] // VCVTPD2PS Vdq,Wdq + (const void *)&gInstructions[ 2757] // VCVTPD2PS Vdq,Wdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_01_l = @@ -11313,13 +11313,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2771] // VCVTPS2PD Vqq,Wdq + (const void *)&gInstructions[ 2781] // VCVTPS2PD Vqq,Wdq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2770] // VCVTPS2PD Vpd,Wq + (const void *)&gInstructions[ 2780] // VCVTPS2PD Vpd,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_00_l = @@ -11347,25 +11347,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3294] // VMULSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 3354] // VMULSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3297] // VMULSS Vss,Hss,Wss + (const void *)&gInstructions[ 3357] // VMULSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3289] // VMULPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3349] // VMULPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3292] // VMULPS Vps,Hps,Wps + (const void *)&gInstructions[ 3352] // VMULPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_59_pp = @@ -11382,25 +11382,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_59_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2667] // VADDSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 2652] // VADDSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2670] // VADDSS Vss,Hss,Wss + (const void *)&gInstructions[ 2655] // VADDSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2662] // VADDPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2647] // VADDPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2665] // VADDPS Vps,Hps,Wps + (const void *)&gInstructions[ 2650] // VADDPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_58_pp = @@ -11417,13 +11417,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_58_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3964] // VXORPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 4046] // VXORPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3966] // VXORPS Vps,Hps,Wps + (const void *)&gInstructions[ 4048] // VXORPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_57_pp = @@ -11440,13 +11440,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_57_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3302] // VORPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 3362] // VORPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3304] // VORPS Vps,Hps,Wps + (const void *)&gInstructions[ 3364] // VORPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_56_pp = @@ -11463,13 +11463,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_56_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2686] // VANDNPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2671] // VANDNPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2688] // VANDNPS Vps,Hps,Wps + (const void *)&gInstructions[ 2673] // VANDNPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_55_pp = @@ -11486,13 +11486,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_55_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2690] // VANDPD Vpd,Hpd,Wpd + (const void *)&gInstructions[ 2675] // VANDPD Vpd,Hpd,Wpd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2692] // VANDPS Vps,Hps,Wps + (const void *)&gInstructions[ 2677] // VANDPS Vps,Hps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_54_pp = @@ -11509,13 +11509,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_54_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3864] // VRCPSS Vss,Hss,Wss + (const void *)&gInstructions[ 3937] // VRCPSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3862] // VRCPPS Vps,Wps + (const void *)&gInstructions[ 3935] // VRCPPS Vps,Wps }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_53_pp = @@ -11532,13 +11532,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_53_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3892] // VRSQRTSS Vss,Hss,Wss + (const void *)&gInstructions[ 3968] // VRSQRTSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3890] // VRSQRTPS Vx,Wx + (const void *)&gInstructions[ 3966] // VRSQRTPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_52_pp = @@ -11555,25 +11555,25 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_52_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3933] // VSQRTSD Vsd,Hsd,Wsd + (const void *)&gInstructions[ 4011] // VSQRTSD Vsd,Hsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3936] // VSQRTSS Vss,Hss,Wss + (const void *)&gInstructions[ 4014] // VSQRTSS Vss,Hss,Wss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3928] // VSQRTPD Vx,Wx + (const void *)&gInstructions[ 4006] // VSQRTPD Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3931] // VSQRTPS Vx,Wx + (const void *)&gInstructions[ 4009] // VSQRTPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_51_pp = @@ -11590,7 +11590,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_51_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3227] // VMOVMSKPD Gy,Ux + (const void *)&gInstructions[ 3283] // VMOVMSKPD Gy,Ux }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod = @@ -11605,7 +11605,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3228] // VMOVMSKPS Gy,Ux + (const void *)&gInstructions[ 3284] // VMOVMSKPS Gy,Ux }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod = @@ -11631,7 +11631,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_50_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1298] // KUNPCKBW rKw,vKb,mKb + (const void *)&gInstructions[ 1288] // KUNPCKBW rKw,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w = @@ -11666,13 +11666,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1299] // KUNPCKDQ rKq,vKd,mKd + (const void *)&gInstructions[ 1289] // KUNPCKDQ rKq,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1300] // KUNPCKWD rKd,vKw,mKw + (const void *)&gInstructions[ 1290] // KUNPCKWD rKd,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w = @@ -11718,13 +11718,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_4b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1221] // KADDD rKd,vKd,mKd + (const void *)&gInstructions[ 1211] // KADDD rKd,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1220] // KADDB rKb,vKb,mKb + (const void *)&gInstructions[ 1210] // KADDB rKb,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w = @@ -11759,13 +11759,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1222] // KADDQ rKq,vKq,mKq + (const void *)&gInstructions[ 1212] // KADDQ rKq,vKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1223] // KADDW rKw,vKw,mKw + (const void *)&gInstructions[ 1213] // KADDW rKw,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w = @@ -11811,7 +11811,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_4a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1233] // KMERGE2L1L rKw,mKw + (const void *)&gInstructions[ 1223] // KMERGE2L1L rKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w = @@ -11857,7 +11857,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_49_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1232] // KMERGE2L1H rKw,mKw + (const void *)&gInstructions[ 1222] // KMERGE2L1H rKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w = @@ -11903,13 +11903,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_48_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1306] // KXORD rKd,vKd,mKd + (const void *)&gInstructions[ 1296] // KXORD rKd,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1305] // KXORB rKb,vKb,mKb + (const void *)&gInstructions[ 1295] // KXORB rKb,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w = @@ -11944,13 +11944,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1307] // KXORQ rKq,vKq,mKq + (const void *)&gInstructions[ 1297] // KXORQ rKq,vKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1308] // KXORW rKw,vKw,mKw + (const void *)&gInstructions[ 1298] // KXORW rKw,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w = @@ -11996,13 +11996,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_47_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1302] // KXNORD rKd,vKd,mKd + (const void *)&gInstructions[ 1292] // KXNORD rKd,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1301] // KXNORB rKb,vKb,mKb + (const void *)&gInstructions[ 1291] // KXNORB rKb,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w = @@ -12037,13 +12037,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1303] // KXNORQ rKq,vKq,mKq + (const void *)&gInstructions[ 1293] // KXNORQ rKq,vKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1304] // KXNORW rKw,vKw,mKw + (const void *)&gInstructions[ 1294] // KXNORW rKw,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w = @@ -12089,13 +12089,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_46_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1279] // KORD rKd,vKd,mKd + (const void *)&gInstructions[ 1269] // KORD rKd,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1278] // KORB rKb,vKb,mKb + (const void *)&gInstructions[ 1268] // KORB rKb,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w = @@ -12130,13 +12130,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1280] // KORQ rKq,vKq,mKq + (const void *)&gInstructions[ 1270] // KORQ rKq,vKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1285] // KORW rKw,vKw,mKw + (const void *)&gInstructions[ 1275] // KORW rKw,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w = @@ -12182,13 +12182,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_45_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1275] // KNOTD rKd,mKd + (const void *)&gInstructions[ 1265] // KNOTD rKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1274] // KNOTB rKb,mKb + (const void *)&gInstructions[ 1264] // KNOTB rKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w = @@ -12223,13 +12223,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1276] // KNOTQ rKq,mKq + (const void *)&gInstructions[ 1266] // KNOTQ rKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1277] // KNOTW rKw,mKw + (const void *)&gInstructions[ 1267] // KNOTW rKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w = @@ -12275,13 +12275,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_44_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1227] // KANDND rKd,vKd,mKd + (const void *)&gInstructions[ 1217] // KANDND rKd,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1226] // KANDNB rKb,vKb,mKb + (const void *)&gInstructions[ 1216] // KANDNB rKb,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w = @@ -12316,13 +12316,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1228] // KANDNQ rKq,vKq,mKq + (const void *)&gInstructions[ 1218] // KANDNQ rKq,vKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1229] // KANDNW rKw,vKw,mKw + (const void *)&gInstructions[ 1219] // KANDNW rKw,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w = @@ -12368,13 +12368,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_42_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1225] // KANDD rKd,vKd,mKd + (const void *)&gInstructions[ 1215] // KANDD rKd,vKd,mKd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1224] // KANDB rKb,vKb,mKb + (const void *)&gInstructions[ 1214] // KANDB rKb,vKb,mKb }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w = @@ -12409,13 +12409,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1230] // KANDQ rKq,vKq,mKq + (const void *)&gInstructions[ 1220] // KANDQ rKq,vKq,mKq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1231] // KANDW rKw,vKw,mKw + (const void *)&gInstructions[ 1221] // KANDW rKw,vKw,mKw }; const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w = @@ -12461,13 +12461,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_41_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2728] // VCOMISD Vsd,Wsd + (const void *)&gInstructions[ 2714] // VCOMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2731] // VCOMISS Vss,Wss + (const void *)&gInstructions[ 2717] // VCOMISS Vss,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2f_pp = @@ -12484,13 +12484,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2f_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3951] // VUCOMISD Vsd,Wsd + (const void *)&gInstructions[ 4030] // VUCOMISD Vsd,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3954] // VUCOMISS Vss,Wss + (const void *)&gInstructions[ 4033] // VUCOMISS Vss,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2e_pp = @@ -12507,13 +12507,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2e_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2784] // VCVTSD2SI Gy,Wsd + (const void *)&gInstructions[ 2794] // VCVTSD2SI Gy,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2802] // VCVTSS2SI Gy,Wss + (const void *)&gInstructions[ 2812] // VCVTSS2SI Gy,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2d_pp = @@ -12530,13 +12530,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2d_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2821] // VCVTTSD2SI Gy,Wsd + (const void *)&gInstructions[ 2845] // VCVTTSD2SI Gy,Wsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2826] // VCVTTSS2SI Gy,Wss + (const void *)&gInstructions[ 2852] // VCVTTSS2SI Gy,Wss }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2c_pp = @@ -12553,7 +12553,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2c_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3234] // VMOVNTPD Mx,Vx + (const void *)&gInstructions[ 3290] // VMOVNTPD Mx,Vx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = @@ -12568,7 +12568,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3236] // VMOVNTPS Mx,Vx + (const void *)&gInstructions[ 3292] // VMOVNTPS Mx,Vx }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod = @@ -12594,13 +12594,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2b_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2794] // VCVTSI2SD Vsd,Hsd,Ey + (const void *)&gInstructions[ 2804] // VCVTSI2SD Vsd,Hsd,Ey }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2797] // VCVTSI2SS Vss,Hss,Ey + (const void *)&gInstructions[ 2807] // VCVTSI2SS Vss,Hss,Ey }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2a_pp = @@ -12617,13 +12617,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2a_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3177] // VMOVAPD Wx,Vx + (const void *)&gInstructions[ 3231] // VMOVAPD Wx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3181] // VMOVAPS Wx,Vx + (const void *)&gInstructions[ 3235] // VMOVAPS Wx,Vx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_29_pp = @@ -12640,13 +12640,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_29_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3176] // VMOVAPD Vx,Wx + (const void *)&gInstructions[ 3230] // VMOVAPD Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3180] // VMOVAPS Vx,Wx + (const void *)&gInstructions[ 3234] // VMOVAPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_28_pp = @@ -12663,7 +12663,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_28_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3212] // VMOVHPD Mq,Vdq + (const void *)&gInstructions[ 3268] // VMOVHPD Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l = @@ -12689,7 +12689,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3216] // VMOVHPS Mq,Vdq + (const void *)&gInstructions[ 3272] // VMOVHPS Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l = @@ -12726,13 +12726,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_17_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3258] // VMOVSHDUP Vx,Wx + (const void *)&gInstructions[ 3314] // VMOVSHDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3211] // VMOVHPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3267] // VMOVHPD Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l = @@ -12758,7 +12758,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3218] // VMOVLHPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3274] // VMOVLHPS Vdq,Hdq,Udq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = @@ -12775,7 +12775,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3215] // VMOVHPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3271] // VMOVHPS Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l = @@ -12812,13 +12812,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_16_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3956] // VUNPCKHPD Vx,Hx,Wx + (const void *)&gInstructions[ 4038] // VUNPCKHPD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3958] // VUNPCKHPS Vx,Hx,Wx + (const void *)&gInstructions[ 4040] // VUNPCKHPS Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_15_pp = @@ -12835,13 +12835,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_15_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3960] // VUNPCKLPD Vx,Hx,Wx + (const void *)&gInstructions[ 4042] // VUNPCKLPD Vx,Hx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3962] // VUNPCKLPS Vx,Hx,Wx + (const void *)&gInstructions[ 4044] // VUNPCKLPS Vx,Hx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_14_pp = @@ -12858,7 +12858,7 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_14_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3222] // VMOVLPD Mq,Vdq + (const void *)&gInstructions[ 3278] // VMOVLPD Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l = @@ -12884,7 +12884,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3226] // VMOVLPS Mq,Vdq + (const void *)&gInstructions[ 3282] // VMOVLPS Mq,Vdq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l = @@ -12921,13 +12921,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_13_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3190] // VMOVDDUP Vqq,Wqq + (const void *)&gInstructions[ 3246] // VMOVDDUP Vqq,Wqq }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3189] // VMOVDDUP Vdq,Wq + (const void *)&gInstructions[ 3245] // VMOVDDUP Vdq,Wq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_03_l = @@ -12944,13 +12944,13 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_03_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3260] // VMOVSLDUP Vx,Wx + (const void *)&gInstructions[ 3316] // VMOVSLDUP Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3221] // VMOVLPD Vdq,Hdq,Mq + (const void *)&gInstructions[ 3277] // VMOVLPD Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l = @@ -12976,7 +12976,7 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3208] // VMOVHLPS Vdq,Hdq,Udq + (const void *)&gInstructions[ 3264] // VMOVHLPS Vdq,Hdq,Udq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = @@ -12993,7 +12993,7 @@ const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3225] // VMOVLPS Vdq,Hdq,Mq + (const void *)&gInstructions[ 3281] // VMOVLPS Vdq,Hdq,Mq }; const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l = @@ -13030,13 +13030,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_12_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3251] // VMOVSD Usd,Hsd,Vsd + (const void *)&gInstructions[ 3307] // VMOVSD Usd,Hsd,Vsd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3252] // VMOVSD Mq,Vsd + (const void *)&gInstructions[ 3308] // VMOVSD Mq,Vsd }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod = @@ -13051,13 +13051,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3267] // VMOVSS Uss,Hss,Vss + (const void *)&gInstructions[ 3323] // VMOVSS Uss,Hss,Vss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3268] // VMOVSS Md,Vss + (const void *)&gInstructions[ 3324] // VMOVSS Md,Vss }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod = @@ -13072,13 +13072,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3272] // VMOVUPD Wx,Vx + (const void *)&gInstructions[ 3328] // VMOVUPD Wx,Vx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3276] // VMOVUPS Wx,Vx + (const void *)&gInstructions[ 3332] // VMOVUPS Wx,Vx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_11_pp = @@ -13095,13 +13095,13 @@ const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_11_pp = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3249] // VMOVSD Vdq,Hdq,Usd + (const void *)&gInstructions[ 3305] // VMOVSD Vdq,Hdq,Usd }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3250] // VMOVSD Vdq,Mq + (const void *)&gInstructions[ 3306] // VMOVSD Vdq,Mq }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod = @@ -13116,13 +13116,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3265] // VMOVSS Vdq,Hdq,Uss + (const void *)&gInstructions[ 3321] // VMOVSS Vdq,Hdq,Uss }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3266] // VMOVSS Vdq,Md + (const void *)&gInstructions[ 3322] // VMOVSS Vdq,Md }; const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod = @@ -13137,13 +13137,13 @@ const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod = const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3271] // VMOVUPD Vx,Wx + (const void *)&gInstructions[ 3327] // VMOVUPD Vx,Wx }; const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3275] // VMOVUPS Vx,Wx + (const void *)&gInstructions[ 3331] // VMOVUPS Vx,Wx }; const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_10_pp = diff --git a/bddisasm/include/bdx86_table_xop.h b/bddisasm/include/bdx86_table_xop.h index b19d0a8..ba3e011 100644 --- a/bddisasm/include/bdx86_table_xop.h +++ b/bddisasm/include/bdx86_table_xop.h @@ -13,13 +13,13 @@ const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1347] // LWPVAL By,Ed,Id + (const void *)&gInstructions[ 1337] // LWPVAL By,Ed,Id }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1346] // LWPINS By,Ed,Id + (const void *)&gInstructions[ 1336] // LWPINS By,Ed,Id }; const ND_TABLE_MODRM_REG gXopMap_mmmmm_0a_opcode_12_modrmreg = @@ -40,7 +40,7 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_0a_opcode_12_modrmreg = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_10_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 197] // BEXTR Gy,Ey,Id + (const void *)&gInstructions[ 189] // BEXTR Gy,Ey,Id }; const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode = @@ -309,103 +309,103 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3527] // VPHSUBDQ Vdq,Wdq + (const void *)&gInstructions[ 3599] // VPHSUBDQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3530] // VPHSUBWD Vdq,Wdq + (const void *)&gInstructions[ 3602] // VPHSUBWD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3525] // VPHSUBBW Vdq,Wdq + (const void *)&gInstructions[ 3597] // VPHSUBBW Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_db_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3518] // VPHADDUDQ Vdq,Wdq + (const void *)&gInstructions[ 3590] // VPHADDUDQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3520] // VPHADDUWQ Vdq,Wdq + (const void *)&gInstructions[ 3592] // VPHADDUWQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3519] // VPHADDUWD Vdq,Wdq + (const void *)&gInstructions[ 3591] // VPHADDUWD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3516] // VPHADDUBQ Vdq,Wdq + (const void *)&gInstructions[ 3588] // VPHADDUBQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3515] // VPHADDUBD Vdq,Wdq + (const void *)&gInstructions[ 3587] // VPHADDUBD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3517] // VPHADDUBW Vdq,Wdq + (const void *)&gInstructions[ 3589] // VPHADDUBW Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_cb_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3513] // VPHADDDQ Vdq,Wdq + (const void *)&gInstructions[ 3585] // VPHADDDQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c7_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3523] // VPHADDWQ Vdq,Wdq + (const void *)&gInstructions[ 3595] // VPHADDWQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3522] // VPHADDWD Vdq,Wdq + (const void *)&gInstructions[ 3594] // VPHADDWD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3510] // VPHADDBQ Vdq,Wdq + (const void *)&gInstructions[ 3582] // VPHADDBQ Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3509] // VPHADDBD Vdq,Wdq + (const void *)&gInstructions[ 3581] // VPHADDBD Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3511] // VPHADDBW Vdq,Wdq + (const void *)&gInstructions[ 3583] // VPHADDBW Vdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3716] // VPSHAQ Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3788] // VPSHAQ Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3715] // VPSHAQ Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3787] // VPSHAQ Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w = @@ -420,13 +420,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3714] // VPSHAD Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3786] // VPSHAD Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3713] // VPSHAD Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3785] // VPSHAD Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w = @@ -441,13 +441,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3718] // VPSHAW Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3790] // VPSHAW Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3717] // VPSHAW Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3789] // VPSHAW Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w = @@ -462,13 +462,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3712] // VPSHAB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3784] // VPSHAB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3711] // VPSHAB Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3783] // VPSHAB Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w = @@ -483,13 +483,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3731] // VPSHLQ Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3803] // VPSHLQ Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3730] // VPSHLQ Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3802] // VPSHLQ Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w = @@ -504,13 +504,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3722] // VPSHLB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3794] // VPSHLB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3723] // VPSHLD Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3795] // VPSHLD Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w = @@ -525,13 +525,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3721] // VPSHLB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3793] // VPSHLB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3732] // VPSHLW Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3804] // VPSHLW Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w = @@ -546,13 +546,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3720] // VPSHLB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3792] // VPSHLB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3719] // VPSHLB Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3791] // VPSHLB Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w = @@ -567,13 +567,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3701] // VPROTQ Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3773] // VPROTQ Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3700] // VPROTQ Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3772] // VPROTQ Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w = @@ -588,13 +588,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3698] // VPROTD Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3770] // VPROTD Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3697] // VPROTD Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3769] // VPROTD Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w = @@ -609,13 +609,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3704] // VPROTW Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3776] // VPROTW Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3703] // VPROTW Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3775] // VPROTW Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w = @@ -630,13 +630,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3695] // VPROTB Vdq,Hdq,Wdq + (const void *)&gInstructions[ 3767] // VPROTB Vdq,Hdq,Wdq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3694] // VPROTB Vdq,Wdq,Hdq + (const void *)&gInstructions[ 3766] // VPROTB Vdq,Wdq,Hdq }; const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w = @@ -651,31 +651,31 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_83_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3084] // VFRCZSD Vdq,Wsd + (const void *)&gInstructions[ 3127] // VFRCZSD Vdq,Wsd }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_82_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3085] // VFRCZSS Vdq,Wss + (const void *)&gInstructions[ 3128] // VFRCZSS Vdq,Wss }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_81_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3082] // VFRCZPD Vx,Wx + (const void *)&gInstructions[ 3125] // VFRCZPD Vx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_80_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3083] // VFRCZPS Vx,Wx + (const void *)&gInstructions[ 3126] // VFRCZPS Vx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2512] // SLWPCB Ry + (const void *)&gInstructions[ 2496] // SLWPCB Ry }; const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod = @@ -690,7 +690,7 @@ const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 1328] // LLWPCB Ry + (const void *)&gInstructions[ 1318] // LLWPCB Ry }; const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod = @@ -720,13 +720,13 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_12_modrmreg = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 199] // BLCI By,Ey + (const void *)&gInstructions[ 191] // BLCI By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 201] // BLCMSK By,Ey + (const void *)&gInstructions[ 193] // BLCMSK By,Ey }; const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg = @@ -747,43 +747,43 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2602] // T1MSKC By,Ey + (const void *)&gInstructions[ 2586] // T1MSKC By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 211] // BLSIC By,Ey + (const void *)&gInstructions[ 203] // BLSIC By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 200] // BLCIC By,Ey + (const void *)&gInstructions[ 192] // BLCIC By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 2636] // TZMSK By,Ey + (const void *)&gInstructions[ 2620] // TZMSK By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 202] // BLCS By,Ey + (const void *)&gInstructions[ 194] // BLCS By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_02_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 207] // BLSFILL By,Ey + (const void *)&gInstructions[ 199] // BLSFILL By,Ey }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 198] // BLCFILL By,Ey + (const void *)&gInstructions[ 190] // BLCFILL By,Ey }; const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_01_modrmreg = @@ -1067,97 +1067,97 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_09_opcode = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ef_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3414] // VPCOMUQ Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3474] // VPCOMUQ Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ee_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3413] // VPCOMUD Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3473] // VPCOMUD Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ed_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3415] // VPCOMUW Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3475] // VPCOMUW Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ec_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3412] // VPCOMUB Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3472] // VPCOMUB Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cf_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3411] // VPCOMQ Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3471] // VPCOMQ Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ce_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3406] // VPCOMD Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3466] // VPCOMD Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cd_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3416] // VPCOMW Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3476] // VPCOMW Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cc_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3405] // VPCOMB Vdq,Hdq,Wdq,Ib + (const void *)&gInstructions[ 3465] // VPCOMB Vdq,Hdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c3_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3699] // VPROTQ Vdq,Wdq,Ib + (const void *)&gInstructions[ 3771] // VPROTQ Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c2_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3696] // VPROTD Vdq,Wdq,Ib + (const void *)&gInstructions[ 3768] // VPROTD Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c1_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3702] // VPROTW Vdq,Wdq,Ib + (const void *)&gInstructions[ 3774] // VPROTW Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c0_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3693] // VPROTB Vdq,Wdq,Ib + (const void *)&gInstructions[ 3765] // VPROTB Vdq,Wdq,Ib }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_b6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3556] // VPMADCSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3628] // VPMADCSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a6_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3555] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3627] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3684] // VPPERM Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3756] // VPPERM Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3683] // VPPERM Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3755] // VPPERM Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w = @@ -1172,13 +1172,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_01_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3376] // VPCMOV Vx,Hx,Lx,Wx + (const void *)&gInstructions[ 3436] // VPCMOV Vx,Hx,Lx,Wx }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_00_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3375] // VPCMOV Vx,Hx,Wx,Lx + (const void *)&gInstructions[ 3435] // VPCMOV Vx,Hx,Wx,Lx }; const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w = @@ -1193,61 +1193,61 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w = const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3546] // VPMACSDQH Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3618] // VPMACSDQH Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3545] // VPMACSDD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3617] // VPMACSDD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_97_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3547] // VPMACSDQL Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3619] // VPMACSDQL Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_96_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3553] // VPMACSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3625] // VPMACSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_95_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3554] // VPMACSWW Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3626] // VPMACSWW Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8f_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3549] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3621] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8e_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3548] // VPMACSSDD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3620] // VPMACSSDD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_87_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3550] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3622] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_86_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3551] // VPMACSSWD Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3623] // VPMACSSWD Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_85_leaf = { ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[ 3552] // VPMACSSWW Vdq,Hdq,Wdq,Ldq + (const void *)&gInstructions[ 3624] // VPMACSSWW Vdq,Hdq,Wdq,Ldq }; const ND_TABLE_OPCODE gXopMap_mmmmm_08_opcode = diff --git a/bddisasm/include/bdx86_tabledefs.h b/bddisasm/include/bdx86_tabledefs.h index d4c1d4c..c1612ab 100644 --- a/bddisasm/include/bdx86_tabledefs.h +++ b/bddisasm/include/bdx86_tabledefs.h @@ -459,6 +459,7 @@ typedef enum _ND_OPERAND_TYPE_SPEC ND_OPT_pCX, // [rCX] ND_OPT_pBXAL, // [rBX + AL] ND_OPT_pDI, // [rDI] + ND_OPT_pBP, // [rBP] ND_OPT_SHS, // Shadow stack. ND_OPT_SHSP, // Shadow stack pointed by the SSP. ND_OPT_SHS0, // Shadow stack pointed by the SSP. diff --git a/bdshemu/bdshemu.c b/bdshemu/bdshemu.c index 6fa7862..a26852f 100644 --- a/bdshemu/bdshemu.c +++ b/bdshemu/bdshemu.c @@ -63,9 +63,6 @@ shemu_memcpy( ND_SIZET Size ) { - void *start = Dest; - ND_UINT32 index = 0; - if (ND_NULL == Dest) { return ND_NULL; @@ -76,14 +73,12 @@ shemu_memcpy( return ND_NULL; } - while (Size--) + for (ND_SIZET index = 0; index < Size; index++) { - *(char *)Dest = *((char *)Source + index); - Dest = (char *)Dest + 1; - index++; + ((char *)Dest)[index] = ((const char *)Source)[index]; } - return start; + return Dest; } @@ -206,7 +201,8 @@ ShemuIsShellcodePtr( ) { return (Gla >= Context->ShellcodeBase && Gla < Context->ShellcodeBase + Context->ShellcodeSize && - Gla + Size > Context->ShellcodeBase && Gla + Size <= Context->ShellcodeBase + Context->ShellcodeSize); + Gla + Size > Context->ShellcodeBase && Gla + Size <= Context->ShellcodeBase + Context->ShellcodeSize && + Size <= Context->ShellcodeSize); } @@ -221,7 +217,8 @@ ShemuIsStackPtr( ) { return (Gla >= Context->StackBase && Gla < Context->StackBase + Context->StackSize && - Gla + Size > Context->StackBase && Gla + Size <= Context->StackBase + Context->StackSize); + Gla + Size > Context->StackBase && Gla + Size <= Context->StackBase + Context->StackSize && + Size <= Context->StackSize); } @@ -236,7 +233,8 @@ ShemuIsIcachePtr( ) { return (Gla >= Context->Icache.Address && Gla < Context->Icache.Address + Context->Icache.Size && - Gla + Size > Context->Icache.Address && Gla + Size <= Context->Icache.Address + Context->Icache.Size); + Gla + Size > Context->Icache.Address && Gla + Size <= Context->Icache.Address + Context->Icache.Size && + Size <= Context->Icache.Size); } diff --git a/bdshemu/bdshemu_x86.c b/bdshemu/bdshemu_x86.c index 28d4df2..ee18b94 100644 --- a/bdshemu/bdshemu_x86.c +++ b/bdshemu/bdshemu_x86.c @@ -2240,7 +2240,7 @@ ShemuX86Emulate( } else { - ND_SINT64 val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]); + ND_SINT64 val = (ND_SINT64)ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]); val = val >> src.Value.Qwords[0]; res.Value.Qwords[0] = (ND_UINT64)val; } @@ -2761,7 +2761,7 @@ check_far_branch: } else { - res.Value.Words[0] = (ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0]; + res.Value.Words[0] = (ND_UINT16)((ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0]); } } else if (dst.Size == 2) @@ -2772,7 +2772,7 @@ check_far_branch: } else { - res.Value.Dwords[0] = (ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0]; + res.Value.Dwords[0] = (ND_UINT32)((ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0]); } } else if (dst.Size == 4) @@ -2783,7 +2783,7 @@ check_far_branch: } else { - res.Value.Qwords[0] = (ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0]; + res.Value.Qwords[0] = (ND_UINT64)((ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0]); } } else @@ -2916,8 +2916,8 @@ check_far_branch: break; } - res.Value.Bytes[0] = (ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]); - res.Value.Bytes[1] = (ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]); + res.Value.Bytes[0] = (ND_UINT8)(ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]); + res.Value.Bytes[1] = (ND_UINT8)(ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]); } // Result in AX (AL - quotient, AH - reminder). @@ -2949,8 +2949,8 @@ check_far_branch: break; } - res.Value.Words[0] = (ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]); - res.Value.Words[1] = (ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]); + res.Value.Words[0] = (ND_UINT16)(ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]); + res.Value.Words[1] = (ND_UINT16)(ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]); } ShemuX86SetGprValue(Context, NDR_DX, 2, res.Value.Words[1], ND_FALSE); @@ -2982,8 +2982,8 @@ check_far_branch: break; } - res.Value.Dwords[0] = (ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]); - res.Value.Dwords[1] = (ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]); + res.Value.Dwords[0] = (ND_UINT32)(ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]); + res.Value.Dwords[1] = (ND_UINT32)(ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]); } ShemuX86SetGprValue(Context, NDR_EDX, 4, res.Value.Dwords[1], ND_FALSE); diff --git a/bindings/pybddisasm/setup.py b/bindings/pybddisasm/setup.py index 0b0497d..83ac395 100644 --- a/bindings/pybddisasm/setup.py +++ b/bindings/pybddisasm/setup.py @@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution from codecs import open VERSION = (0, 3, 0) -LIBRARY_VERSION = (2, 1, 5) +LIBRARY_VERSION = (2, 2, 0) DIR_INCLUDE = '../../inc' here = os.path.abspath(os.path.dirname(__file__)) diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c index b480f5f..0e7f9d0 100644 --- a/disasmtool/disasmtool.c +++ b/disasmtool/disasmtool.c @@ -192,6 +192,7 @@ set_to_string( case ND_SET_AMXTILE: return "AMX-TILE"; case ND_SET_AMXCOMPLEX: return "AMX-COMPLEX"; case ND_SET_AVX: return "AVX"; + case ND_SET_AVX102: return "AVX10_2"; case ND_SET_AVX2: return "AVX2"; case ND_SET_AVX2GATHER: return "AVX2GATHER"; case ND_SET_AVX5124FMAPS: return "AVX5124FMAPS"; @@ -332,6 +333,13 @@ category_to_string( case ND_CAT_AMX: return "AMX"; case ND_CAT_APX: return "APX"; case ND_CAT_AVX: return "AVX"; + case ND_CAT_AVX10BF16: return "AVX10BF16"; + case ND_CAT_AVX10CMPSFP: return "AVX10CMPSFP"; + case ND_CAT_AVX10CONVERT: return "AVX10CONVERT"; + case ND_CAT_AVX10INT: return "AVX10INT"; + case ND_CAT_AVX10MINMAX: return "AVX10MINMAX"; + case ND_CAT_AVX10PARTCOPY: return "AVX10PARTCOPY"; + case ND_CAT_AVX10SCONVERT: return "AVX10SCONVERT"; case ND_CAT_AVX2: return "AVX2"; case ND_CAT_AVX2GATHER: return "AVX2GATHER"; case ND_CAT_AVX512: return "AVX512"; diff --git a/inc/bddisasm_status.h b/inc/bddisasm_status.h index d8e8a64..ecc18f2 100644 --- a/inc/bddisasm_status.h +++ b/inc/bddisasm_status.h @@ -49,6 +49,7 @@ typedef ND_UINT32 NDSTATUS; #define ND_STATUS_INVALID_TILE_REGS 0x80000043 // Tile registers are not unique. #define ND_STATUS_INVALID_DEST_REGS 0x80000044 // Destination register is not unique (used as src). #define ND_STATUS_INVALID_EVEX_BYTE3 0x80000045 // EVEX payload byte 3 is invalid. +#define ND_STATUS_BAD_EVEX_U 0x80000046 // EVEX.U field is invalid. // Not encoding specific. diff --git a/inc/bddisasm_version.h b/inc/bddisasm_version.h index 2a13a2e..4792f5f 100644 --- a/inc/bddisasm_version.h +++ b/inc/bddisasm_version.h @@ -6,8 +6,8 @@ #define BDDISASM_VERSION_H #define DISASM_VERSION_MAJOR 2 -#define DISASM_VERSION_MINOR 1 -#define DISASM_VERSION_REVISION 5 +#define DISASM_VERSION_MINOR 2 +#define DISASM_VERSION_REVISION 0 #define SHEMU_VERSION_MAJOR DISASM_VERSION_MAJOR #define SHEMU_VERSION_MINOR DISASM_VERSION_MINOR diff --git a/inc/bdx86_constants.h b/inc/bdx86_constants.h index 87424a4..0ccea56 100644 --- a/inc/bdx86_constants.h +++ b/inc/bdx86_constants.h @@ -646,6 +646,7 @@ typedef enum _ND_INS_CLASS ND_INS_RETN, ND_INS_RMPADJUST, ND_INS_RMPQUERY, + ND_INS_RMPREAD, ND_INS_RMPUPDATE, ND_INS_ROL, ND_INS_ROR, @@ -760,6 +761,7 @@ typedef enum _ND_INS_CLASS ND_INS_V4FMADDSS, ND_INS_V4FNMADDPS, ND_INS_V4FNMADDSS, + ND_INS_VADDNEPBF16, ND_INS_VADDPD, ND_INS_VADDPH, ND_INS_VADDPS, @@ -802,6 +804,7 @@ typedef enum _ND_INS_CLASS ND_INS_VBROADCASTI64X4, ND_INS_VBROADCASTSD, ND_INS_VBROADCASTSS, + ND_INS_VCMPPBF16, ND_INS_VCMPPD, ND_INS_VCMPPH, ND_INS_VCMPPS, @@ -813,14 +816,34 @@ typedef enum _ND_INS_CLASS ND_INS_VCOMISS, ND_INS_VCOMPRESSPD, ND_INS_VCOMPRESSPS, + ND_INS_VCOMSBF16, + ND_INS_VCOMXSD, + ND_INS_VCOMXSH, + ND_INS_VCOMXSS, + ND_INS_VCVT2PS2PHX, + ND_INS_VCVTBIASPH2BF8, + ND_INS_VCVTBIASPH2BF8S, + ND_INS_VCVTBIASPH2HF8, + ND_INS_VCVTBIASPH2HF8S, ND_INS_VCVTDQ2PD, ND_INS_VCVTDQ2PH, ND_INS_VCVTDQ2PS, + ND_INS_VCVTHF82PH, + ND_INS_VCVTNE2PH2BF8, + ND_INS_VCVTNE2PH2BF8S, + ND_INS_VCVTNE2PH2HF8, + ND_INS_VCVTNE2PH2HF8S, ND_INS_VCVTNE2PS2BF16, + ND_INS_VCVTNEBF162IBS, + ND_INS_VCVTNEBF162IUBS, ND_INS_VCVTNEEBF162PS, ND_INS_VCVTNEEPH2PS, ND_INS_VCVTNEOBF162PS, ND_INS_VCVTNEOPH2PS, + ND_INS_VCVTNEPH2BF8, + ND_INS_VCVTNEPH2BF8S, + ND_INS_VCVTNEPH2HF8, + ND_INS_VCVTNEPH2HF8S, ND_INS_VCVTNEPS2BF16, ND_INS_VCVTPD2DQ, ND_INS_VCVTPD2PH, @@ -829,6 +852,8 @@ typedef enum _ND_INS_CLASS ND_INS_VCVTPD2UDQ, ND_INS_VCVTPD2UQQ, ND_INS_VCVTPH2DQ, + ND_INS_VCVTPH2IBS, + ND_INS_VCVTPH2IUBS, ND_INS_VCVTPH2PD, ND_INS_VCVTPH2PS, ND_INS_VCVTPH2PSX, @@ -838,6 +863,8 @@ typedef enum _ND_INS_CLASS ND_INS_VCVTPH2UW, ND_INS_VCVTPH2W, ND_INS_VCVTPS2DQ, + ND_INS_VCVTPS2IBS, + ND_INS_VCVTPS2IUBS, ND_INS_VCVTPS2PD, ND_INS_VCVTPS2PH, ND_INS_VCVTPS2PHX, @@ -862,26 +889,44 @@ typedef enum _ND_INS_CLASS ND_INS_VCVTSS2SH, ND_INS_VCVTSS2SI, ND_INS_VCVTSS2USI, + ND_INS_VCVTTNEBF162IBS, + ND_INS_VCVTTNEBF162IUBS, ND_INS_VCVTTPD2DQ, + ND_INS_VCVTTPD2DQS, ND_INS_VCVTTPD2QQ, + ND_INS_VCVTTPD2QQS, ND_INS_VCVTTPD2UDQ, + ND_INS_VCVTTPD2UDQS, ND_INS_VCVTTPD2UQQ, + ND_INS_VCVTTPD2UQQS, ND_INS_VCVTTPH2DQ, + ND_INS_VCVTTPH2IBS, + ND_INS_VCVTTPH2IUBS, ND_INS_VCVTTPH2QQ, ND_INS_VCVTTPH2UDQ, ND_INS_VCVTTPH2UQQ, ND_INS_VCVTTPH2UW, ND_INS_VCVTTPH2W, ND_INS_VCVTTPS2DQ, + ND_INS_VCVTTPS2DQS, + ND_INS_VCVTTPS2IBS, + ND_INS_VCVTTPS2IUBS, ND_INS_VCVTTPS2QQ, + ND_INS_VCVTTPS2QQS, ND_INS_VCVTTPS2UDQ, + ND_INS_VCVTTPS2UDQS, ND_INS_VCVTTPS2UQQ, + ND_INS_VCVTTPS2UQQS, ND_INS_VCVTTSD2SI, + ND_INS_VCVTTSD2SIS, ND_INS_VCVTTSD2USI, + ND_INS_VCVTTSD2USIS, ND_INS_VCVTTSH2SI, ND_INS_VCVTTSH2USI, ND_INS_VCVTTSS2SI, + ND_INS_VCVTTSS2SIS, ND_INS_VCVTTSS2USI, + ND_INS_VCVTTSS2USIS, ND_INS_VCVTUDQ2PD, ND_INS_VCVTUDQ2PH, ND_INS_VCVTUDQ2PS, @@ -894,6 +939,7 @@ typedef enum _ND_INS_CLASS ND_INS_VCVTUW2PH, ND_INS_VCVTW2PH, ND_INS_VDBPSADBW, + ND_INS_VDIVNEPBF16, ND_INS_VDIVPD, ND_INS_VDIVPH, ND_INS_VDIVPS, @@ -902,6 +948,7 @@ typedef enum _ND_INS_CLASS ND_INS_VDIVSS, ND_INS_VDPBF16PS, ND_INS_VDPPD, + ND_INS_VDPPHPS, ND_INS_VDPPS, ND_INS_VERR, ND_INS_VERW, @@ -928,18 +975,21 @@ typedef enum _ND_INS_CLASS ND_INS_VFIXUPIMMPS, ND_INS_VFIXUPIMMSD, ND_INS_VFIXUPIMMSS, + ND_INS_VFMADD132NEPBF16, ND_INS_VFMADD132PD, ND_INS_VFMADD132PH, ND_INS_VFMADD132PS, ND_INS_VFMADD132SD, ND_INS_VFMADD132SH, ND_INS_VFMADD132SS, + ND_INS_VFMADD213NEPBF16, ND_INS_VFMADD213PD, ND_INS_VFMADD213PH, ND_INS_VFMADD213PS, ND_INS_VFMADD213SD, ND_INS_VFMADD213SH, ND_INS_VFMADD213SS, + ND_INS_VFMADD231NEPBF16, ND_INS_VFMADD231PD, ND_INS_VFMADD231PH, ND_INS_VFMADD231PS, @@ -963,18 +1013,21 @@ typedef enum _ND_INS_CLASS ND_INS_VFMADDSUB231PS, ND_INS_VFMADDSUBPD, ND_INS_VFMADDSUBPS, + ND_INS_VFMSUB132NEPBF16, ND_INS_VFMSUB132PD, ND_INS_VFMSUB132PH, ND_INS_VFMSUB132PS, ND_INS_VFMSUB132SD, ND_INS_VFMSUB132SH, ND_INS_VFMSUB132SS, + ND_INS_VFMSUB213NEPBF16, ND_INS_VFMSUB213PD, ND_INS_VFMSUB213PH, ND_INS_VFMSUB213PS, ND_INS_VFMSUB213SD, ND_INS_VFMSUB213SH, ND_INS_VFMSUB213SS, + ND_INS_VFMSUB231NEPBF16, ND_INS_VFMSUB231PD, ND_INS_VFMSUB231PH, ND_INS_VFMSUB231PS, @@ -998,18 +1051,21 @@ typedef enum _ND_INS_CLASS ND_INS_VFMSUBSS, ND_INS_VFMULCPH, ND_INS_VFMULCSH, + ND_INS_VFNMADD132NEPBF16, ND_INS_VFNMADD132PD, ND_INS_VFNMADD132PH, ND_INS_VFNMADD132PS, ND_INS_VFNMADD132SD, ND_INS_VFNMADD132SH, ND_INS_VFNMADD132SS, + ND_INS_VFNMADD213NEPBF16, ND_INS_VFNMADD213PD, ND_INS_VFNMADD213PH, ND_INS_VFNMADD213PS, ND_INS_VFNMADD213SD, ND_INS_VFNMADD213SH, ND_INS_VFNMADD213SS, + ND_INS_VFNMADD231NEPBF16, ND_INS_VFNMADD231PD, ND_INS_VFNMADD231PH, ND_INS_VFNMADD231PS, @@ -1020,18 +1076,21 @@ typedef enum _ND_INS_CLASS ND_INS_VFNMADDPS, ND_INS_VFNMADDSD, ND_INS_VFNMADDSS, + ND_INS_VFNMSUB132NEPBF16, ND_INS_VFNMSUB132PD, ND_INS_VFNMSUB132PH, ND_INS_VFNMSUB132PS, ND_INS_VFNMSUB132SD, ND_INS_VFNMSUB132SH, ND_INS_VFNMSUB132SS, + ND_INS_VFNMSUB213NEPBF16, ND_INS_VFNMSUB213PD, ND_INS_VFNMSUB213PH, ND_INS_VFNMSUB213PS, ND_INS_VFNMSUB213SD, ND_INS_VFNMSUB213SH, ND_INS_VFNMSUB213SS, + ND_INS_VFNMSUB231NEPBF16, ND_INS_VFNMSUB231PD, ND_INS_VFNMSUB231PH, ND_INS_VFNMSUB231PS, @@ -1042,6 +1101,7 @@ typedef enum _ND_INS_CLASS ND_INS_VFNMSUBPS, ND_INS_VFNMSUBSD, ND_INS_VFNMSUBSS, + ND_INS_VFPCLASSPBF16, ND_INS_VFPCLASSPD, ND_INS_VFPCLASSPH, ND_INS_VFPCLASSPS, @@ -1064,12 +1124,14 @@ typedef enum _ND_INS_CLASS ND_INS_VGATHERPF1QPS, ND_INS_VGATHERQPD, ND_INS_VGATHERQPS, + ND_INS_VGETEXPPBF16, ND_INS_VGETEXPPD, ND_INS_VGETEXPPH, ND_INS_VGETEXPPS, ND_INS_VGETEXPSD, ND_INS_VGETEXPSH, ND_INS_VGETEXPSS, + ND_INS_VGETMANTPBF16, ND_INS_VGETMANTPD, ND_INS_VGETMANTPH, ND_INS_VGETMANTPS, @@ -1099,6 +1161,7 @@ typedef enum _ND_INS_CLASS ND_INS_VMASKMOVDQU, ND_INS_VMASKMOVPD, ND_INS_VMASKMOVPS, + ND_INS_VMAXPBF16, ND_INS_VMAXPD, ND_INS_VMAXPH, ND_INS_VMAXPS, @@ -1109,6 +1172,14 @@ typedef enum _ND_INS_CLASS ND_INS_VMCLEAR, ND_INS_VMFUNC, ND_INS_VMGEXIT, + ND_INS_VMINMAXNEPBF16, + ND_INS_VMINMAXPD, + ND_INS_VMINMAXPH, + ND_INS_VMINMAXPS, + ND_INS_VMINMAXSD, + ND_INS_VMINMAXSH, + ND_INS_VMINMAXSS, + ND_INS_VMINPBF16, ND_INS_VMINPD, ND_INS_VMINPH, ND_INS_VMINPS, @@ -1158,6 +1229,7 @@ typedef enum _ND_INS_CLASS ND_INS_VMRESUME, ND_INS_VMRUN, ND_INS_VMSAVE, + ND_INS_VMULNEPBF16, ND_INS_VMULPD, ND_INS_VMULPH, ND_INS_VMULPS, @@ -1524,16 +1596,19 @@ typedef enum _ND_INS_CLASS ND_INS_VRCP28PS, ND_INS_VRCP28SD, ND_INS_VRCP28SS, + ND_INS_VRCPPBF16, ND_INS_VRCPPH, ND_INS_VRCPPS, ND_INS_VRCPSH, ND_INS_VRCPSS, + ND_INS_VREDUCENEPBF16, ND_INS_VREDUCEPD, ND_INS_VREDUCEPH, ND_INS_VREDUCEPS, ND_INS_VREDUCESD, ND_INS_VREDUCESH, ND_INS_VREDUCESS, + ND_INS_VRNDSCALENEPBF16, ND_INS_VRNDSCALEPD, ND_INS_VRNDSCALEPH, ND_INS_VRNDSCALEPS, @@ -1552,10 +1627,12 @@ typedef enum _ND_INS_CLASS ND_INS_VRSQRT28PS, ND_INS_VRSQRT28SD, ND_INS_VRSQRT28SS, + ND_INS_VRSQRTPBF16, ND_INS_VRSQRTPH, ND_INS_VRSQRTPS, ND_INS_VRSQRTSH, ND_INS_VRSQRTSS, + ND_INS_VSCALEFPBF16, ND_INS_VSCALEFPD, ND_INS_VSCALEFPH, ND_INS_VSCALEFPS, @@ -1588,6 +1665,7 @@ typedef enum _ND_INS_CLASS ND_INS_VSM3RNDS2, ND_INS_VSM4KEY4, ND_INS_VSM4RNDS4, + ND_INS_VSQRTNEPBF16, ND_INS_VSQRTPD, ND_INS_VSQRTPH, ND_INS_VSQRTPS, @@ -1595,6 +1673,7 @@ typedef enum _ND_INS_CLASS ND_INS_VSQRTSH, ND_INS_VSQRTSS, ND_INS_VSTMXCSR, + ND_INS_VSUBNEPBF16, ND_INS_VSUBPD, ND_INS_VSUBPH, ND_INS_VSUBPS, @@ -1606,6 +1685,9 @@ typedef enum _ND_INS_CLASS ND_INS_VUCOMISD, ND_INS_VUCOMISH, ND_INS_VUCOMISS, + ND_INS_VUCOMXSD, + ND_INS_VUCOMXSH, + ND_INS_VUCOMXSS, ND_INS_VUNPCKHPD, ND_INS_VUNPCKHPS, ND_INS_VUNPCKLPD, @@ -1663,6 +1745,7 @@ typedef enum _ND_INS_SET ND_SET_AMXTILE, ND_SET_APX_F, ND_SET_AVX, + ND_SET_AVX102, ND_SET_AVX2, ND_SET_AVX2GATHER, ND_SET_AVX5124FMAPS, @@ -1798,6 +1881,13 @@ typedef enum _ND_INS_TYPE ND_CAT_APX, ND_CAT_ARITH, ND_CAT_AVX, + ND_CAT_AVX10BF16, + ND_CAT_AVX10CMPSFP, + ND_CAT_AVX10CONVERT, + ND_CAT_AVX10INT, + ND_CAT_AVX10MINMAX, + ND_CAT_AVX10PARTCOPY, + ND_CAT_AVX10SCONVERT, ND_CAT_AVX2, ND_CAT_AVX2GATHER, ND_CAT_AVX512, diff --git a/inc/bdx86_core.h b/inc/bdx86_core.h index 53f2036..9887298 100644 --- a/inc/bdx86_core.h +++ b/inc/bdx86_core.h @@ -347,24 +347,25 @@ typedef ND_UINT32 ND_REG_SIZE; // Misc macros. // +// NOTE: Macros that accept a size (in bytes) are undefined if the size is not in the interval [1, 8]. + // Sign extend 8 bit to 64 bit. -#define ND_SIGN_EX_8(x) (((x) & 0x00000080) ? (0xFFFFFFFFFFFFFF00 | (x)) : ((x) & 0xFF)) +#define ND_SIGN_EX_8(x) ND_SIGN_EX(1, x) // Sign extend 16 bit to 64 bit. -#define ND_SIGN_EX_16(x) (((x) & 0x00008000) ? (0xFFFFFFFFFFFF0000 | (x)) : ((x) & 0xFFFF)) +#define ND_SIGN_EX_16(x) ND_SIGN_EX(2, x) // Sign extend 32 bit to 64 bit. -#define ND_SIGN_EX_32(x) (((x) & 0x80000000) ? (0xFFFFFFFF00000000 | (x)) : ((x) & 0xFFFFFFFF)) -// Sign extend to 64 bit, with minimal branches -#define ND_SIGN_EX(sz, x) (((x) & ND_SIZE_TO_MASK(sz)) | (~ND_SIZE_TO_MASK(sz) * ND_GET_SIGN(sz, x))) +#define ND_SIGN_EX_32(x) ND_SIGN_EX(4, x) +// Sign extend sz bytes to 64 bits. +#define ND_SIGN_EX(sz, x) ((((ND_UINT64)(x)) & ND_SIZE_TO_MASK(sz)) | (~ND_SIZE_TO_MASK(sz) * ND_GET_SIGN(sz, x))) // Trim 64 bits to sz bytes. -#define ND_TRIM(sz, x) ((sz) == 1 ? (x) & 0xFF : (sz) == 2 ? (x) & 0xFFFF : \ - (sz) == 4 ? (x) & 0xFFFFFFFF : (x)) +#define ND_TRIM(sz, x) ((ND_UINT64)(x) & ND_SIZE_TO_MASK(sz)) // Returns most significant bit, given size in bytes sz. -#define ND_MSB(sz, x) (((x) >> ( (sz) * 8 - 1)) & 1) +#define ND_MSB(sz, x) ((((x)) >> (((sz) * 8) - 1)) & 1) // Returns least significant bit. #define ND_LSB(sz, x) ((x) & 1) // Convert a size in bytes to a bitmask. -#define ND_SIZE_TO_MASK(sz) (((sz) < 8) ? ((1ULL << ((sz) * 8)) - 1) : (0xFFFFFFFFFFFFFFFF)) +#define ND_SIZE_TO_MASK(sz) (0xFFFFFFFFFFFFFFFFull >> ((8 - (sz)) * 8)) // Get bit at position bit from x. #define ND_GET_BIT(bit, x) (((x) >> (bit)) & 1) // Return the sign of sz bytes long value x. @@ -373,12 +374,12 @@ typedef ND_UINT32 ND_REG_SIZE; #define ND_SET_SIGN(sz, x) ND_SIGN_EX(sz, x) -#define ND_FETCH_64(b) (((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b))) | \ - (((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b) + 4) << 32))) -#define ND_FETCH_32(b) (((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b))) | \ - (((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b) + 2) << 16))) -#define ND_FETCH_16(b) (((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b))) | \ - (((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b) + 1) << 8))) +#define ND_FETCH_64(b) ((ND_UINT64)(((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b))) | \ + (((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b) + 4) << 32)))) +#define ND_FETCH_32(b) ((ND_UINT32)(((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b))) | \ + (((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b) + 2) << 16)))) +#define ND_FETCH_16(b) ((ND_UINT16)(((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b))) | \ + (((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b) + 1) << 8)))) #define ND_FETCH_8(b) (*((const ND_UINT8 *)(b))) @@ -956,7 +957,7 @@ typedef union _ND_SIB } ND_SIB; // -// 2-bytes VEX. Exactly as Intel defined it. +// 2-bytes VEX prefix. // typedef union _ND_VEX2 { @@ -972,9 +973,8 @@ typedef union _ND_VEX2 }; } ND_VEX2; - // -// 3-bytes VEX. Exactly as Intel defined it. +// 3-bytes VEX prefix. // typedef union _ND_VEX3 { @@ -995,9 +995,8 @@ typedef union _ND_VEX3 }; } ND_VEX3; - // -// XOP. Exactly as AMD defined it. +// XOP prefix. // typedef union _ND_XOP { @@ -1018,9 +1017,8 @@ typedef union _ND_XOP }; } ND_XOP; - // -// EVEX prefix. Exactly as Intel defined it. +// EVEX prefix. // typedef union _ND_EVEX { @@ -1037,7 +1035,7 @@ typedef union _ND_EVEX ND_UINT8 r : 1; // ~R or ~R3 ND_UINT8 p : 2; // p0, p1 - ND_UINT8 x4 : 1; // ~X4 (repurposed from a hard-coded 1 bit). + ND_UINT8 u : 1; // ~U (repurposed from a hard-coded 1 bit). ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 ND_UINT8 w : 1; // W diff --git a/inc/bdx86_cpuidflags.h b/inc/bdx86_cpuidflags.h index dad9212..6d653a8 100644 --- a/inc/bdx86_cpuidflags.h +++ b/inc/bdx86_cpuidflags.h @@ -136,5 +136,6 @@ #define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 8) #define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 4) #define ND_CFF_RMPQUERY ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 6) +#define ND_CFF_RMPREAD ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 21) #endif // CPUID_FLAGS_H diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py index 405bdfa..ec45542 100644 --- a/isagenerator/disasmlib.py +++ b/isagenerator/disasmlib.py @@ -291,6 +291,7 @@ valid_impops = {# register size 'pBXALb' : ('pBXAL', 'b'), # Implicit [RBX + AL], as used by XLAT. 'pDIq' : ('pDI', 'q'), # Implicit qword [RDI]. 'pDIdq' : ('pDI', 'dq'), # Implicit xmmword [RDI]. + 'pBP' : ('pBP', 'v'), # Implicit operand size loaded from [RBP]. RBP is subject to stack address size. # Implicit shadow stack accesses. 'SHS' : ('SHS', 'q'), # Shadow stack (SSP) implicit access, 1 qword (use by CET instructions). diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat index 3e982d4..ac5c7c4 100644 --- a/isagenerator/instructions/cpuid.dat +++ b/isagenerator/instructions/cpuid.dat @@ -150,3 +150,4 @@ MCOMMIT : 0x80000008, 0xFFFFFFFF, EBX, 8 SNP : 0x8000001F, 0xFFFFFFFF, EAX, 4 RMPQUERY : 0x8000001F, 0xFFFFFFFF, EAX, 6 +RMPREAD : 0x8000001F, 0xFFFFFFFF, EAX, 21 diff --git a/isagenerator/instructions/flags.dat b/isagenerator/instructions/flags.dat index fccd60f..1077edc 100644 --- a/isagenerator/instructions/flags.dat +++ b/isagenerator/instructions/flags.dat @@ -113,3 +113,6 @@ ZERO : CF=0|PF=0|AF=0|ZF=0|SF=0|OF=0 # UINTR flags access, as done by TESTUI. UINTR : CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 + +# AVX 10.2 Compare Scalar FP With Enhanced EFLAGS +CMPSFP : CF=m|PF=m|AF=0|ZF=m|SF=m|OF=m diff --git a/isagenerator/instructions/table_evex_1.dat b/isagenerator/instructions/table_evex_1.dat index f89a3d2..a666502 100644 --- a/isagenerator/instructions/table_evex_1.dat +++ b/isagenerator/instructions/table_evex_1.dat @@ -52,8 +52,12 @@ VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS +VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP +VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS +VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP +VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP # 0x50 - 0x5F VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R @@ -145,6 +149,8 @@ VPSRLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPSLLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R VPCMPEQB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:1 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R +VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:1 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R VPCMPEQW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R @@ -172,6 +178,7 @@ VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 VCVTUSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 VMOVD ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 VMOVQ ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 +VMOVD ; Vdq,Wd ; ; evex m:1 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s, e:E9NF, w:W|R VMOVQ ; Vdq,Wq ; ; evex m:1 p:2 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R VMOVDQA32 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R VMOVDQA64 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R @@ -205,6 +212,7 @@ VPSRLD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 VPSRLQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xD3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R VPADDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xD4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R VPMULLW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VMOVD ; Wd,Vdq ; ; evex m:1 p:1 l:0 w:0 0xD6 /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s, e:E9NF, w:W|R VMOVQ ; Wq,Vdq ; ; evex m:1 p:1 l:0 w:1 0xD6 /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R VPSUBUSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R VPSUBUSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R diff --git a/isagenerator/instructions/table_evex_2.dat b/isagenerator/instructions/table_evex_2.dat index fd70ef9..5be7ba7 100644 --- a/isagenerator/instructions/table_evex_2.dat +++ b/isagenerator/instructions/table_evex_2.dat @@ -135,8 +135,15 @@ VRSQRT14SS ; Vdq{K}{z},Hdq,Wss ; ; evex m:2 p:1 l:x w:0 VRSQRT14SD ; Vdq{K}{z},Hdq,Wsd ; ; evex m:2 p:1 l:x w:1 0x4F /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R # 0x50 - 0x5F +VPDPBUUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0x50 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R VPDPBUSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x50 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VPDPBSUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x50 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPBSSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x50 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPBUUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0x51 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R VPDPBUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x51 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VPDPBSUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x51 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPBSSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x51 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VDPPHPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0x52 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R VPDPWSSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x52 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R VDPBF16PS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x52 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R|R VP4DPWSSD ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x52 /r:mem ; s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R @@ -165,6 +172,7 @@ VBLENDMPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 VBLENDMPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R VPBLENDMB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R VPBLENDMW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R +VCVT2PS2PHX ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x67 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R VP2INTERSECTD ; rKq+1,Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R VP2INTERSECTQ ; rKq+1,Hfv,Wfv|B64 ; ; evex m:2 p:3 l:x w:1 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R @@ -178,6 +186,7 @@ VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0 VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R VPSHRDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R VPSHRDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VCVTBIASPH2BF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:2 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R VPERMI2B ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x75 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R VPERMI2W ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R @@ -335,6 +344,12 @@ VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 VGF2P8MULB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R # 0xD0 - 0xDF +VPDPWUUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0xD2 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPWUSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xD2 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPWSUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0xD2 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPWUUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPWUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R +VPDPWSUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R VAESENC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDC /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R VAESENCLAST ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDD /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R VAESDEC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDE /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R diff --git a/isagenerator/instructions/table_evex_3.dat b/isagenerator/instructions/table_evex_3.dat index 926e21e..6f3bd4d 100644 --- a/isagenerator/instructions/table_evex_3.dat +++ b/isagenerator/instructions/table_evex_3.dat @@ -12,6 +12,7 @@ VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VRNDSCALENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x08 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R @@ -57,6 +58,7 @@ VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VGETMANTPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x26 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R @@ -77,6 +79,7 @@ VPCMPW ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 # 0x40 - 0x4F VDBPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x42 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R +VMPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:2 l:x w:0 0x42 /r ib ; s:AVX102, t:AVX10INT, l:fvm, e:E4NF, w:W|R|R|R|R VSHUFI32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R @@ -86,6 +89,13 @@ VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R +VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R +VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R +VMINMAXNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E4, w:W|R|R|R|R +VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R +VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R +VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R @@ -93,6 +103,7 @@ VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R +VREDUCENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x56 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R @@ -101,6 +112,7 @@ VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R VFPCLASSPS ; rKq{K},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R VFPCLASSPD ; rKq{K},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VFPCLASSPBF16 ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x66 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VFPCLASSSH ; rKq{K},Wsh,Ib ; ; evex m:3 p:0 l:i w:0 0x67 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R VFPCLASSSS ; rKq{K},Wss,Ib ; ; evex m:3 p:1 l:i w:0 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R VFPCLASSSD ; rKq{K},Wsd,Ib ; ; evex m:3 p:1 l:i w:1 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R @@ -124,6 +136,7 @@ VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 # 0xC0 - 0xCF VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R +VCMPPBF16 ; rK{K},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0xC2 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R|R VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R diff --git a/isagenerator/instructions/table_evex_4.dat b/isagenerator/instructions/table_evex_4.dat index b0e04eb..fa9cb49 100644 --- a/isagenerator/instructions/table_evex_4.dat +++ b/isagenerator/instructions/table_evex_4.dat @@ -776,27 +776,27 @@ PUSH2 ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:0 PUSH2P ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg ; s:APX_F, t:PUSH, w:R|R|W, v:legacy, e:APX_EVEX_PP2, a:D64 -# AES instructions. -ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg ; s:APX_F, t:AESKL, w:W|R|R|W|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy -ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg ; s:APX_F, t:AESKL, w:W|R|RW|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy -AESDEC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESDEC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESENC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -AESENC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +# AES instructions. Were included in initial APX revisions, later removed in revision 4.0. +#ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg ; s:APX_F, t:AESKL, w:W|R|R|W|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy +#ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg ; s:APX_F, t:AESKL, w:W|R|RW|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy +#AESDEC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESDEC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESENC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +#AESENC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy -# SHA instructions. -SHA1RNDS4 ; Vdq,Wdq,Ib ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy -SHA1NEXTE ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy -SHA1MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy -SHA1MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy -SHA256MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy -SHA256MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy -SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy +# SHA instructions. Were included in initial APX revisions, later removed in revision 4.0. +#SHA1RNDS4 ; Vdq,Wdq,Ib ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy +#SHA1NEXTE ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +#SHA1MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +#SHA1MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +#SHA256MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +#SHA256MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +#SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy # INVEPT, INVPCID, INVVPID diff --git a/isagenerator/instructions/table_evex_5.dat b/isagenerator/instructions/table_evex_5.dat index 477dfa7..79d50c3 100644 --- a/isagenerator/instructions/table_evex_5.dat +++ b/isagenerator/instructions/table_evex_5.dat @@ -8,22 +8,38 @@ VMOVSH ; Vdq{K}{z},Wsh ; ; evex m:5 p:2 l:i w:0 VMOVSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:5 p:2 l:i w:0 0x10 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R VMOVSH ; Wsh{K},Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R VMOVSH ; Wsh{K}{z},Hdq,Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R +VCVTBIASPH2HF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R +VCVTNEPH2HF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R +VCVTNE2PH2HF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R +VCVTBIASPH2HF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R +VCVTNEPH2HF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R +VCVTNE2PH2HF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R +VCVTHF82PH ; Vfv{K}{z},Whv ; ; evex m:5 p:3 l:x w:0 0x1E /r ; s:AVX102, t:AVX10CONVERT, l:hv, e:E2, w:W|R|R # 0x20 - 0x2F VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 +VUCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 +VCOMSBF16 ; Vdq,Wsh ; Fv ; evex m:5 p:1 l:i w:0 0x2F /r ; s:AVX102, t:AVX10BF16, l:t1s16, e:E10NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 +VCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP + +# 0x40 - 0x4F +VGETEXPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x42 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R # 0x50 - 0x5F VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VSQRTNEPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x51 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VADDNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x58 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMULNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x59 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R @@ -34,19 +50,52 @@ VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1 VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VSUBNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMINPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5D /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VDIVNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMAXPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5F /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R # 0x60 - 0x6F +VCVTTPH2IBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2IBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R +VCVTPH2IBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2IBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R +VCVTTPH2IUBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2IUBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R +VCVTPH2IUBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2IUBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R +VCVTTPS2UDQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPD2UDQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2UQQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R +VCVTTPD2UQQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTSS2USIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 +VCVTTSD2USIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 +VCVTTPS2DQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPD2DQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2QQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R +VCVTTPD2QQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R +VCVTTSS2SIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 +VCVTTSD2SIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64 + VMOVW ; Vdq,Mw ; ; evex m:5 p:1 l:0 w:i 0x6E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R VMOVW ; Vdq,Rd ; ; evex m:5 p:1 l:0 w:i 0x6E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R +VMOVW ; Vdq,Ww ; ; evex m:5 p:2 l:0 w:0 0x6E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R # 0x70 - 0x7F +VCVTBIASPH2BF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R +VCVTNEPH2BF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R +VCVTNE2PH2BF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 @@ -66,3 +115,4 @@ VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0 VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R VMOVW ; Mw,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R VMOVW ; Rd,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R +VMOVW ; Ww,Vdq ; ; evex m:5 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R diff --git a/isagenerator/instructions/table_evex_6.dat b/isagenerator/instructions/table_evex_6.dat index 625294a..bfa47d6 100644 --- a/isagenerator/instructions/table_evex_6.dat +++ b/isagenerator/instructions/table_evex_6.dat @@ -8,14 +8,17 @@ VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0 VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R # 0x20 - 0x2F +VSCALEFPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x2C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R # 0x40 - 0x4F VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VRCPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x4C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R VRCPPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R VRCPSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R +VRSQRTPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x4E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R @@ -28,36 +31,48 @@ VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 # 0x90 - 0x9F VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x98 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9A /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R # 0xA0 - 0xAF VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xA8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R # 0xB0 - 0xBF VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xB8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R diff --git a/isagenerator/instructions/table_legacy_0.dat b/isagenerator/instructions/table_legacy_0.dat index 6947551..4008757 100644 --- a/isagenerator/instructions/table_legacy_0.dat +++ b/isagenerator/instructions/table_legacy_0.dat @@ -343,8 +343,8 @@ MOV ; Eb,Ib ; ; 0xC6 /0 ib ; s:I XABORT ; Ib ; yIP,EAX ; 0xC6 /0xF8 ib ; s:TSX, t:UNCOND_BR, w:R|W|RCW, i:RTM MOV ; Ev,Iz ; ; 0xC7 /0 iz ; s:I86, t:DATAXFER, w:W|R, a:OP2SIGNEXO1, p:XRELEASE|HLEWOL XBEGIN ; Jz ; yIP,EAX ; 0xC7 /0xF8 cz ; s:TSX, t:COND_BR, w:R|RCW|CW, i:RTM -ENTER ; Iw,Ib ; rBP,sSP,Kv ; 0xC8 iw ib ; s:I186, t:MISC, w:R|R|RW|RW|W, a:D64 -LEAVE ; ; sBP,rBP,rSP,Kv ; 0xC9 ; s:I186, t:MISC, w:R|RW|RW|R, a:D64 +ENTER ; Iw,Ib ; rBP,rSP,Kv,sBP,pBP; 0xC8 iw ib ; s:I186, t:MISC, w:R|R|RW|RW|W|RW|R, a:D64 +LEAVE ; ; sBP,rBP,sSP,Kv ; 0xC9 ; s:I186, t:MISC, w:R|RW|RW|R, a:D64 RETF ; Iw ; CS,rIP,Kv2,SHS2 ; 0xCA iw ; s:I86, t:RET, w:R|W|W|R|R RETF ; ; CS,rIP,Kv2,SHS2 ; 0xCB ; s:I86, t:RET, w:W|W|R|R INT3 ; ; CS,rIP,Kv3,Fv,SHS3 ; 0xCC ; s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX diff --git a/isagenerator/instructions/table_legacy_1.dat b/isagenerator/instructions/table_legacy_1.dat index 65be382..b47a67c 100644 --- a/isagenerator/instructions/table_legacy_1.dat +++ b/isagenerator/instructions/table_legacy_1.dat @@ -81,6 +81,7 @@ MWAITX ; ; EAX,ECX,EBX ; NP 0x0F 0x01 /0xF CLZERO ; ; rAX ; 0x0F 0x01 /0xFC ; s:CLZERO, t:MISC, w:R RDPRU ; ; EAX,EDX,ECX,Fv ; NP 0x0F 0x01 /0xFD ; s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RMPQUERY ; ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFD ; s:SNP, t:SYSTEM, w:R|RW|W|RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPQUERY +RMPREAD ; ; RAX,pCXdq,Fv ; 0xF2 0x0F 0x01 /0xFD ; s:SNP, t:SYSTEM, w:RW|W|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPREAD INVLPGB ; ; rAX,ECX,EDX ; NP 0x0F 0x01 /0xFE ; s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL RMPADJUST ; ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:R|RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL RMPUPDATE ; ; RAX,pCXdq,Fv ; 0xF2 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL