diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c
index 7b5e409..8ff32c6 100644
--- a/bddisasm/bddisasm.c
+++ b/bddisasm/bddisasm.c
@@ -203,6 +203,8 @@ static const uint16_t gOperandMap[] =
     ND_OPE_S,       // ND_OPT_MEM_SHSP
     ND_OPE_S,       // ND_OPT_MEM_SHS0
 
+    ND_OPE_L,       // ND_OPT_Im2z
+
     ND_OPE_S,       // ND_OPT_CR_0
     ND_OPE_S,       // ND_OPT_IDTR
     ND_OPE_S,       // ND_OPT_GDTR
@@ -529,10 +531,7 @@ NdFetchVex3(
             // Vex.R and Vex.X have been tested by the initial if.
 
             // Vex.vvvv must be less than 8.
-            if ((Instrux->Exs.v & 0x8) == 0x8)
-            {
-                return ND_STATUS_INVALID_ENCODING_IN_MODE;
-            }
+            Instrux->Exs.v &= 7;
 
             // Vex.B is ignored, so we force it to 0.
             Instrux->Exs.b = 0;
@@ -1243,7 +1242,7 @@ NdGetCompDispSize(
     case ND_TUPLE_T1S16:
         return 2;
     case ND_TUPLE_T1S:
-        return Instrux->Exs.w ? 8 : 4;
+        return !!(Instrux->Attributes & ND_FLAG_WIG) ? 4 : Instrux->Exs.w ? 8 : 4;
     case ND_TUPLE_T1F:
         return (uint8_t)MemSize;
     case ND_TUPLE_T2:
@@ -2330,6 +2329,13 @@ NdParseOperand(
         }
         break;
 
+    case ND_OPT_Im2z:
+        {
+            operand->Type = ND_OP_IMM;
+            operand->Info.Immediate.Imm = Instrux->SseImmediate & 3;
+        }
+        break;
+
     case ND_OPT_J:
         // Fetch the relative offset. NOTE: The size of the relative can't exceed 4 bytes.
         status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (uint8_t)size);
@@ -2571,12 +2577,6 @@ memory:
             {
                 if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == REG_RBP))
                 {
-                    // Some instructions (example: MPX) don't support RIP relative addressing.
-                    if (!!(Instrux->Attributes & ND_FLAG_NO_RIP_REL))
-                    {
-                        return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED;
-                    }
-
                     //
                     // RIP relative addressing addresses a memory region relative to the current RIP; However,
                     // the current RIP, when executing the current instruction, is already updated and points
@@ -2585,6 +2585,12 @@ memory:
                     // addressing, as long as we're in long mode.
                     //
                     operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64);
+
+                    // Some instructions (example: MPX) don't support RIP relative addressing.
+                    if (operand->Info.Memory.IsRipRel && !!(Instrux->Attributes & ND_FLAG_NO_RIP_REL))
+                    {
+                        return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED;
+                    }
                 }
                 else
                 {
@@ -2728,7 +2734,12 @@ memory:
         operand->Type = ND_OP_REG;
         operand->Info.Register.Type = ND_REG_SSE;
         operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
-        operand->Info.Register.Reg = ((Instrux->SseImmediate >> 4) & 0xF) | ((Instrux->SseImmediate & 8) << 1);
+        operand->Info.Register.Reg = (Instrux->SseImmediate >> 4) & 0xF;
+
+        if (Instrux->DefCode != ND_CODE_64)
+        {
+            operand->Info.Register.Reg &= 0x7;
+        }
 
         Offset = Instrux->Length;
         break;
@@ -3637,6 +3648,7 @@ NdGetEffectiveOpMode(
         break;
     case ND_CODE_64:
         Instrux->EfOpMode = (width || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32);
+        Instrux->AddrMode = !!(Instrux->Attributes & ND_FLAG_I67) ? ND_ADDR_64 : Instrux->AddrMode;
         break;
     default:
         return ND_STATUS_INVALID_INSTRUX;
@@ -3692,7 +3704,8 @@ NdValidateInstruction(
         }
 
         // VSIB instructions have a restriction: the same vector register can't be used by more than one operand.
-        if (ND_HAS_VSIB(Instrux))
+        // The exception is SCATTER*, which can use the VSIB reg as two sources.
+        if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER)
         {
             uint8_t usedVects[32] = { 0 };
 
@@ -3769,8 +3782,10 @@ NdValidateInstruction(
                 }
             }
 
-            // EVEX.b must be 0 if SAE/ER is not used.
-            if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && !ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux))
+            // EVEX.b must be 0 if SAE/ER is not used, but can be ignored if the ignore embedded rounding flag is set.
+            if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && 
+                !ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux) &&
+                !(Instrux->Attributes & ND_FLAG_IER))
             {
                 return ND_STATUS_ER_SAE_NOT_SUPPORTED;
             }
@@ -4483,7 +4498,7 @@ NdToText(
 
         case ND_OP_IMM:
             {
-                switch (pOp->RawSize)
+                switch (pOp->Size)
                 {
                 case 1:
                     status = NdSprintf(temp, sizeof(temp), "0x%02x", (uint8_t)pOp->Info.Immediate.Imm);
@@ -4563,8 +4578,10 @@ NdToText(
 
         case ND_OP_MEM:
             {
-                // Prepend the size.
-                switch (pOp->Size)
+                // Prepend the size. For VSIB addressing, store the VSIB element size, not the total accessed size.
+                ND_OPERAND_SIZE size = pOp->Info.Memory.IsVsib ? pOp->Info.Memory.Vsib.ElemSize : pOp->Size;
+
+                switch (size)
                 {
                 case 1:
                     res = nd_strcat_s(Buffer, BufferSize, "byte ptr ");
diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
index c1c5089..adb305d 100644
--- a/bddisasm/include/instructions.h
+++ b/bddisasm/include/instructions.h
@@ -5,7 +5,7 @@
 #ifndef _INSTRUCTIONS_H_
 #define _INSTRUCTIONS_H_
 
-const ND_INSTRUCTION gInstructions[2554] = 
+const ND_INSTRUCTION gInstructions[2557] = 
 {
     // Pos:0 Instruction:"AAA" Encoding:"0x37"/""
     {
@@ -177,7 +177,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:12 Instruction:"ADC Ev,Iz" Encoding:"0x82 /2 iz"/"MI"
+    // Pos:12 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI"
     {
         ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
@@ -186,8 +186,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF,
         0,
         0,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
@@ -331,7 +331,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:23 Instruction:"ADD Ev,Iz" Encoding:"0x82 /0 iz"/"MI"
+    // Pos:23 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI"
     {
         ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
@@ -340,8 +340,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF,
         0,
         0,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -653,7 +653,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:47 Instruction:"AND Ev,Iz" Encoding:"0x82 /4 iz"/"MI"
+    // Pos:47 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI"
     {
         ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
@@ -662,8 +662,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF,
         0|REG_RFLAG_AF,
         0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -984,7 +984,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 43, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -997,7 +997,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 44, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1010,7 +1010,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 45, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1023,7 +1023,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 46, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1036,7 +1036,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 47, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1049,7 +1049,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_MODRM, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1062,7 +1062,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_MODRM, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1075,7 +1075,7 @@ const ND_INSTRUCTION gInstructions[2554] =
     {
         ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 49, 
         ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 
+        0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 
         0,
         0,
         0,
@@ -1976,7 +1976,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:146 Instruction:"CMP Ev,Iz" Encoding:"0x82 /7 iz"/"MI"
+    // Pos:146 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI"
     {
         ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
@@ -1985,8 +1985,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF,
         0,
         0,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -2386,7 +2386,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_v, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:174 Instruction:"CVTDQ2PD Vx,Wpd" Encoding:"0xF3 0x0F 0xE6 /r"/"RM"
+    // Pos:174 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM"
     {
         ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 114, 
         ND_MOD_ANY, 
@@ -2396,7 +2396,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
     // Pos:175 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM"
@@ -3447,7 +3447,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:253 Instruction:"FCOM ST(i),ST(0)" Encoding:"0xDC /2:reg"/"M"
+    // Pos:253 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M"
     {
         ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, 
         ND_MOD_ANY, 
@@ -3456,8 +3456,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         0,
-        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), 
         OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), 
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -3533,7 +3533,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:259 Instruction:"FCOMP ST(i),ST(0)" Encoding:"0xDC /3:reg"/"M"
+    // Pos:259 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M"
     {
         ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, 
         ND_MOD_ANY, 
@@ -3542,8 +3542,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         0,
-        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), 
         OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), 
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -4699,7 +4699,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:347 Instruction:"FST ST(0),ST(i)" Encoding:"0xDD /2:reg"/"M"
+    // Pos:347 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M"
     {
         ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, 
         ND_MOD_ANY, 
@@ -4708,8 +4708,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         0,
-        OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), 
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -4767,7 +4767,7 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:352 Instruction:"FSTP ST(0),ST(i)" Encoding:"0xDD /3:reg"/"M"
+    // Pos:352 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M"
     {
         ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, 
         ND_MOD_ANY, 
@@ -4776,8 +4776,8 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         0,
-        OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_FPU_STX, ND_OPS_ft, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_FPU_ST0, ND_OPS_ft, ND_OPF_R, 0, 0), 
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
@@ -5124,9 +5124,35 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:378 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
+    // Pos:378 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M"
+    {
+        ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 252, 
+        ND_MOD_ANY, 
+        0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_M, ND_OPS_rx, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
+    }, 
+
+    // Pos:379 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M"
+    {
+        ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 253, 
+        ND_MOD_ANY, 
+        0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_M, ND_OPS_rx, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
+    }, 
+
+    // Pos:380 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M"
     {
-        ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 252, 
+        ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 254, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 
         0,
@@ -5137,9 +5163,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:379 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
+    // Pos:381 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/""
     {
-        ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 253, 
+        ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 255, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5149,9 +5175,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:380 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
+    // Pos:382 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/""
     {
-        ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 254, 
+        ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 256, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5161,9 +5187,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:381 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
+    // Pos:383 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/""
     {
-        ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 255, 
+        ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 257, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5173,9 +5199,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:382 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
+    // Pos:384 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/""
     {
-        ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 256, 
+        ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 258, 
         ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, 
         0,
@@ -5186,9 +5212,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:383 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
+    // Pos:385 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI"
     {
-        ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 257, 
+        ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 259, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -5200,9 +5226,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:384 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
+    // Pos:386 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI"
     {
-        ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 258, 
+        ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 260, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -5214,9 +5240,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:385 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
+    // Pos:387 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM"
     {
-        ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 259, 
+        ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 261, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -5227,9 +5253,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:386 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
+    // Pos:388 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM"
     {
-        ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 260, 
+        ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 262, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -5240,9 +5266,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:387 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
+    // Pos:389 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM"
     {
-        ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 261, 
+        ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 263, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -5253,9 +5279,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:388 Instruction:"HLT" Encoding:"0xF4"/""
+    // Pos:390 Instruction:"HLT" Encoding:"0xF4"/""
     {
-        ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 262, 
+        ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 264, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -5264,9 +5290,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:389 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
+    // Pos:391 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM"
     {
-        ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 263, 
+        ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 265, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -5277,9 +5303,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:390 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
+    // Pos:392 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM"
     {
-        ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 264, 
+        ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 266, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -5290,9 +5316,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:391 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
+    // Pos:393 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M"
     {
-        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 265, 
+        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 267, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5306,9 +5332,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:392 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
+    // Pos:394 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M"
     {
-        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 265, 
+        ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 267, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5321,9 +5347,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:393 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
+    // Pos:395 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5335,9 +5361,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:394 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
+    // Pos:396 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5350,9 +5376,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:395 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
+    // Pos:397 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5365,9 +5391,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:396 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
+    // Pos:398 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5380,9 +5406,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:397 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
+    // Pos:399 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M"
     {
-        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 266, 
+        ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5395,9 +5421,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:398 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
+    // Pos:400 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I"
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5409,9 +5435,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:399 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
+    // Pos:401 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I"
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5423,9 +5449,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:400 Instruction:"IN AL,DX" Encoding:"0xEC"/""
+    // Pos:402 Instruction:"IN AL,DX" Encoding:"0xEC"/""
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5437,9 +5463,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:401 Instruction:"IN eAX,DX" Encoding:"0xED"/""
+    // Pos:403 Instruction:"IN eAX,DX" Encoding:"0xED"/""
     {
-        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 267, 
+        ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5451,9 +5477,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:402 Instruction:"INC Zv" Encoding:"0x40"/"O"
+    // Pos:404 Instruction:"INC Zv" Encoding:"0x40"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5464,9 +5490,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:403 Instruction:"INC Zv" Encoding:"0x41"/"O"
+    // Pos:405 Instruction:"INC Zv" Encoding:"0x41"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5477,9 +5503,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:404 Instruction:"INC Zv" Encoding:"0x42"/"O"
+    // Pos:406 Instruction:"INC Zv" Encoding:"0x42"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5490,9 +5516,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:405 Instruction:"INC Zv" Encoding:"0x43"/"O"
+    // Pos:407 Instruction:"INC Zv" Encoding:"0x43"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5503,9 +5529,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:406 Instruction:"INC Zv" Encoding:"0x44"/"O"
+    // Pos:408 Instruction:"INC Zv" Encoding:"0x44"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5516,9 +5542,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:407 Instruction:"INC Zv" Encoding:"0x45"/"O"
+    // Pos:409 Instruction:"INC Zv" Encoding:"0x45"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5529,9 +5555,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:408 Instruction:"INC Zv" Encoding:"0x46"/"O"
+    // Pos:410 Instruction:"INC Zv" Encoding:"0x46"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5542,9 +5568,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:409 Instruction:"INC Zv" Encoding:"0x47"/"O"
+    // Pos:411 Instruction:"INC Zv" Encoding:"0x47"/"O"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -5555,9 +5581,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:410 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
+    // Pos:412 Instruction:"INC Eb" Encoding:"0xFE /0"/"M"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5568,9 +5594,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:411 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
+    // Pos:413 Instruction:"INC Ev" Encoding:"0xFF /0"/"M"
     {
-        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 268, 
+        ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -5581,9 +5607,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:412 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
+    // Pos:414 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
     {
-        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 269, 
+        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 271, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -5595,9 +5621,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:413 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
+    // Pos:415 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
     {
-        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 270, 
+        ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 272, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -5609,9 +5635,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:414 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
+    // Pos:416 Instruction:"INSB Yb,DX" Encoding:"0x6C"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 271, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5624,9 +5650,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:415 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
+    // Pos:417 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 271, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5640,9 +5666,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:416 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
+    // Pos:418 Instruction:"INSD Yz,DX" Encoding:"0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 272, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5655,9 +5681,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:417 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
+    // Pos:419 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 272, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5671,9 +5697,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:418 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
+    // Pos:420 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI"
     {
-        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 273, 
+        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 275, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -5685,9 +5711,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:419 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
+    // Pos:421 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI"
     {
-        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 273, 
+        ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 275, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -5699,9 +5725,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:420 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
+    // Pos:422 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII"
     {
-        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 274, 
+        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 276, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
         0,
@@ -5714,9 +5740,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:421 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
+    // Pos:423 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM"
     {
-        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 274, 
+        ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 276, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
         0,
@@ -5727,9 +5753,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:422 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
+    // Pos:424 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 275, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5742,9 +5768,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:423 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
+    // Pos:425 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/""
     {
-        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 275, 
+        ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -5758,9 +5784,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:424 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
+    // Pos:426 Instruction:"INT Ib" Encoding:"0xCD ib"/"I"
     {
-        ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 276, 
+        ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 278, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_VM,
@@ -5775,9 +5801,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:425 Instruction:"INT1" Encoding:"0xF1"/""
+    // Pos:427 Instruction:"INT1" Encoding:"0xF1"/""
     {
-        ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 277, 
+        ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 279, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_VM,
@@ -5790,9 +5816,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:426 Instruction:"INT3" Encoding:"0xCC"/""
+    // Pos:428 Instruction:"INT3" Encoding:"0xCC"/""
     {
-        ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 278, 
+        ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 280, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_VM,
@@ -5806,9 +5832,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:427 Instruction:"INTO" Encoding:"0xCE"/""
+    // Pos:429 Instruction:"INTO" Encoding:"0xCE"/""
     {
-        ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 279, 
+        ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 281, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_VM,
@@ -5822,9 +5848,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:428 Instruction:"INVD" Encoding:"0x0F 0x08"/""
+    // Pos:430 Instruction:"INVD" Encoding:"0x0F 0x08"/""
     {
-        ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 280, 
+        ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 282, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0,
@@ -5833,9 +5859,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:429 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
+    // Pos:431 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM"
     {
-        ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 281, 
+        ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 283, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -5847,9 +5873,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:430 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
+    // Pos:432 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M"
     {
-        ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 282, 
+        ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 284, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 
         0,
@@ -5859,9 +5885,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:431 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
+    // Pos:433 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/""
     {
-        ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 283, 
+        ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 285, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -5872,9 +5898,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:432 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/""
+    // Pos:434 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/""
     {
-        ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 284, 
+        ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 286, 
         ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
         0,
@@ -5886,9 +5912,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:433 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
+    // Pos:435 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM"
     {
-        ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 285, 
+        ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 287, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, 
         0,
@@ -5899,9 +5925,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:434 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
+    // Pos:436 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM"
     {
-        ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 286, 
+        ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 288, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -5913,9 +5939,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:435 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
+    // Pos:437 Instruction:"IRETD" Encoding:"ds32 0xCF"/""
     {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 287, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 289, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0,
@@ -5929,9 +5955,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:436 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
+    // Pos:438 Instruction:"IRETQ" Encoding:"ds64 0xCF"/""
     {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 288, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 290, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0,
@@ -5945,9 +5971,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:437 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
+    // Pos:439 Instruction:"IRETW" Encoding:"ds16 0xCF"/""
     {
-        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 289, 
+        ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 291, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0,
@@ -5961,9 +5987,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:438 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
+    // Pos:440 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 290, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_ZF,
@@ -5975,9 +6001,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:439 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
+    // Pos:441 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 290, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_ZF,
@@ -5989,9 +6015,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:440 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
+    // Pos:442 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 291, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF,
@@ -6003,9 +6029,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:441 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
+    // Pos:443 Instruction:"JC Jb" Encoding:"0x72 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 291, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF,
@@ -6017,9 +6043,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:442 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
+    // Pos:444 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 292, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 294, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
@@ -6031,9 +6057,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:443 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
+    // Pos:445 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 293, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 295, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
@@ -6045,9 +6071,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:444 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
+    // Pos:446 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 294, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_OF,
@@ -6059,9 +6085,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:445 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
+    // Pos:447 Instruction:"JL Jb" Encoding:"0x7C cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 294, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_OF,
@@ -6073,9 +6099,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:446 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
+    // Pos:448 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 295, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF,
@@ -6087,9 +6113,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:447 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
+    // Pos:449 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 295, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF,
@@ -6101,9 +6127,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:448 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
+    // Pos:450 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D"
     {
-        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 296, 
+        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
         ND_MOD_ANY, 
         ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
@@ -6114,9 +6140,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:449 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
+    // Pos:451 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D"
     {
-        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 296, 
+        ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
         ND_MOD_ANY, 
         ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
@@ -6127,9 +6153,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:450 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
+    // Pos:452 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M"
     {
-        ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 296, 
+        ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
         0,
@@ -6140,9 +6166,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:451 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M"
+    // Pos:453 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M"
     {
-        ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 297, 
+        ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 299, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0,
@@ -6153,9 +6179,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:452 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
+    // Pos:454 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D"
     {
-        ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 297, 
+        ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 299, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -6166,9 +6192,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:453 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
+    // Pos:455 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D"
     {
-        ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
+        ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 300, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -6180,9 +6206,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:454 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
+    // Pos:456 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M"
     {
-        ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 298, 
+        ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 300, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 
         0,
@@ -6194,9 +6220,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:455 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
+    // Pos:457 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 299, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_ZF,
@@ -6208,9 +6234,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:456 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
+    // Pos:458 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 299, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_ZF,
@@ -6222,9 +6248,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:457 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
+    // Pos:459 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 300, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF,
@@ -6236,9 +6262,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:458 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
+    // Pos:460 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 300, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_CF,
@@ -6250,9 +6276,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:459 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
+    // Pos:461 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_OF,
@@ -6264,9 +6290,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:460 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
+    // Pos:462 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_OF,
@@ -6278,9 +6304,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:461 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
+    // Pos:463 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF,
@@ -6292,9 +6318,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:462 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
+    // Pos:464 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF,
@@ -6306,9 +6332,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:463 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
+    // Pos:465 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_OF,
@@ -6320,9 +6346,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:464 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
+    // Pos:466 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_OF,
@@ -6334,9 +6360,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:465 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
+    // Pos:467 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_PF,
@@ -6348,9 +6374,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:466 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
+    // Pos:468 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_PF,
@@ -6362,9 +6388,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:467 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
+    // Pos:469 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF,
@@ -6376,9 +6402,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:468 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
+    // Pos:470 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF,
@@ -6390,9 +6416,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:469 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
+    // Pos:471 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_ZF,
@@ -6404,9 +6430,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:470 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
+    // Pos:472 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_ZF,
@@ -6418,9 +6444,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:471 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
+    // Pos:473 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_OF,
@@ -6432,9 +6458,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:472 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
+    // Pos:474 Instruction:"JO Jb" Encoding:"0x70 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_OF,
@@ -6446,9 +6472,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:473 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
+    // Pos:475 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_PF,
@@ -6460,9 +6486,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:474 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
+    // Pos:476 Instruction:"JP Jb" Encoding:"0x7A cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_PF,
@@ -6474,9 +6500,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:475 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
+    // Pos:477 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D"
     {
-        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 309, 
+        ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 311, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
@@ -6488,9 +6514,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:476 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
+    // Pos:478 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF,
@@ -6502,9 +6528,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:477 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
+    // Pos:479 Instruction:"JS Jb" Encoding:"0x78 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_SF,
@@ -6516,9 +6542,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:478 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
+    // Pos:480 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_ZF,
@@ -6530,9 +6556,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:479 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
+    // Pos:481 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D"
     {
-        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 311, 
+        ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, 
         ND_MOD_ANY, 
         ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 
         0|REG_RFLAG_ZF,
@@ -6544,9 +6570,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:480 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
+    // Pos:482 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 312, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 314, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6558,9 +6584,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:481 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
+    // Pos:483 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 313, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 315, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6572,9 +6598,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:482 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
+    // Pos:484 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 314, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 316, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6586,9 +6612,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:483 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
+    // Pos:485 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM"
     {
-        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 315, 
+        ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 317, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6600,9 +6626,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:484 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
+    // Pos:486 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 316, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 318, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6614,9 +6640,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:485 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
+    // Pos:487 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 317, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 319, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6628,9 +6654,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:486 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
+    // Pos:488 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 318, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 320, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6642,9 +6668,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:487 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
+    // Pos:489 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 319, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 321, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6656,9 +6682,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:488 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
+    // Pos:490 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 320, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 322, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6670,9 +6696,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:489 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
+    // Pos:491 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM"
     {
-        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 321, 
+        ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 323, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6684,9 +6710,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:490 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
+    // Pos:492 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 322, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 324, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6698,9 +6724,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:491 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
+    // Pos:493 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM"
     {
-        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 323, 
+        ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 325, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6712,9 +6738,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:492 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
+    // Pos:494 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM"
     {
-        ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 324, 
+        ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 326, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -6725,9 +6751,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:493 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
+    // Pos:495 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM"
     {
-        ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 325, 
+        ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 327, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -6738,9 +6764,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:494 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
+    // Pos:496 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6751,9 +6777,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:495 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
+    // Pos:497 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6764,9 +6790,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:496 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
+    // Pos:498 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6777,9 +6803,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_rK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:497 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:499 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6790,9 +6816,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:498 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:500 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 326, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -6803,9 +6829,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:499 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
+    // Pos:501 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6816,9 +6842,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:500 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
+    // Pos:502 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6829,9 +6855,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:501 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
+    // Pos:503 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6842,9 +6868,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_rK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:502 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:504 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6855,9 +6881,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:503 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:505 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 327, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6868,9 +6894,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:504 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
+    // Pos:506 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6881,9 +6907,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:505 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
+    // Pos:507 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6894,9 +6920,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:506 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
+    // Pos:508 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6907,9 +6933,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_rK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:507 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
+    // Pos:509 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6920,9 +6946,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:508 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
+    // Pos:510 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 328, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -6933,9 +6959,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:509 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
+    // Pos:511 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6946,9 +6972,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:510 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
+    // Pos:512 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6959,9 +6985,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:511 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
+    // Pos:513 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6972,9 +6998,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_rK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:512 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
+    // Pos:514 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6985,9 +7011,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:513 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
+    // Pos:515 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM"
     {
-        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 329, 
+        ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -6998,9 +7024,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:514 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
+    // Pos:516 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 330, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 332, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7011,9 +7037,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:515 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
+    // Pos:517 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 331, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 333, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7024,9 +7050,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:516 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
+    // Pos:518 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 332, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 334, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7037,9 +7063,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:517 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
+    // Pos:519 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM"
     {
-        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 333, 
+        ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 335, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7050,9 +7076,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:518 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
+    // Pos:520 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 334, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 336, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7064,9 +7090,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:519 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
+    // Pos:521 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 335, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 337, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7078,9 +7104,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:520 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
+    // Pos:522 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 336, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 338, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7092,9 +7118,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:521 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
+    // Pos:523 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 337, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7106,9 +7132,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:522 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
+    // Pos:524 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 338, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 340, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7120,9 +7146,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:523 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
+    // Pos:525 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 339, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 341, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7134,9 +7160,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:524 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
+    // Pos:526 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM"
     {
-        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 340, 
+        ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 342, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7148,9 +7174,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:525 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
+    // Pos:527 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM"
     {
-        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 341, 
+        ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 343, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7162,9 +7188,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:526 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
+    // Pos:528 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 342, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 344, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7176,9 +7202,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:527 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
+    // Pos:529 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 343, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 345, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7190,9 +7216,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:528 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
+    // Pos:530 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 344, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 346, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7204,9 +7230,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:529 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
+    // Pos:531 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 345, 
+        ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 347, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7218,9 +7244,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:530 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
+    // Pos:532 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 346, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 348, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7232,9 +7258,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:531 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
+    // Pos:533 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 347, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 349, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7246,9 +7272,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:532 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
+    // Pos:534 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 348, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 350, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7260,9 +7286,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:533 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
+    // Pos:535 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI"
     {
-        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 349, 
+        ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 351, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7274,9 +7300,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:534 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
+    // Pos:536 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 352, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7287,9 +7313,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:535 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
+    // Pos:537 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 351, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 353, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7300,9 +7326,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:536 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
+    // Pos:538 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 352, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 354, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7313,9 +7339,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:537 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
+    // Pos:539 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM"
     {
-        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 353, 
+        ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 355, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7326,9 +7352,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:538 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
+    // Pos:540 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 354, 
+        ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 356, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7340,9 +7366,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:539 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
+    // Pos:541 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 355, 
+        ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 357, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7354,9 +7380,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:540 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
+    // Pos:542 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM"
     {
-        ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 356, 
+        ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 358, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7368,9 +7394,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:541 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
+    // Pos:543 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 357, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 359, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7382,9 +7408,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:542 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
+    // Pos:544 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 358, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 360, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7396,9 +7422,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:543 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
+    // Pos:545 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 359, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 361, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7410,9 +7436,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:544 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
+    // Pos:546 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM"
     {
-        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 360, 
+        ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 362, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7424,9 +7450,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:545 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
+    // Pos:547 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 363, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 
         0,
@@ -7438,9 +7464,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:546 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
+    // Pos:548 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 364, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7452,9 +7478,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:547 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
+    // Pos:549 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 365, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 
         0,
@@ -7466,9 +7492,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:548 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
+    // Pos:550 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM"
     {
-        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 364, 
+        ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 366, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 
         0,
@@ -7480,9 +7506,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:549 Instruction:"LAHF" Encoding:"0x9F"/""
+    // Pos:551 Instruction:"LAHF" Encoding:"0x9F"/""
     {
-        ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 365, 
+        ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 367, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF,
@@ -7493,9 +7519,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:550 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
+    // Pos:552 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM"
     {
-        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 366, 
+        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 368, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -7507,9 +7533,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:551 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
+    // Pos:553 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM"
     {
-        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 366, 
+        ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 368, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -7521,9 +7547,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:552 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
+    // Pos:554 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM"
     {
-        ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 367, 
+        ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 369, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -7534,9 +7560,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:553 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
+    // Pos:555 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M"
     {
-        ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 368, 
+        ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 370, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -7547,9 +7573,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:554 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
+    // Pos:556 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM"
     {
-        ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 369, 
+        ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 371, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0,
@@ -7561,9 +7587,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:555 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:557 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 370, 
+        ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 372, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -7573,9 +7599,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_oq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:556 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
+    // Pos:558 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM"
     {
-        ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 371, 
+        ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 373, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 
         0,
@@ -7586,9 +7612,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_0, ND_OPF_N, 0, 0), 
     }, 
 
-    // Pos:557 Instruction:"LEAVE" Encoding:"0xC9"/""
+    // Pos:559 Instruction:"LEAVE" Encoding:"0xC9"/""
     {
-        ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 372, 
+        ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 374, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -7601,9 +7627,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:558 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
+    // Pos:560 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM"
     {
-        ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 373, 
+        ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 375, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0,
@@ -7615,9 +7641,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:559 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
+    // Pos:561 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/""
     {
-        ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 374, 
+        ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 376, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
         0,
@@ -7626,9 +7652,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:560 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
+    // Pos:562 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM"
     {
-        ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 375, 
+        ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 377, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -7640,9 +7666,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:561 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
+    // Pos:563 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M"
     {
-        ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 376, 
+        ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 378, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
         0,
@@ -7653,9 +7679,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:562 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
+    // Pos:564 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM"
     {
-        ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 377, 
+        ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 379, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -7667,9 +7693,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:563 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
+    // Pos:565 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M"
     {
-        ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 378, 
+        ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 380, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
         0,
@@ -7680,9 +7706,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:564 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
+    // Pos:566 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M"
     {
-        ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 379, 
+        ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, 
         ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
         0,
@@ -7693,9 +7719,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:565 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
+    // Pos:567 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M"
     {
-        ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 380, 
+        ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 382, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
         0,
@@ -7705,9 +7731,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:566 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
+    // Pos:568 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M"
     {
-        ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 381, 
+        ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 383, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 
         0,
@@ -7718,30 +7744,6 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:567 Instruction:"LOADALL" Encoding:"0x0F 0x05"/""
-    {
-        ND_INS_LOADALL, ND_CAT_UNDOC, ND_SET_I486REAL, 382, 
-        ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
-        0,
-        0,
-        0,
-        0,
-        OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
-    }, 
-
-    // Pos:568 Instruction:"LOADALLD" Encoding:"0x0F 0x07"/""
-    {
-        ND_INS_LOADALLD, ND_CAT_UNDOC, ND_SET_I486REAL, 383, 
-        ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
-        0,
-        0,
-        0,
-        0,
-        OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
-    }, 
-
     // Pos:569 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/""
     {
         ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, 
@@ -8930,9 +8932,22 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:658 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
+    // Pos:658 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 423, 
+        ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 423, 
+        ND_MOD_ANY, 
+        0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
+    }, 
+
+    // Pos:659 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM"
+    {
+        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -8943,9 +8958,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:659 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
+    // Pos:660 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR"
     {
-        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 423, 
+        ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -8956,9 +8971,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:660 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
+    // Pos:661 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM"
     {
-        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 424, 
+        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -8969,9 +8984,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:661 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
+    // Pos:662 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR"
     {
-        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 424, 
+        ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -8982,9 +8997,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:662 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
+    // Pos:663 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM"
     {
-        ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, 
+        ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 426, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -8995,9 +9010,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:663 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
+    // Pos:664 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM"
     {
-        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, 
+        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9008,9 +9023,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:664 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
+    // Pos:665 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR"
     {
-        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 426, 
+        ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9021,22 +9036,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:665 Instruction:"MOVLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM"
-    {
-        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, 
-        ND_MOD_ANY, 
-        0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
-        0,
-        0,
-        0,
-        0,
-        OP(ND_OPT_V, ND_OPS_q, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
-    }, 
-
     // Pos:666 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR"
     {
-        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 427, 
+        ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 428, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9049,7 +9051,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:667 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM"
     {
-        ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 428, 
+        ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 429, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9062,7 +9064,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:668 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM"
     {
-        ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 429, 
+        ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 430, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9075,7 +9077,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:669 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR"
     {
-        ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 430, 
+        ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 431, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9088,7 +9090,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:670 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM"
     {
-        ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 431, 
+        ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 432, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -9101,7 +9103,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:671 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR"
     {
-        ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 432, 
+        ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
         0,
@@ -9114,7 +9116,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:672 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 433, 
+        ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 434, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9127,7 +9129,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:673 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 434, 
+        ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 435, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9140,7 +9142,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:674 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR"
     {
-        ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 435, 
+        ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 436, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -9153,7 +9155,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:675 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 436, 
+        ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 437, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
         0,
@@ -9166,7 +9168,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:676 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR"
     {
-        ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 437, 
+        ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 438, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 
         0,
@@ -9179,7 +9181,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:677 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
         0,
@@ -9192,7 +9194,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:678 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9205,7 +9207,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:679 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -9218,7 +9220,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:680 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -9231,7 +9233,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:681 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9244,7 +9246,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:682 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9257,7 +9259,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:683 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -9270,7 +9272,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:684 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR"
     {
-        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 438, 
+        ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9283,7 +9285,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:685 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM"
     {
-        ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, 
+        ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 440, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9296,7 +9298,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:686 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 440, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9312,7 +9314,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:687 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 440, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9329,7 +9331,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:688 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, 
+        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9342,7 +9344,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:689 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 441, 
+        ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9355,7 +9357,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:690 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9371,7 +9373,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:691 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9388,7 +9390,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:692 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM"
     {
-        ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 442, 
+        ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 443, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -9401,7 +9403,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:693 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM"
     {
-        ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 443, 
+        ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 444, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 
         0,
@@ -9414,7 +9416,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:694 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 444, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9430,7 +9432,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:695 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 444, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9447,7 +9449,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:696 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 445, 
+        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 446, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9460,7 +9462,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:697 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 445, 
+        ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 446, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9473,7 +9475,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:698 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 446, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9489,7 +9491,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:699 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/""
     {
-        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 446, 
+        ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -9506,7 +9508,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:700 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM"
     {
-        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 447, 
+        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 448, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9519,7 +9521,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:701 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM"
     {
-        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 447, 
+        ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 448, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9532,7 +9534,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:702 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM"
     {
-        ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 448, 
+        ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 449, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
         0,
@@ -9545,7 +9547,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:703 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, 
+        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9558,7 +9560,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:704 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 449, 
+        ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 450, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9571,7 +9573,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:705 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM"
     {
-        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, 
+        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 451, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9584,7 +9586,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:706 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR"
     {
-        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 450, 
+        ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 451, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9597,7 +9599,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:707 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM"
     {
-        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 451, 
+        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 452, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9610,7 +9612,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:708 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM"
     {
-        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 451, 
+        ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 452, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9623,7 +9625,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:709 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI"
     {
-        ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 452, 
+        ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 453, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -9637,7 +9639,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:710 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M"
     {
-        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 453, 
+        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 454, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9652,7 +9654,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:711 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M"
     {
-        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 453, 
+        ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 454, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9667,7 +9669,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:712 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 454, 
+        ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 455, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9680,7 +9682,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:713 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 455, 
+        ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 456, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9693,7 +9695,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:714 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 456, 
+        ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 457, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -9706,7 +9708,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:715 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM"
     {
-        ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 457, 
+        ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 458, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -9719,7 +9721,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:716 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM"
     {
-        ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 458, 
+        ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 459, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -9734,7 +9736,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:717 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/""
     {
-        ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 459, 
+        ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 460, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 
         0,
@@ -9747,7 +9749,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:718 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/""
     {
-        ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 460, 
+        ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 461, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9761,7 +9763,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:719 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M"
     {
-        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 461, 
+        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 462, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9774,7 +9776,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:720 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M"
     {
-        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 461, 
+        ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 462, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9787,7 +9789,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:721 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9800,7 +9802,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:722 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9813,7 +9815,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:723 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9826,7 +9828,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:724 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9839,7 +9841,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:725 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9852,7 +9854,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:726 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9865,7 +9867,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:727 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9878,7 +9880,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:728 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9891,7 +9893,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:729 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9903,7 +9905,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:730 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9915,7 +9917,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:731 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9927,7 +9929,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:732 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9939,7 +9941,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:733 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9951,7 +9953,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:734 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9963,7 +9965,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:735 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9975,7 +9977,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:736 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9987,7 +9989,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:737 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -9999,7 +10001,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:738 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10012,7 +10014,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:739 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10025,7 +10027,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:740 Instruction:"NOP Gv,Ev" Encoding:"0xF3 0x0F 0x1B /r:reg"/"RM"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10038,7 +10040,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x66 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10051,7 +10053,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0xF3 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10064,7 +10066,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0xF2 0x0F 0x1C /0:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10077,7 +10079,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:744 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10090,7 +10092,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:745 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /1"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10103,7 +10105,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:746 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /2"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10116,7 +10118,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:747 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /3"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10129,7 +10131,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:748 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /4"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10142,7 +10144,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:749 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /5"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10155,7 +10157,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:750 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /6"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10168,7 +10170,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /7"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10181,7 +10183,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10194,7 +10196,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:753 Instruction:"NOP Mv,Gv" Encoding:"0x0F 0x1E /r:mem"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10207,7 +10209,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:754 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10220,7 +10222,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:755 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10233,7 +10235,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:756 Instruction:"NOP Rv,Gv" Encoding:"rexw 0x0F 0x1E /1:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10246,7 +10248,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:757 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /2:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10259,7 +10261,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:758 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /3:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10272,7 +10274,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:759 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /4:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10285,7 +10287,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:760 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /5:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10298,7 +10300,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:761 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /6:reg"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10311,7 +10313,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:762 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xF8"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10324,7 +10326,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:763 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xF9"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10337,7 +10339,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:764 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFA"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10350,7 +10352,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:765 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFB"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10363,7 +10365,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:766 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFC"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10376,7 +10378,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:767 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFD"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10389,7 +10391,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:768 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFE"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10402,7 +10404,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:769 Instruction:"NOP Rv,Gv" Encoding:"0x0F 0x1E /0xFF"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10415,7 +10417,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:770 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR"
     {
-        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 462, 
+        ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10428,7 +10430,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:771 Instruction:"NOP" Encoding:"0x90"/""
     {
-        ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 462, 
+        ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 463, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -10439,7 +10441,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:772 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M"
     {
-        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 463, 
+        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 464, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10451,7 +10453,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:773 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M"
     {
-        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 463, 
+        ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 464, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10463,7 +10465,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:774 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10477,7 +10479,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:775 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10491,7 +10493,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:776 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10505,7 +10507,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:777 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10519,7 +10521,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:778 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -10533,7 +10535,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:779 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -10547,7 +10549,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:780 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10561,7 +10563,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:781 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10573,23 +10575,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:782 Instruction:"OR Ev,Iz" Encoding:"0x82 /1 iz"/"MI"
+    // Pos:782 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0,
         0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF,
         0|REG_RFLAG_AF,
         0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
     // Pos:783 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI"
     {
-        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 464, 
+        ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -10603,7 +10605,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:784 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM"
     {
-        ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 465, 
+        ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 466, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -10616,7 +10618,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:785 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM"
     {
-        ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 466, 
+        ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 467, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -10629,7 +10631,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:786 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I"
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10643,7 +10645,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:787 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I"
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10657,7 +10659,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:788 Instruction:"OUT DX,AL" Encoding:"0xEE"/""
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10671,7 +10673,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:789 Instruction:"OUT DX,eAX" Encoding:"0xEF"/""
     {
-        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 467, 
+        ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10685,7 +10687,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:790 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 468, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10700,7 +10702,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:791 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 468, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10716,7 +10718,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:792 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10731,7 +10733,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:793 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10747,7 +10749,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:794 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10762,7 +10764,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:795 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/""
     {
-        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, 
+        ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM,
@@ -10778,7 +10780,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:796 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM"
     {
-        ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 471, 
+        ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 472, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -10791,7 +10793,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:797 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM"
     {
-        ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 471, 
+        ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 472, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -10804,7 +10806,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:798 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM"
     {
-        ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 472, 
+        ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 473, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -10817,7 +10819,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:799 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM"
     {
-        ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 472, 
+        ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 473, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -10830,7 +10832,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:800 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM"
     {
-        ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 473, 
+        ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 474, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -10843,7 +10845,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:801 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM"
     {
-        ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 473, 
+        ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 474, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -10856,7 +10858,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:802 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM"
     {
-        ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 474, 
+        ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 475, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -10869,7 +10871,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:803 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM"
     {
-        ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 474, 
+        ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 475, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -10882,7 +10884,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:804 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM"
     {
-        ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 475, 
+        ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 476, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -10895,7 +10897,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:805 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM"
     {
-        ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 475, 
+        ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 476, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -10908,7 +10910,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:806 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM"
     {
-        ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 476, 
+        ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 477, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -10921,7 +10923,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:807 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM"
     {
-        ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 477, 
+        ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 478, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -10934,7 +10936,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:808 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM"
     {
-        ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 477, 
+        ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 478, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -10947,7 +10949,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:809 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM"
     {
-        ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 478, 
+        ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 479, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -10960,7 +10962,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:810 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM"
     {
-        ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 478, 
+        ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 479, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -10973,7 +10975,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:811 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM"
     {
-        ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 479, 
+        ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 480, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -10986,7 +10988,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:812 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM"
     {
-        ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 479, 
+        ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 480, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -10999,7 +11001,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:813 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM"
     {
-        ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 480, 
+        ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 481, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
         0,
@@ -11012,7 +11014,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:814 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM"
     {
-        ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 480, 
+        ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 481, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11025,7 +11027,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:815 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM"
     {
-        ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 481, 
+        ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 482, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11038,7 +11040,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:816 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM"
     {
-        ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 481, 
+        ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 482, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11051,7 +11053,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:817 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM"
     {
-        ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 482, 
+        ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 483, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11064,7 +11066,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:818 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM"
     {
-        ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 482, 
+        ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 483, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11077,7 +11079,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:819 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM"
     {
-        ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 483, 
+        ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 484, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11090,7 +11092,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:820 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM"
     {
-        ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 483, 
+        ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 484, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11103,7 +11105,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:821 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM"
     {
-        ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 484, 
+        ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 485, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11116,7 +11118,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:822 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM"
     {
-        ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 484, 
+        ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 485, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11129,7 +11131,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:823 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM"
     {
-        ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 485, 
+        ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 486, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11142,7 +11144,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:824 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM"
     {
-        ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 485, 
+        ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 486, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11155,7 +11157,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:825 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI"
     {
-        ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 486, 
+        ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 487, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -11169,7 +11171,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:826 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI"
     {
-        ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 486, 
+        ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 487, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -11183,7 +11185,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:827 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM"
     {
-        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 487, 
+        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 488, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11196,7 +11198,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:828 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM"
     {
-        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 487, 
+        ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 488, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11209,7 +11211,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:829 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM"
     {
-        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 488, 
+        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 489, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11222,7 +11224,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:830 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM"
     {
-        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 488, 
+        ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 489, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11235,7 +11237,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:831 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/""
     {
-        ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 489, 
+        ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 490, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -11246,7 +11248,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:832 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM"
     {
-        ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 490, 
+        ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 491, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11259,7 +11261,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:833 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM"
     {
-        ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 490, 
+        ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 491, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11272,7 +11274,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:834 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM"
     {
-        ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 491, 
+        ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 492, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11285,7 +11287,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:835 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM"
     {
-        ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 492, 
+        ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 493, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11298,7 +11300,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:836 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM"
     {
-        ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 492, 
+        ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 493, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11311,7 +11313,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:837 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM"
     {
-        ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 493, 
+        ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 494, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11325,7 +11327,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:838 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI"
     {
-        ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 494, 
+        ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 495, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11339,7 +11341,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:839 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI"
     {
-        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 495, 
+        ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 496, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, 
         0,
@@ -11353,7 +11355,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:840 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 496, 
+        ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 497, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11366,7 +11368,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:841 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM"
     {
-        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 496, 
+        ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 497, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11379,7 +11381,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:842 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 497, 
+        ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 498, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11392,7 +11394,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:843 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM"
     {
-        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 497, 
+        ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 498, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11405,7 +11407,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:844 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM"
     {
-        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 498, 
+        ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 499, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11418,7 +11420,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:845 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 499, 
+        ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 500, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11431,7 +11433,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:846 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM"
     {
-        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 499, 
+        ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 500, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11444,7 +11446,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:847 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 500, 
+        ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 501, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
         0,
@@ -11462,7 +11464,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:848 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI"
     {
-        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 501, 
+        ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 502, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
         0,
@@ -11480,7 +11482,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:849 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 502, 
+        ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 503, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11493,7 +11495,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:850 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM"
     {
-        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 502, 
+        ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 503, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11506,7 +11508,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:851 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 503, 
+        ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 504, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11519,7 +11521,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:852 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM"
     {
-        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 503, 
+        ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 504, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11532,7 +11534,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:853 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM"
     {
-        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 504, 
+        ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 505, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
         0,
@@ -11545,7 +11547,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:854 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 505, 
+        ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 506, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11558,7 +11560,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:855 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM"
     {
-        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 505, 
+        ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 506, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11571,7 +11573,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:856 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 506, 
+        ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 507, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
         0,
@@ -11587,7 +11589,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:857 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI"
     {
-        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 507, 
+        ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 508, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 
         0,
@@ -11603,7 +11605,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:858 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/""
     {
-        ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 508, 
+        ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 509, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, 
         0,
@@ -11614,7 +11616,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:859 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/""
     {
-        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 509, 
+        ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 510, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 
         0,
@@ -11629,7 +11631,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:860 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 510, 
+        ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 511, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -11643,7 +11645,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:861 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM"
     {
-        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 511, 
+        ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 512, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -11657,7 +11659,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:862 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 512, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 513, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11671,7 +11673,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:863 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 512, 
+        ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 513, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11685,7 +11687,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:864 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
     {
-        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 513, 
+        ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 514, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11699,7 +11701,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:865 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI"
     {
-        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 514, 
+        ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 515, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11713,7 +11715,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:866 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 515, 
+        ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 516, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -11727,7 +11729,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:867 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 515, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 516, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -11741,7 +11743,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:868 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 515, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 516, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11755,7 +11757,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:869 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 515, 
+        ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 516, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -11769,7 +11771,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:870 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM"
     {
-        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 516, 
+        ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 517, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11782,7 +11784,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:871 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM"
     {
-        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 517, 
+        ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 518, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11795,7 +11797,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:872 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM"
     {
-        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 518, 
+        ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 519, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11808,7 +11810,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:873 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM"
     {
-        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 519, 
+        ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 520, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11821,7 +11823,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:874 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM"
     {
-        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 520, 
+        ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 521, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11834,7 +11836,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:875 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM"
     {
-        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 521, 
+        ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 522, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11847,7 +11849,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:876 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM"
     {
-        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 522, 
+        ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 523, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11860,7 +11862,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:877 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM"
     {
-        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 523, 
+        ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 524, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11873,7 +11875,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:878 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM"
     {
-        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 524, 
+        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 525, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11884,9 +11886,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:879 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
+    // Pos:879 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
     {
-        ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 524, 
+        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 526, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11897,9 +11899,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:880 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM"
+    // Pos:880 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
     {
-        ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 525, 
+        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 527, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11910,9 +11912,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:881 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM"
+    // Pos:881 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
     {
-        ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 526, 
+        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 528, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11923,9 +11925,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:882 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM"
+    // Pos:882 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM"
     {
-        ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 527, 
+        ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 529, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11938,7 +11940,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:883 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM"
     {
-        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 528, 
+        ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 530, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11951,7 +11953,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:884 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM"
     {
-        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 529, 
+        ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11964,7 +11966,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:885 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM"
     {
-        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 530, 
+        ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11977,7 +11979,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:886 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM"
     {
-        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 531, 
+        ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -11990,7 +11992,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:887 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM"
     {
-        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 532, 
+        ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12003,7 +12005,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:888 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM"
     {
-        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 533, 
+        ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12016,7 +12018,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:889 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM"
     {
-        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 534, 
+        ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12029,7 +12031,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:890 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM"
     {
-        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 535, 
+        ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 537, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12042,7 +12044,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:891 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 536, 
+        ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 538, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12055,7 +12057,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:892 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM"
     {
-        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 536, 
+        ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 538, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12068,7 +12070,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:893 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 537, 
+        ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 539, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12081,7 +12083,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:894 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM"
     {
-        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 537, 
+        ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 539, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12094,7 +12096,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:895 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 538, 
+        ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 540, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12107,7 +12109,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:896 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM"
     {
-        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 538, 
+        ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 540, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12120,7 +12122,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:897 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM"
     {
-        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 539, 
+        ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 541, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12133,7 +12135,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:898 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 540, 
+        ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 542, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12146,7 +12148,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:899 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM"
     {
-        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 540, 
+        ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 542, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12159,7 +12161,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:900 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 541, 
+        ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 543, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12172,7 +12174,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:901 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM"
     {
-        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 541, 
+        ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 543, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12185,7 +12187,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:902 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 542, 
+        ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 544, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12198,7 +12200,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:903 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM"
     {
-        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 542, 
+        ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 544, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12211,7 +12213,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:904 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM"
     {
-        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 543, 
+        ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 545, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12224,7 +12226,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:905 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM"
     {
-        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 544, 
+        ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 546, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12237,7 +12239,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:906 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 545, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 547, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12251,7 +12253,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:907 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 545, 
+        ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 547, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12265,7 +12267,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:908 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 546, 
+        ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 548, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12279,7 +12281,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:909 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI"
     {
-        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 547, 
+        ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 549, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12293,7 +12295,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:910 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 548, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 550, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12307,7 +12309,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:911 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 548, 
+        ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 550, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12321,7 +12323,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:912 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 548, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 550, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12335,7 +12337,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:913 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI"
     {
-        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 548, 
+        ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 550, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12349,7 +12351,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:914 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 549, 
+        ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 551, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12362,7 +12364,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:915 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM"
     {
-        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 549, 
+        ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 551, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12375,7 +12377,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:916 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 550, 
+        ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 552, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12388,7 +12390,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:917 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM"
     {
-        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 550, 
+        ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 552, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12401,7 +12403,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:918 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM"
     {
-        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 551, 
+        ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 553, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12414,7 +12416,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:919 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM"
     {
-        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 552, 
+        ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 554, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12427,7 +12429,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:920 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 553, 
+        ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 555, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12440,7 +12442,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:921 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM"
     {
-        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 553, 
+        ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 555, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12453,7 +12455,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:922 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 554, 
+        ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 556, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12466,7 +12468,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:923 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM"
     {
-        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 554, 
+        ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 556, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12479,7 +12481,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:924 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM"
     {
-        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 555, 
+        ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 557, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12492,7 +12494,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:925 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM"
     {
-        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 556, 
+        ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 558, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12505,7 +12507,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:926 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM"
     {
-        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 557, 
+        ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 559, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12518,7 +12520,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:927 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM"
     {
-        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 558, 
+        ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 560, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12531,7 +12533,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:928 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 559, 
+        ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 561, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12544,7 +12546,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:929 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM"
     {
-        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 559, 
+        ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 561, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12557,7 +12559,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:930 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 560, 
+        ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 562, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12570,7 +12572,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:931 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM"
     {
-        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 560, 
+        ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 562, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12583,7 +12585,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:932 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM"
     {
-        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 561, 
+        ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 563, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12596,7 +12598,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:933 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM"
     {
-        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 562, 
+        ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 564, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12609,7 +12611,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:934 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 563, 
+        ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 565, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -12622,7 +12624,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:935 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM"
     {
-        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 563, 
+        ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 565, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12635,7 +12637,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:936 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM"
     {
-        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 564, 
+        ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 566, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12648,7 +12650,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:937 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM"
     {
-        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 565, 
+        ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 567, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12661,7 +12663,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:938 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM"
     {
-        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 566, 
+        ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 568, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12674,7 +12676,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:939 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM"
     {
-        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 567, 
+        ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 569, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12687,7 +12689,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:940 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM"
     {
-        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 568, 
+        ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 570, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12700,7 +12702,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:941 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM"
     {
-        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 569, 
+        ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 571, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12713,7 +12715,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:942 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM"
     {
-        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 570, 
+        ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 572, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12726,7 +12728,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:943 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM"
     {
-        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 571, 
+        ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 573, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12739,7 +12741,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:944 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM"
     {
-        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 572, 
+        ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 574, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12752,7 +12754,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:945 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM"
     {
-        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 573, 
+        ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 575, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12765,7 +12767,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:946 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM"
     {
-        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 574, 
+        ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 576, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12778,7 +12780,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:947 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM"
     {
-        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 575, 
+        ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 577, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12791,7 +12793,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:948 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM"
     {
-        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 576, 
+        ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 578, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12804,7 +12806,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:949 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 577, 
+        ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 579, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -12817,7 +12819,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:950 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM"
     {
-        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 577, 
+        ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 579, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -12830,7 +12832,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:951 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM"
     {
-        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 578, 
+        ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 580, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -12843,7 +12845,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:952 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 579, 
+        ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 581, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12856,7 +12858,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:953 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM"
     {
-        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 579, 
+        ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 581, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12869,7 +12871,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:954 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 580, 
+        ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 582, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12882,7 +12884,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:955 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM"
     {
-        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 580, 
+        ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 582, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12895,7 +12897,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:956 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM"
     {
-        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 581, 
+        ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 583, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -12908,7 +12910,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:957 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 582, 
+        ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 584, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -12921,7 +12923,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:958 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM"
     {
-        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 582, 
+        ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 584, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12934,7 +12936,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:959 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 583, 
+        ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 585, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
         0,
@@ -12947,7 +12949,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:960 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM"
     {
-        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 583, 
+        ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 585, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -12960,7 +12962,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:961 Instruction:"POP FS" Encoding:"0x0F 0xA1"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -12973,7 +12975,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:962 Instruction:"POP GS" Encoding:"0x0F 0xA9"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -12986,7 +12988,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:963 Instruction:"POP ES" Encoding:"0x07"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -12999,7 +13001,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:964 Instruction:"POP SS" Encoding:"0x17"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -13012,7 +13014,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:965 Instruction:"POP DS" Encoding:"0x1F"/""
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -13025,7 +13027,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:966 Instruction:"POP Zv" Encoding:"0x58"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13038,7 +13040,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:967 Instruction:"POP Zv" Encoding:"0x59"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13051,7 +13053,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:968 Instruction:"POP Zv" Encoding:"0x5A"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13064,7 +13066,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:969 Instruction:"POP Zv" Encoding:"0x5B"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13077,7 +13079,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:970 Instruction:"POP Zv" Encoding:"0x5C"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13090,7 +13092,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:971 Instruction:"POP Zv" Encoding:"0x5D"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13103,7 +13105,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:972 Instruction:"POP Zv" Encoding:"0x5E"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13116,7 +13118,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:973 Instruction:"POP Zv" Encoding:"0x5F"/"O"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13129,7 +13131,7 @@ const ND_INSTRUCTION gInstructions[2554] =
 
     // Pos:974 Instruction:"POP Ev" Encoding:"0x8F /0"/"M"
     {
-        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 584, 
+        ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
         0,
@@ -13140,9 +13142,22 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:975 Instruction:"POPA" Encoding:"0x61"/""
+    // Pos:975 Instruction:"POPA" Encoding:"ds16 0x61"/""
+    {
+        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 587, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
+        0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
+        OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
+    }, 
+
+    // Pos:976 Instruction:"POPAD" Encoding:"ds32 0x61"/""
     {
-        ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 585, 
+        ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 588, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -13153,9 +13168,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:976 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
+    // Pos:977 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM"
     {
-        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 586, 
+        ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 589, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 
         0,
@@ -13167,9 +13182,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:977 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
+    // Pos:978 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 587, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 590, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13180,9 +13195,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:978 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
+    // Pos:979 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 588, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 591, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13193,9 +13208,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:979 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
+    // Pos:980 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/""
     {
-        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 589, 
+        ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 592, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -13206,9 +13221,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:980 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
+    // Pos:981 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 590, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 593, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13219,9 +13234,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:981 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
+    // Pos:982 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM"
     {
-        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 590, 
+        ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 593, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13232,9 +13247,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:982 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
+    // Pos:983 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13244,9 +13259,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:983 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
+    // Pos:984 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13256,9 +13271,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:984 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
+    // Pos:985 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13268,9 +13283,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:985 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
+    // Pos:986 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
     {
-        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591, 
+        ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13280,9 +13295,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:986 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
+    // Pos:987 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
     {
-        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 592, 
+        ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 595, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13292,9 +13307,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:987 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
+    // Pos:988 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
     {
-        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 593, 
+        ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 596, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13304,9 +13319,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:988 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
+    // Pos:989 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
     {
-        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 594, 
+        ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 597, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -13316,9 +13331,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:989 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
+    // Pos:990 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
     {
-        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 595, 
+        ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 598, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -13328,9 +13343,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:990 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
+    // Pos:991 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
     {
-        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 596, 
+        ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 599, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -13340,9 +13355,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:991 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
+    // Pos:992 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
     {
-        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 597, 
+        ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 600, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -13352,9 +13367,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:992 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
+    // Pos:993 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
     {
-        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 598, 
+        ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 601, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13364,9 +13379,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:993 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
+    // Pos:994 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
     {
-        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 599, 
+        ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 602, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -13376,9 +13391,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:994 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
+    // Pos:995 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 600, 
+        ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 603, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13389,9 +13404,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:995 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
+    // Pos:996 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM"
     {
-        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 600, 
+        ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 603, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13402,9 +13417,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:996 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:997 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 601, 
+        ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 604, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -13415,9 +13430,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:997 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
+    // Pos:998 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM"
     {
-        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 601, 
+        ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 604, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -13428,9 +13443,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:998 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
+    // Pos:999 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 602, 
+        ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 605, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13442,9 +13457,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:999 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1000 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 603, 
+        ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 606, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13456,9 +13471,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1000 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1001 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 604, 
+        ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 607, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13470,9 +13485,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1001 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
+    // Pos:1002 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI"
     {
-        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 605, 
+        ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 608, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13484,9 +13499,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1002 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1003 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 606, 
+        ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 609, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -13497,9 +13512,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1003 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
+    // Pos:1004 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM"
     {
-        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 606, 
+        ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 609, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -13510,9 +13525,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1004 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1005 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 607, 
+        ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 610, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -13523,9 +13538,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1005 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
+    // Pos:1006 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM"
     {
-        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 607, 
+        ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 610, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -13536,9 +13551,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1006 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1007 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 608, 
+        ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 611, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 
         0,
@@ -13549,9 +13564,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1007 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
+    // Pos:1008 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM"
     {
-        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 608, 
+        ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 611, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 
         0,
@@ -13562,9 +13577,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1008 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1009 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 609, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 612, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13575,9 +13590,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1009 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
+    // Pos:1010 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 609, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 612, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13588,9 +13603,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1010 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
+    // Pos:1011 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 609, 
+        ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 612, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13601,9 +13616,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1011 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
+    // Pos:1012 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM"
     {
-        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 609, 
+        ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 612, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13614,9 +13629,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1012 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
+    // Pos:1013 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI"
     {
-        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 610, 
+        ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 613, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13627,9 +13642,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1013 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1014 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 611, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 614, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13640,9 +13655,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1014 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
+    // Pos:1015 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 611, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 614, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13653,9 +13668,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1015 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
+    // Pos:1016 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 611, 
+        ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 614, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13666,9 +13681,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1016 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
+    // Pos:1017 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM"
     {
-        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 611, 
+        ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 614, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13679,9 +13694,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1017 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1018 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 612, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 615, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13692,9 +13707,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1018 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
+    // Pos:1019 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 612, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 615, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13705,9 +13720,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1019 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
+    // Pos:1020 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 612, 
+        ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 615, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13718,9 +13733,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1020 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
+    // Pos:1021 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM"
     {
-        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 612, 
+        ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 615, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13731,9 +13746,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1021 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
+    // Pos:1022 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 613, 
+        ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 616, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
         0,
@@ -13744,9 +13759,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1022 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1023 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 614, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 617, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13757,9 +13772,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1023 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
+    // Pos:1024 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 614, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 617, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13770,9 +13785,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1024 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
+    // Pos:1025 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 614, 
+        ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 617, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13783,9 +13798,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1025 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
+    // Pos:1026 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM"
     {
-        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 614, 
+        ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 617, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13796,9 +13811,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1026 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1027 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 615, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 618, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13809,9 +13824,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1027 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
+    // Pos:1028 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 615, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 618, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13822,9 +13837,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1028 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
+    // Pos:1029 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 615, 
+        ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 618, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13835,9 +13850,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1029 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
+    // Pos:1030 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM"
     {
-        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 615, 
+        ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 618, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13848,9 +13863,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1030 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1031 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 616, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 619, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13861,9 +13876,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1031 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
+    // Pos:1032 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 616, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 619, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13874,9 +13889,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1032 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
+    // Pos:1033 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 616, 
+        ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 619, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13887,9 +13902,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1033 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
+    // Pos:1034 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM"
     {
-        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 616, 
+        ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 619, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13900,9 +13915,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1034 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
+    // Pos:1035 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI"
     {
-        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 617, 
+        ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 620, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13913,9 +13928,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1035 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1036 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 618, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 621, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13926,9 +13941,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1036 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
+    // Pos:1037 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 618, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 621, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13939,9 +13954,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1037 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
+    // Pos:1038 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 618, 
+        ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 621, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13952,9 +13967,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1038 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
+    // Pos:1039 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM"
     {
-        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 618, 
+        ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 621, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13965,9 +13980,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1039 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1040 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 619, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 622, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -13978,9 +13993,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1040 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
+    // Pos:1041 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 619, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 622, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -13991,9 +14006,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1041 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
+    // Pos:1042 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 619, 
+        ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 622, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14004,9 +14019,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1042 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
+    // Pos:1043 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM"
     {
-        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 619, 
+        ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 622, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14017,9 +14032,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1043 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
+    // Pos:1044 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 620, 
+        ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 623, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14030,9 +14045,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1044 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
+    // Pos:1045 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM"
     {
-        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 620, 
+        ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 623, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14043,9 +14058,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1045 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
+    // Pos:1046 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 621, 
+        ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 624, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14056,9 +14071,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1046 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
+    // Pos:1047 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM"
     {
-        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 621, 
+        ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 624, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14069,9 +14084,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1047 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
+    // Pos:1048 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 622, 
+        ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 625, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14082,9 +14097,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1048 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
+    // Pos:1049 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM"
     {
-        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 622, 
+        ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 625, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14095,9 +14110,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1049 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
+    // Pos:1050 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 623, 
+        ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 626, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14108,9 +14123,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1050 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
+    // Pos:1051 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM"
     {
-        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 623, 
+        ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 626, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14121,9 +14136,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1051 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
+    // Pos:1052 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 624, 
+        ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 627, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14134,9 +14149,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1052 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
+    // Pos:1053 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM"
     {
-        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 624, 
+        ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 627, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14147,9 +14162,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1053 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
+    // Pos:1054 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 625, 
+        ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 628, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14160,9 +14175,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1054 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
+    // Pos:1055 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM"
     {
-        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 625, 
+        ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 628, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14173,9 +14188,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1055 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
+    // Pos:1056 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 626, 
+        ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 629, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14186,9 +14201,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1056 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
+    // Pos:1057 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM"
     {
-        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 626, 
+        ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 629, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14199,9 +14214,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1057 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
+    // Pos:1058 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 627, 
+        ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 630, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14212,9 +14227,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1058 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
+    // Pos:1059 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM"
     {
-        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 627, 
+        ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 630, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14225,9 +14240,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1059 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
+    // Pos:1060 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM"
     {
-        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 628, 
+        ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 631, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 
         0,
@@ -14238,9 +14253,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1060 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
+    // Pos:1061 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM"
     {
-        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 629, 
+        ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 632, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -14252,9 +14267,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1061 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
+    // Pos:1062 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M"
     {
-        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 630, 
+        ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 633, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, 
         0,
@@ -14264,9 +14279,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1062 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
+    // Pos:1063 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 631, 
+        ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 634, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14277,9 +14292,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1063 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
+    // Pos:1064 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM"
     {
-        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 631, 
+        ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 634, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14290,9 +14305,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1064 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
+    // Pos:1065 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 632, 
+        ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 635, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14303,9 +14318,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1065 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
+    // Pos:1066 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM"
     {
-        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 632, 
+        ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 635, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14316,9 +14331,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1066 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
+    // Pos:1067 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM"
     {
-        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 633, 
+        ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 636, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14329,9 +14344,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1067 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
+    // Pos:1068 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 634, 
+        ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 637, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14342,9 +14357,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1068 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
+    // Pos:1069 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM"
     {
-        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 634, 
+        ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 637, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14355,9 +14370,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1069 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
+    // Pos:1070 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 635, 
+        ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 638, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14368,9 +14383,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1070 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
+    // Pos:1071 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM"
     {
-        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 635, 
+        ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 638, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14381,9 +14396,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1071 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
+    // Pos:1072 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 636, 
+        ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 639, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14394,9 +14409,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1072 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
+    // Pos:1073 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM"
     {
-        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 636, 
+        ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 639, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14407,9 +14422,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1073 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
+    // Pos:1074 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM"
     {
-        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 637, 
+        ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 640, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14420,9 +14435,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1074 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
+    // Pos:1075 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 638, 
+        ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 641, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14433,9 +14448,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1075 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
+    // Pos:1076 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM"
     {
-        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 638, 
+        ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 641, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14446,9 +14461,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1076 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
+    // Pos:1077 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14459,9 +14474,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1077 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
+    // Pos:1078 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14472,9 +14487,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1078 Instruction:"PUSH ES" Encoding:"0x06"/""
+    // Pos:1079 Instruction:"PUSH ES" Encoding:"0x06"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -14485,9 +14500,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1079 Instruction:"PUSH CS" Encoding:"0x0E"/""
+    // Pos:1080 Instruction:"PUSH CS" Encoding:"0x0E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -14498,9 +14513,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1080 Instruction:"PUSH SS" Encoding:"0x16"/""
+    // Pos:1081 Instruction:"PUSH SS" Encoding:"0x16"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -14511,9 +14526,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1081 Instruction:"PUSH DS" Encoding:"0x1E"/""
+    // Pos:1082 Instruction:"PUSH DS" Encoding:"0x1E"/""
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -14524,9 +14539,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1082 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
+    // Pos:1083 Instruction:"PUSH Zv" Encoding:"0x50"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14537,9 +14552,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1083 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
+    // Pos:1084 Instruction:"PUSH Zv" Encoding:"0x51"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14550,9 +14565,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1084 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
+    // Pos:1085 Instruction:"PUSH Zv" Encoding:"0x52"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14563,9 +14578,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1085 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
+    // Pos:1086 Instruction:"PUSH Zv" Encoding:"0x53"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14576,9 +14591,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1086 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
+    // Pos:1087 Instruction:"PUSH Zv" Encoding:"0x54"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14589,9 +14604,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1087 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
+    // Pos:1088 Instruction:"PUSH Zv" Encoding:"0x55"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14602,9 +14617,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1088 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
+    // Pos:1089 Instruction:"PUSH Zv" Encoding:"0x56"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14615,9 +14630,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1089 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
+    // Pos:1090 Instruction:"PUSH Zv" Encoding:"0x57"/"O"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14628,9 +14643,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1090 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
+    // Pos:1091 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14641,9 +14656,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1091 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
+    // Pos:1092 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14654,9 +14669,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1092 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
+    // Pos:1093 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M"
     {
-        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 639, 
+        ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 
         0,
@@ -14667,9 +14682,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1093 Instruction:"PUSHA" Encoding:"0x60"/""
+    // Pos:1094 Instruction:"PUSHA" Encoding:"ds16 0x60"/""
     {
-        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 640, 
+        ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 643, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
         0,
@@ -14680,9 +14695,22 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1094 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
+    // Pos:1095 Instruction:"PUSHAD" Encoding:"ds32 0x60"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 641, 
+        ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 644, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
+        0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
+    }, 
+
+    // Pos:1096 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/""
+    {
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 645, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14693,9 +14721,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1095 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
+    // Pos:1097 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 642, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 646, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14706,9 +14734,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1096 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
+    // Pos:1098 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/""
     {
-        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 643, 
+        ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 647, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 
         0,
@@ -14719,9 +14747,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1097 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
+    // Pos:1099 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/""
     {
-        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 644, 
+        ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 648, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 
         0,
@@ -14734,9 +14762,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1098 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
+    // Pos:1100 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 645, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 649, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 
         0,
@@ -14747,9 +14775,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Q, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1099 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
+    // Pos:1101 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM"
     {
-        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 645, 
+        ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 649, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -14760,9 +14788,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1100 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
+    // Pos:1102 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14774,9 +14802,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1101 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
+    // Pos:1103 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14788,9 +14816,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1102 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
+    // Pos:1104 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14802,9 +14830,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1103 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
+    // Pos:1105 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14816,9 +14844,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1104 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
+    // Pos:1106 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14830,9 +14858,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1105 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
+    // Pos:1107 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC"
     {
-        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 646, 
+        ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14844,9 +14872,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1106 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
+    // Pos:1108 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 647, 
+        ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 651, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -14857,9 +14885,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1107 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
+    // Pos:1109 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM"
     {
-        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 648, 
+        ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 652, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -14870,9 +14898,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1108 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
+    // Pos:1110 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14884,9 +14912,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1109 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
+    // Pos:1111 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14898,9 +14926,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1110 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
+    // Pos:1112 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14912,9 +14940,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1111 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
+    // Pos:1113 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14926,9 +14954,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1112 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
+    // Pos:1114 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14940,9 +14968,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1113 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
+    // Pos:1115 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC"
     {
-        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 649, 
+        ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -14954,9 +14982,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1114 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
+    // Pos:1116 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M"
     {
-        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 650, 
+        ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 654, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
         0,
@@ -14967,9 +14995,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1115 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
+    // Pos:1117 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M"
     {
-        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 651, 
+        ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 655, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
         0,
@@ -14980,9 +15008,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1116 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
+    // Pos:1118 Instruction:"RDMSR" Encoding:"0x0F 0x32"/""
     {
-        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 652, 
+        ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 656, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, 
         0,
@@ -14995,22 +15023,22 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1117 Instruction:"RDPID Rv" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1119 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 653, 
+        ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 657, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_R, ND_OPS_v, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_R, ND_OPS_yf, ND_OPF_W, 0, 0), 
         OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1118 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
+    // Pos:1120 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/""
     {
-        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 654, 
+        ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 658, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
         0,
@@ -15023,9 +15051,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1119 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
+    // Pos:1121 Instruction:"RDPMC" Encoding:"0x0F 0x33"/""
     {
-        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 655, 
+        ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 659, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -15038,9 +15066,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1120 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
+    // Pos:1122 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/""
     {
-        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 656, 
+        ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 660, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 
         0,
@@ -15053,9 +15081,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1121 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
+    // Pos:1123 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 657, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 661, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 
         0,
@@ -15066,9 +15094,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1122 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
+    // Pos:1124 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M"
     {
-        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 657, 
+        ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 661, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 
         0,
@@ -15079,9 +15107,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1123 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
+    // Pos:1125 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 658, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 662, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 
         0,
@@ -15092,9 +15120,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1124 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
+    // Pos:1126 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M"
     {
-        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 658, 
+        ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 662, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 
         0,
@@ -15105,9 +15133,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1125 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
+    // Pos:1127 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M"
     {
-        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 659, 
+        ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 663, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15117,9 +15145,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1126 Instruction:"RDSSPD Rd" Encoding:"a0xF3 0x0F 0x1E /1:reg"/"M"
+    // Pos:1128 Instruction:"RDSSPD Rd" Encoding:"a0xF3 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 660, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 664, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -15130,9 +15158,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1127 Instruction:"RDSSPQ Rq" Encoding:"a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
+    // Pos:1129 Instruction:"RDSSPQ Rq" Encoding:"a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
     {
-        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 661, 
+        ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 665, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -15143,9 +15171,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1128 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
+    // Pos:1130 Instruction:"RDTSC" Encoding:"0x0F 0x31"/""
     {
-        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 662, 
+        ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 666, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -15157,9 +15185,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1129 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
+    // Pos:1131 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/""
     {
-        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 663, 
+        ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 667, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, 
         0,
@@ -15173,25 +15201,25 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1130 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
+    // Pos:1132 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I"
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 664, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 668, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_I, ND_OPS_w, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_w, ND_OPF_R, 0, 0), 
         OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
         OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
         OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1131 Instruction:"RETF" Encoding:"0xCB"/""
+    // Pos:1133 Instruction:"RETF" Encoding:"0xCB"/""
     {
-        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 664, 
+        ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 668, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -15204,25 +15232,25 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1132 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
+    // Pos:1134 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I"
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 665, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 669, 
         ND_MOD_ANY, 
         ND_PREF_BND, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_I, ND_OPS_w, ND_OPF_SEX_DWS|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_w, ND_OPF_R, 0, 0), 
         OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
         OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
         OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
         OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1133 Instruction:"RETN" Encoding:"0xC3"/""
+    // Pos:1135 Instruction:"RETN" Encoding:"0xC3"/""
     {
-        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 665, 
+        ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 669, 
         ND_MOD_ANY, 
         ND_PREF_BND, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 
         0,
@@ -15234,9 +15262,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1134 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
+    // Pos:1136 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 666, 
+        ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 670, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
         0,
@@ -15249,9 +15277,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1135 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
+    // Pos:1137 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/""
     {
-        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 667, 
+        ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 671, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 
         0,
@@ -15263,9 +15291,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1136 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
+    // Pos:1138 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15277,9 +15305,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1137 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
+    // Pos:1139 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15291,9 +15319,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1138 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
+    // Pos:1140 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15305,9 +15333,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1139 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
+    // Pos:1141 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15319,9 +15347,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1140 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
+    // Pos:1142 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15333,9 +15361,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1141 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
+    // Pos:1143 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC"
     {
-        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 668, 
+        ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15347,9 +15375,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1142 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
+    // Pos:1144 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15361,9 +15389,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1143 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
+    // Pos:1145 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15375,9 +15403,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1144 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
+    // Pos:1146 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15389,9 +15417,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1145 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
+    // Pos:1147 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15403,9 +15431,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1146 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
+    // Pos:1148 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15417,9 +15445,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1147 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
+    // Pos:1149 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC"
     {
-        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 669, 
+        ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15431,9 +15459,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1148 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
+    // Pos:1150 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI"
     {
-        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 670, 
+        ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 674, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -15445,9 +15473,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1149 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
+    // Pos:1151 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 671, 
+        ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 675, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -15459,9 +15487,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1150 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
+    // Pos:1152 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI"
     {
-        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 672, 
+        ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 676, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -15473,9 +15501,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1151 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
+    // Pos:1153 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI"
     {
-        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 673, 
+        ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 677, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -15487,9 +15515,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1152 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
+    // Pos:1154 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI"
     {
-        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 674, 
+        ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 678, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 
         0,
@@ -15501,9 +15529,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1153 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
+    // Pos:1155 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM"
     {
-        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 675, 
+        ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 679, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15514,9 +15542,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1154 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
+    // Pos:1156 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M"
     {
-        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 676, 
+        ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 680, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15526,9 +15554,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1155 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
+    // Pos:1157 Instruction:"RSM" Encoding:"0x0F 0xAA"/""
     {
-        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 677, 
+        ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 681, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0,
@@ -15540,9 +15568,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1156 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
+    // Pos:1158 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 678, 
+        ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 682, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -15553,9 +15581,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1157 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
+    // Pos:1159 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM"
     {
-        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 679, 
+        ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 683, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -15566,9 +15594,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1158 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
+    // Pos:1160 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
     {
-        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 680, 
+        ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 684, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -15579,9 +15607,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1159 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
+    // Pos:1161 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M"
     {
-        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 681, 
+        ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 685, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15591,9 +15619,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_s, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1160 Instruction:"SAHF" Encoding:"0x9E"/""
+    // Pos:1162 Instruction:"SAHF" Encoding:"0x9E"/""
     {
-        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 682, 
+        ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 686, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -15604,9 +15632,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1161 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
+    // Pos:1163 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15618,9 +15646,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1162 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
+    // Pos:1164 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15632,9 +15660,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1163 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
+    // Pos:1165 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15646,9 +15674,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1164 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
+    // Pos:1166 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15660,9 +15688,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1165 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
+    // Pos:1167 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15674,9 +15702,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1166 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
+    // Pos:1168 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC"
     {
-        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 683, 
+        ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15688,9 +15716,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1167 Instruction:"SALC" Encoding:"0xD6"/""
+    // Pos:1169 Instruction:"SALC" Encoding:"0xD6"/""
     {
-        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 684, 
+        ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 688, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_CF,
@@ -15701,9 +15729,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1168 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
+    // Pos:1170 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15715,9 +15743,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1169 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
+    // Pos:1171 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15729,9 +15757,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1170 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
+    // Pos:1172 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15743,9 +15771,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1171 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
+    // Pos:1173 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15757,9 +15785,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1172 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
+    // Pos:1174 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15771,9 +15799,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1173 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
+    // Pos:1175 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC"
     {
-        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 685, 
+        ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -15785,9 +15813,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1174 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1176 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 686, 
+        ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 690, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -15799,9 +15827,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1175 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
+    // Pos:1177 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
     {
-        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 687, 
+        ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 691, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0|REG_RFLAG_CF,
@@ -15812,9 +15840,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1176 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
+    // Pos:1178 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15826,9 +15854,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1177 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
+    // Pos:1179 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15840,9 +15868,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1178 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
+    // Pos:1180 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15854,9 +15882,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1179 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
+    // Pos:1181 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15868,9 +15896,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1180 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
+    // Pos:1182 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_CF,
@@ -15882,9 +15910,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1181 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
+    // Pos:1183 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_CF,
@@ -15896,9 +15924,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1182 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
+    // Pos:1184 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15910,9 +15938,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1183 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
+    // Pos:1185 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15924,23 +15952,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1184 Instruction:"SBB Ev,Iz" Encoding:"0x82 /3 iz"/"MI"
+    // Pos:1186 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0|REG_RFLAG_CF,
         0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF,
         0,
         0,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1185 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
+    // Pos:1187 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI"
     {
-        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 688, 
+        ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -15952,9 +15980,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1186 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
+    // Pos:1188 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 689, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -15967,9 +15995,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1187 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
+    // Pos:1189 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 689, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_ZF|REG_RFLAG_DF,
@@ -15983,9 +16011,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1188 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
+    // Pos:1190 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 690, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -15998,9 +16026,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1189 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
+    // Pos:1191 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 690, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_ZF|REG_RFLAG_DF,
@@ -16014,9 +16042,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1190 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
+    // Pos:1192 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 691, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -16029,9 +16057,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1191 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
+    // Pos:1193 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 691, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_ZF|REG_RFLAG_DF,
@@ -16045,9 +16073,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1192 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
+    // Pos:1194 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 692, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -16060,9 +16088,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1193 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
+    // Pos:1195 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/""
     {
-        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 692, 
+        ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, 
         ND_MOD_ANY, 
         ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_ZF|REG_RFLAG_DF,
@@ -16076,9 +16104,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1194 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
+    // Pos:1196 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 693, 
+        ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 697, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SERIALIZE, 
         0,
@@ -16087,9 +16115,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1195 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
+    // Pos:1197 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 694, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 698, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_ZF,
@@ -16100,9 +16128,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1196 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
+    // Pos:1198 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 695, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 699, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -16113,9 +16141,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1197 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
+    // Pos:1199 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 696, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 700, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_OF,
@@ -16126,9 +16154,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1198 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
+    // Pos:1200 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 697, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF,
@@ -16139,9 +16167,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1199 Instruction:"SETNB Eb" Encoding:"0x0F 0x97 /r"/"M"
+    // Pos:1201 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 698, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF|REG_RFLAG_ZF,
@@ -16152,9 +16180,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1200 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
+    // Pos:1202 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 699, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_CF,
@@ -16165,9 +16193,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1201 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
+    // Pos:1203 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 700, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_OF,
@@ -16178,9 +16206,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1202 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
+    // Pos:1204 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF,
@@ -16191,9 +16219,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1203 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
+    // Pos:1205 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_OF,
@@ -16204,9 +16232,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1204 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
+    // Pos:1206 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_PF,
@@ -16217,9 +16245,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1205 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
+    // Pos:1207 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_SF,
@@ -16230,9 +16258,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1206 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
+    // Pos:1208 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 709, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_ZF,
@@ -16243,9 +16271,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1207 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
+    // Pos:1209 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_OF,
@@ -16256,9 +16284,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1208 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
+    // Pos:1210 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 711, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_PF,
@@ -16269,9 +16297,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1209 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
+    // Pos:1211 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_SF,
@@ -16282,9 +16310,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1210 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
+    // Pos:1212 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 709, 
+        ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 713, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -16295,9 +16323,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1211 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
+    // Pos:1213 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M"
     {
-        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, 
+        ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 
         0|REG_RFLAG_ZF,
@@ -16308,9 +16336,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1212 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
+    // Pos:1214 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/""
     {
-        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 711, 
+        ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 715, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 
         0,
@@ -16319,9 +16347,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1213 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
+    // Pos:1215 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M"
     {
-        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 712, 
+        ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 716, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16332,9 +16360,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1214 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
+    // Pos:1216 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM"
     {
-        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 713, 
+        ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 717, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16345,9 +16373,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1215 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
+    // Pos:1217 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM"
     {
-        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 714, 
+        ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 718, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16358,9 +16386,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1216 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
+    // Pos:1218 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM"
     {
-        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 715, 
+        ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 719, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16371,9 +16399,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1217 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
+    // Pos:1219 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI"
     {
-        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 716, 
+        ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 720, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16385,9 +16413,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1218 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
+    // Pos:1220 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM"
     {
-        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 717, 
+        ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 721, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16398,9 +16426,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1219 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
+    // Pos:1221 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM"
     {
-        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 718, 
+        ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 722, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16411,9 +16439,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1220 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
+    // Pos:1222 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM"
     {
-        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 719, 
+        ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 723, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 
         0,
@@ -16425,9 +16453,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1221 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
+    // Pos:1223 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16439,9 +16467,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1222 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
+    // Pos:1224 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16453,9 +16481,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1223 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
+    // Pos:1225 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16467,9 +16495,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1224 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
+    // Pos:1226 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16481,9 +16509,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1225 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
+    // Pos:1227 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16495,9 +16523,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1226 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
+    // Pos:1228 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC"
     {
-        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 720, 
+        ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16509,9 +16537,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1227 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
+    // Pos:1229 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 721, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 725, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16524,9 +16552,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1228 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
+    // Pos:1230 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC"
     {
-        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 721, 
+        ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 725, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16539,9 +16567,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1229 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1231 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 722, 
+        ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 726, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -16553,9 +16581,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1230 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
+    // Pos:1232 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16567,9 +16595,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1231 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
+    // Pos:1233 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16581,9 +16609,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1232 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
+    // Pos:1234 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16595,9 +16623,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1233 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
+    // Pos:1235 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16609,9 +16637,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1234 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
+    // Pos:1236 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16623,9 +16651,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1235 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
+    // Pos:1237 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC"
     {
-        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 723, 
+        ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16637,9 +16665,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1236 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
+    // Pos:1238 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 724, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 728, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16652,9 +16680,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1237 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
+    // Pos:1239 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC"
     {
-        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 724, 
+        ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 728, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16667,9 +16695,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1238 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
+    // Pos:1240 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV"
     {
-        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 725, 
+        ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 729, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 
         0,
@@ -16681,9 +16709,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_B, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1239 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1241 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 726, 
+        ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 730, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -16695,9 +16723,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1240 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
+    // Pos:1242 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI"
     {
-        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 727, 
+        ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 731, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -16709,9 +16737,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1241 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
+    // Pos:1243 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M"
     {
-        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 728, 
+        ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 732, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16722,9 +16750,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1242 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
+    // Pos:1244 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/""
     {
-        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 729, 
+        ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 733, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -16734,9 +16762,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1243 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
+    // Pos:1245 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 730, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 734, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16747,9 +16775,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1244 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
+    // Pos:1246 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M"
     {
-        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 730, 
+        ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 734, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16760,9 +16788,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1245 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
+    // Pos:1247 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M"
     {
-        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 731, 
+        ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 735, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 
         0,
@@ -16772,9 +16800,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1246 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
+    // Pos:1248 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/""
     {
-        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 732, 
+        ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 736, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -16783,9 +16811,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1247 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
+    // Pos:1249 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 737, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16796,9 +16824,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1248 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
+    // Pos:1250 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M"
     {
-        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 733, 
+        ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 737, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16809,9 +16837,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1249 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
+    // Pos:1251 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M"
     {
-        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 734, 
+        ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 738, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -16821,9 +16849,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1250 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
+    // Pos:1252 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 735, 
+        ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 739, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -16834,9 +16862,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1251 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
+    // Pos:1253 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 736, 
+        ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 740, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -16847,9 +16875,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1252 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
+    // Pos:1254 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 737, 
+        ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 741, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -16860,9 +16888,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1253 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
+    // Pos:1255 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM"
     {
-        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 738, 
+        ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 742, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -16873,9 +16901,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1254 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
+    // Pos:1256 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/""
     {
-        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 739, 
+        ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 743, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 
         0,
@@ -16885,9 +16913,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1255 Instruction:"STC" Encoding:"0xF9"/""
+    // Pos:1257 Instruction:"STC" Encoding:"0xF9"/""
     {
-        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 740, 
+        ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 744, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -16897,9 +16925,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1256 Instruction:"STD" Encoding:"0xFD"/""
+    // Pos:1258 Instruction:"STD" Encoding:"0xFD"/""
     {
-        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 741, 
+        ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 745, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -16909,9 +16937,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1257 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
+    // Pos:1259 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/""
     {
-        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 742, 
+        ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 746, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -16920,9 +16948,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1258 Instruction:"STI" Encoding:"0xFB"/""
+    // Pos:1260 Instruction:"STI" Encoding:"0xFB"/""
     {
-        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 743, 
+        ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 747, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -16932,9 +16960,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1259 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
+    // Pos:1261 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M"
     {
-        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 744, 
+        ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 748, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 
         0,
@@ -16945,9 +16973,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1260 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
+    // Pos:1262 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 745, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 749, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -16960,9 +16988,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1261 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
+    // Pos:1263 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 745, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 749, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -16976,9 +17004,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1262 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
+    // Pos:1264 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 746, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 750, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -16991,9 +17019,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1263 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
+    // Pos:1265 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 746, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 750, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -17007,9 +17035,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1264 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
+    // Pos:1266 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 747, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 751, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -17022,9 +17050,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1265 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
+    // Pos:1267 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 747, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 751, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -17038,9 +17066,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1266 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
+    // Pos:1268 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 748, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -17053,9 +17081,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1267 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
+    // Pos:1269 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/""
     {
-        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 748, 
+        ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 
         0|REG_RFLAG_DF,
@@ -17069,9 +17097,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1268 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
+    // Pos:1270 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 753, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17082,9 +17110,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1269 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
+    // Pos:1271 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M"
     {
-        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 749, 
+        ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 753, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17095,9 +17123,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1270 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
+    // Pos:1272 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M"
     {
-        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 750, 
+        ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 754, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -17107,9 +17135,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_oq, ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1271 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
+    // Pos:1273 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17121,9 +17149,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1272 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
+    // Pos:1274 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17135,9 +17163,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1273 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
+    // Pos:1275 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17149,9 +17177,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1274 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
+    // Pos:1276 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17163,9 +17191,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1275 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
+    // Pos:1277 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -17177,9 +17205,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1276 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
+    // Pos:1278 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -17191,9 +17219,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1277 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
+    // Pos:1279 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17205,9 +17233,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1278 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
+    // Pos:1280 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17219,23 +17247,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1279 Instruction:"SUB Ev,Iz" Encoding:"0x82 /5 iz"/"MI"
+    // Pos:1281 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0,
         0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF,
         0,
         0,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1280 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
+    // Pos:1282 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI"
     {
-        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 751, 
+        ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17247,9 +17275,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1281 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
+    // Pos:1283 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 752, 
+        ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 756, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -17260,9 +17288,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1282 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
+    // Pos:1284 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 753, 
+        ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 757, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -17273,9 +17301,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1283 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
+    // Pos:1285 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 754, 
+        ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 758, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -17286,9 +17314,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1284 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
+    // Pos:1286 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM"
     {
-        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 755, 
+        ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 759, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -17299,9 +17327,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1285 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
+    // Pos:1287 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR"
     {
-        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 756, 
+        ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 760, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17312,9 +17340,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_S, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1286 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
+    // Pos:1288 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M"
     {
-        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 757, 
+        ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 761, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17324,9 +17352,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1287 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
+    // Pos:1289 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M"
     {
-        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 758, 
+        ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 762, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17336,9 +17364,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_s, ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1288 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
+    // Pos:1290 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/""
     {
-        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 759, 
+        ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 763, 
         ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 
         0,
@@ -17349,11 +17377,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1289 Instruction:"SYSCALL" Encoding:"o64 0x0F 0x05"/""
+    // Pos:1291 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/""
     {
-        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 760, 
-        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
-        0, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_O64, ND_CFF_FSC, 
+        ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 764, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
+        0, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_FSC, 
         0,
         0,
         0,
@@ -17370,9 +17398,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1290 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
+    // Pos:1292 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/""
     {
-        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 761, 
+        ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 765, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, 
         0,
@@ -17390,9 +17418,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1291 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
+    // Pos:1293 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/""
     {
-        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 762, 
+        ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 766, 
         ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, 
         0,
@@ -17406,11 +17434,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1292 Instruction:"SYSRET" Encoding:"o64 0x0F 0x07"/""
+    // Pos:1294 Instruction:"SYSRET" Encoding:"0x0F 0x07"/""
     {
-        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 763, 
-        ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
-        0, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, ND_FLAG_O64, ND_CFF_FSC, 
+        ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 767, 
+        ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
+        0, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, 
         0,
         0,
         0,
@@ -17425,9 +17453,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1293 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
+    // Pos:1295 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM"
     {
-        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 764, 
+        ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 768, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
         0,
@@ -17438,9 +17466,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1294 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
+    // Pos:1296 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/""
     {
-        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 765, 
+        ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 769, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, 
         0,
@@ -17452,9 +17480,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1295 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1297 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 766, 
+        ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 770, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
         0,
@@ -17466,9 +17494,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1296 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1298 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 767, 
+        ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 771, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
         0,
@@ -17480,9 +17508,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1297 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1299 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 768, 
+        ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 772, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
         0,
@@ -17494,9 +17522,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1298 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
+    // Pos:1300 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/""
     {
-        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 769, 
+        ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 773, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 
         0,
@@ -17508,9 +17536,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_vT, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1299 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
+    // Pos:1301 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17522,9 +17550,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1300 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
+    // Pos:1302 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17536,9 +17564,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1301 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
+    // Pos:1303 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -17550,9 +17578,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1302 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
+    // Pos:1304 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -17564,9 +17592,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1303 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
+    // Pos:1305 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17578,9 +17606,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1304 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
+    // Pos:1306 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17592,9 +17620,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1305 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
+    // Pos:1307 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17606,9 +17634,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1306 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
+    // Pos:1308 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI"
     {
-        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 770, 
+        ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17620,9 +17648,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1307 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1309 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 771, 
+        ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 775, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -17633,9 +17661,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1308 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1310 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 772, 
+        ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 776, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -17646,9 +17674,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1309 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
+    // Pos:1311 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/""
     {
-        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 773, 
+        ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 777, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -17657,9 +17685,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1310 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
+    // Pos:1312 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M"
     {
-        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 774, 
+        ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 778, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -17670,9 +17698,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_rT, ND_OPS_t, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1311 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
+    // Pos:1313 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/""
     {
-        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 775, 
+        ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 779, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 
         0,
@@ -17682,9 +17710,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_rT, ND_OPS_t, ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1312 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
+    // Pos:1314 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/""
     {
-        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 776, 
+        ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 780, 
         ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 
         0,
@@ -17693,9 +17721,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1313 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
+    // Pos:1315 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 777, 
+        ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 781, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
         0,
@@ -17708,9 +17736,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1314 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
+    // Pos:1316 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM"
     {
-        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 778, 
+        ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 782, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 
         0,
@@ -17722,9 +17750,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1315 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
+    // Pos:1317 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM"
     {
-        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 779, 
+        ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 783, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 
         0,
@@ -17735,9 +17763,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1316 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
+    // Pos:1318 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 780, 
+        ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 784, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -17749,9 +17777,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1317 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
+    // Pos:1319 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM"
     {
-        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 781, 
+        ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 785, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -17763,9 +17791,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1318 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
+    // Pos:1320 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM"
     {
-        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 782, 
+        ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 786, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17776,9 +17804,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1319 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
+    // Pos:1321 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM"
     {
-        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 783, 
+        ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 787, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -17789,9 +17817,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1320 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
+    // Pos:1322 Instruction:"UD2" Encoding:"0x0F 0x0B"/""
     {
-        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 784, 
+        ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 788, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -17800,9 +17828,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1321 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
+    // Pos:1323 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 785, 
+        ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 789, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
         0,
@@ -17813,9 +17841,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1322 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
+    // Pos:1324 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M"
     {
-        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 786, 
+        ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 790, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 
         0,
@@ -17827,9 +17855,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1323 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
+    // Pos:1325 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 787, 
+        ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 791, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -17840,9 +17868,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1324 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
+    // Pos:1326 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM"
     {
-        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 788, 
+        ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 792, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -17853,9 +17881,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1325 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
+    // Pos:1327 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 789, 
+        ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 793, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -17866,9 +17894,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1326 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
+    // Pos:1328 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM"
     {
-        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 790, 
+        ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 794, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -17879,9 +17907,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1327 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
+    // Pos:1329 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 791, 
+        ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 795, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
         0,
@@ -17894,9 +17922,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1328 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
+    // Pos:1330 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM"
     {
-        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 792, 
+        ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 796, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
         0,
@@ -17909,9 +17937,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1329 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
+    // Pos:1331 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 793, 
+        ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 797, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
         0,
@@ -17924,9 +17952,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1330 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
+    // Pos:1332 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM"
     {
-        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 794, 
+        ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 798, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 
         0,
@@ -17939,9 +17967,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1331 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
+    // Pos:1333 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 795, 
+        ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 799, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -17954,9 +17982,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1332 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1334 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 795, 
+        ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 799, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -17968,9 +17996,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1333 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
+    // Pos:1335 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 796, 
+        ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 800, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -17983,9 +18011,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1334 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
+    // Pos:1336 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 796, 
+        ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 800, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -17997,9 +18025,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1335 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
+    // Pos:1337 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 797, 
+        ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 801, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18012,9 +18040,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1336 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1338 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 797, 
+        ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 801, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18026,9 +18054,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1337 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
+    // Pos:1339 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 798, 
+        ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 802, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18041,9 +18069,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1338 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
+    // Pos:1340 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM"
     {
-        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 798, 
+        ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 802, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18055,9 +18083,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1339 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1341 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 799, 
+        ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 803, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18069,9 +18097,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1340 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
+    // Pos:1342 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM"
     {
-        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 800, 
+        ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 804, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18083,9 +18111,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1341 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1343 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 801, 
+        ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 805, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
         0,
@@ -18097,9 +18125,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1342 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:1344 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 801, 
+        ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 805, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
         0,
@@ -18111,9 +18139,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1343 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1345 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 802, 
+        ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 806, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
         0,
@@ -18125,9 +18153,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1344 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1346 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 802, 
+        ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 806, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
         0,
@@ -18139,9 +18167,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1345 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1347 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 803, 
+        ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 807, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
         0,
@@ -18153,9 +18181,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1346 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1348 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 803, 
+        ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 807, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
         0,
@@ -18167,9 +18195,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1347 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1349 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 804, 
+        ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 808, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 
         0,
@@ -18181,9 +18209,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1348 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1350 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 804, 
+        ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 808, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
         0,
@@ -18195,9 +18223,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1349 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
+    // Pos:1351 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM"
     {
-        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 805, 
+        ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 809, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
         0,
@@ -18208,9 +18236,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1350 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
+    // Pos:1352 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI"
     {
-        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 806, 
+        ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 810, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 
         0,
@@ -18222,9 +18250,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1351 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
+    // Pos:1353 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 807, 
+        ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 811, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18238,9 +18266,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1352 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
+    // Pos:1354 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI"
     {
-        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 808, 
+        ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 812, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18254,9 +18282,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1353 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
+    // Pos:1355 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 809, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 813, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18269,9 +18297,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1354 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1356 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 809, 
+        ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 813, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18283,9 +18311,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1355 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
+    // Pos:1357 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 810, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 814, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18298,9 +18326,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1356 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
+    // Pos:1358 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM"
     {
-        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 810, 
+        ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 814, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18312,9 +18340,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1357 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
+    // Pos:1359 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 811, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 815, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18327,9 +18355,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1358 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1360 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 811, 
+        ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 815, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18341,9 +18369,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1359 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
+    // Pos:1361 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 812, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 816, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18356,9 +18384,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1360 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
+    // Pos:1362 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM"
     {
-        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 812, 
+        ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 816, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18370,9 +18398,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1361 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
+    // Pos:1363 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 813, 
+        ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 817, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18385,9 +18413,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1362 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
+    // Pos:1364 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM"
     {
-        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 814, 
+        ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 818, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18400,9 +18428,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1363 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
+    // Pos:1365 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 815, 
+        ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 819, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18415,9 +18443,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1364 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
+    // Pos:1366 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI"
     {
-        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 816, 
+        ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 820, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18430,9 +18458,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1365 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
+    // Pos:1367 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 817, 
+        ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 821, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18445,9 +18473,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1366 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
+    // Pos:1368 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML"
     {
-        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 818, 
+        ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 822, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18460,9 +18488,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1367 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
+    // Pos:1369 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 819, 
+        ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 823, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18473,9 +18501,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1368 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
+    // Pos:1370 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 820, 
+        ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 824, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18487,9 +18515,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1369 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
+    // Pos:1371 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 821, 
+        ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 825, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18501,9 +18529,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1370 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
+    // Pos:1372 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 822, 
+        ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 826, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18515,9 +18543,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1371 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
+    // Pos:1373 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 823, 
+        ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 827, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18529,9 +18557,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1372 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
+    // Pos:1374 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 824, 
+        ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 828, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18543,9 +18571,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1373 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
+    // Pos:1375 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM"
     {
-        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 825, 
+        ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 829, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -18556,9 +18584,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1374 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
+    // Pos:1376 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM"
     {
-        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 826, 
+        ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 830, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18570,9 +18598,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1375 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
+    // Pos:1377 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 827, 
+        ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 831, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18584,9 +18612,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1376 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
+    // Pos:1378 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 828, 
+        ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 832, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18598,9 +18626,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1377 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
+    // Pos:1379 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 829, 
+        ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 833, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -18612,9 +18640,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1378 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
+    // Pos:1380 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM"
     {
-        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 830, 
+        ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 834, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18626,9 +18654,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1379 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
+    // Pos:1381 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 831, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 835, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18640,9 +18668,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1380 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
+    // Pos:1382 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM"
     {
-        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 831, 
+        ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 835, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18653,9 +18681,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1381 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
+    // Pos:1383 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 832, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 836, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18667,9 +18695,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1382 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
+    // Pos:1384 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM"
     {
-        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 832, 
+        ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 836, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18680,9 +18708,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1383 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1385 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 833, 
+        ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 837, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18696,9 +18724,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1384 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1386 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 833, 
+        ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 837, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18711,9 +18739,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1385 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1387 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 834, 
+        ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 838, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18727,9 +18755,24 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1386 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
+    // Pos:1388 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 835, 
+        ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 838, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
+        0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
+    }, 
+
+    // Pos:1389 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI"
+    {
+        ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 839, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18743,9 +18786,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1387 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1390 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 835, 
+        ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 839, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18758,9 +18801,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1388 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
+    // Pos:1391 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 836, 
+        ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 840, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18774,24 +18817,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1389 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI"
-    {
-        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 836, 
-        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
-        0,
-        0,
-        0,
-        0,
-        OP(ND_OPT_V, ND_OPS_ss, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_ss, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
-    }, 
-
-    // Pos:1390 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
+    // Pos:1392 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI"
     {
-        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 836, 
+        ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 840, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18804,9 +18832,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1391 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
+    // Pos:1393 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 837, 
+        ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 841, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18818,9 +18846,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1392 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
+    // Pos:1394 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 837, 
+        ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 841, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18832,9 +18860,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1393 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
+    // Pos:1395 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 838, 
+        ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 842, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18846,9 +18874,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1394 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
+    // Pos:1396 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM"
     {
-        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 838, 
+        ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 842, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18860,9 +18888,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1395 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
+    // Pos:1397 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 839, 
+        ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 843, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18874,9 +18902,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1396 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
+    // Pos:1398 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR"
     {
-        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 840, 
+        ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 844, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18888,11 +18916,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1397 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
+    // Pos:1399 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 841, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 845, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
+        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
         0,
         0,
@@ -18902,9 +18930,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1398 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
+    // Pos:1400 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 841, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 845, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18915,9 +18943,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1399 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
+    // Pos:1401 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 841, 
+        ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 845, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18928,9 +18956,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1400 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1402 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 842, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 846, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18942,9 +18970,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1401 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
+    // Pos:1403 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 842, 
+        ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -18955,9 +18983,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1402 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
+    // Pos:1404 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM"
     {
-        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 843, 
+        ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 847, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
         0,
@@ -18970,23 +18998,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1403 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
+    // Pos:1405 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM"
     {
-        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 844, 
+        ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 848, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
+        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
         0,
         0,
         0,
         0,
         OP(ND_OPT_V, ND_OPS_h, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1404 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1406 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 845, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 849, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -18998,9 +19026,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1405 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1407 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 845, 
+        ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 849, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19011,9 +19039,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1406 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
+    // Pos:1408 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 846, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19025,9 +19053,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1407 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1409 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 850, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19038,9 +19066,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1408 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1410 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, 
+        ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 850, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19051,9 +19079,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1409 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
+    // Pos:1411 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 847, 
+        ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 851, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19065,9 +19093,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1410 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1412 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 848, 
+        ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 852, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19079,11 +19107,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1411 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
+    // Pos:1413 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 849, 
+        ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 853, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
+        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
         0,
         0,
@@ -19093,9 +19121,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1412 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
+    // Pos:1414 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 854, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19107,9 +19135,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1413 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
+    // Pos:1415 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 850, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 854, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
         0,
@@ -19120,9 +19148,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1414 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
+    // Pos:1416 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM"
     {
-        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 850, 
+        ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 854, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
         0,
@@ -19133,9 +19161,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1415 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1417 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 851, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 855, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19147,9 +19175,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1416 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
+    // Pos:1418 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 851, 
+        ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 855, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19160,9 +19188,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1417 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
+    // Pos:1419 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 852, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 856, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19174,9 +19202,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1418 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
+    // Pos:1420 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 852, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 856, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19187,9 +19215,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1419 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
+    // Pos:1421 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM"
     {
-        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 852, 
+        ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 856, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19200,9 +19228,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1420 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
+    // Pos:1422 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 853, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 857, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19215,9 +19243,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1421 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
+    // Pos:1423 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 853, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 857, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
         0,
@@ -19229,9 +19257,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1422 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
+    // Pos:1424 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI"
     {
-        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 853, 
+        ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 857, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 
         0,
@@ -19243,9 +19271,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1423 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
+    // Pos:1425 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM"
     {
-        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 854, 
+        ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 858, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19257,9 +19285,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1424 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1426 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 855, 
+        ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 859, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19271,9 +19299,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1425 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1427 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 856, 
+        ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 860, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19285,9 +19313,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1426 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1428 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 857, 
+        ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 861, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19299,9 +19327,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1427 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
+    // Pos:1429 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 858, 
+        ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 862, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19313,9 +19341,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1428 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1430 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 859, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 863, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19326,9 +19354,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1429 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
+    // Pos:1431 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 859, 
+        ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 863, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19339,9 +19367,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1430 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
+    // Pos:1432 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 860, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 864, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19354,9 +19382,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1431 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1433 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 860, 
+        ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 864, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19368,9 +19396,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1432 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
+    // Pos:1434 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 861, 
+        ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 865, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19381,23 +19409,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1433 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
+    // Pos:1435 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 862, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 866, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
+        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
         0,
         0,
         0,
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), 
+        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1434 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
+    // Pos:1436 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 862, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 866, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19409,9 +19437,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1435 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1437 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 862, 
+        ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 866, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19423,9 +19451,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1436 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1438 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 863, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 867, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19437,9 +19465,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1437 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
+    // Pos:1439 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM"
     {
-        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 863, 
+        ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 867, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19451,9 +19479,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1438 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
+    // Pos:1440 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 864, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 868, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19466,9 +19494,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1439 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
+    // Pos:1441 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM"
     {
-        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 864, 
+        ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 868, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19480,9 +19508,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1440 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1442 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 865, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 869, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19493,9 +19521,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1441 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
+    // Pos:1443 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM"
     {
-        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 865, 
+        ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 869, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19506,9 +19534,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1442 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
+    // Pos:1444 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM"
     {
-        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 866, 
+        ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 870, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19519,9 +19547,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1443 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
+    // Pos:1445 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 867, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19533,9 +19561,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1444 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
+    // Pos:1446 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM"
     {
-        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 867, 
+        ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 871, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19546,9 +19574,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1445 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1447 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 868, 
+        ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19560,9 +19588,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1446 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1448 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 869, 
+        ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 873, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19574,9 +19602,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1447 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
+    // Pos:1449 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 870, 
+        ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 874, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19588,9 +19616,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1448 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
+    // Pos:1450 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 875, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19602,9 +19630,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1449 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
+    // Pos:1451 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM"
     {
-        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 871, 
+        ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 875, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19615,9 +19643,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1450 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1452 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, 
+        ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 876, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19629,9 +19657,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1451 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1453 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 873, 
+        ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 877, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19643,9 +19671,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1452 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1454 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 874, 
+        ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 878, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19657,9 +19685,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1453 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1455 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 875, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 879, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19670,9 +19698,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1454 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
+    // Pos:1456 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 875, 
+        ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 879, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19683,9 +19711,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1455 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
+    // Pos:1457 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 876, 
+        ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 880, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19696,9 +19724,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1456 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1458 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 877, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 881, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19709,9 +19737,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1457 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
+    // Pos:1459 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM"
     {
-        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 877, 
+        ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 881, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19722,9 +19750,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1458 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
+    // Pos:1460 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM"
     {
-        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 878, 
+        ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 882, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19735,11 +19763,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1459 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1461 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 879, 
+        ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
+        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
         0,
         0,
@@ -19749,9 +19777,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1460 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
+    // Pos:1462 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 880, 
+        ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 884, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19763,9 +19791,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1461 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1463 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 881, 
+        ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 885, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19777,9 +19805,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1462 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
+    // Pos:1464 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM"
     {
-        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, 
+        ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 886, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -19791,23 +19819,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1463 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
+    // Pos:1465 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
+        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
         0,
         0,
         0,
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, ND_OPD_ER, 0), 
+        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1464 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
+    // Pos:1466 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, 
+        ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19819,9 +19847,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1465 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
+    // Pos:1467 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM"
     {
-        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 884, 
+        ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 888, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19833,9 +19861,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1466 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
+    // Pos:1468 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI"
     {
-        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 885, 
+        ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 889, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -19849,9 +19877,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1467 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
+    // Pos:1469 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 886, 
+        ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 890, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19864,9 +19892,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1468 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1470 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 886, 
+        ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 890, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19878,9 +19906,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1469 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
+    // Pos:1471 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 887, 
+        ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 891, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19893,9 +19921,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1470 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
+    // Pos:1472 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 887, 
+        ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 891, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19907,9 +19935,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1471 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
+    // Pos:1473 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 888, 
+        ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 892, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19922,9 +19950,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1472 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1474 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 888, 
+        ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 892, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19936,9 +19964,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1473 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
+    // Pos:1475 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 889, 
+        ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 893, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -19951,9 +19979,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1474 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
+    // Pos:1476 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM"
     {
-        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 889, 
+        ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 893, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19965,9 +19993,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1475 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:1477 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 890, 
+        ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 894, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 
         0,
@@ -19980,9 +20008,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1476 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
+    // Pos:1478 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI"
     {
-        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 891, 
+        ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 895, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -19995,9 +20023,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1477 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
+    // Pos:1479 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI"
     {
-        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 892, 
+        ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 896, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -20010,9 +20038,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1478 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
+    // Pos:1480 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M"
     {
-        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 893, 
+        ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 897, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -20023,9 +20051,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1479 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
+    // Pos:1481 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M"
     {
-        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 894, 
+        ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 898, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -20036,9 +20064,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1480 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
+    // Pos:1482 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 895, 
+        ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 899, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -20050,9 +20078,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1481 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
+    // Pos:1483 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM"
     {
-        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 896, 
+        ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 900, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -20064,9 +20092,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1482 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
+    // Pos:1484 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 897, 
+        ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 901, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20078,9 +20106,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1483 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
+    // Pos:1485 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM"
     {
-        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 898, 
+        ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 902, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20092,9 +20120,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1484 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
+    // Pos:1486 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 899, 
+        ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 903, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -20106,9 +20134,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1485 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
+    // Pos:1487 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 900, 
+        ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 904, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20121,9 +20149,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1486 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
+    // Pos:1488 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 901, 
+        ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 905, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -20136,9 +20164,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1487 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
+    // Pos:1489 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 902, 
+        ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 906, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -20151,9 +20179,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1488 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
+    // Pos:1490 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 903, 
+        ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 907, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20166,9 +20194,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1489 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
+    // Pos:1491 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI"
     {
-        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 904, 
+        ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 908, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -20180,9 +20208,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1490 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
+    // Pos:1492 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 905, 
+        ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 909, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20195,9 +20223,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1491 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
+    // Pos:1493 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 906, 
+        ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 910, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -20210,9 +20238,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1492 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
+    // Pos:1494 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 907, 
+        ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 911, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -20225,9 +20253,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1493 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
+    // Pos:1495 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI"
     {
-        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 908, 
+        ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 912, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20240,9 +20268,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1494 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1496 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 909, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 913, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20254,9 +20282,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1495 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1497 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 909, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 913, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20268,9 +20296,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1496 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
+    // Pos:1498 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 909, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 913, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -20282,9 +20310,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1497 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
+    // Pos:1499 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI"
     {
-        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 909, 
+        ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 913, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -20296,9 +20324,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1498 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
+    // Pos:1500 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 910, 
+        ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 914, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20312,9 +20340,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1499 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
+    // Pos:1501 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 911, 
+        ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 915, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20328,9 +20356,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1500 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
+    // Pos:1502 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 912, 
+        ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 916, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20344,9 +20372,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1501 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
+    // Pos:1503 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI"
     {
-        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 913, 
+        ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 917, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20360,9 +20388,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1502 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
+    // Pos:1504 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 914, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 918, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20375,9 +20403,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1503 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
+    // Pos:1505 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 914, 
+        ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 918, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20389,9 +20417,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1504 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
+    // Pos:1506 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 915, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 919, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20404,9 +20432,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1505 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
+    // Pos:1507 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM"
     {
-        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 915, 
+        ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 919, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20418,9 +20446,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1506 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
+    // Pos:1508 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 916, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 920, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20433,11 +20461,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1507 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:x w:1 0x99 /r"/"RVM"
+    // Pos:1509 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 916, 
+        ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 920, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -20447,9 +20475,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1508 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
+    // Pos:1510 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 917, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 921, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20462,11 +20490,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1509 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x99 /r"/"RVM"
+    // Pos:1511 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM"
     {
-        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 917, 
+        ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 921, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -20476,9 +20504,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1510 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
+    // Pos:1512 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 918, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 922, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20491,9 +20519,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1511 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
+    // Pos:1513 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 918, 
+        ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 922, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20505,9 +20533,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1512 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
+    // Pos:1514 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 919, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 923, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20520,9 +20548,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1513 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
+    // Pos:1515 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM"
     {
-        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 919, 
+        ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 923, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20534,9 +20562,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1514 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
+    // Pos:1516 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 920, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 924, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20549,11 +20577,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1515 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xA9 /r"/"RVM"
+    // Pos:1517 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 920, 
+        ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 924, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -20563,9 +20591,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1516 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
+    // Pos:1518 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 921, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 925, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20578,11 +20606,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1517 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xA9 /r"/"RVM"
+    // Pos:1519 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM"
     {
-        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 921, 
+        ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 925, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -20592,9 +20620,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1518 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
+    // Pos:1520 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 922, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 926, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20607,9 +20635,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1519 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
+    // Pos:1521 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 922, 
+        ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 926, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20621,9 +20649,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1520 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
+    // Pos:1522 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 923, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 927, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20636,9 +20664,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1521 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
+    // Pos:1523 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM"
     {
-        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 923, 
+        ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 927, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20650,9 +20678,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1522 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
+    // Pos:1524 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 924, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 928, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20665,11 +20693,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1523 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xB9 /r"/"RVM"
+    // Pos:1525 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 924, 
+        ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 928, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -20679,9 +20707,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1524 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
+    // Pos:1526 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 925, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 929, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20694,11 +20722,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1525 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xB9 /r"/"RVM"
+    // Pos:1527 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM"
     {
-        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 925, 
+        ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 929, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -20708,9 +20736,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1526 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
+    // Pos:1528 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 926, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 930, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20723,9 +20751,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1527 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
+    // Pos:1529 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 926, 
+        ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 930, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20738,9 +20766,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1528 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
+    // Pos:1530 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 927, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 931, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20753,9 +20781,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1529 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
+    // Pos:1531 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM"
     {
-        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 927, 
+        ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 931, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20768,9 +20796,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1530 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
+    // Pos:1532 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 928, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 932, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20783,9 +20811,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1531 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
+    // Pos:1533 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 928, 
+        ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 932, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20798,9 +20826,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1532 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
+    // Pos:1534 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 929, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 933, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20813,9 +20841,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1533 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
+    // Pos:1535 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 929, 
+        ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 933, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -20828,9 +20856,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1534 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
+    // Pos:1536 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 930, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 934, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20843,9 +20871,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1535 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
+    // Pos:1537 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 930, 
+        ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 934, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20857,9 +20885,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1536 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
+    // Pos:1538 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 931, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 935, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20872,9 +20900,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1537 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
+    // Pos:1539 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 931, 
+        ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 935, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20886,9 +20914,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1538 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
+    // Pos:1540 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 932, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 936, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20901,9 +20929,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1539 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
+    // Pos:1541 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 932, 
+        ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 936, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20915,9 +20943,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1540 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
+    // Pos:1542 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 933, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 937, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20930,9 +20958,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1541 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
+    // Pos:1543 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 933, 
+        ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 937, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20944,9 +20972,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1542 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
+    // Pos:1544 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 934, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 938, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20959,9 +20987,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1543 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
+    // Pos:1545 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 934, 
+        ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 938, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -20973,9 +21001,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1544 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
+    // Pos:1546 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 935, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 939, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -20988,9 +21016,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1545 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
+    // Pos:1547 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM"
     {
-        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 935, 
+        ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 939, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21002,9 +21030,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1546 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
+    // Pos:1548 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 936, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 940, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21017,9 +21045,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1547 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
+    // Pos:1549 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 936, 
+        ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 940, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21032,9 +21060,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1548 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
+    // Pos:1550 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 937, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 941, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21047,9 +21075,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1549 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
+    // Pos:1551 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM"
     {
-        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 937, 
+        ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 941, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21062,9 +21090,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1550 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
+    // Pos:1552 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 938, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 942, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21077,9 +21105,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1551 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
+    // Pos:1553 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 938, 
+        ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 942, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21091,9 +21119,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1552 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
+    // Pos:1554 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 939, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 943, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21106,9 +21134,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1553 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
+    // Pos:1555 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM"
     {
-        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 939, 
+        ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 943, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21120,9 +21148,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1554 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
+    // Pos:1556 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 940, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 944, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21135,11 +21163,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1555 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:x w:1 0x9B /r"/"RVM"
+    // Pos:1557 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 940, 
+        ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 944, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21149,9 +21177,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1556 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
+    // Pos:1558 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 941, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 945, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21164,11 +21192,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1557 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x9B /r"/"RVM"
+    // Pos:1559 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM"
     {
-        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 941, 
+        ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 945, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21178,9 +21206,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1558 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
+    // Pos:1560 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 942, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 946, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21193,9 +21221,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1559 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
+    // Pos:1561 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 942, 
+        ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 946, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21207,9 +21235,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1560 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
+    // Pos:1562 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 943, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 947, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21222,9 +21250,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1561 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
+    // Pos:1563 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM"
     {
-        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 943, 
+        ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 947, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21236,9 +21264,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1562 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
+    // Pos:1564 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 944, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 948, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21251,11 +21279,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1563 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xAB /r"/"RVM"
+    // Pos:1565 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 944, 
+        ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 948, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21265,9 +21293,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1564 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
+    // Pos:1566 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 945, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 949, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21280,11 +21308,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1565 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xAB /r"/"RVM"
+    // Pos:1567 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM"
     {
-        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 945, 
+        ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 949, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21294,9 +21322,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1566 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
+    // Pos:1568 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 946, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 950, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21309,9 +21337,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1567 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
+    // Pos:1569 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 946, 
+        ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 950, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21323,9 +21351,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1568 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
+    // Pos:1570 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 947, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 951, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21338,9 +21366,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1569 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
+    // Pos:1571 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM"
     {
-        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 947, 
+        ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 951, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21352,9 +21380,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1570 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
+    // Pos:1572 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 948, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 952, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21367,11 +21395,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1571 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xBB /r"/"RVM"
+    // Pos:1573 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 948, 
+        ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 952, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21381,9 +21409,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1572 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
+    // Pos:1574 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 949, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 953, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21396,11 +21424,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1573 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xBB /r"/"RVM"
+    // Pos:1575 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM"
     {
-        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 949, 
+        ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 953, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21410,9 +21438,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1574 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
+    // Pos:1576 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 950, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 954, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21425,9 +21453,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1575 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
+    // Pos:1577 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 950, 
+        ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 954, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21439,9 +21467,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1576 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
+    // Pos:1578 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 951, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 955, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21454,9 +21482,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1577 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
+    // Pos:1579 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 951, 
+        ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 955, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21468,9 +21496,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1578 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
+    // Pos:1580 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 952, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 956, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21483,9 +21511,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1579 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
+    // Pos:1581 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 952, 
+        ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 956, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21497,9 +21525,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1580 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
+    // Pos:1582 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 953, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 957, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21512,9 +21540,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1581 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
+    // Pos:1583 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 953, 
+        ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 957, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21526,9 +21554,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1582 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
+    // Pos:1584 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 954, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 958, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21541,9 +21569,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1583 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
+    // Pos:1585 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 954, 
+        ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 958, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21555,9 +21583,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1584 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
+    // Pos:1586 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 955, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 959, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21570,9 +21598,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1585 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
+    // Pos:1587 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM"
     {
-        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 955, 
+        ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 959, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21584,9 +21612,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1586 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
+    // Pos:1588 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 956, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 960, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21599,9 +21627,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1587 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
+    // Pos:1589 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 956, 
+        ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 960, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21614,9 +21642,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1588 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
+    // Pos:1590 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 957, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 961, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21629,9 +21657,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1589 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
+    // Pos:1591 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 957, 
+        ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 961, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21644,9 +21672,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1590 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
+    // Pos:1592 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 958, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 962, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21659,9 +21687,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1591 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
+    // Pos:1593 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 958, 
+        ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 962, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21674,9 +21702,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1592 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
+    // Pos:1594 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 959, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 963, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21689,9 +21717,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1593 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
+    // Pos:1595 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 959, 
+        ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 963, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21704,9 +21732,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1594 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
+    // Pos:1596 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 960, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 964, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21719,9 +21747,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1595 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
+    // Pos:1597 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 960, 
+        ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 964, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21734,9 +21762,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1596 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
+    // Pos:1598 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 961, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 965, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21749,9 +21777,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1597 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
+    // Pos:1599 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM"
     {
-        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 961, 
+        ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 965, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -21764,9 +21792,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1598 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
+    // Pos:1600 Instruction:"VFNMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 962, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 966, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21779,9 +21807,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1599 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
+    // Pos:1601 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 962, 
+        ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 966, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21793,9 +21821,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1600 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
+    // Pos:1602 Instruction:"VFNMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 963, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 967, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21808,9 +21836,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1601 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
+    // Pos:1603 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM"
     {
-        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 963, 
+        ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 967, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21822,9 +21850,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1602 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
+    // Pos:1604 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 964, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 968, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21837,9 +21865,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1603 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
+    // Pos:1605 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 964, 
+        ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 968, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21851,9 +21879,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1604 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
+    // Pos:1606 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 965, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 969, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21866,9 +21894,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1605 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
+    // Pos:1607 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM"
     {
-        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 965, 
+        ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 969, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21880,9 +21908,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1606 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
+    // Pos:1608 Instruction:"VFNMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 966, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 970, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21895,9 +21923,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1607 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
+    // Pos:1609 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 966, 
+        ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 970, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21909,9 +21937,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1608 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
+    // Pos:1610 Instruction:"VFNMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 967, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 971, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21924,9 +21952,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1609 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
+    // Pos:1611 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM"
     {
-        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 967, 
+        ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 971, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -21938,9 +21966,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1610 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
+    // Pos:1612 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 968, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 972, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21953,11 +21981,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1611 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xAD /r"/"RVM"
+    // Pos:1613 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 968, 
+        ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 972, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21967,9 +21995,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1612 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
+    // Pos:1614 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 969, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 973, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -21982,11 +22010,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1613 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xAD /r"/"RVM"
+    // Pos:1615 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM"
     {
-        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 969, 
+        ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 973, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -21996,9 +22024,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1614 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
+    // Pos:1616 Instruction:"VFNMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 970, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 974, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22011,9 +22039,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1615 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
+    // Pos:1617 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 970, 
+        ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 974, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22025,9 +22053,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1616 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
+    // Pos:1618 Instruction:"VFNMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 971, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 975, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22040,9 +22068,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1617 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
+    // Pos:1619 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM"
     {
-        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 971, 
+        ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 975, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22054,9 +22082,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1618 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
+    // Pos:1620 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 972, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 976, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22069,11 +22097,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1619 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xBD /r"/"RVM"
+    // Pos:1621 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 972, 
+        ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 976, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22083,9 +22111,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1620 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
+    // Pos:1622 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 973, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 977, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22098,11 +22126,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1621 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xBD /r"/"RVM"
+    // Pos:1623 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM"
     {
-        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 973, 
+        ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 977, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22112,9 +22140,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1622 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
+    // Pos:1624 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 974, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 978, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22127,9 +22155,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1623 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
+    // Pos:1625 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 974, 
+        ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 978, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22142,9 +22170,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1624 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
+    // Pos:1626 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 975, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 979, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22157,9 +22185,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1625 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
+    // Pos:1627 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 975, 
+        ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 979, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22172,9 +22200,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1626 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
+    // Pos:1628 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 976, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 980, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22187,9 +22215,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1627 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
+    // Pos:1629 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 976, 
+        ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 980, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22202,9 +22230,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1628 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
+    // Pos:1630 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 977, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 981, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22217,9 +22245,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1629 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
+    // Pos:1631 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM"
     {
-        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 977, 
+        ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 981, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22232,9 +22260,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1630 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
+    // Pos:1632 Instruction:"VFNMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 978, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 982, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22247,9 +22275,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1631 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
+    // Pos:1633 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 978, 
+        ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 982, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22261,9 +22289,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1632 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
+    // Pos:1634 Instruction:"VFNMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 979, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 983, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22276,9 +22304,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1633 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
+    // Pos:1635 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM"
     {
-        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 979, 
+        ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 983, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22290,9 +22318,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1634 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
+    // Pos:1636 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 980, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 984, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22305,11 +22333,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1635 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0x9F /r"/"RVM"
+    // Pos:1637 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 980, 
+        ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 984, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22319,9 +22347,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1636 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
+    // Pos:1638 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 981, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 985, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22334,11 +22362,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1637 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0x9F /r"/"RVM"
+    // Pos:1639 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM"
     {
-        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 981, 
+        ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 985, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22348,9 +22376,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1638 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
+    // Pos:1640 Instruction:"VFNMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 982, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 986, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22363,9 +22391,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1639 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
+    // Pos:1641 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 982, 
+        ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 986, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22377,9 +22405,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1640 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
+    // Pos:1642 Instruction:"VFNMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 983, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 987, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22392,9 +22420,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1641 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
+    // Pos:1643 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM"
     {
-        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 983, 
+        ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 987, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22406,9 +22434,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1642 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
+    // Pos:1644 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 984, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 988, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22421,11 +22449,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1643 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xAF /r"/"RVM"
+    // Pos:1645 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 984, 
+        ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 988, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22435,9 +22463,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1644 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
+    // Pos:1646 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 985, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 989, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22450,11 +22478,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1645 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xAF /r"/"RVM"
+    // Pos:1647 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM"
     {
-        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 985, 
+        ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 989, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22464,9 +22492,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1646 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
+    // Pos:1648 Instruction:"VFNMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 986, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 990, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22479,9 +22507,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1647 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
+    // Pos:1649 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 986, 
+        ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 990, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22493,9 +22521,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1648 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
+    // Pos:1650 Instruction:"VFNMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 987, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 991, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22508,9 +22536,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1649 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
+    // Pos:1651 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM"
     {
-        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 987, 
+        ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 991, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
@@ -22522,9 +22550,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1650 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
+    // Pos:1652 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 988, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 992, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22537,11 +22565,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1651 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:0 w:1 0xBF /r"/"RVM"
+    // Pos:1653 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 988, 
+        ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 992, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22551,9 +22579,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1652 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
+    // Pos:1654 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 989, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 993, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22566,11 +22594,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1653 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:0 w:0 0xBF /r"/"RVM"
+    // Pos:1655 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM"
     {
-        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 989, 
+        ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 993, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 
         0,
         0,
         0,
@@ -22580,9 +22608,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1654 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
+    // Pos:1656 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 990, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 994, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22595,9 +22623,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1655 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
+    // Pos:1657 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 990, 
+        ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 994, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22610,9 +22638,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1656 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
+    // Pos:1658 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 991, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 995, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22625,9 +22653,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1657 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
+    // Pos:1659 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 991, 
+        ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 995, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22640,9 +22668,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1658 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
+    // Pos:1660 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 992, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 996, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22655,9 +22683,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1659 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
+    // Pos:1661 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 992, 
+        ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 996, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22670,9 +22698,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1660 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
+    // Pos:1662 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 993, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 997, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22685,9 +22713,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1661 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
+    // Pos:1663 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM"
     {
-        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 993, 
+        ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 997, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 
         0,
@@ -22700,9 +22728,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1662 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
+    // Pos:1664 Instruction:"VFPCLASSPD rKq{K},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 994, 
+        ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 998, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -22715,9 +22743,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1663 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
+    // Pos:1665 Instruction:"VFPCLASSPS rKq{K},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 995, 
+        ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 999, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -22730,9 +22758,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1664 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
+    // Pos:1666 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 996, 
+        ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1000, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -22745,9 +22773,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1665 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
+    // Pos:1667 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI"
     {
-        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 997, 
+        ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1001, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -22760,9 +22788,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1666 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
+    // Pos:1668 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM"
     {
-        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 998, 
+        ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1002, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -22773,9 +22801,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1667 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
+    // Pos:1669 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM"
     {
-        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 999, 
+        ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1003, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -22786,9 +22814,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1668 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
+    // Pos:1670 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM"
     {
-        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1000, 
+        ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1004, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -22799,9 +22827,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1669 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
+    // Pos:1671 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM"
     {
-        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1001, 
+        ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1005, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -22812,9 +22840,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1670 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
+    // Pos:1672 Instruction:"VGATHERDPD Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1002, 
+        ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1006, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22826,9 +22854,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1671 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
+    // Pos:1673 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1002, 
+        ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1006, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -22840,9 +22868,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1672 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
+    // Pos:1674 Instruction:"VGATHERDPS Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1003, 
+        ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1007, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22854,9 +22882,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1673 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
+    // Pos:1675 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1003, 
+        ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1007, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -22868,9 +22896,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1674 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
+    // Pos:1676 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1004, 
+        ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1008, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22881,9 +22909,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1675 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
+    // Pos:1677 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1005, 
+        ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1009, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22894,9 +22922,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1676 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
+    // Pos:1678 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1006, 
+        ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1010, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22907,9 +22935,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1677 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
+    // Pos:1679 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1007, 
+        ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1011, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22920,9 +22948,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1678 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
+    // Pos:1680 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1008, 
+        ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1012, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22933,9 +22961,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1679 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
+    // Pos:1681 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1009, 
+        ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1013, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22946,9 +22974,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1680 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
+    // Pos:1682 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1010, 
+        ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1014, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22959,9 +22987,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1681 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
+    // Pos:1683 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA"
     {
-        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1011, 
+        ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1015, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -22972,9 +23000,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1682 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
+    // Pos:1684 Instruction:"VGATHERQPD Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1012, 
+        ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1016, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -22986,9 +23014,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1683 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
+    // Pos:1685 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1012, 
+        ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1016, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -23000,9 +23028,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1684 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
+    // Pos:1686 Instruction:"VGATHERQPS Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM"
     {
-        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1013, 
+        ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1017, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23014,9 +23042,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1685 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
+    // Pos:1687 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV"
     {
-        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1013, 
+        ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1017, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -23028,9 +23056,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:1686 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
+    // Pos:1688 Instruction:"VGETEXPPD Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1014, 
+        ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1018, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23042,9 +23070,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1687 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
+    // Pos:1689 Instruction:"VGETEXPPS Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM"
     {
-        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1015, 
+        ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1019, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23056,9 +23084,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1688 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
+    // Pos:1690 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1016, 
+        ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1020, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23071,9 +23099,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1689 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
+    // Pos:1691 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM"
     {
-        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1017, 
+        ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1021, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23086,9 +23114,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1690 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
+    // Pos:1692 Instruction:"VGETMANTPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1018, 
+        ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1022, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23101,9 +23129,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1691 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
+    // Pos:1693 Instruction:"VGETMANTPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI"
     {
-        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1019, 
+        ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1023, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23116,9 +23144,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1692 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
+    // Pos:1694 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1020, 
+        ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1024, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23132,9 +23160,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1693 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
+    // Pos:1695 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI"
     {
-        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1021, 
+        ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1025, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23148,9 +23176,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1694 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
+    // Pos:1696 Instruction:"VGF2P8AFFINEINVQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1022, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1026, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -23164,9 +23192,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1695 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
+    // Pos:1697 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1022, 
+        ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1026, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -23179,9 +23207,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1696 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
+    // Pos:1698 Instruction:"VGF2P8AFFINEQB Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1023, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1027, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -23195,9 +23223,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1697 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
+    // Pos:1699 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1023, 
+        ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1027, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -23210,9 +23238,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1698 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
+    // Pos:1700 Instruction:"VGF2P8MULB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1024, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1028, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -23225,9 +23253,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1699 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
+    // Pos:1701 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM"
     {
-        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1024, 
+        ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1028, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 
         0,
@@ -23239,9 +23267,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1700 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1702 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1025, 
+        ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1029, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23253,9 +23281,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1701 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
+    // Pos:1703 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM"
     {
-        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1026, 
+        ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1030, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23267,9 +23295,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1702 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1704 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1027, 
+        ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1031, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23281,9 +23309,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1703 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
+    // Pos:1705 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM"
     {
-        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1028, 
+        ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1032, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23295,9 +23323,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1704 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
+    // Pos:1706 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1029, 
+        ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1033, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23310,9 +23338,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1705 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
+    // Pos:1707 Instruction:"VINSERTF32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1030, 
+        ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1034, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23326,9 +23354,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1706 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
+    // Pos:1708 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1031, 
+        ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1035, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -23342,9 +23370,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1707 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
+    // Pos:1709 Instruction:"VINSERTF64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1032, 
+        ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1036, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -23358,9 +23386,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1708 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
+    // Pos:1710 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1033, 
+        ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1037, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23374,9 +23402,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1709 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
+    // Pos:1711 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI"
     {
-        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1034, 
+        ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1038, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -23389,9 +23417,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1710 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
+    // Pos:1712 Instruction:"VINSERTI32X4 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1035, 
+        ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1039, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23405,9 +23433,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1711 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
+    // Pos:1713 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1036, 
+        ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1040, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -23421,9 +23449,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1712 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
+    // Pos:1714 Instruction:"VINSERTI64X2 Vu{K}{z},aKq,Hu,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1037, 
+        ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1041, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -23437,9 +23465,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1713 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
+    // Pos:1715 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI"
     {
-        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1038, 
+        ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1042, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23453,9 +23481,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1714 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1716 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1039, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1043, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23468,9 +23496,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1715 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1717 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1039, 
+        ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1043, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23483,9 +23511,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1716 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
+    // Pos:1718 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1039, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1043, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23498,9 +23526,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1717 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
+    // Pos:1719 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI"
     {
-        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1039, 
+        ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1043, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23513,9 +23541,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1718 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
+    // Pos:1720 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM"
     {
-        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1040, 
+        ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1044, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23526,9 +23554,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1719 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
+    // Pos:1721 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M"
     {
-        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1041, 
+        ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1045, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
         0,
@@ -23539,9 +23567,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1720 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
+    // Pos:1722 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM"
     {
-        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1042, 
+        ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1046, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23553,9 +23581,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1721 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
+    // Pos:1723 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1043, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1047, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23567,9 +23595,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1722 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
+    // Pos:1724 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1043, 
+        ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1047, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23581,9 +23609,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1723 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
+    // Pos:1725 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1044, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1048, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23595,9 +23623,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1724 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
+    // Pos:1726 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR"
     {
-        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1044, 
+        ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1048, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23609,9 +23637,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1725 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
+    // Pos:1727 Instruction:"VMAXPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1045, 
+        ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1049, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23624,9 +23652,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1726 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1728 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1045, 
+        ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1049, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23638,9 +23666,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1727 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
+    // Pos:1729 Instruction:"VMAXPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1046, 
+        ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1050, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23653,9 +23681,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1728 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
+    // Pos:1730 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1046, 
+        ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1050, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23667,9 +23695,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1729 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
+    // Pos:1731 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1047, 
+        ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1051, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23682,9 +23710,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1730 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1732 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1047, 
+        ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1051, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23696,9 +23724,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1731 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
+    // Pos:1733 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1048, 
+        ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1052, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23711,9 +23739,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1732 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
+    // Pos:1734 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM"
     {
-        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1048, 
+        ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1052, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23725,9 +23753,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1733 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/""
+    // Pos:1735 Instruction:"VMCALL" Encoding:"0x0F 0x01 /0xC1"/""
     {
-        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1049, 
+        ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1053, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -23736,9 +23764,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1734 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1736 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1050, 
+        ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1054, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -23749,9 +23777,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1735 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
+    // Pos:1737 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/""
     {
-        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1051, 
+        ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1055, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -23760,9 +23788,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1736 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
+    // Pos:1738 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1052, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1056, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -23771,9 +23799,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1737 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
+    // Pos:1739 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1052, 
+        ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1056, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -23782,9 +23810,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1738 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
+    // Pos:1740 Instruction:"VMINPD Vn{K}{z},aKq,Hn,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1053, 
+        ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1057, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23797,9 +23825,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1739 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1741 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1053, 
+        ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1057, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23811,9 +23839,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1740 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
+    // Pos:1742 Instruction:"VMINPS Vn{K}{z},aKq,Hn,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1054, 
+        ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1058, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23826,9 +23854,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1741 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
+    // Pos:1743 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1054, 
+        ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1058, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23840,9 +23868,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1742 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
+    // Pos:1744 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1055, 
+        ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1059, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23855,9 +23883,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1743 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1745 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1055, 
+        ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1059, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23869,9 +23897,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1744 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
+    // Pos:1746 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1056, 
+        ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1060, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23884,9 +23912,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:1745 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
+    // Pos:1747 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM"
     {
-        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1056, 
+        ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1060, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23898,9 +23926,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1746 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/""
+    // Pos:1748 Instruction:"VMLAUNCH" Encoding:"0x0F 0x01 /0xC2"/""
     {
-        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1057, 
+        ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1061, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -23910,9 +23938,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1747 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
+    // Pos:1749 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/""
     {
-        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1058, 
+        ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1062, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -23922,9 +23950,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1748 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
+    // Pos:1750 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1059, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1063, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -23933,9 +23961,20 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1749 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
+    // Pos:1751 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/""
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1060, 
+        ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1063, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_SGX|ND_MOD_TSX, 
+        0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
+        0,
+        0,
+        0,
+        0,
+    }, 
+
+    // Pos:1752 Instruction:"VMOVAPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM"
+    {
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1064, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23947,9 +23986,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1750 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
+    // Pos:1753 Instruction:"VMOVAPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1060, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1064, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -23961,9 +24000,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1751 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
+    // Pos:1754 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1060, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1064, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23974,9 +24013,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1752 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
+    // Pos:1755 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1060, 
+        ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1064, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -23987,9 +24026,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1753 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
+    // Pos:1756 Instruction:"VMOVAPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1061, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1065, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24001,9 +24040,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1754 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
+    // Pos:1757 Instruction:"VMOVAPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1061, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1065, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24015,9 +24054,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1755 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
+    // Pos:1758 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1061, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1065, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24028,9 +24067,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1756 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
+    // Pos:1759 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR"
     {
-        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1061, 
+        ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1065, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24041,9 +24080,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1757 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1760 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1062, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1066, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24054,9 +24093,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1758 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1761 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1062, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1066, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24067,9 +24106,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1759 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
+    // Pos:1762 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1062, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1066, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24080,9 +24119,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1760 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
+    // Pos:1763 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR"
     {
-        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1062, 
+        ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1066, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24093,9 +24132,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1761 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
+    // Pos:1764 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1063, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1067, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24107,9 +24146,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1762 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
+    // Pos:1765 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1063, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1067, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24121,9 +24160,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1763 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
+    // Pos:1766 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1063, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1067, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24135,9 +24174,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1764 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
+    // Pos:1767 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1063, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1067, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24148,9 +24187,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1765 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
+    // Pos:1768 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1063, 
+        ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1067, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24161,9 +24200,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1766 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
+    // Pos:1769 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1064, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1068, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24174,9 +24213,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1767 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
+    // Pos:1770 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1064, 
+        ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1068, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24187,9 +24226,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1768 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1771 Instruction:"VMOVDQA32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1065, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24201,9 +24240,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1769 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1772 Instruction:"VMOVDQA32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1065, 
+        ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24215,9 +24254,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1770 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1773 Instruction:"VMOVDQA64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1066, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24229,9 +24268,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1771 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1774 Instruction:"VMOVDQA64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1066, 
+        ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24243,9 +24282,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1772 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
+    // Pos:1775 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1067, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1071, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24256,9 +24295,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1773 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
+    // Pos:1776 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR"
     {
-        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1067, 
+        ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1071, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24269,9 +24308,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1774 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1777 Instruction:"VMOVDQU16 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1068, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1072, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -24283,9 +24322,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1775 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1778 Instruction:"VMOVDQU16 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1068, 
+        ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1072, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -24297,9 +24336,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1776 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1779 Instruction:"VMOVDQU32 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24311,9 +24350,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1777 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1780 Instruction:"VMOVDQU32 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1069, 
+        ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24325,9 +24364,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1778 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
+    // Pos:1781 Instruction:"VMOVDQU64 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24339,9 +24378,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1779 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
+    // Pos:1782 Instruction:"VMOVDQU64 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1070, 
+        ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24353,9 +24392,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1780 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
+    // Pos:1783 Instruction:"VMOVDQU8 Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1071, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1075, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -24367,9 +24406,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1781 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
+    // Pos:1784 Instruction:"VMOVDQU8 Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR"
     {
-        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1071, 
+        ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1075, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -24381,9 +24420,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1782 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
+    // Pos:1785 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1072, 
+        ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1076, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24395,9 +24434,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1783 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
+    // Pos:1786 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM"
     {
-        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1072, 
+        ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1076, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24409,9 +24448,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1784 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
+    // Pos:1787 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24423,9 +24462,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1785 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
+    // Pos:1788 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1073, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24436,9 +24475,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1786 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1789 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1073, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1077, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24450,9 +24489,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1787 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1790 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1073, 
+        ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1077, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24463,9 +24502,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1788 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
+    // Pos:1791 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1078, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24477,9 +24516,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1789 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
+    // Pos:1792 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1074, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1078, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24490,9 +24529,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1790 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
+    // Pos:1793 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1074, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1078, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24504,9 +24543,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1791 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
+    // Pos:1794 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR"
     {
-        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1074, 
+        ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1078, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24517,9 +24556,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1792 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
+    // Pos:1795 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1075, 
+        ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1079, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24531,9 +24570,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1793 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
+    // Pos:1796 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM"
     {
-        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1075, 
+        ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1079, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24545,9 +24584,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1794 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
+    // Pos:1797 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1076, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24559,9 +24598,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1795 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
+    // Pos:1798 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1076, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24572,9 +24611,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1796 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1799 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1076, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1080, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24586,9 +24625,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1797 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1800 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1076, 
+        ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1080, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24599,9 +24638,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1798 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
+    // Pos:1801 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24613,9 +24652,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1799 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
+    // Pos:1802 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1077, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24626,9 +24665,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1800 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
+    // Pos:1803 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1077, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1081, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24640,9 +24679,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1801 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
+    // Pos:1804 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR"
     {
-        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1077, 
+        ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1081, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24653,9 +24692,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1802 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1805 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1078, 
+        ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1082, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24666,9 +24705,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1803 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
+    // Pos:1806 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM"
     {
-        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1079, 
+        ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1083, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24679,9 +24718,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1804 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
+    // Pos:1807 Instruction:"VMOVNTDQ Mn,Vn" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1080, 
+        ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24692,9 +24731,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1805 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
+    // Pos:1808 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR"
     {
-        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1080, 
+        ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1084, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24705,9 +24744,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1806 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
+    // Pos:1809 Instruction:"VMOVNTDQA Vn,Mn" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1081, 
+        ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24718,9 +24757,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1807 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
+    // Pos:1810 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM"
     {
-        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1081, 
+        ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1085, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24731,9 +24770,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1808 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
+    // Pos:1811 Instruction:"VMOVNTPD Mn,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1082, 
+        ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24744,9 +24783,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1809 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1812 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1082, 
+        ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1086, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24757,9 +24796,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1810 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
+    // Pos:1813 Instruction:"VMOVNTPS Mn,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1083, 
+        ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24770,9 +24809,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1811 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
+    // Pos:1814 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR"
     {
-        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1083, 
+        ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1087, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24783,9 +24822,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1812 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1815 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24796,9 +24835,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1813 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1816 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24809,9 +24848,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1814 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
+    // Pos:1817 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24822,9 +24861,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1815 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
+    // Pos:1818 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24835,9 +24874,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1816 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
+    // Pos:1819 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24848,9 +24887,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1817 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
+    // Pos:1820 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24861,9 +24900,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1818 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
+    // Pos:1821 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24874,9 +24913,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1819 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
+    // Pos:1822 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR"
     {
-        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1084, 
+        ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24887,9 +24926,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1820 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
+    // Pos:1823 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24901,9 +24940,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1821 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
+    // Pos:1824 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24916,9 +24955,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1822 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
+    // Pos:1825 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24930,9 +24969,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1823 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
+    // Pos:1826 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -24945,9 +24984,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1824 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1827 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24959,9 +24998,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1825 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1828 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24972,9 +25011,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1826 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1829 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24986,9 +25025,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1827 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1830 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1085, 
+        ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -24999,9 +25038,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1828 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
+    // Pos:1831 Instruction:"VMOVSHDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1086, 
+        ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25013,9 +25052,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1829 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
+    // Pos:1832 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM"
     {
-        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1086, 
+        ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1090, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25026,9 +25065,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1830 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
+    // Pos:1833 Instruction:"VMOVSLDUP Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1087, 
+        ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1091, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25040,9 +25079,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1831 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
+    // Pos:1834 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM"
     {
-        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1087, 
+        ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1091, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25053,9 +25092,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1832 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
+    // Pos:1835 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25067,9 +25106,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1833 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
+    // Pos:1836 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25082,9 +25121,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1834 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
+    // Pos:1837 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25096,9 +25135,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1835 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
+    // Pos:1838 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25111,9 +25150,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1836 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
+    // Pos:1839 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25125,9 +25164,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1837 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
+    // Pos:1840 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25138,9 +25177,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1838 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
+    // Pos:1841 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25152,9 +25191,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1839 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
+    // Pos:1842 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR"
     {
-        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1088, 
+        ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1092, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25165,9 +25204,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1840 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
+    // Pos:1843 Instruction:"VMOVUPD Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25179,9 +25218,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1841 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
+    // Pos:1844 Instruction:"VMOVUPD Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1089, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1093, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25193,9 +25232,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1842 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
+    // Pos:1845 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25206,9 +25245,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1843 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
+    // Pos:1846 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1089, 
+        ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1093, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25219,9 +25258,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1844 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
+    // Pos:1847 Instruction:"VMOVUPS Vn{K}{z},aKq,Wn" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25233,9 +25272,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1845 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
+    // Pos:1848 Instruction:"VMOVUPS Wn{K}{z},aKq,Vn" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1090, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1094, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25247,9 +25286,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1846 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
+    // Pos:1849 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1090, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1094, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25260,9 +25299,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1847 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
+    // Pos:1850 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR"
     {
-        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1090, 
+        ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1094, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25273,9 +25312,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1848 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
+    // Pos:1851 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI"
     {
-        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1091, 
+        ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1095, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25288,9 +25327,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1849 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1852 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1092, 
+        ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1096, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25301,9 +25340,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1850 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
+    // Pos:1853 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M"
     {
-        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1093, 
+        ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1097, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25314,9 +25353,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1851 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
+    // Pos:1854 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR"
     {
-        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1094, 
+        ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1098, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25328,9 +25367,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1852 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/""
+    // Pos:1855 Instruction:"VMRESUME" Encoding:"0x0F 0x01 /0xC3"/""
     {
-        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1095, 
+        ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1099, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25340,9 +25379,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1853 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
+    // Pos:1856 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/""
     {
-        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1096, 
+        ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1100, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -25352,9 +25391,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1854 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
+    // Pos:1857 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/""
     {
-        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1097, 
+        ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1101, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 
         0,
@@ -25363,9 +25402,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:1855 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
+    // Pos:1858 Instruction:"VMULPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1098, 
+        ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1102, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25378,9 +25417,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1856 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
+    // Pos:1859 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1098, 
+        ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1102, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25392,9 +25431,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1857 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
+    // Pos:1860 Instruction:"VMULPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1099, 
+        ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1103, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25407,9 +25446,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1858 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
+    // Pos:1861 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1099, 
+        ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1103, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25421,9 +25460,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1859 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
+    // Pos:1862 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1100, 
+        ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1104, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25436,9 +25475,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1860 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
+    // Pos:1863 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1100, 
+        ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1104, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25450,9 +25489,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1861 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
+    // Pos:1864 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1101, 
+        ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1105, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25465,9 +25504,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:1862 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
+    // Pos:1865 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM"
     {
-        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1101, 
+        ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1105, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25479,9 +25518,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1863 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
+    // Pos:1866 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM"
     {
-        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1102, 
+        ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1106, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25493,9 +25532,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1864 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/""
+    // Pos:1867 Instruction:"VMXOFF" Encoding:"0x0F 0x01 /0xC4"/""
     {
-        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1103, 
+        ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1107, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25505,9 +25544,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1865 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
+    // Pos:1868 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M"
     {
-        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1104, 
+        ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1108, 
         ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 
         0,
@@ -25518,9 +25557,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1866 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
+    // Pos:1869 Instruction:"VORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1105, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1109, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -25533,9 +25572,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1867 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
+    // Pos:1870 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1105, 
+        ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1109, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25547,9 +25586,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1868 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
+    // Pos:1871 Instruction:"VORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1106, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1110, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -25562,9 +25601,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1869 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
+    // Pos:1872 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM"
     {
-        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1106, 
+        ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1110, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25576,9 +25615,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1870 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
+    // Pos:1873 Instruction:"VP2INTERSECTD rKq+1,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1107, 
+        ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1111, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
         0,
@@ -25590,9 +25629,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1871 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
+    // Pos:1874 Instruction:"VP2INTERSECTQ rKq+1,Hn,Wn|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM"
     {
-        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1108, 
+        ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1112, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 
         0,
@@ -25604,9 +25643,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1872 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
+    // Pos:1875 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1109, 
+        ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1113, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
         0,
@@ -25619,9 +25658,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1873 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
+    // Pos:1876 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM"
     {
-        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1110, 
+        ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1114, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 
         0,
@@ -25634,9 +25673,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1874 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
+    // Pos:1877 Instruction:"VPABSB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1111, 
+        ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1115, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25648,9 +25687,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1875 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
+    // Pos:1878 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM"
     {
-        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1111, 
+        ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1115, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25661,9 +25700,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1876 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
+    // Pos:1879 Instruction:"VPABSD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1112, 
+        ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1116, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25675,9 +25714,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1877 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
+    // Pos:1880 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM"
     {
-        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1112, 
+        ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1116, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25688,9 +25727,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1878 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
+    // Pos:1881 Instruction:"VPABSQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM"
     {
-        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1113, 
+        ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1117, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25702,9 +25741,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1879 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
+    // Pos:1882 Instruction:"VPABSW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1114, 
+        ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1118, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25716,9 +25755,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1880 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
+    // Pos:1883 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM"
     {
-        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1114, 
+        ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1118, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25729,9 +25768,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1881 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
+    // Pos:1884 Instruction:"VPACKSSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1115, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1119, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25744,9 +25783,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1882 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
+    // Pos:1885 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM"
     {
-        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1115, 
+        ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1119, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25758,9 +25797,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1883 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
+    // Pos:1886 Instruction:"VPACKSSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1116, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1120, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25773,9 +25812,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1884 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
+    // Pos:1887 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM"
     {
-        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1116, 
+        ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1120, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25787,9 +25826,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1885 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
+    // Pos:1888 Instruction:"VPACKUSDW Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1117, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1121, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25802,9 +25841,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1886 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
+    // Pos:1889 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM"
     {
-        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1117, 
+        ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1121, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25816,9 +25855,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1887 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
+    // Pos:1890 Instruction:"VPACKUSWB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1118, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1122, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25831,9 +25870,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1888 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
+    // Pos:1891 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM"
     {
-        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1118, 
+        ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1122, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25845,9 +25884,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1889 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
+    // Pos:1892 Instruction:"VPADDB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1119, 
+        ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1123, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25860,9 +25899,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1890 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
+    // Pos:1893 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM"
     {
-        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1119, 
+        ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1123, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25874,9 +25913,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1891 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
+    // Pos:1894 Instruction:"VPADDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1120, 
+        ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1124, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25889,9 +25928,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1892 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
+    // Pos:1895 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM"
     {
-        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1120, 
+        ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1124, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25903,9 +25942,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1893 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
+    // Pos:1896 Instruction:"VPADDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1121, 
+        ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1125, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -25918,9 +25957,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1894 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
+    // Pos:1897 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM"
     {
-        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1121, 
+        ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1125, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25932,9 +25971,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1895 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
+    // Pos:1898 Instruction:"VPADDSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1122, 
+        ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1126, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25947,9 +25986,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1896 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
+    // Pos:1899 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM"
     {
-        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1122, 
+        ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1126, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25961,9 +26000,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1897 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
+    // Pos:1900 Instruction:"VPADDSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1123, 
+        ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1127, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -25976,9 +26015,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1898 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
+    // Pos:1901 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM"
     {
-        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1123, 
+        ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1127, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -25990,9 +26029,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1899 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
+    // Pos:1902 Instruction:"VPADDUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1124, 
+        ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1128, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26005,9 +26044,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1900 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
+    // Pos:1903 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM"
     {
-        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1124, 
+        ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1128, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26019,9 +26058,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1901 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
+    // Pos:1904 Instruction:"VPADDUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1125, 
+        ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1129, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26034,9 +26073,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1902 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
+    // Pos:1905 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM"
     {
-        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1125, 
+        ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1129, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26048,9 +26087,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1903 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
+    // Pos:1906 Instruction:"VPADDW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1126, 
+        ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1130, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26063,9 +26102,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1904 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
+    // Pos:1907 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM"
     {
-        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1126, 
+        ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1130, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26077,9 +26116,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1905 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
+    // Pos:1908 Instruction:"VPALIGNR Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1127, 
+        ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1131, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26093,9 +26132,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1906 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
+    // Pos:1909 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI"
     {
-        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1127, 
+        ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1131, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26108,9 +26147,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1907 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
+    // Pos:1910 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM"
     {
-        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1128, 
+        ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1132, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26122,9 +26161,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1908 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
+    // Pos:1911 Instruction:"VPANDD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1129, 
+        ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1133, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26137,9 +26176,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1909 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
+    // Pos:1912 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM"
     {
-        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1130, 
+        ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1134, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26151,9 +26190,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1910 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
+    // Pos:1913 Instruction:"VPANDND Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1131, 
+        ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1135, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26166,9 +26205,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1911 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
+    // Pos:1914 Instruction:"VPANDNQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM"
     {
-        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1132, 
+        ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1136, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26181,9 +26220,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1912 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
+    // Pos:1915 Instruction:"VPANDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM"
     {
-        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1133, 
+        ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1137, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26196,9 +26235,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1913 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
+    // Pos:1916 Instruction:"VPAVGB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1134, 
+        ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1138, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26211,9 +26250,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1914 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
+    // Pos:1917 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM"
     {
-        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1134, 
+        ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1138, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26225,9 +26264,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1915 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
+    // Pos:1918 Instruction:"VPAVGW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1135, 
+        ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1139, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26240,9 +26279,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1916 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
+    // Pos:1919 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM"
     {
-        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1135, 
+        ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1139, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26254,9 +26293,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1917 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
+    // Pos:1920 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1136, 
+        ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1140, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -26269,9 +26308,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1918 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:1921 Instruction:"VPBLENDMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1137, 
+        ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1141, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26284,9 +26323,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1919 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
+    // Pos:1922 Instruction:"VPBLENDMD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1138, 
+        ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1142, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26299,9 +26338,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1920 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
+    // Pos:1923 Instruction:"VPBLENDMQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1139, 
+        ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1143, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26314,9 +26353,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1921 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
+    // Pos:1924 Instruction:"VPBLENDMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM"
     {
-        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1140, 
+        ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1144, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26329,9 +26368,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1922 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
+    // Pos:1925 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML"
     {
-        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1141, 
+        ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1145, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26344,9 +26383,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1923 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
+    // Pos:1926 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI"
     {
-        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1142, 
+        ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1146, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26359,9 +26398,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1924 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
+    // Pos:1927 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1143, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1147, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26373,9 +26412,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1925 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
+    // Pos:1928 Instruction:"VPBROADCASTB Vn{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1143, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1147, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26387,9 +26426,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1926 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
+    // Pos:1929 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM"
     {
-        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1143, 
+        ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1147, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -26400,9 +26439,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1927 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
+    // Pos:1930 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1144, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1148, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26414,9 +26453,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1928 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
+    // Pos:1931 Instruction:"VPBROADCASTD Vn{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1144, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1148, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26428,9 +26467,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1929 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
+    // Pos:1932 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM"
     {
-        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1144, 
+        ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1148, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -26441,9 +26480,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1930 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
+    // Pos:1933 Instruction:"VPBROADCASTMB2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1145, 
+        ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1149, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
         0,
@@ -26454,9 +26493,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1931 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
+    // Pos:1934 Instruction:"VPBROADCASTMW2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM"
     {
-        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1146, 
+        ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1150, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
         0,
@@ -26467,9 +26506,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1932 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
+    // Pos:1935 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1147, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1151, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26481,9 +26520,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1933 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
+    // Pos:1936 Instruction:"VPBROADCASTQ Vn{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1147, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1151, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26495,9 +26534,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1934 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
+    // Pos:1937 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM"
     {
-        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1147, 
+        ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1151, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -26508,9 +26547,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1935 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
+    // Pos:1938 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1148, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1152, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26522,9 +26561,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1936 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
+    // Pos:1939 Instruction:"VPBROADCASTW Vn{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1148, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1152, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26536,9 +26575,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_R, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1937 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
+    // Pos:1940 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM"
     {
-        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1148, 
+        ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1152, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -26549,9 +26588,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1938 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
+    // Pos:1941 Instruction:"VPCLMULQDQ Vn,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1149, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1153, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
         0,
@@ -26564,24 +26603,24 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1939 Instruction:"VPCLMULQDQ Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x44 /r ib"/"RVMI"
+    // Pos:1942 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI"
     {
-        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1149, 
+        ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1153, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1940 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
+    // Pos:1943 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1150, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1154, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -26594,9 +26633,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1941 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
+    // Pos:1944 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM"
     {
-        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1150, 
+        ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1154, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -26609,9 +26648,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1942 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
+    // Pos:1945 Instruction:"VPCMPB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1151, 
+        ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1155, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26625,9 +26664,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1943 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
+    // Pos:1946 Instruction:"VPCMPD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1152, 
+        ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1156, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26641,9 +26680,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1944 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
+    // Pos:1947 Instruction:"VPCMPEQB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1153, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1157, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26656,9 +26695,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1945 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
+    // Pos:1948 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM"
     {
-        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1153, 
+        ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1157, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26670,9 +26709,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1946 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
+    // Pos:1949 Instruction:"VPCMPEQD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1154, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1158, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26685,9 +26724,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1947 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
+    // Pos:1950 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM"
     {
-        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1154, 
+        ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1158, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26699,9 +26738,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1948 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
+    // Pos:1951 Instruction:"VPCMPEQQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1155, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1159, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26714,9 +26753,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1949 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
+    // Pos:1952 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM"
     {
-        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1155, 
+        ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1159, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26728,9 +26767,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1950 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
+    // Pos:1953 Instruction:"VPCMPEQW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1156, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1160, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26743,9 +26782,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1951 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
+    // Pos:1954 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM"
     {
-        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1156, 
+        ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1160, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26757,9 +26796,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1952 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
+    // Pos:1955 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1157, 
+        ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1161, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26775,9 +26814,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1953 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
+    // Pos:1956 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI"
     {
-        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1158, 
+        ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1162, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26793,9 +26832,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1954 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
+    // Pos:1957 Instruction:"VPCMPGTB rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1159, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1163, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26808,9 +26847,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1955 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
+    // Pos:1958 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM"
     {
-        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1159, 
+        ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1163, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26822,9 +26861,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1956 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
+    // Pos:1959 Instruction:"VPCMPGTD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1160, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1164, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26837,9 +26876,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1957 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
+    // Pos:1960 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM"
     {
-        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1160, 
+        ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1164, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26851,9 +26890,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1958 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
+    // Pos:1961 Instruction:"VPCMPGTQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1161, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1165, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26866,9 +26905,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1959 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
+    // Pos:1962 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM"
     {
-        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1161, 
+        ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1165, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26880,9 +26919,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1960 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
+    // Pos:1963 Instruction:"VPCMPGTW rKq{K},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1162, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1166, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26895,9 +26934,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1961 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
+    // Pos:1964 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM"
     {
-        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1162, 
+        ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1166, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26909,9 +26948,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1962 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
+    // Pos:1965 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1163, 
+        ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1167, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26925,9 +26964,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1963 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
+    // Pos:1966 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI"
     {
-        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1164, 
+        ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1168, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -26941,9 +26980,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:1964 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
+    // Pos:1967 Instruction:"VPCMPQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1165, 
+        ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1169, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26957,9 +26996,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1965 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
+    // Pos:1968 Instruction:"VPCMPUB rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1166, 
+        ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1170, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -26973,9 +27012,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1966 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
+    // Pos:1969 Instruction:"VPCMPUD rKq{K},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1167, 
+        ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1171, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -26989,9 +27028,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1967 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
+    // Pos:1970 Instruction:"VPCMPUQ rKq{K},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1168, 
+        ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1172, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27005,9 +27044,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1968 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
+    // Pos:1971 Instruction:"VPCMPUW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1169, 
+        ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1173, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -27021,9 +27060,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1969 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
+    // Pos:1972 Instruction:"VPCMPW rKq{K},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI"
     {
-        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1170, 
+        ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1174, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -27037,9 +27076,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1970 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
+    // Pos:1973 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1171, 
+        ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1175, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27052,9 +27091,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1971 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
+    // Pos:1974 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1172, 
+        ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1176, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27067,11 +27106,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1972 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
+    // Pos:1975 Instruction:"VPCOMPRESSB Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1173, 
+        ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1177, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
         0,
         0,
@@ -27081,9 +27120,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1973 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
+    // Pos:1976 Instruction:"VPCOMPRESSD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1174, 
+        ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1178, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27095,9 +27134,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1974 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
+    // Pos:1977 Instruction:"VPCOMPRESSQ Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1175, 
+        ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1179, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27109,11 +27148,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1975 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
+    // Pos:1978 Instruction:"VPCOMPRESSW Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR"
     {
-        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1176, 
+        ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1180, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
         0,
         0,
@@ -27123,9 +27162,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1976 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
+    // Pos:1979 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1177, 
+        ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1181, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27138,9 +27177,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1977 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
+    // Pos:1980 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1178, 
+        ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1182, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27153,9 +27192,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1978 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
+    // Pos:1981 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1179, 
+        ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1183, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27168,9 +27207,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1979 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
+    // Pos:1982 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1180, 
+        ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1184, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27183,9 +27222,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1980 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
+    // Pos:1983 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI"
     {
-        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1181, 
+        ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1185, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27198,9 +27237,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1981 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
+    // Pos:1984 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI"
     {
-        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1182, 
+        ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1186, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -27213,9 +27252,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1982 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
+    // Pos:1985 Instruction:"VPCONFLICTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1183, 
+        ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1187, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
         0,
@@ -27227,9 +27266,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1983 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
+    // Pos:1986 Instruction:"VPCONFLICTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM"
     {
-        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1184, 
+        ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1188, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
         0,
@@ -27241,9 +27280,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1984 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
+    // Pos:1987 Instruction:"VPDPBUSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1185, 
+        ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1189, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
         0,
@@ -27256,9 +27295,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1985 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
+    // Pos:1988 Instruction:"VPDPBUSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1186, 
+        ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1190, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
         0,
@@ -27271,9 +27310,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1986 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
+    // Pos:1989 Instruction:"VPDPWSSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1187, 
+        ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1191, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
         0,
@@ -27286,9 +27325,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1987 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
+    // Pos:1990 Instruction:"VPDPWSSDS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM"
     {
-        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1188, 
+        ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1192, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 
         0,
@@ -27301,9 +27340,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1988 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
+    // Pos:1991 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1189, 
+        ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1193, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -27316,9 +27355,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1989 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
+    // Pos:1992 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI"
     {
-        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1190, 
+        ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1194, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -27331,9 +27370,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1990 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
+    // Pos:1993 Instruction:"VPERMB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1191, 
+        ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1195, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
         0,
@@ -27346,9 +27385,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1991 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
+    // Pos:1994 Instruction:"VPERMD Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1192, 
+        ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1196, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27361,9 +27400,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1992 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
+    // Pos:1995 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM"
     {
-        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1192, 
+        ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1196, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -27375,9 +27414,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1993 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
+    // Pos:1996 Instruction:"VPERMI2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1193, 
+        ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1197, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
         0,
@@ -27390,9 +27429,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1994 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
+    // Pos:1997 Instruction:"VPERMI2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1194, 
+        ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1198, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27405,9 +27444,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1995 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
+    // Pos:1998 Instruction:"VPERMI2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1195, 
+        ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1199, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27420,9 +27459,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1996 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
+    // Pos:1999 Instruction:"VPERMI2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM"
     {
-        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1196, 
+        ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27435,9 +27474,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:1997 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
+    // Pos:2000 Instruction:"VPERMI2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM"
     {
-        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1197, 
+        ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1201, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27450,9 +27489,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:1998 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
+    // Pos:2001 Instruction:"VPERMI2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM"
     {
-        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1198, 
+        ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1202, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -27465,41 +27504,43 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:1999 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
+    // Pos:2002 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1199, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1203, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
+        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
-        OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
+        OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_Im2z, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2000 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
+    // Pos:2003 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1199, 
+        ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1203, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
+        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
-        OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
-        OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_Im2z, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2001 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
+    // Pos:2004 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1199, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1204, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
         0,
         0,
@@ -27507,25 +27548,29 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_Im2z, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2002 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
+    // Pos:2005 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM"
     {
-        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1199, 
+        ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1204, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
         0,
         0,
         0,
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_Im2z, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2003 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
+    // Pos:2006 Instruction:"VPERMILPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1205, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27535,12 +27580,12 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
         OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
+        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2004 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
+    // Pos:2007 Instruction:"VPERMILPD Vn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 
+        ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1205, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27549,13 +27594,13 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
+        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2005 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
+    // Pos:2008 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1200, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1205, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -27567,9 +27612,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2006 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
+    // Pos:2009 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI"
     {
-        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1200, 
+        ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1205, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -27581,43 +27626,41 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2007 Instruction:"VPERMILzz2PD Vx,Hx,Wx,Lx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r ib"/"RVMLI"
+    // Pos:2010 Instruction:"VPERMILPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM"
     {
-        ND_INS_VPERMILzz2PD, ND_CAT_XOP, ND_SET_XOP, 1201, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1206, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
+        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
+        OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_n, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2008 Instruction:"VPERMILzz2PD Vx,Hx,Lx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r ib"/"RVLMI"
+    // Pos:2011 Instruction:"VPERMILPS Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI"
     {
-        ND_INS_VPERMILzz2PD, ND_CAT_XOP, ND_SET_XOP, 1201, 
+        ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1206, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
+        0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_V, ND_OPS_n, ND_OPF_W, ND_OPD_MASK|ND_OPD_Z, 0), 
+        OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2009 Instruction:"VPERMILzz2PS Vx,Hx,Wx,Lx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r ib"/"RVMLI"
+    // Pos:2012 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM"
     {
-        ND_INS_VPERMILzz2PS, ND_CAT_XOP, ND_SET_XOP, 1202, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1206, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
@@ -27625,29 +27668,25 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2010 Instruction:"VPERMILzz2PS Vx,Hx,Lx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r ib"/"RVLMI"
+    // Pos:2013 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI"
     {
-        ND_INS_VPERMILzz2PS, ND_CAT_XOP, ND_SET_XOP, 1202, 
+        ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1206, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
         0,
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_x, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2011 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
+    // Pos:2014 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1207, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27660,9 +27699,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2012 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
+    // Pos:2015 Instruction:"VPERMPD Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1207, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27675,9 +27714,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2013 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
+    // Pos:2016 Instruction:"VPERMPD Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1203, 
+        ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1207, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27690,9 +27729,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2014 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
+    // Pos:2017 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI"
     {
-        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1203, 
+        ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1207, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -27704,9 +27743,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2015 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
+    // Pos:2018 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1204, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1208, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27719,9 +27758,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2016 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
+    // Pos:2019 Instruction:"VPERMPS Vu{K}{z},aKq,Hu,Wu|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1204, 
+        ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1208, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27734,9 +27773,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2017 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
+    // Pos:2020 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM"
     {
-        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1204, 
+        ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1208, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -27748,9 +27787,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_qq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2018 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
+    // Pos:2021 Instruction:"VPERMQ Vu{K}{z},aKq,Hu,Wu|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1205, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1209, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27763,9 +27802,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_u, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2019 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
+    // Pos:2022 Instruction:"VPERMQ Vu{K}{z},aKq,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1205, 
+        ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1209, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27778,9 +27817,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2020 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
+    // Pos:2023 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI"
     {
-        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1205, 
+        ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1209, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -27792,9 +27831,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2021 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
+    // Pos:2024 Instruction:"VPERMT2B Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1206, 
+        ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1210, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
         0,
@@ -27807,9 +27846,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2022 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
+    // Pos:2025 Instruction:"VPERMT2D Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1207, 
+        ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1211, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27822,9 +27861,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2023 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
+    // Pos:2026 Instruction:"VPERMT2PD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1208, 
+        ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1212, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27837,9 +27876,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2024 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
+    // Pos:2027 Instruction:"VPERMT2PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM"
     {
-        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1209, 
+        ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1213, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27852,9 +27891,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2025 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
+    // Pos:2028 Instruction:"VPERMT2Q Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM"
     {
-        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1210, 
+        ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1214, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27867,9 +27906,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2026 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
+    // Pos:2029 Instruction:"VPERMT2W Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM"
     {
-        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1211, 
+        ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1215, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -27882,9 +27921,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2027 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
+    // Pos:2030 Instruction:"VPERMW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM"
     {
-        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1212, 
+        ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1216, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -27897,11 +27936,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2028 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
+    // Pos:2031 Instruction:"VPEXPANDB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1213, 
+        ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1217, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
         0,
         0,
@@ -27911,9 +27950,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2029 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
+    // Pos:2032 Instruction:"VPEXPANDD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1214, 
+        ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1218, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27925,9 +27964,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2030 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
+    // Pos:2033 Instruction:"VPEXPANDQ Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM"
     {
-        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1215, 
+        ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1219, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -27939,11 +27978,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2031 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
+    // Pos:2034 Instruction:"VPEXPANDW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM"
     {
-        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1216, 
+        ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1220, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
         0,
         0,
@@ -27953,11 +27992,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2032 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
+    // Pos:2035 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1217, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1221, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -27967,11 +28006,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2033 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
+    // Pos:2036 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1217, 
+        ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1221, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -27981,11 +28020,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2034 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x14 /r:mem ib"/"MRI"
+    // Pos:2037 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1217, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1221, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
@@ -27995,23 +28034,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2035 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x14 /r:reg ib"/"MRI"
+    // Pos:2038 Instruction:"VPEXTRB Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1217, 
+        ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1221, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), 
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2036 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
+    // Pos:2039 Instruction:"VPEXTRD Ed,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1218, 
+        ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1222, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -28023,9 +28062,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2037 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
+    // Pos:2040 Instruction:"VPEXTRD Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1218, 
+        ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1222, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28037,9 +28076,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2038 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
+    // Pos:2041 Instruction:"VPEXTRQ Eq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1219, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1223, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -28051,9 +28090,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2039 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
+    // Pos:2042 Instruction:"VPEXTRQ Ey,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r ib"/"MRI"
     {
-        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1219, 
+        ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1223, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28065,9 +28104,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2040 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
+    // Pos:2043 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1224, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -28079,11 +28118,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2041 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
+    // Pos:2044 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1224, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -28093,11 +28132,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2042 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
+    // Pos:2045 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1220, 
+        ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1224, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -28107,11 +28146,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2043 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:0 0xC5 /r:reg ib"/"RMI"
+    // Pos:2046 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1220, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1224, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
@@ -28121,11 +28160,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2044 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x15 /r:mem ib"/"MRI"
+    // Pos:2047 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1220, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1224, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
@@ -28135,23 +28174,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2045 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x15 /r:reg ib"/"MRI"
+    // Pos:2048 Instruction:"VPEXTRW Rd,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI"
     {
-        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1220, 
+        ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1224, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
         0,
-        OP(ND_OPT_R, ND_OPS_y, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_R, ND_OPS_d, ND_OPF_W, 0, 0), 
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_R, 0, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2046 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
+    // Pos:2049 Instruction:"VPGATHERDD Vn{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1221, 
+        ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1225, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -28163,9 +28202,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm32n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2047 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
+    // Pos:2050 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1221, 
+        ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1225, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -28177,9 +28216,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2048 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
+    // Pos:2051 Instruction:"VPGATHERDQ Vn{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1222, 
+        ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1226, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -28191,9 +28230,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm32h, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2049 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
+    // Pos:2052 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1222, 
+        ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1226, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -28205,9 +28244,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2050 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
+    // Pos:2053 Instruction:"VPGATHERQD Vh{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1223, 
+        ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1227, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -28219,9 +28258,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2051 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
+    // Pos:2054 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1223, 
+        ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1227, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -28233,9 +28272,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2052 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
+    // Pos:2055 Instruction:"VPGATHERQQ Vn{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1224, 
+        ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1228, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -28247,9 +28286,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_vm64n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2053 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
+    // Pos:2056 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV"
     {
-        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1224, 
+        ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1228, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 
         0,
@@ -28261,9 +28300,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_x, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2054 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
+    // Pos:2057 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM"
     {
-        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1225, 
+        ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1229, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28274,9 +28313,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2055 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
+    // Pos:2058 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM"
     {
-        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1226, 
+        ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1230, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28287,9 +28326,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2056 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
+    // Pos:2059 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM"
     {
-        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1227, 
+        ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1231, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28300,9 +28339,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2057 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
+    // Pos:2060 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM"
     {
-        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1228, 
+        ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1232, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28314,9 +28353,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2058 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
+    // Pos:2061 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM"
     {
-        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1229, 
+        ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1233, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28327,9 +28366,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2059 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
+    // Pos:2062 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM"
     {
-        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1230, 
+        ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1234, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28341,9 +28380,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2060 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
+    // Pos:2063 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM"
     {
-        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1231, 
+        ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1235, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28354,9 +28393,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2061 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
+    // Pos:2064 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM"
     {
-        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1232, 
+        ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1236, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28367,9 +28406,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2062 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
+    // Pos:2065 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM"
     {
-        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1233, 
+        ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1237, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28380,9 +28419,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2063 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
+    // Pos:2066 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM"
     {
-        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1234, 
+        ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1238, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28393,9 +28432,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2064 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
+    // Pos:2067 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM"
     {
-        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1235, 
+        ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1239, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28406,9 +28445,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2065 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
+    // Pos:2068 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM"
     {
-        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1236, 
+        ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1240, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28419,9 +28458,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2066 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
+    // Pos:2069 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM"
     {
-        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1237, 
+        ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1241, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28433,9 +28472,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2067 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
+    // Pos:2070 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM"
     {
-        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1238, 
+        ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1242, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28446,9 +28485,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2068 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
+    // Pos:2071 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM"
     {
-        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1239, 
+        ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1243, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28459,9 +28498,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2069 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
+    // Pos:2072 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM"
     {
-        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1240, 
+        ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1244, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28472,9 +28511,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2070 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
+    // Pos:2073 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM"
     {
-        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1241, 
+        ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1245, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28485,9 +28524,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2071 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
+    // Pos:2074 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM"
     {
-        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1242, 
+        ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1246, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28499,9 +28538,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2072 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
+    // Pos:2075 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM"
     {
-        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1243, 
+        ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1247, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28512,9 +28551,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2073 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
+    // Pos:2076 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM"
     {
-        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1244, 
+        ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1248, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28526,9 +28565,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2074 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
+    // Pos:2077 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM"
     {
-        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1245, 
+        ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1249, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28540,9 +28579,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2075 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
+    // Pos:2078 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM"
     {
-        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1246, 
+        ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1250, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28553,11 +28592,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2076 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2079 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1247, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1251, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -28568,11 +28607,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2077 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2080 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1247, 
+        ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1251, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -28583,9 +28622,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2078 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
+    // Pos:2081 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1247, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1251, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28598,9 +28637,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2079 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
+    // Pos:2082 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1247, 
+        ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1251, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28613,9 +28652,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2080 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2083 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1248, 
+        ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1252, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -28628,9 +28667,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2081 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
+    // Pos:2084 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1248, 
+        ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1252, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28643,9 +28682,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2082 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2085 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1249, 
+        ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1253, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -28658,9 +28697,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2083 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
+    // Pos:2086 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI"
     {
-        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1249, 
+        ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1253, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -28673,11 +28712,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2084 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2087 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1250, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1254, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -28688,11 +28727,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2085 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2088 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1250, 
+        ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1254, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -28703,11 +28742,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2086 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:0 0xC4 /r:mem ib"/"RVMI"
+    // Pos:2089 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1250, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1254, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
@@ -28718,24 +28757,24 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2087 Instruction:"VPINSRW Vdq,Hdq,Ry,Ib" Encoding:"vex m:1 p:1 l:0 w:0 0xC4 /r:reg ib"/"RVMI"
+    // Pos:2090 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI"
     {
-        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1250, 
+        ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1254, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
+        0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
         0,
         0,
         0,
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_R, ND_OPS_y, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_R, ND_OPS_d, ND_OPF_R, 0, 0), 
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2088 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
+    // Pos:2091 Instruction:"VPLZCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1251, 
+        ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1255, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
         0,
@@ -28747,9 +28786,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2089 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
+    // Pos:2092 Instruction:"VPLZCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM"
     {
-        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1252, 
+        ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1256, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 
         0,
@@ -28761,9 +28800,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2090 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
+    // Pos:2093 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML"
     {
-        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1253, 
+        ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1257, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28776,9 +28815,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2091 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
+    // Pos:2094 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1254, 
+        ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1258, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28791,9 +28830,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2092 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
+    // Pos:2095 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML"
     {
-        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1255, 
+        ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1259, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28806,9 +28845,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2093 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
+    // Pos:2096 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1256, 
+        ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1260, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28821,9 +28860,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2094 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
+    // Pos:2097 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1257, 
+        ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1261, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28836,9 +28875,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2095 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
+    // Pos:2098 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1258, 
+        ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1262, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28851,9 +28890,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2096 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
+    // Pos:2099 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1259, 
+        ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1263, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28866,9 +28905,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2097 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
+    // Pos:2100 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML"
     {
-        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1260, 
+        ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1264, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28881,9 +28920,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2098 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
+    // Pos:2101 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1261, 
+        ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1265, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28896,9 +28935,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2099 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
+    // Pos:2102 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML"
     {
-        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1262, 
+        ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1266, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28911,9 +28950,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2100 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
+    // Pos:2103 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1263, 
+        ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1267, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28926,9 +28965,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2101 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
+    // Pos:2104 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML"
     {
-        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1264, 
+        ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1268, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -28941,9 +28980,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2102 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
+    // Pos:2105 Instruction:"VPMADD52HUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM"
     {
-        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1265, 
+        ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1269, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
         0,
@@ -28956,9 +28995,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2103 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
+    // Pos:2106 Instruction:"VPMADD52LUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM"
     {
-        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1266, 
+        ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1270, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 
         0,
@@ -28971,9 +29010,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2104 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
+    // Pos:2107 Instruction:"VPMADDUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1271, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -28986,9 +29025,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2105 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
+    // Pos:2108 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM"
     {
-        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1267, 
+        ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1271, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29000,9 +29039,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2106 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
+    // Pos:2109 Instruction:"VPMADDWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, 
+        ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1272, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29015,9 +29054,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2107 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
+    // Pos:2110 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM"
     {
-        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1268, 
+        ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1272, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29029,9 +29068,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2108 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
+    // Pos:2111 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1269, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1273, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29043,9 +29082,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2109 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
+    // Pos:2112 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1269, 
+        ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1273, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29057,9 +29096,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2110 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
+    // Pos:2113 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1270, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1274, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29071,9 +29110,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_M, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2111 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
+    // Pos:2114 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR"
     {
-        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1270, 
+        ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1274, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29085,9 +29124,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2112 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
+    // Pos:2115 Instruction:"VPMAXSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1271, 
+        ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29100,9 +29139,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2113 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
+    // Pos:2116 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM"
     {
-        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1271, 
+        ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1275, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29114,9 +29153,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2114 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
+    // Pos:2117 Instruction:"VPMAXSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1272, 
+        ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1276, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29129,9 +29168,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2115 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
+    // Pos:2118 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM"
     {
-        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1272, 
+        ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1276, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29143,9 +29182,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2116 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
+    // Pos:2119 Instruction:"VPMAXSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM"
     {
-        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1273, 
+        ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1277, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29158,9 +29197,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2117 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
+    // Pos:2120 Instruction:"VPMAXSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, 
+        ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1278, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29173,9 +29212,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2118 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
+    // Pos:2121 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM"
     {
-        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1274, 
+        ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1278, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29187,9 +29226,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2119 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
+    // Pos:2122 Instruction:"VPMAXUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 
+        ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1279, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29202,9 +29241,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2120 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
+    // Pos:2123 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM"
     {
-        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1275, 
+        ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1279, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29216,9 +29255,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2121 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
+    // Pos:2124 Instruction:"VPMAXUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1276, 
+        ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1280, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29231,9 +29270,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2122 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
+    // Pos:2125 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM"
     {
-        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1276, 
+        ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1280, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29245,9 +29284,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2123 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
+    // Pos:2126 Instruction:"VPMAXUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM"
     {
-        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1277, 
+        ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1281, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29260,9 +29299,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2124 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
+    // Pos:2127 Instruction:"VPMAXUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1278, 
+        ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29275,9 +29314,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2125 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
+    // Pos:2128 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM"
     {
-        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1278, 
+        ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1282, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29289,9 +29328,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2126 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
+    // Pos:2129 Instruction:"VPMINSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1279, 
+        ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1283, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29304,9 +29343,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2127 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
+    // Pos:2130 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM"
     {
-        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1279, 
+        ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1283, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29318,9 +29357,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2128 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
+    // Pos:2131 Instruction:"VPMINSD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1280, 
+        ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1284, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29333,9 +29372,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2129 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
+    // Pos:2132 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM"
     {
-        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1280, 
+        ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1284, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29347,9 +29386,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2130 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
+    // Pos:2133 Instruction:"VPMINSQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM"
     {
-        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1281, 
+        ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1285, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29362,9 +29401,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2131 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
+    // Pos:2134 Instruction:"VPMINSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1282, 
+        ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29377,9 +29416,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2132 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
+    // Pos:2135 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM"
     {
-        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1282, 
+        ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1286, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29391,9 +29430,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2133 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
+    // Pos:2136 Instruction:"VPMINUB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1283, 
+        ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1287, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29406,9 +29445,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2134 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
+    // Pos:2137 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM"
     {
-        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1283, 
+        ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1287, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29420,9 +29459,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2135 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
+    // Pos:2138 Instruction:"VPMINUD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1284, 
+        ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1288, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29435,9 +29474,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2136 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
+    // Pos:2139 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM"
     {
-        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1284, 
+        ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1288, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29449,9 +29488,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2137 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
+    // Pos:2140 Instruction:"VPMINUQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM"
     {
-        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1285, 
+        ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1289, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29464,9 +29503,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2138 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
+    // Pos:2141 Instruction:"VPMINUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, 
+        ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1290, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29479,9 +29518,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2139 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
+    // Pos:2142 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM"
     {
-        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1286, 
+        ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1290, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29493,9 +29532,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2140 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
+    // Pos:2143 Instruction:"VPMOVB2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1287, 
+        ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1291, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29506,9 +29545,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2141 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
+    // Pos:2144 Instruction:"VPMOVD2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1288, 
+        ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1292, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -29519,9 +29558,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2142 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
+    // Pos:2145 Instruction:"VPMOVDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR"
     {
-        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1289, 
+        ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1293, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29533,9 +29572,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2143 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
+    // Pos:2146 Instruction:"VPMOVDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR"
     {
-        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1290, 
+        ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1294, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29547,9 +29586,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2144 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
+    // Pos:2147 Instruction:"VPMOVM2B Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1291, 
+        ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1295, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29560,9 +29599,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2145 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
+    // Pos:2148 Instruction:"VPMOVM2D Vn,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1292, 
+        ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1296, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -29573,9 +29612,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2146 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
+    // Pos:2149 Instruction:"VPMOVM2Q Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1293, 
+        ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1297, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -29586,9 +29625,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2147 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
+    // Pos:2150 Instruction:"VPMOVM2W Vn,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM"
     {
-        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1294, 
+        ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1298, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29599,9 +29638,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_mK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2148 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
+    // Pos:2151 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM"
     {
-        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1295, 
+        ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1299, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29612,9 +29651,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2149 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
+    // Pos:2152 Instruction:"VPMOVQ2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM"
     {
-        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1296, 
+        ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1300, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -29625,9 +29664,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2150 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
+    // Pos:2153 Instruction:"VPMOVQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR"
     {
-        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1297, 
+        ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1301, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29639,9 +29678,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2151 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
+    // Pos:2154 Instruction:"VPMOVQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR"
     {
-        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1298, 
+        ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1302, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29653,9 +29692,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2152 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
+    // Pos:2155 Instruction:"VPMOVQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR"
     {
-        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1299, 
+        ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1303, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29667,9 +29706,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2153 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
+    // Pos:2156 Instruction:"VPMOVSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR"
     {
-        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1300, 
+        ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1304, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29681,9 +29720,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2154 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
+    // Pos:2157 Instruction:"VPMOVSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR"
     {
-        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1301, 
+        ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1305, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29695,9 +29734,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2155 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
+    // Pos:2158 Instruction:"VPMOVSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR"
     {
-        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1302, 
+        ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1306, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29709,9 +29748,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2156 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
+    // Pos:2159 Instruction:"VPMOVSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR"
     {
-        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1303, 
+        ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1307, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29723,9 +29762,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2157 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
+    // Pos:2160 Instruction:"VPMOVSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR"
     {
-        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1304, 
+        ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1308, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29737,9 +29776,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2158 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
+    // Pos:2161 Instruction:"VPMOVSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR"
     {
-        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1305, 
+        ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1309, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29751,9 +29790,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2159 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
+    // Pos:2162 Instruction:"VPMOVSXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1306, 
+        ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1310, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29765,9 +29804,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2160 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
+    // Pos:2163 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1306, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1310, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29778,9 +29817,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2161 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
+    // Pos:2164 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM"
     {
-        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1306, 
+        ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1310, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29791,9 +29830,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2162 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
+    // Pos:2165 Instruction:"VPMOVSXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1307, 
+        ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1311, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29805,9 +29844,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_e, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2163 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
+    // Pos:2166 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1307, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1311, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29818,9 +29857,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2164 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
+    // Pos:2167 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM"
     {
-        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1307, 
+        ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1311, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29831,9 +29870,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2165 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
+    // Pos:2168 Instruction:"VPMOVSXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1308, 
+        ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1312, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -29845,9 +29884,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2166 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
+    // Pos:2169 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1308, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1312, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29858,9 +29897,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2167 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
+    // Pos:2170 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM"
     {
-        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1308, 
+        ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1312, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29871,9 +29910,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2168 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
+    // Pos:2171 Instruction:"VPMOVSXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1309, 
+        ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1313, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29885,9 +29924,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2169 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
+    // Pos:2172 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1309, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1313, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29898,9 +29937,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2170 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
+    // Pos:2173 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM"
     {
-        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1309, 
+        ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1313, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29911,9 +29950,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2171 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
+    // Pos:2174 Instruction:"VPMOVSXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1310, 
+        ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1314, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29925,9 +29964,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2172 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
+    // Pos:2175 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1310, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1314, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29938,9 +29977,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2173 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
+    // Pos:2176 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM"
     {
-        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1310, 
+        ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1314, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29951,9 +29990,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2174 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
+    // Pos:2177 Instruction:"VPMOVSXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1311, 
+        ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1315, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -29965,9 +30004,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2175 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
+    // Pos:2178 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1311, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1315, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -29978,9 +30017,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2176 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
+    // Pos:2179 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM"
     {
-        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1311, 
+        ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1315, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -29991,9 +30030,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2177 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
+    // Pos:2180 Instruction:"VPMOVUSDB Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1312, 
+        ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1316, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30005,9 +30044,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2178 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
+    // Pos:2181 Instruction:"VPMOVUSDW Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR"
     {
-        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1313, 
+        ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1317, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30019,9 +30058,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2179 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
+    // Pos:2182 Instruction:"VPMOVUSQB We{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1314, 
+        ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1318, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30033,9 +30072,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2180 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
+    // Pos:2183 Instruction:"VPMOVUSQD Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1315, 
+        ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1319, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30047,9 +30086,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2181 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
+    // Pos:2184 Instruction:"VPMOVUSQW Wf{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR"
     {
-        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1316, 
+        ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30061,9 +30100,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2182 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
+    // Pos:2185 Instruction:"VPMOVUSWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR"
     {
-        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1317, 
+        ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1321, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30075,9 +30114,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2183 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
+    // Pos:2186 Instruction:"VPMOVW2M rKq,Un" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM"
     {
-        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1318, 
+        ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1322, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30088,9 +30127,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_U, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2184 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
+    // Pos:2187 Instruction:"VPMOVWB Wh{K}{z},aKq,Vn" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR"
     {
-        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1319, 
+        ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1323, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30102,9 +30141,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2185 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
+    // Pos:2188 Instruction:"VPMOVZXBD Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1320, 
+        ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30116,9 +30155,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2186 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
+    // Pos:2189 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1320, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1324, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30129,9 +30168,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2187 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
+    // Pos:2190 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM"
     {
-        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1320, 
+        ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1324, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -30142,9 +30181,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2188 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
+    // Pos:2191 Instruction:"VPMOVZXBQ Vn{K}{z},aKq,We" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1321, 
+        ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30156,9 +30195,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_e, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2189 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
+    // Pos:2192 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1321, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1325, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30169,9 +30208,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_w, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2190 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
+    // Pos:2193 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM"
     {
-        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1321, 
+        ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1325, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -30182,9 +30221,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2191 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
+    // Pos:2194 Instruction:"VPMOVZXBW Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1322, 
+        ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1326, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30196,9 +30235,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2192 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
+    // Pos:2195 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1322, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1326, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30209,9 +30248,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2193 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
+    // Pos:2196 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM"
     {
-        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1322, 
+        ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1326, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -30222,9 +30261,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2194 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
+    // Pos:2197 Instruction:"VPMOVZXDQ Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1323, 
+        ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1327, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30236,9 +30275,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2195 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
+    // Pos:2198 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1323, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1327, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30249,9 +30288,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2196 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
+    // Pos:2199 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM"
     {
-        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1323, 
+        ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1327, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -30262,9 +30301,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2197 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
+    // Pos:2200 Instruction:"VPMOVZXWD Vn{K}{z},aKq,Wh" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1324, 
+        ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30276,9 +30315,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_h, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2198 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
+    // Pos:2201 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1324, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30289,9 +30328,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2199 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
+    // Pos:2202 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM"
     {
-        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1324, 
+        ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1328, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -30302,9 +30341,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2200 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
+    // Pos:2203 Instruction:"VPMOVZXWQ Vn{K}{z},aKq,Wf" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1325, 
+        ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30316,9 +30355,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_f, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2201 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
+    // Pos:2204 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1325, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30329,9 +30368,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_d, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2202 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
+    // Pos:2205 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM"
     {
-        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1325, 
+        ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1329, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -30342,9 +30381,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2203 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
+    // Pos:2206 Instruction:"VPMULDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1326, 
+        ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30357,9 +30396,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2204 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
+    // Pos:2207 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM"
     {
-        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1326, 
+        ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1330, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30371,9 +30410,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2205 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
+    // Pos:2208 Instruction:"VPMULHRSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1327, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30386,9 +30425,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2206 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
+    // Pos:2209 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM"
     {
-        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1327, 
+        ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1331, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30400,9 +30439,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2207 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
+    // Pos:2210 Instruction:"VPMULHUW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1328, 
+        ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1332, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30415,9 +30454,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2208 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
+    // Pos:2211 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM"
     {
-        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1328, 
+        ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1332, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30429,9 +30468,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2209 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
+    // Pos:2212 Instruction:"VPMULHW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1329, 
+        ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1333, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30444,9 +30483,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2210 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
+    // Pos:2213 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM"
     {
-        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1329, 
+        ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1333, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30458,9 +30497,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2211 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
+    // Pos:2214 Instruction:"VPMULLD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1330, 
+        ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1334, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30473,9 +30512,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2212 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
+    // Pos:2215 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM"
     {
-        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1330, 
+        ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1334, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30487,9 +30526,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2213 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
+    // Pos:2216 Instruction:"VPMULLQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM"
     {
-        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1331, 
+        ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1335, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -30502,9 +30541,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2214 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
+    // Pos:2217 Instruction:"VPMULLW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1332, 
+        ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1336, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -30517,9 +30556,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2215 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
+    // Pos:2218 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM"
     {
-        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1332, 
+        ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1336, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30531,9 +30570,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2216 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
+    // Pos:2219 Instruction:"VPMULTISHIFTQB Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM"
     {
-        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1333, 
+        ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1337, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 
         0,
@@ -30546,9 +30585,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2217 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
+    // Pos:2220 Instruction:"VPMULUDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1334, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1338, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30561,9 +30600,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2218 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
+    // Pos:2221 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM"
     {
-        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1334, 
+        ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1338, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30575,9 +30614,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2219 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
+    // Pos:2222 Instruction:"VPOPCNTB Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1335, 
+        ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1339, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
         0,
@@ -30589,9 +30628,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2220 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
+    // Pos:2223 Instruction:"VPOPCNTD Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1336, 
+        ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1340, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
         0,
@@ -30603,9 +30642,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2221 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
+    // Pos:2224 Instruction:"VPOPCNTQ Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM"
     {
-        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1337, 
+        ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1341, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 
         0,
@@ -30617,9 +30656,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2222 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
+    // Pos:2225 Instruction:"VPOPCNTW Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM"
     {
-        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1338, 
+        ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1342, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
         0,
@@ -30631,9 +30670,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2223 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
+    // Pos:2226 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM"
     {
-        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1339, 
+        ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1343, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -30645,9 +30684,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2224 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
+    // Pos:2227 Instruction:"VPORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1340, 
+        ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1344, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30660,9 +30699,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2225 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
+    // Pos:2228 Instruction:"VPORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM"
     {
-        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1341, 
+        ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1345, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30675,9 +30714,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2226 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
+    // Pos:2229 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1342, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1346, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30690,9 +30729,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_L, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2227 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
+    // Pos:2230 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM"
     {
-        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1342, 
+        ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1346, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30705,9 +30744,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2228 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
+    // Pos:2231 Instruction:"VPROLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1343, 
+        ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1347, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30720,9 +30759,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2229 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
+    // Pos:2232 Instruction:"VPROLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI"
     {
-        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1344, 
+        ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1348, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30735,9 +30774,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2230 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2233 Instruction:"VPROLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1345, 
+        ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1349, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30750,9 +30789,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2231 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2234 Instruction:"VPROLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1346, 
+        ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1350, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30765,9 +30804,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2232 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
+    // Pos:2235 Instruction:"VPRORD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1347, 
+        ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1351, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30780,9 +30819,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2233 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
+    // Pos:2236 Instruction:"VPRORQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI"
     {
-        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1348, 
+        ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1352, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30795,9 +30834,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2234 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2237 Instruction:"VPRORVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1349, 
+        ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1353, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30810,9 +30849,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2235 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2238 Instruction:"VPRORVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1350, 
+        ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1354, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -30825,9 +30864,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2236 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
+    // Pos:2239 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1351, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1355, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30839,9 +30878,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2237 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
+    // Pos:2240 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1351, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1355, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30853,9 +30892,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2238 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
+    // Pos:2241 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM"
     {
-        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1351, 
+        ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1355, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30867,9 +30906,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2239 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
+    // Pos:2242 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1352, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1356, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30881,9 +30920,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2240 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
+    // Pos:2243 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1352, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1356, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30895,9 +30934,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2241 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
+    // Pos:2244 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM"
     {
-        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1352, 
+        ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1356, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30909,9 +30948,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2242 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
+    // Pos:2245 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1353, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1357, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30923,9 +30962,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2243 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
+    // Pos:2246 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1353, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1357, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30937,9 +30976,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2244 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
+    // Pos:2247 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM"
     {
-        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1353, 
+        ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1357, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30951,9 +30990,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2245 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
+    // Pos:2248 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1354, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1358, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30965,9 +31004,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2246 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
+    // Pos:2249 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1354, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1358, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30979,9 +31018,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2247 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
+    // Pos:2250 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM"
     {
-        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1354, 
+        ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1358, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -30993,9 +31032,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2248 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2251 Instruction:"VPSADBW Vn,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1355, 
+        ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1359, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31007,9 +31046,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2249 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
+    // Pos:2252 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM"
     {
-        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1355, 
+        ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1359, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31021,9 +31060,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2250 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2253 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1356, 
+        ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1360, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31035,9 +31074,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2251 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
+    // Pos:2254 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1357, 
+        ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1361, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31049,9 +31088,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2252 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2255 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1358, 
+        ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1362, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31063,9 +31102,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_h, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2253 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
+    // Pos:2256 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR"
     {
-        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1359, 
+        ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1363, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31077,9 +31116,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2254 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
+    // Pos:2257 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1360, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1364, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31091,9 +31130,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2255 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
+    // Pos:2258 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM"
     {
-        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1360, 
+        ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1364, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31105,9 +31144,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2256 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
+    // Pos:2259 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1361, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1365, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31119,9 +31158,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2257 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
+    // Pos:2260 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM"
     {
-        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1361, 
+        ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1365, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31133,9 +31172,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2258 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
+    // Pos:2261 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1362, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1366, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31147,9 +31186,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2259 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
+    // Pos:2262 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM"
     {
-        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1362, 
+        ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1366, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31161,9 +31200,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2260 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
+    // Pos:2263 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1363, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1367, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31175,9 +31214,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2261 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
+    // Pos:2264 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM"
     {
-        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1363, 
+        ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1367, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31189,9 +31228,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2262 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
+    // Pos:2265 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1368, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31203,9 +31242,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2263 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
+    // Pos:2266 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1368, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31217,9 +31256,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2264 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
+    // Pos:2267 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1368, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31227,13 +31266,13 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2265 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM"
+    // Pos:2268 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, 
+        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1368, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31245,9 +31284,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2266 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
+    // Pos:2269 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, 
+        ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1369, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31259,23 +31298,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2267 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM"
+    // Pos:2270 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1364, 
-        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
-        0,
-        0,
-        0,
-        0,
-        OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
-        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
-    }, 
-
-    // Pos:2268 Instruction:"VPSHLDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI"
-    {
-        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1365, 
+        ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1370, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31289,9 +31314,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2269 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
+    // Pos:2271 Instruction:"VPSHLDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1366, 
+        ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1371, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31305,9 +31330,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2270 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
+    // Pos:2272 Instruction:"VPSHLDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1367, 
+        ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1372, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31320,9 +31345,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2271 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
+    // Pos:2273 Instruction:"VPSHLDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1368, 
+        ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1373, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31335,9 +31360,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2272 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
+    // Pos:2274 Instruction:"VPSHLDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM"
     {
-        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1369, 
+        ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1374, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31350,9 +31375,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2273 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
+    // Pos:2275 Instruction:"VPSHLDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1370, 
+        ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1375, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31366,9 +31391,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2274 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
+    // Pos:2276 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1371, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1376, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31380,9 +31405,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2275 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
+    // Pos:2277 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM"
     {
-        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1371, 
+        ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1376, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
         0,
@@ -31394,9 +31419,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2276 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
+    // Pos:2278 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV"
+    {
+        ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1377, 
+        ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
+        0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 
+        0,
+        0,
+        0,
+        0,
+        OP(ND_OPT_V, ND_OPS_dq, ND_OPF_W, 0, 0), 
+        OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
+        OP(ND_OPT_H, ND_OPS_dq, ND_OPF_R, 0, 0), 
+    }, 
+
+    // Pos:2279 Instruction:"VPSHRDD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1372, 
+        ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1378, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31410,9 +31449,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2277 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
+    // Pos:2280 Instruction:"VPSHRDQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1373, 
+        ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1379, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31426,9 +31465,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2278 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
+    // Pos:2281 Instruction:"VPSHRDVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1374, 
+        ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1380, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31441,9 +31480,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2279 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
+    // Pos:2282 Instruction:"VPSHRDVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1375, 
+        ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1381, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31456,9 +31495,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2280 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
+    // Pos:2283 Instruction:"VPSHRDVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM"
     {
-        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1376, 
+        ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1382, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31471,9 +31510,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2281 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
+    // Pos:2284 Instruction:"VPSHRDW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI"
     {
-        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1377, 
+        ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1383, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 
         0,
@@ -31487,9 +31526,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2282 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
+    // Pos:2285 Instruction:"VPSHUFB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1378, 
+        ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1384, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31502,9 +31541,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2283 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
+    // Pos:2286 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM"
     {
-        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1378, 
+        ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1384, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31516,9 +31555,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2284 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
+    // Pos:2287 Instruction:"VPSHUFBITQMB rK{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM"
     {
-        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1379, 
+        ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1385, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 
         0,
@@ -31531,9 +31570,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2285 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
+    // Pos:2288 Instruction:"VPSHUFD Vn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1380, 
+        ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1386, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31546,9 +31585,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2286 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2289 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1380, 
+        ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1386, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31560,9 +31599,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2287 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2290 Instruction:"VPSHUFHW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1381, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1387, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31575,9 +31614,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2288 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2291 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1381, 
+        ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1387, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31589,9 +31628,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2289 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
+    // Pos:2292 Instruction:"VPSHUFLW Vn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1382, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1388, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31604,9 +31643,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2290 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
+    // Pos:2293 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI"
     {
-        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1382, 
+        ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1388, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31618,9 +31657,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2291 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
+    // Pos:2294 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM"
     {
-        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1383, 
+        ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1389, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31632,9 +31671,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2292 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
+    // Pos:2295 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM"
     {
-        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1384, 
+        ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1390, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31646,9 +31685,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2293 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
+    // Pos:2296 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM"
     {
-        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1385, 
+        ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1391, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31660,9 +31699,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2294 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
+    // Pos:2297 Instruction:"VPSLLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1386, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1392, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31675,9 +31714,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2295 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
+    // Pos:2298 Instruction:"VPSLLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1386, 
+        ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1392, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31690,9 +31729,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2296 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
+    // Pos:2299 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1386, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1392, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31704,9 +31743,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2297 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
+    // Pos:2300 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM"
     {
-        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1386, 
+        ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1392, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31718,9 +31757,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2298 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
+    // Pos:2301 Instruction:"VPSLLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1387, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1393, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31732,9 +31771,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2299 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
+    // Pos:2302 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI"
     {
-        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1387, 
+        ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1393, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31746,9 +31785,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2300 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
+    // Pos:2303 Instruction:"VPSLLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1388, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31761,9 +31800,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2301 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
+    // Pos:2304 Instruction:"VPSLLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1388, 
+        ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31776,9 +31815,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2302 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
+    // Pos:2305 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1388, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1394, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31790,9 +31829,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2303 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
+    // Pos:2306 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM"
     {
-        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1388, 
+        ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1394, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31804,9 +31843,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2304 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
+    // Pos:2307 Instruction:"VPSLLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1389, 
+        ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1395, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31819,9 +31858,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2305 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
+    // Pos:2308 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1389, 
+        ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1395, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -31833,9 +31872,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2306 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
+    // Pos:2309 Instruction:"VPSLLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1390, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1396, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31848,9 +31887,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2307 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
+    // Pos:2310 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM"
     {
-        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1390, 
+        ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1396, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -31862,9 +31901,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2308 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
+    // Pos:2311 Instruction:"VPSLLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM"
     {
-        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1391, 
+        ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1397, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31877,11 +31916,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2309 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
+    // Pos:2312 Instruction:"VPSLLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1392, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1398, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -31892,9 +31931,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2310 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
+    // Pos:2313 Instruction:"VPSLLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1392, 
+        ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1398, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -31907,9 +31946,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2311 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
+    // Pos:2314 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1392, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1398, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31921,9 +31960,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2312 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
+    // Pos:2315 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM"
     {
-        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1392, 
+        ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1398, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31935,9 +31974,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2313 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
+    // Pos:2316 Instruction:"VPSRAD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1393, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31950,9 +31989,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2314 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
+    // Pos:2317 Instruction:"VPSRAD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1393, 
+        ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -31965,9 +32004,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2315 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
+    // Pos:2318 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1393, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1399, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31979,9 +32018,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2316 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
+    // Pos:2319 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM"
     {
-        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1393, 
+        ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1399, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -31993,9 +32032,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2317 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
+    // Pos:2320 Instruction:"VPSRAQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1400, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32008,9 +32047,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2318 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
+    // Pos:2321 Instruction:"VPSRAQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM"
     {
-        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1394, 
+        ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1400, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32023,9 +32062,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2319 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
+    // Pos:2322 Instruction:"VPSRAVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1395, 
+        ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1401, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32038,9 +32077,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2320 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
+    // Pos:2323 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM"
     {
-        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1395, 
+        ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1401, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -32052,9 +32091,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2321 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
+    // Pos:2324 Instruction:"VPSRAVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM"
     {
-        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1396, 
+        ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1402, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32067,9 +32106,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2322 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
+    // Pos:2325 Instruction:"VPSRAVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM"
     {
-        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1397, 
+        ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1403, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32082,11 +32121,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2323 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
+    // Pos:2326 Instruction:"VPSRAW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1398, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1404, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -32097,9 +32136,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2324 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
+    // Pos:2327 Instruction:"VPSRAW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1398, 
+        ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1404, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32112,9 +32151,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2325 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
+    // Pos:2328 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1398, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1404, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32126,9 +32165,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2326 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
+    // Pos:2329 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM"
     {
-        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1398, 
+        ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1404, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32140,9 +32179,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2327 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
+    // Pos:2330 Instruction:"VPSRLD Hn{K}{z},aKq,Wn|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1405, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32155,9 +32194,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2328 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
+    // Pos:2331 Instruction:"VPSRLD Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1399, 
+        ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1405, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32170,9 +32209,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2329 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
+    // Pos:2332 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1399, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1405, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32184,9 +32223,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2330 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
+    // Pos:2333 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM"
     {
-        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1399, 
+        ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1405, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32198,9 +32237,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2331 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
+    // Pos:2334 Instruction:"VPSRLDQ Hn,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1400, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32212,9 +32251,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2332 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
+    // Pos:2335 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI"
     {
-        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1400, 
+        ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1406, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32226,9 +32265,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2333 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
+    // Pos:2336 Instruction:"VPSRLQ Hn{K}{z},aKq,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1401, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1407, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32241,9 +32280,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2334 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
+    // Pos:2337 Instruction:"VPSRLQ Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1401, 
+        ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1407, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32256,9 +32295,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2335 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
+    // Pos:2338 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1401, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1407, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32270,9 +32309,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2336 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
+    // Pos:2339 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM"
     {
-        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1401, 
+        ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1407, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32284,9 +32323,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2337 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
+    // Pos:2340 Instruction:"VPSRLVD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1402, 
+        ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1408, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32299,9 +32338,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2338 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
+    // Pos:2341 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1402, 
+        ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1408, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -32313,9 +32352,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2339 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
+    // Pos:2342 Instruction:"VPSRLVQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1403, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1409, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32328,9 +32367,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2340 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
+    // Pos:2343 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM"
     {
-        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1403, 
+        ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1409, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 
         0,
@@ -32342,9 +32381,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2341 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
+    // Pos:2344 Instruction:"VPSRLVW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM"
     {
-        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1404, 
+        ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32357,11 +32396,11 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2342 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
+    // Pos:2345 Instruction:"VPSRLW Hn{K}{z},aKq,Wn,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1405, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1411, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
-        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
+        0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
         0,
         0,
@@ -32372,9 +32411,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2343 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
+    // Pos:2346 Instruction:"VPSRLW Vn{K}{z},aKq,Hn,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1405, 
+        ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1411, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32387,9 +32426,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2344 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
+    // Pos:2347 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1405, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1411, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32401,9 +32440,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2345 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
+    // Pos:2348 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM"
     {
-        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1405, 
+        ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1411, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32415,9 +32454,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_dq, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2346 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
+    // Pos:2349 Instruction:"VPSUBB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1406, 
+        ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1412, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32430,9 +32469,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2347 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
+    // Pos:2350 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM"
     {
-        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1406, 
+        ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1412, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32444,9 +32483,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2348 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
+    // Pos:2351 Instruction:"VPSUBD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1407, 
+        ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1413, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32459,9 +32498,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2349 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
+    // Pos:2352 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM"
     {
-        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1407, 
+        ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1413, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32473,9 +32512,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2350 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
+    // Pos:2353 Instruction:"VPSUBQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1408, 
+        ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1414, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32488,9 +32527,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2351 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
+    // Pos:2354 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM"
     {
-        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1408, 
+        ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1414, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32502,9 +32541,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2352 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
+    // Pos:2355 Instruction:"VPSUBSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1409, 
+        ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1415, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32517,9 +32556,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2353 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
+    // Pos:2356 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM"
     {
-        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1409, 
+        ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1415, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32531,9 +32570,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2354 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
+    // Pos:2357 Instruction:"VPSUBSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 
+        ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1416, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32546,9 +32585,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2355 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
+    // Pos:2358 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM"
     {
-        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1410, 
+        ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1416, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32560,9 +32599,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2356 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
+    // Pos:2359 Instruction:"VPSUBUSB Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1411, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1417, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32575,9 +32614,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2357 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
+    // Pos:2360 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM"
     {
-        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1411, 
+        ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1417, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32589,9 +32628,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2358 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
+    // Pos:2361 Instruction:"VPSUBUSW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1412, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1418, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32604,9 +32643,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2359 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
+    // Pos:2362 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM"
     {
-        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1412, 
+        ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1418, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32618,9 +32657,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2360 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
+    // Pos:2363 Instruction:"VPSUBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 
+        ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1419, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32633,9 +32672,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2361 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
+    // Pos:2364 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM"
     {
-        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1413, 
+        ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1419, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32647,9 +32686,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2362 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
+    // Pos:2365 Instruction:"VPTERNLOGD Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1414, 
+        ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1420, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32663,9 +32702,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2363 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
+    // Pos:2366 Instruction:"VPTERNLOGQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI"
     {
-        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1415, 
+        ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1421, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32679,9 +32718,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2364 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
+    // Pos:2367 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM"
     {
-        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1416, 
+        ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1422, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32693,9 +32732,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2365 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2368 Instruction:"VPTESTMB rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1417, 
+        ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1423, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32708,9 +32747,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2366 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2369 Instruction:"VPTESTMD rKq{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1418, 
+        ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1424, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32723,9 +32762,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2367 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2370 Instruction:"VPTESTMQ rKq{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1419, 
+        ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1425, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32738,9 +32777,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2368 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2371 Instruction:"VPTESTMW rKq{K}{z},aKq,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1420, 
+        ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1426, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32753,9 +32792,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2369 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
+    // Pos:2372 Instruction:"VPTESTNMB rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1421, 
+        ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1427, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32768,9 +32807,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2370 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
+    // Pos:2373 Instruction:"VPTESTNMD rKq{K},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1422, 
+        ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1428, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32783,9 +32822,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2371 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
+    // Pos:2374 Instruction:"VPTESTNMQ rKq{K},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1423, 
+        ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1429, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32798,9 +32837,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2372 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
+    // Pos:2375 Instruction:"VPTESTNMW rKq{K},aKq,Hn,Wn" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM"
     {
-        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1424, 
+        ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1430, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32813,9 +32852,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2373 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
+    // Pos:2376 Instruction:"VPUNPCKHBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1425, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32828,9 +32867,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2374 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
+    // Pos:2377 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1425, 
+        ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1431, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32842,9 +32881,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2375 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
+    // Pos:2378 Instruction:"VPUNPCKHDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1426, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1432, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32857,9 +32896,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2376 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
+    // Pos:2379 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM"
     {
-        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1426, 
+        ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1432, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32871,9 +32910,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2377 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
+    // Pos:2380 Instruction:"VPUNPCKHQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1427, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1433, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32886,9 +32925,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2378 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
+    // Pos:2381 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM"
     {
-        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1427, 
+        ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1433, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32900,9 +32939,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2379 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
+    // Pos:2382 Instruction:"VPUNPCKHWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1428, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32915,9 +32954,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2380 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
+    // Pos:2383 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM"
     {
-        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1428, 
+        ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1434, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32929,9 +32968,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2381 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
+    // Pos:2384 Instruction:"VPUNPCKLBW Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1429, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1435, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -32944,9 +32983,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2382 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
+    // Pos:2385 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1429, 
+        ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1435, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32958,9 +32997,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2383 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
+    // Pos:2386 Instruction:"VPUNPCKLDQ Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1430, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1436, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -32973,9 +33012,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2384 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
+    // Pos:2387 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1430, 
+        ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1436, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -32987,9 +33026,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2385 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
+    // Pos:2388 Instruction:"VPUNPCKLQDQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1431, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1437, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33002,9 +33041,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2386 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
+    // Pos:2389 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM"
     {
-        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1431, 
+        ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1437, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33016,9 +33055,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2387 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
+    // Pos:2390 Instruction:"VPUNPCKLWD Vn{K}{z},aKq,Hn,Wn" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1432, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 
         0,
@@ -33031,9 +33070,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2388 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
+    // Pos:2391 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM"
     {
-        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1432, 
+        ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1438, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33045,9 +33084,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2389 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
+    // Pos:2392 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM"
     {
-        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1433, 
+        ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1439, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33059,9 +33098,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2390 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
+    // Pos:2393 Instruction:"VPXORD Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1434, 
+        ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1440, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33074,9 +33113,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2391 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
+    // Pos:2394 Instruction:"VPXORQ Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM"
     {
-        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1435, 
+        ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1441, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33089,9 +33128,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2392 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
+    // Pos:2395 Instruction:"VRANGEPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1436, 
+        ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1442, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33105,9 +33144,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2393 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
+    // Pos:2396 Instruction:"VRANGEPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1437, 
+        ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1443, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33121,9 +33160,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2394 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
+    // Pos:2397 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1438, 
+        ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1444, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33137,9 +33176,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2395 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
+    // Pos:2398 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI"
     {
-        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1439, 
+        ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1445, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33153,9 +33192,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2396 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
+    // Pos:2399 Instruction:"VRCP14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1440, 
+        ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1446, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33167,9 +33206,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2397 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
+    // Pos:2400 Instruction:"VRCP14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM"
     {
-        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1441, 
+        ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1447, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33181,9 +33220,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2398 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
+    // Pos:2401 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1442, 
+        ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1448, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33196,9 +33235,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2399 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
+    // Pos:2402 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM"
     {
-        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1443, 
+        ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1449, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33211,9 +33250,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2400 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
+    // Pos:2403 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1444, 
+        ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1450, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33225,9 +33264,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2401 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
+    // Pos:2404 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM"
     {
-        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1445, 
+        ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1451, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33239,9 +33278,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2402 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
+    // Pos:2405 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1446, 
+        ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1452, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33254,9 +33293,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:2403 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
+    // Pos:2406 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM"
     {
-        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1447, 
+        ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1453, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33269,9 +33308,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:2404 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
+    // Pos:2407 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM"
     {
-        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1448, 
+        ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1454, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33282,9 +33321,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2405 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
+    // Pos:2408 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM"
     {
-        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1449, 
+        ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1455, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33296,9 +33335,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2406 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
+    // Pos:2409 Instruction:"VREDUCEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1450, 
+        ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1456, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33311,9 +33350,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2407 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
+    // Pos:2410 Instruction:"VREDUCEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI"
     {
-        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1451, 
+        ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1457, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33326,9 +33365,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2408 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
+    // Pos:2411 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1452, 
+        ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1458, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33342,9 +33381,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2409 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
+    // Pos:2412 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI"
     {
-        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1453, 
+        ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1459, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -33358,9 +33397,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2410 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
+    // Pos:2413 Instruction:"VRNDSCALEPD Vn{K}{z},aKq,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1454, 
+        ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1460, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33373,9 +33412,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2411 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
+    // Pos:2414 Instruction:"VRNDSCALEPS Vn{K}{z},aKq,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI"
     {
-        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1455, 
+        ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1461, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33388,9 +33427,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2412 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
+    // Pos:2415 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1456, 
+        ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1462, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33404,9 +33443,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2413 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
+    // Pos:2416 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI"
     {
-        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1457, 
+        ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1463, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33420,9 +33459,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2414 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
+    // Pos:2417 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1458, 
+        ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1464, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33434,9 +33473,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2415 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
+    // Pos:2418 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI"
     {
-        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1459, 
+        ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1465, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33448,9 +33487,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2416 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
+    // Pos:2419 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1460, 
+        ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1466, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33463,9 +33502,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2417 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
+    // Pos:2420 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI"
     {
-        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1461, 
+        ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1467, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33478,9 +33517,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2418 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
+    // Pos:2421 Instruction:"VRSQRT14PD Vn{K}{z},aKq,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1462, 
+        ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1468, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33492,9 +33531,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2419 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
+    // Pos:2422 Instruction:"VRSQRT14PS Vn{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM"
     {
-        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1463, 
+        ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1469, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33506,9 +33545,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2420 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
+    // Pos:2423 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1464, 
+        ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1470, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33521,9 +33560,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2421 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
+    // Pos:2424 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM"
     {
-        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1465, 
+        ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1471, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33536,9 +33575,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2422 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
+    // Pos:2425 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1466, 
+        ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1472, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33550,9 +33589,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2423 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
+    // Pos:2426 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM"
     {
-        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1467, 
+        ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1473, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33564,9 +33603,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_oq, ND_OPF_R, ND_OPD_SAE|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2424 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
+    // Pos:2427 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1468, 
+        ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1474, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33579,9 +33618,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:2425 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
+    // Pos:2428 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM"
     {
-        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1469, 
+        ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1475, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 
         0,
@@ -33594,9 +33633,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_SAE, 0), 
     }, 
 
-    // Pos:2426 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
+    // Pos:2429 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM"
     {
-        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1470, 
+        ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1476, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33607,9 +33646,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2427 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
+    // Pos:2430 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM"
     {
-        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1471, 
+        ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1477, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33621,9 +33660,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2428 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
+    // Pos:2431 Instruction:"VSCALEFPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1472, 
+        ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1478, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33636,9 +33675,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2429 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
+    // Pos:2432 Instruction:"VSCALEFPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM"
     {
-        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1473, 
+        ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1479, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33651,9 +33690,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2430 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
+    // Pos:2433 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1474, 
+        ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1480, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33666,9 +33705,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:2431 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
+    // Pos:2434 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM"
     {
-        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1475, 
+        ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1481, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33681,9 +33720,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:2432 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2435 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1476, 
+        ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1482, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33695,9 +33734,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2433 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
+    // Pos:2436 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1477, 
+        ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1483, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33709,9 +33748,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2434 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
+    // Pos:2437 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1478, 
+        ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1484, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33722,9 +33761,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2435 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
+    // Pos:2438 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1479, 
+        ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1485, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33735,9 +33774,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2436 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
+    // Pos:2439 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1480, 
+        ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1486, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33748,9 +33787,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2437 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
+    // Pos:2440 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1481, 
+        ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1487, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33761,9 +33800,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2438 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
+    // Pos:2441 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1482, 
+        ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1488, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33774,9 +33813,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2439 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
+    // Pos:2442 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1483, 
+        ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1489, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33787,9 +33826,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2440 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
+    // Pos:2443 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1484, 
+        ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1490, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33800,9 +33839,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2441 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
+    // Pos:2444 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA"
     {
-        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1485, 
+        ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1491, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 
         0,
@@ -33813,9 +33852,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_aK, ND_OPS_q, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2442 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2445 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1486, 
+        ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1492, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33827,9 +33866,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_n, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2443 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
+    // Pos:2446 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vh" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR"
     {
-        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1487, 
+        ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1493, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33841,9 +33880,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_V, ND_OPS_h, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2444 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
+    // Pos:2447 Instruction:"VSHUFF32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1488, 
+        ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1494, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33857,9 +33896,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2445 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
+    // Pos:2448 Instruction:"VSHUFF64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1489, 
+        ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1495, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33873,9 +33912,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2446 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
+    // Pos:2449 Instruction:"VSHUFI32X4 Vu{K}{z},aKq,Hu,Wu|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1490, 
+        ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1496, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33889,9 +33928,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2447 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
+    // Pos:2450 Instruction:"VSHUFI64X2 Vu{K}{z},aKq,Hu,Wu|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1491, 
+        ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33905,9 +33944,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2448 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
+    // Pos:2451 Instruction:"VSHUFPD Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1492, 
+        ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1498, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33921,9 +33960,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2449 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2452 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1492, 
+        ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1498, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33936,9 +33975,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2450 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
+    // Pos:2453 Instruction:"VSHUFPS Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1493, 
+        ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33952,9 +33991,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2451 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
+    // Pos:2454 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI"
     {
-        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1493, 
+        ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1499, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33967,9 +34006,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_I, ND_OPS_b, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2452 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
+    // Pos:2455 Instruction:"VSQRTPD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1494, 
+        ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -33981,9 +34020,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2453 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
+    // Pos:2456 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1494, 
+        ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1500, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -33994,9 +34033,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2454 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
+    // Pos:2457 Instruction:"VSQRTPS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1495, 
+        ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34008,9 +34047,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2455 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
+    // Pos:2458 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM"
     {
-        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1495, 
+        ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1501, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34021,9 +34060,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2456 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
+    // Pos:2459 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1496, 
+        ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34036,9 +34075,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:2457 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2460 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1496, 
+        ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1502, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34050,9 +34089,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2458 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
+    // Pos:2461 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 
+        ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1503, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34065,9 +34104,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:2459 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
+    // Pos:2462 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM"
     {
-        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1497, 
+        ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1503, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34079,9 +34118,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2460 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
+    // Pos:2463 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M"
     {
-        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1498, 
+        ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1504, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 
         0,
@@ -34092,9 +34131,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2461 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
+    // Pos:2464 Instruction:"VSUBPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1499, 
+        ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1505, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34107,9 +34146,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2462 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2465 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1499, 
+        ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1505, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34121,9 +34160,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2463 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
+    // Pos:2466 Instruction:"VSUBPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1500, 
+        ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1506, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34136,9 +34175,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_ER|ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2464 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
+    // Pos:2467 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1500, 
+        ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1506, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34150,9 +34189,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2465 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
+    // Pos:2468 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1501, 
+        ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1507, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34165,9 +34204,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:2466 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2469 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1501, 
+        ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1507, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34179,9 +34218,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_sd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2467 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
+    // Pos:2470 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1502, 
+        ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1508, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34194,9 +34233,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, ND_OPD_ER, 0), 
     }, 
 
-    // Pos:2468 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
+    // Pos:2471 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM"
     {
-        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1502, 
+        ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1508, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34208,9 +34247,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ss, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2469 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
+    // Pos:2472 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM"
     {
-        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1503, 
+        ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1509, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34222,9 +34261,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2470 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
+    // Pos:2473 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM"
     {
-        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1504, 
+        ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1510, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34236,9 +34275,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2471 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
+    // Pos:2474 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1505, 
+        ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1511, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34250,9 +34289,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2472 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
+    // Pos:2475 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1505, 
+        ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1511, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34264,9 +34303,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2473 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
+    // Pos:2476 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1506, 
+        ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1512, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34278,9 +34317,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2474 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
+    // Pos:2477 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM"
     {
-        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1506, 
+        ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1512, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34292,9 +34331,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2475 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
+    // Pos:2478 Instruction:"VUNPCKHPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1507, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1513, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34307,9 +34346,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2476 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2479 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1507, 
+        ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1513, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34321,9 +34360,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2477 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
+    // Pos:2480 Instruction:"VUNPCKHPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1508, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1514, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34336,9 +34375,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2478 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
+    // Pos:2481 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM"
     {
-        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1508, 
+        ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1514, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34350,9 +34389,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2479 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
+    // Pos:2482 Instruction:"VUNPCKLPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1509, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1515, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34365,9 +34404,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2480 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2483 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1509, 
+        ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1515, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34379,9 +34418,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2481 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
+    // Pos:2484 Instruction:"VUNPCKLPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1510, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1516, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 
         0,
@@ -34394,9 +34433,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2482 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
+    // Pos:2485 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM"
     {
-        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1510, 
+        ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1516, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34408,9 +34447,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2483 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
+    // Pos:2486 Instruction:"VXORPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1511, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1517, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -34423,9 +34462,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B64, 0), 
     }, 
 
-    // Pos:2484 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2487 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1511, 
+        ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1517, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34437,9 +34476,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2485 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
+    // Pos:2488 Instruction:"VXORPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1512, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1518, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 
         0,
@@ -34452,9 +34491,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_n, ND_OPF_R, ND_OPD_B32, 0), 
     }, 
 
-    // Pos:2486 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
+    // Pos:2489 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM"
     {
-        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1512, 
+        ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1518, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 
         0,
@@ -34466,9 +34505,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2487 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
+    // Pos:2490 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/""
     {
-        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1513, 
+        ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1519, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
         0,
@@ -34478,9 +34517,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2488 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
+    // Pos:2491 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/""
     {
-        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1514, 
+        ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1520, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 
         0, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 
         0,
@@ -34490,9 +34529,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2489 Instruction:"WAIT" Encoding:"0x9B"/""
+    // Pos:2492 Instruction:"WAIT" Encoding:"0x9B"/""
     {
-        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1515, 
+        ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1521, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, 
         0,
@@ -34501,9 +34540,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2490 Instruction:"WBINVD" Encoding:"NP 0x0F 0x09"/""
+    // Pos:2493 Instruction:"WBINVD" Encoding:"0x0F 0x09"/""
     {
-        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1516, 
+        ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1522, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 
         0,
@@ -34512,9 +34551,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2491 Instruction:"WBNOINVD" Encoding:"0xF3 0x0F 0x09"/""
+    // Pos:2494 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/""
     {
-        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1517, 
+        ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1523, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, 
         0,
@@ -34523,9 +34562,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2492 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
+    // Pos:2495 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M"
     {
-        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1518, 
+        ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1524, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
         0,
@@ -34536,9 +34575,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2493 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
+    // Pos:2496 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M"
     {
-        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1519, 
+        ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1525, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 
         0,
@@ -34549,9 +34588,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2494 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
+    // Pos:2497 Instruction:"WRMSR" Encoding:"0x0F 0x30"/""
     {
-        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1520, 
+        ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1526, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, 
         0,
@@ -34564,9 +34603,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2495 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
+    // Pos:2498 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/""
     {
-        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1521, 
+        ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1527, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 
         0,
@@ -34579,9 +34618,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2496 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
+    // Pos:2499 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M"
     {
-        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1522, 
+        ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1528, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34591,9 +34630,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_E, ND_OPS_d, ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2497 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2500 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1523, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1529, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -34604,9 +34643,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2498 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
+    // Pos:2501 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
     {
-        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1524, 
+        ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1530, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -34617,9 +34656,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2499 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2502 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1525, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1531, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -34630,9 +34669,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2500 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
+    // Pos:2503 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
     {
-        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1526, 
+        ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1532, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 
         0,
@@ -34643,9 +34682,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_G, ND_OPS_y, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2501 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
+    // Pos:2504 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I"
     {
-        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1527, 
+        ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1533, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 
         0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
         0,
@@ -34656,9 +34695,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_RCW, 0, 0), 
     }, 
 
-    // Pos:2502 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
+    // Pos:2505 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1528, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1534, 
         ND_MOD_ANY, 
         ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34670,9 +34709,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2503 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
+    // Pos:2506 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR"
     {
-        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1528, 
+        ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1534, 
         ND_MOD_ANY, 
         ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34684,9 +34723,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2504 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
+    // Pos:2507 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D"
     {
-        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1529, 
+        ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1535, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
         0,
@@ -34694,13 +34733,13 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
         0,
         OP(ND_OPT_J, ND_OPS_z, ND_OPF_R, 0, 0), 
-        OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_RW, 0, 0), 
         OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT|ND_OPF_CW, 0, 0), 
     }, 
 
-    // Pos:2505 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
+    // Pos:2508 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34711,9 +34750,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_G, ND_OPS_b, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2506 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
+    // Pos:2509 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34724,9 +34763,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_G, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2507 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O"
+    // Pos:2510 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34737,9 +34776,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2508 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O"
+    // Pos:2511 Instruction:"XCHG rAX,Zv" Encoding:"0x91"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34750,9 +34789,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2509 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O"
+    // Pos:2512 Instruction:"XCHG rAX,Zv" Encoding:"0x92"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34763,9 +34802,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2510 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O"
+    // Pos:2513 Instruction:"XCHG rAX,Zv" Encoding:"0x93"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34776,9 +34815,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2511 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O"
+    // Pos:2514 Instruction:"XCHG rAX,Zv" Encoding:"0x94"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34789,9 +34828,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2512 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O"
+    // Pos:2515 Instruction:"XCHG rAX,Zv" Encoding:"0x95"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34802,9 +34841,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2513 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O"
+    // Pos:2516 Instruction:"XCHG rAX,Zv" Encoding:"0x96"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34815,9 +34854,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2514 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O"
+    // Pos:2517 Instruction:"XCHG rAX,Zv" Encoding:"0x97"/"O"
     {
-        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1530, 
+        ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1536, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34828,9 +34867,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_Z, ND_OPS_v, ND_OPF_RW, 0, 0), 
     }, 
 
-    // Pos:2515 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
+    // Pos:2518 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/""
     {
-        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1531, 
+        ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1537, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34839,9 +34878,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2516 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
+    // Pos:2519 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/""
     {
-        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1532, 
+        ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1538, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34850,9 +34889,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2517 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
+    // Pos:2520 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/""
     {
-        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1533, 
+        ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1539, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34861,9 +34900,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2518 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
+    // Pos:2521 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/""
     {
-        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1534, 
+        ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1540, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34872,9 +34911,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2519 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
+    // Pos:2522 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/""
     {
-        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1535, 
+        ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1541, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34883,9 +34922,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2520 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
+    // Pos:2523 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/""
     {
-        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1536, 
+        ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1542, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
         0,
@@ -34894,9 +34933,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2521 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
+    // Pos:2524 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/""
     {
-        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1537, 
+        ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1543, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -34909,9 +34948,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2522 Instruction:"XLATB" Encoding:"0xD7"/""
+    // Pos:2525 Instruction:"XLATB" Encoding:"0xD7"/""
     {
-        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1538, 
+        ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1544, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34922,9 +34961,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_MEM_rBX_AL, ND_OPS_b, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2523 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
+    // Pos:2526 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34936,9 +34975,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2524 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
+    // Pos:2527 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34950,9 +34989,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2525 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
+    // Pos:2528 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34964,9 +35003,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2526 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
+    // Pos:2529 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -34978,9 +35017,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2527 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
+    // Pos:2530 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -34992,9 +35031,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2528 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
+    // Pos:2531 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 
         0,
@@ -35006,9 +35045,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2529 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
+    // Pos:2532 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -35020,9 +35059,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2530 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
+    // Pos:2533 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -35034,23 +35073,23 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2531 Instruction:"XOR Ev,Iz" Encoding:"0x82 /6 iz"/"MI"
+    // Pos:2534 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 
         0,
         0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF,
         0|REG_RFLAG_AF,
         0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF,
-        OP(ND_OPT_E, ND_OPS_v, ND_OPF_RW, 0, 0), 
-        OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
+        OP(ND_OPT_E, ND_OPS_b, ND_OPF_RW, 0, 0), 
+        OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1|ND_OPF_R, 0, 0), 
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2532 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
+    // Pos:2535 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI"
     {
-        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1539, 
+        ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1545, 
         ND_MOD_ANY, 
         ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -35062,9 +35101,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2533 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
+    // Pos:2536 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1540, 
+        ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1546, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 
         0,
@@ -35075,9 +35114,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_pd, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2534 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
+    // Pos:2537 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM"
     {
-        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1541, 
+        ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1547, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 
         0,
@@ -35088,9 +35127,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_W, ND_OPS_ps, ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2535 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
+    // Pos:2538 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/""
     {
-        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1542, 
+        ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1548, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
         0,
@@ -35099,9 +35138,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2536 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2539 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1543, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1549, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35115,9 +35154,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2537 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
+    // Pos:2540 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M"
     {
-        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1544, 
+        ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1550, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35131,9 +35170,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2538 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2541 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1545, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1551, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
         0,
@@ -35147,9 +35186,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2539 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
+    // Pos:2542 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M"
     {
-        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1546, 
+        ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1552, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
         0,
@@ -35163,9 +35202,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2540 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2543 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1547, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1553, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35179,9 +35218,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2541 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
+    // Pos:2544 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M"
     {
-        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1548, 
+        ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1554, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35195,9 +35234,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2542 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2545 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1549, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1555, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
         0,
@@ -35211,9 +35250,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2543 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
+    // Pos:2546 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M"
     {
-        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1550, 
+        ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1556, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 
         0,
@@ -35227,9 +35266,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2544 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2547 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1551, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1557, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35243,9 +35282,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2545 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
+    // Pos:2548 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M"
     {
-        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1552, 
+        ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1558, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35259,9 +35298,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2546 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2549 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1553, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1559, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
         0,
@@ -35275,9 +35314,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2547 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
+    // Pos:2550 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M"
     {
-        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1554, 
+        ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1560, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 
         0,
@@ -35291,9 +35330,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT|ND_OPF_R, 0, 0), 
     }, 
 
-    // Pos:2548 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
+    // Pos:2551 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/""
     {
-        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1555, 
+        ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1561, 
         ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 
         0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 
         0,
@@ -35306,9 +35345,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT|ND_OPF_W, 0, 0), 
     }, 
 
-    // Pos:2549 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
+    // Pos:2552 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/""
     {
-        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1556, 
+        ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1562, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -35317,9 +35356,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2550 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
+    // Pos:2553 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/""
     {
-        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1557, 
+        ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1563, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -35328,9 +35367,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2551 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
+    // Pos:2554 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/""
     {
-        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1558, 
+        ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1564, 
         ND_MOD_ANY, 
         ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 
         0,
@@ -35339,9 +35378,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2552 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
+    // Pos:2555 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/""
     {
-        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1559, 
+        ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1565, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 
         0,
@@ -35350,9 +35389,9 @@ const ND_INSTRUCTION gInstructions[2554] =
         0,
     }, 
 
-    // Pos:2553 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
+    // Pos:2556 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/""
     {
-        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1560, 
+        ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1566, 
         ND_MOD_ANY, 
         0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 
         0,
diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h
index b227082..b300927 100644
--- a/bddisasm/include/mnemonics.h
+++ b/bddisasm/include/mnemonics.h
@@ -1,7 +1,7 @@
 #ifndef _MNEMONICS_H_
 #define _MNEMONICS_H_
 
-const char *gMnemonics[1561] = 
+const char *gMnemonics[1567] = 
 {
     "AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", 
     "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDECLAST", 
@@ -40,109 +40,109 @@ const char *gMnemonics[1561] =
     "FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", "FSTP", "FSTPNCE", 
     "FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", "FTST", "FUCOM", 
     "FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", "FXCH", "FXRSTOR", 
-    "FXSAVE", "FXTRACT", "FYL2X", "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB", 
-    "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", "HADDPS", "HLT", "HSUBPD", 
-    "HSUBPS", "IDIV", "IMUL", "IN", "INC", "INCSSPD", "INCSSPQ", 
-    "INSB", "INSD", "INSERTPS", "INSERTQ", "INSW", "INT", "INT1", 
-    "INT3", "INTO", "INVD", "INVEPT", "INVLPG", "INVLPGA", "INVLPGB", 
-    "INVPCID", "INVVPID", "IRETD", "IRETQ", "IRETW", "JBE", "JC", 
-    "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", "JMPF", "JNBE", 
-    "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", "JO", "JP", 
-    "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", "KANDB", 
-    "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", "KANDW", 
-    "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", "KMOVW", 
-    "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", "KORQ", "KORTESTB", 
-    "KORTESTD", "KORTESTQ", "KORTESTW", "KORW", "KSHIFTLB", "KSHIFTLD", 
-    "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", 
-    "KTESTB", "KTESTD", "KTESTQ", "KTESTW", "KUNPCKBW", "KUNPCKDQ", 
-    "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", "KXNORW", "KXORB", 
-    "KXORD", "KXORQ", "KXORW", "LAHF", "LAR", "LDDQU", "LDMXCSR", 
-    "LDS", "LDTILECFG", "LEA", "LEAVE", "LES", "LFENCE", "LFS", "LGDT", 
-    "LGS", "LIDT", "LLDT", "LLWPCB", "LMSW", "LOADALL", "LOADALLD", 
+    "FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", "FYL2XP1", 
+    "GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", 
+    "HADDPS", "HLT", "HSUBPD", "HSUBPS", "IDIV", "IMUL", "IN", "INC", 
+    "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", "INSERTQ", 
+    "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", "INVLPG", 
+    "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", "IRETQ", 
+    "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", 
+    "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", 
+    "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", 
+    "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", 
+    "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", 
+    "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", 
+    "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", "KORW", 
+    "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", 
+    "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", "KTESTW", 
+    "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", 
+    "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", "LAR", 
+    "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", "LES", 
+    "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LLDT", "LLWPCB", "LMSW", 
     "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", "LOOPNZ", "LOOPZ", 
     "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", "MASKMOVDQU", 
     "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", "MCOMMIT", "MFENCE", 
     "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", "MONITORX", "MONTMUL", 
     "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B", 
-    "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHPD", "MOVHPS", 
-    "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", 
-    "MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", "MOVNTSD", 
-    "MOVNTSS", "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", 
-    "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", 
-    "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", "MULSS", 
-    "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", "ORPD", 
-    "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", "PABSW", 
-    "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", "PADDD", 
-    "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", "PALIGNR", 
-    "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", "PBLENDVB", 
-    "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW", 
-    "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW", 
-    "PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP", "PEXT", 
-    "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", "PFACC", 
-    "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", "PFMUL", 
-    "PFNACC", "PFPNACC", "PFRCPIT1", "PFRCPIT2", "PFRCPV", "PFRSQIT1", 
-    "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", "PHADDD", "PHADDSW", 
-    "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", "PHSUBW", "PI2FD", 
-    "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", "PMADDUBSW", 
-    "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", "PMAXUD", 
-    "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", "PMINUW", 
-    "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", "PMOVSXWD", 
-    "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", "PMOVZXWD", 
-    "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", "PMULHW", 
-    "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPCNT", "POPFD", 
-    "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", "PREFETCHM", 
-    "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", 
-    "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", 
-    "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", 
-    "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", 
-    "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", 
-    "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", 
-    "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", 
-    "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHFD", "PUSHFQ", 
-    "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", 
-    "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", "RDPMC", 
-    "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", 
-    "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR", 
-    "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT", 
-    "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL", 
-    "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD", 
-    "SCASQ", "SCASW", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", 
-    "SETNB", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", 
-    "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", 
-    "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", 
-    "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", 
-    "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", 
-    "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", 
-    "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", 
-    "STOSQ", "STOSW", "STR", "STTILECFG", "SUB", "SUBPD", "SUBPS", 
-    "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL", 
-    "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDPBF16PS", "TDPBSSD", 
-    "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TILELOADD", "TILELOADDT1", 
-    "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", 
-    "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", 
-    "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", 
-    "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", 
-    "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", 
-    "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", 
-    "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", 
-    "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", 
-    "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", 
-    "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", 
-    "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", 
-    "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", 
-    "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD", 
-    "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16", 
-    "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", 
-    "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ", 
-    "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI", 
-    "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD", 
-    "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", 
-    "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", 
-    "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD", 
-    "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS", 
-    "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS", 
-    "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD", 
-    "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", 
+    "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHLPS", "MOVHPD", 
+    "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", 
+    "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", 
+    "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", 
+    "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", 
+    "MOVUPS", "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", 
+    "MULSS", "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", 
+    "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", 
+    "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", 
+    "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", 
+    "PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", 
+    "PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", 
+    "PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", 
+    "PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP", 
+    "PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", 
+    "PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", 
+    "PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2", 
+    "PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", 
+    "PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", 
+    "PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", 
+    "PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", 
+    "PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", 
+    "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", 
+    "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", 
+    "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", 
+    "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD", 
+    "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", 
+    "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", 
+    "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", 
+    "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", 
+    "PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", 
+    "PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", 
+    "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", 
+    "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", 
+    "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", 
+    "PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", 
+    "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", 
+    "RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", 
+    "RDTSC", "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", 
+    "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", 
+    "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", 
+    "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", 
+    "SCASD", "SCASQ", "SCASW", "SERIALIZE", "SETBE", "SETC", "SETL", 
+    "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", 
+    "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", 
+    "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", 
+    "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", 
+    "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", 
+    "SLDT", "SLWPCB", "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", 
+    "SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", 
+    "STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "SUB", 
+    "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", 
+    "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", 
+    "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", 
+    "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", 
+    "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", 
+    "UD0", "UD1", "UD2", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", 
+    "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", 
+    "V4FNMADDSS", "VADDPD", "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", 
+    "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", 
+    "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", 
+    "VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", 
+    "VBLENDPS", "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", 
+    "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", 
+    "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", 
+    "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", 
+    "VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", 
+    "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", 
+    "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", 
+    "VCVTPD2UQQ", "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", 
+    "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", 
+    "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", 
+    "VCVTSS2SD", "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", 
+    "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", 
+    "VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", 
+    "VCVTUDQ2PD", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", 
+    "VCVTUSI2SS", "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", 
+    "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", 
+    "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8", 
     "VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4", 
     "VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS", 
     "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD", 
@@ -202,7 +202,7 @@ const char *gMnemonics[1561] =
     "VPCOMW", "VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS", 
     "VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", 
     "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q", 
-    "VPERMI2W", "VPERMILPD", "VPERMILPS", "VPERMILzz2PD", "VPERMILzz2PS", 
+    "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS", 
     "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD", 
     "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD", 
     "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW", 
@@ -232,15 +232,15 @@ const char *gMnemonics[1561] =
     "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD", 
     "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ", 
     "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW", 
-    "VPSHLB", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ", "VPSHLDVW", 
-    "VPSHLDW", "VPSHLQ", "VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ", 
-    "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB", "VPSHUFD", 
-    "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD", 
-    "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW", 
-    "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW", 
-    "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW", 
-    "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", 
-    "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", 
+    "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ", 
+    "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ", 
+    "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB", 
+    "VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW", 
+    "VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW", 
+    "VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW", 
+    "VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ", 
+    "VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", 
+    "VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", 
     "VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB", 
     "VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", 
     "VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", 
diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h
index 4f81d61..50007f6 100644
--- a/bddisasm/include/table_evex.h
+++ b/bddisasm/include/table_evex.h
@@ -4,7 +4,7 @@
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1327]
+    (const void *)&gInstructions[1329]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = 
@@ -39,13 +39,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1550]
+    (const void *)&gInstructions[1552]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1552]
+    (const void *)&gInstructions[1554]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = 
@@ -71,7 +71,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1328]
+    (const void *)&gInstructions[1330]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = 
@@ -95,13 +95,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1554]
+    (const void *)&gInstructions[1556]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1556]
+    (const void *)&gInstructions[1558]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = 
@@ -127,7 +127,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1329]
+    (const void *)&gInstructions[1331]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = 
@@ -162,13 +162,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1558]
+    (const void *)&gInstructions[1560]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1560]
+    (const void *)&gInstructions[1562]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = 
@@ -194,7 +194,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1330]
+    (const void *)&gInstructions[1332]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = 
@@ -218,13 +218,13 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1562]
+    (const void *)&gInstructions[1564]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1564]
+    (const void *)&gInstructions[1566]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = 
@@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1341]
+    (const void *)&gInstructions[1343]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = 
@@ -267,7 +267,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1343]
+    (const void *)&gInstructions[1345]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = 
@@ -284,7 +284,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1345]
+    (const void *)&gInstructions[1347]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = 
@@ -301,7 +301,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1347]
+    (const void *)&gInstructions[1349]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = 
@@ -318,13 +318,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1361]
+    (const void *)&gInstructions[1363]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1362]
+    (const void *)&gInstructions[1364]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = 
@@ -350,13 +350,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1368]
+    (const void *)&gInstructions[1370]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1379]
+    (const void *)&gInstructions[1381]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = 
@@ -382,13 +382,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1369]
+    (const void *)&gInstructions[1371]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1371]
+    (const void *)&gInstructions[1373]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = 
@@ -423,13 +423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1370]
+    (const void *)&gInstructions[1372]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1372]
+    (const void *)&gInstructions[1374]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = 
@@ -475,13 +475,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1374]
+    (const void *)&gInstructions[1376]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1932]
+    (const void *)&gInstructions[1935]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = 
@@ -507,13 +507,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1375]
+    (const void *)&gInstructions[1377]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1377]
+    (const void *)&gInstructions[1379]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = 
@@ -548,13 +548,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1376]
+    (const void *)&gInstructions[1378]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1378]
+    (const void *)&gInstructions[1380]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = 
@@ -600,7 +600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1381]
+    (const void *)&gInstructions[1383]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = 
@@ -626,13 +626,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1395]
+    (const void *)&gInstructions[1397]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1396]
+    (const void *)&gInstructions[1398]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = 
@@ -658,7 +658,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1402]
+    (const void *)&gInstructions[1404]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = 
@@ -673,7 +673,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1403]
+    (const void *)&gInstructions[1405]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = 
@@ -688,7 +688,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2280]
+    (const void *)&gInstructions[2283]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = 
@@ -714,7 +714,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1412]
+    (const void *)&gInstructions[1414]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = 
@@ -729,7 +729,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2178]
+    (const void *)&gInstructions[2181]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = 
@@ -755,7 +755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1475]
+    (const void *)&gInstructions[1477]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = 
@@ -770,7 +770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1872]
+    (const void *)&gInstructions[1875]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = 
@@ -805,7 +805,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1986]
+    (const void *)&gInstructions[1989]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = 
@@ -831,13 +831,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1480]
+    (const void *)&gInstructions[1482]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1481]
+    (const void *)&gInstructions[1483]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = 
@@ -874,13 +874,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1482]
+    (const void *)&gInstructions[1484]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1483]
+    (const void *)&gInstructions[1485]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = 
@@ -906,13 +906,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1502]
+    (const void *)&gInstructions[1504]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1504]
+    (const void *)&gInstructions[1506]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = 
@@ -938,13 +938,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1506]
+    (const void *)&gInstructions[1508]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1508]
+    (const void *)&gInstructions[1510]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = 
@@ -970,13 +970,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1510]
+    (const void *)&gInstructions[1512]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1512]
+    (const void *)&gInstructions[1514]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = 
@@ -1002,13 +1002,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1514]
+    (const void *)&gInstructions[1516]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1516]
+    (const void *)&gInstructions[1518]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = 
@@ -1034,13 +1034,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1518]
+    (const void *)&gInstructions[1520]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1520]
+    (const void *)&gInstructions[1522]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = 
@@ -1066,13 +1066,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1522]
+    (const void *)&gInstructions[1524]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1524]
+    (const void *)&gInstructions[1526]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = 
@@ -1098,13 +1098,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1534]
+    (const void *)&gInstructions[1536]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1536]
+    (const void *)&gInstructions[1538]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = 
@@ -1130,13 +1130,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1538]
+    (const void *)&gInstructions[1540]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1540]
+    (const void *)&gInstructions[1542]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = 
@@ -1162,13 +1162,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1542]
+    (const void *)&gInstructions[1544]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1544]
+    (const void *)&gInstructions[1546]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = 
@@ -1194,13 +1194,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1566]
+    (const void *)&gInstructions[1568]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1568]
+    (const void *)&gInstructions[1570]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = 
@@ -1226,13 +1226,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1570]
+    (const void *)&gInstructions[1572]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1572]
+    (const void *)&gInstructions[1574]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = 
@@ -1258,13 +1258,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1574]
+    (const void *)&gInstructions[1576]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1576]
+    (const void *)&gInstructions[1578]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = 
@@ -1290,13 +1290,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1578]
+    (const void *)&gInstructions[1580]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1580]
+    (const void *)&gInstructions[1582]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = 
@@ -1322,13 +1322,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1582]
+    (const void *)&gInstructions[1584]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1584]
+    (const void *)&gInstructions[1586]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = 
@@ -1354,13 +1354,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1598]
+    (const void *)&gInstructions[1600]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1600]
+    (const void *)&gInstructions[1602]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = 
@@ -1386,13 +1386,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1602]
+    (const void *)&gInstructions[1604]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1604]
+    (const void *)&gInstructions[1606]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = 
@@ -1418,13 +1418,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1606]
+    (const void *)&gInstructions[1608]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1608]
+    (const void *)&gInstructions[1610]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = 
@@ -1450,13 +1450,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1610]
+    (const void *)&gInstructions[1612]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1612]
+    (const void *)&gInstructions[1614]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = 
@@ -1482,13 +1482,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1614]
+    (const void *)&gInstructions[1616]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1616]
+    (const void *)&gInstructions[1618]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = 
@@ -1514,13 +1514,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1618]
+    (const void *)&gInstructions[1620]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1620]
+    (const void *)&gInstructions[1622]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = 
@@ -1546,13 +1546,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1630]
+    (const void *)&gInstructions[1632]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1632]
+    (const void *)&gInstructions[1634]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = 
@@ -1578,13 +1578,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1634]
+    (const void *)&gInstructions[1636]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1636]
+    (const void *)&gInstructions[1638]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = 
@@ -1610,13 +1610,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1638]
+    (const void *)&gInstructions[1640]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1640]
+    (const void *)&gInstructions[1642]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = 
@@ -1642,13 +1642,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1642]
+    (const void *)&gInstructions[1644]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1644]
+    (const void *)&gInstructions[1646]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = 
@@ -1674,13 +1674,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1646]
+    (const void *)&gInstructions[1648]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1648]
+    (const void *)&gInstructions[1650]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = 
@@ -1706,13 +1706,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1650]
+    (const void *)&gInstructions[1652]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1652]
+    (const void *)&gInstructions[1654]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = 
@@ -1738,13 +1738,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1670]
+    (const void *)&gInstructions[1672]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1672]
+    (const void *)&gInstructions[1674]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = 
@@ -1779,13 +1779,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1674]
+    (const void *)&gInstructions[1676]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1675]
+    (const void *)&gInstructions[1677]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = 
@@ -1811,13 +1811,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1678]
+    (const void *)&gInstructions[1680]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1679]
+    (const void *)&gInstructions[1681]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = 
@@ -1843,13 +1843,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2434]
+    (const void *)&gInstructions[2437]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2435]
+    (const void *)&gInstructions[2438]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = 
@@ -1875,13 +1875,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2438]
+    (const void *)&gInstructions[2441]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2439]
+    (const void *)&gInstructions[2442]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = 
@@ -1942,13 +1942,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1676]
+    (const void *)&gInstructions[1678]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1677]
+    (const void *)&gInstructions[1679]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = 
@@ -1974,13 +1974,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1680]
+    (const void *)&gInstructions[1682]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1681]
+    (const void *)&gInstructions[1683]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = 
@@ -2006,13 +2006,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2436]
+    (const void *)&gInstructions[2439]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2437]
+    (const void *)&gInstructions[2440]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = 
@@ -2038,13 +2038,13 @@ const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2440]
+    (const void *)&gInstructions[2443]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2441]
+    (const void *)&gInstructions[2444]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = 
@@ -2105,13 +2105,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1682]
+    (const void *)&gInstructions[1684]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1684]
+    (const void *)&gInstructions[1686]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = 
@@ -2146,13 +2146,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1686]
+    (const void *)&gInstructions[1688]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1687]
+    (const void *)&gInstructions[1689]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = 
@@ -2178,13 +2178,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1688]
+    (const void *)&gInstructions[1690]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1689]
+    (const void *)&gInstructions[1691]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = 
@@ -2210,7 +2210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1698]
+    (const void *)&gInstructions[1700]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = 
@@ -2236,7 +2236,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1806]
+    (const void *)&gInstructions[1809]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = 
@@ -2260,7 +2260,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1930]
+    (const void *)&gInstructions[1933]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = 
@@ -2295,13 +2295,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1870]
+    (const void *)&gInstructions[1873]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1871]
+    (const void *)&gInstructions[1874]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = 
@@ -2327,7 +2327,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1873]
+    (const void *)&gInstructions[1876]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = 
@@ -2362,7 +2362,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1987]
+    (const void *)&gInstructions[1990]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = 
@@ -2388,7 +2388,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1874]
+    (const void *)&gInstructions[1877]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = 
@@ -2405,7 +2405,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1876]
+    (const void *)&gInstructions[1879]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = 
@@ -2431,7 +2431,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1878]
+    (const void *)&gInstructions[1881]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = 
@@ -2457,7 +2457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1879]
+    (const void *)&gInstructions[1882]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = 
@@ -2474,7 +2474,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1885]
+    (const void *)&gInstructions[1888]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = 
@@ -2500,13 +2500,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1918]
+    (const void *)&gInstructions[1921]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1921]
+    (const void *)&gInstructions[1924]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = 
@@ -2532,13 +2532,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1919]
+    (const void *)&gInstructions[1922]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1920]
+    (const void *)&gInstructions[1923]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = 
@@ -2564,7 +2564,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1924]
+    (const void *)&gInstructions[1927]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = 
@@ -2590,7 +2590,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1925]
+    (const void *)&gInstructions[1928]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = 
@@ -2625,7 +2625,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1927]
+    (const void *)&gInstructions[1930]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = 
@@ -2651,13 +2651,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1928]
+    (const void *)&gInstructions[1931]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1933]
+    (const void *)&gInstructions[1936]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_w = 
@@ -2692,7 +2692,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1931]
+    (const void *)&gInstructions[1934]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = 
@@ -2716,7 +2716,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2138]
+    (const void *)&gInstructions[2141]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = 
@@ -2733,7 +2733,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1935]
+    (const void *)&gInstructions[1938]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = 
@@ -2759,7 +2759,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1936]
+    (const void *)&gInstructions[1939]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = 
@@ -2794,7 +2794,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1948]
+    (const void *)&gInstructions[1951]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = 
@@ -2809,13 +2809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2140]
+    (const void *)&gInstructions[2143]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2183]
+    (const void *)&gInstructions[2186]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = 
@@ -2850,7 +2850,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1958]
+    (const void *)&gInstructions[1961]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = 
@@ -2876,13 +2876,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1972]
+    (const void *)&gInstructions[1975]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1975]
+    (const void *)&gInstructions[1978]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = 
@@ -2908,13 +2908,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1973]
+    (const void *)&gInstructions[1976]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1974]
+    (const void *)&gInstructions[1977]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = 
@@ -2940,13 +2940,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1982]
+    (const void *)&gInstructions[1985]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1983]
+    (const void *)&gInstructions[1986]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = 
@@ -2972,7 +2972,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1984]
+    (const void *)&gInstructions[1987]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = 
@@ -2998,7 +2998,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1985]
+    (const void *)&gInstructions[1988]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = 
@@ -3024,13 +3024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1990]
+    (const void *)&gInstructions[1993]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2027]
+    (const void *)&gInstructions[2030]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = 
@@ -3056,13 +3056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1991]
+    (const void *)&gInstructions[1994]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2018]
+    (const void *)&gInstructions[2021]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = 
@@ -3088,13 +3088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1993]
+    (const void *)&gInstructions[1996]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1998]
+    (const void *)&gInstructions[2001]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = 
@@ -3120,13 +3120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1994]
+    (const void *)&gInstructions[1997]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1997]
+    (const void *)&gInstructions[2000]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = 
@@ -3152,13 +3152,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1995]
+    (const void *)&gInstructions[1998]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1996]
+    (const void *)&gInstructions[1999]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = 
@@ -3184,7 +3184,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1999]
+    (const void *)&gInstructions[2006]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = 
@@ -3210,7 +3210,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2003]
+    (const void *)&gInstructions[2010]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = 
@@ -3236,13 +3236,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2011]
+    (const void *)&gInstructions[2014]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2015]
+    (const void *)&gInstructions[2018]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = 
@@ -3257,13 +3257,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2012]
+    (const void *)&gInstructions[2015]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2016]
+    (const void *)&gInstructions[2019]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = 
@@ -3300,13 +3300,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2021]
+    (const void *)&gInstructions[2024]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2026]
+    (const void *)&gInstructions[2029]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = 
@@ -3332,13 +3332,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2022]
+    (const void *)&gInstructions[2025]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2025]
+    (const void *)&gInstructions[2028]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = 
@@ -3364,13 +3364,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2023]
+    (const void *)&gInstructions[2026]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2024]
+    (const void *)&gInstructions[2027]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = 
@@ -3396,13 +3396,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2028]
+    (const void *)&gInstructions[2031]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2031]
+    (const void *)&gInstructions[2034]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = 
@@ -3428,13 +3428,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2029]
+    (const void *)&gInstructions[2032]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2030]
+    (const void *)&gInstructions[2033]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = 
@@ -3460,13 +3460,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2046]
+    (const void *)&gInstructions[2049]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2048]
+    (const void *)&gInstructions[2051]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = 
@@ -3501,13 +3501,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2050]
+    (const void *)&gInstructions[2053]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2052]
+    (const void *)&gInstructions[2055]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = 
@@ -3542,13 +3542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2088]
+    (const void *)&gInstructions[2091]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2089]
+    (const void *)&gInstructions[2092]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = 
@@ -3574,7 +3574,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2102]
+    (const void *)&gInstructions[2105]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = 
@@ -3600,7 +3600,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2103]
+    (const void *)&gInstructions[2106]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = 
@@ -3626,7 +3626,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2104]
+    (const void *)&gInstructions[2107]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = 
@@ -3643,7 +3643,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2112]
+    (const void *)&gInstructions[2115]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = 
@@ -3660,13 +3660,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2114]
+    (const void *)&gInstructions[2117]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2116]
+    (const void *)&gInstructions[2119]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = 
@@ -3692,13 +3692,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2121]
+    (const void *)&gInstructions[2124]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2123]
+    (const void *)&gInstructions[2126]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = 
@@ -3724,7 +3724,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2124]
+    (const void *)&gInstructions[2127]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = 
@@ -3741,19 +3741,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2126]
+    (const void *)&gInstructions[2129]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2145]
+    (const void *)&gInstructions[2148]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2146]
+    (const void *)&gInstructions[2149]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = 
@@ -3788,13 +3788,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2128]
+    (const void *)&gInstructions[2131]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2130]
+    (const void *)&gInstructions[2133]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = 
@@ -3809,13 +3809,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2141]
+    (const void *)&gInstructions[2144]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2149]
+    (const void *)&gInstructions[2152]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = 
@@ -3850,13 +3850,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2135]
+    (const void *)&gInstructions[2138]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2137]
+    (const void *)&gInstructions[2140]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = 
@@ -3882,7 +3882,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2142]
+    (const void *)&gInstructions[2145]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = 
@@ -3897,7 +3897,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2185]
+    (const void *)&gInstructions[2188]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = 
@@ -3914,7 +3914,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2143]
+    (const void *)&gInstructions[2146]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = 
@@ -3929,7 +3929,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2197]
+    (const void *)&gInstructions[2200]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = 
@@ -3946,13 +3946,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2144]
+    (const void *)&gInstructions[2147]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2147]
+    (const void *)&gInstructions[2150]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = 
@@ -3976,7 +3976,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2203]
+    (const void *)&gInstructions[2206]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = 
@@ -4002,7 +4002,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2150]
+    (const void *)&gInstructions[2153]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = 
@@ -4017,7 +4017,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2188]
+    (const void *)&gInstructions[2191]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = 
@@ -4034,7 +4034,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2151]
+    (const void *)&gInstructions[2154]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = 
@@ -4049,7 +4049,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2194]
+    (const void *)&gInstructions[2197]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = 
@@ -4075,7 +4075,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2152]
+    (const void *)&gInstructions[2155]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = 
@@ -4090,7 +4090,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2200]
+    (const void *)&gInstructions[2203]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = 
@@ -4107,7 +4107,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2153]
+    (const void *)&gInstructions[2156]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = 
@@ -4122,7 +4122,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2159]
+    (const void *)&gInstructions[2162]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = 
@@ -4139,7 +4139,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2154]
+    (const void *)&gInstructions[2157]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = 
@@ -4154,7 +4154,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2171]
+    (const void *)&gInstructions[2174]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = 
@@ -4171,7 +4171,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2155]
+    (const void *)&gInstructions[2158]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = 
@@ -4186,7 +4186,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2162]
+    (const void *)&gInstructions[2165]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = 
@@ -4203,7 +4203,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2156]
+    (const void *)&gInstructions[2159]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = 
@@ -4218,7 +4218,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2168]
+    (const void *)&gInstructions[2171]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = 
@@ -4244,7 +4244,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2157]
+    (const void *)&gInstructions[2160]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = 
@@ -4259,7 +4259,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2174]
+    (const void *)&gInstructions[2177]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = 
@@ -4276,7 +4276,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2158]
+    (const void *)&gInstructions[2161]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = 
@@ -4291,7 +4291,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2165]
+    (const void *)&gInstructions[2168]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = 
@@ -4308,7 +4308,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2177]
+    (const void *)&gInstructions[2180]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = 
@@ -4323,7 +4323,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2322]
+    (const void *)&gInstructions[2325]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = 
@@ -4349,7 +4349,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2179]
+    (const void *)&gInstructions[2182]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = 
@@ -4364,7 +4364,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2308]
+    (const void *)&gInstructions[2311]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = 
@@ -4390,7 +4390,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2180]
+    (const void *)&gInstructions[2183]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = 
@@ -4405,13 +4405,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2230]
+    (const void *)&gInstructions[2233]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2231]
+    (const void *)&gInstructions[2234]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = 
@@ -4437,7 +4437,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2181]
+    (const void *)&gInstructions[2184]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = 
@@ -4452,13 +4452,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2234]
+    (const void *)&gInstructions[2237]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2235]
+    (const void *)&gInstructions[2238]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = 
@@ -4484,7 +4484,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2182]
+    (const void *)&gInstructions[2185]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = 
@@ -4499,7 +4499,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2341]
+    (const void *)&gInstructions[2344]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = 
@@ -4525,7 +4525,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2184]
+    (const void *)&gInstructions[2187]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = 
@@ -4540,7 +4540,7 @@ const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2191]
+    (const void *)&gInstructions[2194]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = 
@@ -4557,7 +4557,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2205]
+    (const void *)&gInstructions[2208]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = 
@@ -4574,13 +4574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2211]
+    (const void *)&gInstructions[2214]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2213]
+    (const void *)&gInstructions[2216]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = 
@@ -4606,7 +4606,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2216]
+    (const void *)&gInstructions[2219]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = 
@@ -4632,13 +4632,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2219]
+    (const void *)&gInstructions[2222]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2222]
+    (const void *)&gInstructions[2225]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = 
@@ -4664,13 +4664,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2220]
+    (const void *)&gInstructions[2223]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2221]
+    (const void *)&gInstructions[2224]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = 
@@ -4696,13 +4696,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2250]
+    (const void *)&gInstructions[2253]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2251]
+    (const void *)&gInstructions[2254]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = 
@@ -4737,13 +4737,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2252]
+    (const void *)&gInstructions[2255]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2253]
+    (const void *)&gInstructions[2256]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = 
@@ -4778,13 +4778,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2270]
+    (const void *)&gInstructions[2272]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2271]
+    (const void *)&gInstructions[2273]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = 
@@ -4810,7 +4810,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2272]
+    (const void *)&gInstructions[2274]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = 
@@ -4836,13 +4836,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2278]
+    (const void *)&gInstructions[2281]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2279]
+    (const void *)&gInstructions[2282]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = 
@@ -4868,7 +4868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2282]
+    (const void *)&gInstructions[2285]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = 
@@ -4885,7 +4885,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2284]
+    (const void *)&gInstructions[2287]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = 
@@ -4911,13 +4911,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2304]
+    (const void *)&gInstructions[2307]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2306]
+    (const void *)&gInstructions[2309]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = 
@@ -4943,13 +4943,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2319]
+    (const void *)&gInstructions[2322]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2321]
+    (const void *)&gInstructions[2324]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = 
@@ -4975,13 +4975,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2337]
+    (const void *)&gInstructions[2340]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2339]
+    (const void *)&gInstructions[2342]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = 
@@ -5007,13 +5007,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2365]
+    (const void *)&gInstructions[2368]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2368]
+    (const void *)&gInstructions[2371]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = 
@@ -5028,13 +5028,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2369]
+    (const void *)&gInstructions[2372]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2372]
+    (const void *)&gInstructions[2375]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = 
@@ -5060,13 +5060,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2366]
+    (const void *)&gInstructions[2369]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2367]
+    (const void *)&gInstructions[2370]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = 
@@ -5081,13 +5081,13 @@ const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2370]
+    (const void *)&gInstructions[2373]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2371]
+    (const void *)&gInstructions[2374]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = 
@@ -5113,13 +5113,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2396]
+    (const void *)&gInstructions[2399]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2397]
+    (const void *)&gInstructions[2400]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = 
@@ -5145,13 +5145,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2398]
+    (const void *)&gInstructions[2401]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2399]
+    (const void *)&gInstructions[2402]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = 
@@ -5177,13 +5177,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2400]
+    (const void *)&gInstructions[2403]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2401]
+    (const void *)&gInstructions[2404]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = 
@@ -5220,13 +5220,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2402]
+    (const void *)&gInstructions[2405]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2403]
+    (const void *)&gInstructions[2406]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = 
@@ -5252,13 +5252,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2418]
+    (const void *)&gInstructions[2421]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2419]
+    (const void *)&gInstructions[2422]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = 
@@ -5284,13 +5284,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2420]
+    (const void *)&gInstructions[2423]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2421]
+    (const void *)&gInstructions[2424]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = 
@@ -5316,13 +5316,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2422]
+    (const void *)&gInstructions[2425]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2423]
+    (const void *)&gInstructions[2426]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = 
@@ -5359,13 +5359,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2424]
+    (const void *)&gInstructions[2427]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2425]
+    (const void *)&gInstructions[2428]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = 
@@ -5391,13 +5391,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2428]
+    (const void *)&gInstructions[2431]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2429]
+    (const void *)&gInstructions[2432]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = 
@@ -5423,13 +5423,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2430]
+    (const void *)&gInstructions[2433]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2431]
+    (const void *)&gInstructions[2434]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = 
@@ -5455,13 +5455,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2432]
+    (const void *)&gInstructions[2435]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2433]
+    (const void *)&gInstructions[2436]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = 
@@ -5496,13 +5496,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2442]
+    (const void *)&gInstructions[2445]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2443]
+    (const void *)&gInstructions[2446]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = 
@@ -5800,7 +5800,7 @@ const ND_TABLE_OPCODE gEvexTable_root_02_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1331]
+    (const void *)&gInstructions[1333]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = 
@@ -5815,7 +5815,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1333]
+    (const void *)&gInstructions[1335]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = 
@@ -5830,7 +5830,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1335]
+    (const void *)&gInstructions[1337]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = 
@@ -5845,7 +5845,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1337]
+    (const void *)&gInstructions[1339]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = 
@@ -5871,7 +5871,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1353]
+    (const void *)&gInstructions[1355]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = 
@@ -5886,7 +5886,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1355]
+    (const void *)&gInstructions[1357]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = 
@@ -5912,7 +5912,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1357]
+    (const void *)&gInstructions[1359]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = 
@@ -5927,7 +5927,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1359]
+    (const void *)&gInstructions[1361]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = 
@@ -5953,7 +5953,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1383]
+    (const void *)&gInstructions[1385]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = 
@@ -5968,7 +5968,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1385]
+    (const void *)&gInstructions[1387]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = 
@@ -5983,7 +5983,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1386]
+    (const void *)&gInstructions[1389]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = 
@@ -5998,7 +5998,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1388]
+    (const void *)&gInstructions[1391]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = 
@@ -6024,7 +6024,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1391]
+    (const void *)&gInstructions[1393]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = 
@@ -6039,7 +6039,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1393]
+    (const void *)&gInstructions[1395]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = 
@@ -6065,13 +6065,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1397]
+    (const void *)&gInstructions[1399]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1426]
+    (const void *)&gInstructions[1428]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = 
@@ -6086,7 +6086,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1404]
+    (const void *)&gInstructions[1406]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = 
@@ -6101,7 +6101,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1443]
+    (const void *)&gInstructions[1445]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = 
@@ -6127,13 +6127,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1400]
+    (const void *)&gInstructions[1402]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1427]
+    (const void *)&gInstructions[1429]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = 
@@ -6148,7 +6148,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1415]
+    (const void *)&gInstructions[1417]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = 
@@ -6163,7 +6163,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1448]
+    (const void *)&gInstructions[1450]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = 
@@ -6189,7 +6189,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1406]
+    (const void *)&gInstructions[1408]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = 
@@ -6204,7 +6204,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1417]
+    (const void *)&gInstructions[1419]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = 
@@ -6219,7 +6219,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1430]
+    (const void *)&gInstructions[1432]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = 
@@ -6234,7 +6234,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1438]
+    (const void *)&gInstructions[1440]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = 
@@ -6260,13 +6260,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1409]
+    (const void *)&gInstructions[1411]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1423]
+    (const void *)&gInstructions[1425]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = 
@@ -6281,13 +6281,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1463]
+    (const void *)&gInstructions[1465]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1464]
+    (const void *)&gInstructions[1466]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w = 
@@ -6302,7 +6302,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1465]
+    (const void *)&gInstructions[1467]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = 
@@ -6319,13 +6319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1410]
+    (const void *)&gInstructions[1412]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1424]
+    (const void *)&gInstructions[1426]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = 
@@ -6340,13 +6340,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1411]
+    (const void *)&gInstructions[1413]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1425]
+    (const void *)&gInstructions[1427]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = 
@@ -6361,13 +6361,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1432]
+    (const void *)&gInstructions[1434]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1442]
+    (const void *)&gInstructions[1444]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = 
@@ -6384,13 +6384,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1428]
+    (const void *)&gInstructions[1430]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1440]
+    (const void *)&gInstructions[1442]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = 
@@ -6407,13 +6407,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1433]
+    (const void *)&gInstructions[1435]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1434]
+    (const void *)&gInstructions[1436]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w = 
@@ -6428,7 +6428,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1436]
+    (const void *)&gInstructions[1438]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = 
@@ -6445,13 +6445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1445]
+    (const void *)&gInstructions[1447]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1450]
+    (const void *)&gInstructions[1452]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = 
@@ -6466,13 +6466,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1459]
+    (const void *)&gInstructions[1461]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1461]
+    (const void *)&gInstructions[1463]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = 
@@ -6487,13 +6487,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1460]
+    (const void *)&gInstructions[1462]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1462]
+    (const void *)&gInstructions[1464]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = 
@@ -6519,13 +6519,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1446]
+    (const void *)&gInstructions[1448]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1451]
+    (const void *)&gInstructions[1453]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = 
@@ -6540,13 +6540,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1447]
+    (const void *)&gInstructions[1449]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1452]
+    (const void *)&gInstructions[1454]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = 
@@ -6561,13 +6561,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1455]
+    (const void *)&gInstructions[1457]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1458]
+    (const void *)&gInstructions[1460]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = 
@@ -6584,13 +6584,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1453]
+    (const void *)&gInstructions[1455]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1456]
+    (const void *)&gInstructions[1458]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = 
@@ -6607,7 +6607,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1467]
+    (const void *)&gInstructions[1469]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = 
@@ -6622,7 +6622,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1469]
+    (const void *)&gInstructions[1471]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = 
@@ -6637,7 +6637,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1471]
+    (const void *)&gInstructions[1473]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = 
@@ -6652,7 +6652,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1473]
+    (const void *)&gInstructions[1475]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = 
@@ -6678,7 +6678,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1725]
+    (const void *)&gInstructions[1727]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = 
@@ -6693,7 +6693,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1727]
+    (const void *)&gInstructions[1729]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = 
@@ -6708,7 +6708,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1729]
+    (const void *)&gInstructions[1731]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = 
@@ -6723,7 +6723,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1731]
+    (const void *)&gInstructions[1733]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = 
@@ -6749,7 +6749,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1738]
+    (const void *)&gInstructions[1740]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = 
@@ -6764,7 +6764,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1740]
+    (const void *)&gInstructions[1742]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = 
@@ -6779,7 +6779,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1742]
+    (const void *)&gInstructions[1744]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = 
@@ -6794,7 +6794,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1744]
+    (const void *)&gInstructions[1746]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = 
@@ -6820,7 +6820,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1749]
+    (const void *)&gInstructions[1752]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = 
@@ -6835,7 +6835,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1753]
+    (const void *)&gInstructions[1756]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = 
@@ -6861,7 +6861,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1750]
+    (const void *)&gInstructions[1753]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = 
@@ -6876,7 +6876,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1754]
+    (const void *)&gInstructions[1757]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = 
@@ -6902,13 +6902,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1757]
+    (const void *)&gInstructions[1760]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1812]
+    (const void *)&gInstructions[1815]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_w = 
@@ -6945,13 +6945,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1758]
+    (const void *)&gInstructions[1761]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1813]
+    (const void *)&gInstructions[1816]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_w = 
@@ -6977,7 +6977,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1814]
+    (const void *)&gInstructions[1817]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = 
@@ -7014,7 +7014,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1761]
+    (const void *)&gInstructions[1764]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = 
@@ -7029,7 +7029,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1762]
+    (const void *)&gInstructions[1765]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = 
@@ -7044,7 +7044,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1763]
+    (const void *)&gInstructions[1766]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = 
@@ -7070,7 +7070,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1782]
+    (const void *)&gInstructions[1785]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = 
@@ -7096,7 +7096,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1798]
+    (const void *)&gInstructions[1801]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = 
@@ -7131,7 +7131,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1794]
+    (const void *)&gInstructions[1797]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = 
@@ -7166,7 +7166,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1830]
+    (const void *)&gInstructions[1833]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = 
@@ -7192,13 +7192,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1768]
+    (const void *)&gInstructions[1771]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1770]
+    (const void *)&gInstructions[1773]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = 
@@ -7213,13 +7213,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1774]
+    (const void *)&gInstructions[1777]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1780]
+    (const void *)&gInstructions[1783]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = 
@@ -7234,13 +7234,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1776]
+    (const void *)&gInstructions[1779]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1778]
+    (const void *)&gInstructions[1781]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = 
@@ -7266,13 +7266,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1769]
+    (const void *)&gInstructions[1772]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1771]
+    (const void *)&gInstructions[1774]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = 
@@ -7287,13 +7287,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1775]
+    (const void *)&gInstructions[1778]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1781]
+    (const void *)&gInstructions[1784]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = 
@@ -7308,13 +7308,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1777]
+    (const void *)&gInstructions[1780]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1779]
+    (const void *)&gInstructions[1782]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = 
@@ -7340,7 +7340,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1784]
+    (const void *)&gInstructions[1787]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = 
@@ -7375,7 +7375,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1788]
+    (const void *)&gInstructions[1791]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = 
@@ -7401,7 +7401,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1792]
+    (const void *)&gInstructions[1795]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = 
@@ -7436,7 +7436,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1828]
+    (const void *)&gInstructions[1831]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = 
@@ -7462,7 +7462,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1785]
+    (const void *)&gInstructions[1788]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = 
@@ -7497,7 +7497,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1789]
+    (const void *)&gInstructions[1792]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = 
@@ -7543,7 +7543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1795]
+    (const void *)&gInstructions[1798]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = 
@@ -7578,7 +7578,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1799]
+    (const void *)&gInstructions[1802]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = 
@@ -7624,7 +7624,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1804]
+    (const void *)&gInstructions[1807]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = 
@@ -7659,7 +7659,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1808]
+    (const void *)&gInstructions[1811]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = 
@@ -7683,7 +7683,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1810]
+    (const void *)&gInstructions[1813]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = 
@@ -7718,7 +7718,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1815]
+    (const void *)&gInstructions[1818]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = 
@@ -7755,7 +7755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1820]
+    (const void *)&gInstructions[1823]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = 
@@ -7770,7 +7770,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1821]
+    (const void *)&gInstructions[1824]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = 
@@ -7794,7 +7794,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1832]
+    (const void *)&gInstructions[1835]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = 
@@ -7809,7 +7809,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1833]
+    (const void *)&gInstructions[1836]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = 
@@ -7833,7 +7833,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1840]
+    (const void *)&gInstructions[1843]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = 
@@ -7848,7 +7848,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1844]
+    (const void *)&gInstructions[1847]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = 
@@ -7874,7 +7874,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1822]
+    (const void *)&gInstructions[1825]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = 
@@ -7889,7 +7889,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1823]
+    (const void *)&gInstructions[1826]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = 
@@ -7913,7 +7913,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1834]
+    (const void *)&gInstructions[1837]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = 
@@ -7928,7 +7928,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1835]
+    (const void *)&gInstructions[1838]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = 
@@ -7952,7 +7952,7 @@ const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1841]
+    (const void *)&gInstructions[1844]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = 
@@ -7967,7 +7967,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1845]
+    (const void *)&gInstructions[1848]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = 
@@ -7993,7 +7993,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1855]
+    (const void *)&gInstructions[1858]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = 
@@ -8008,7 +8008,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1857]
+    (const void *)&gInstructions[1860]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = 
@@ -8023,7 +8023,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1859]
+    (const void *)&gInstructions[1862]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = 
@@ -8038,7 +8038,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1861]
+    (const void *)&gInstructions[1864]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = 
@@ -8064,7 +8064,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1866]
+    (const void *)&gInstructions[1869]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = 
@@ -8079,7 +8079,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1868]
+    (const void *)&gInstructions[1871]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = 
@@ -8105,7 +8105,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1881]
+    (const void *)&gInstructions[1884]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = 
@@ -8131,7 +8131,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1883]
+    (const void *)&gInstructions[1886]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = 
@@ -8148,7 +8148,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1887]
+    (const void *)&gInstructions[1890]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = 
@@ -8165,7 +8165,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1889]
+    (const void *)&gInstructions[1892]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = 
@@ -8182,7 +8182,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1891]
+    (const void *)&gInstructions[1894]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = 
@@ -8208,7 +8208,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1893]
+    (const void *)&gInstructions[1896]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = 
@@ -8234,7 +8234,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1895]
+    (const void *)&gInstructions[1898]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = 
@@ -8251,7 +8251,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1897]
+    (const void *)&gInstructions[1900]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = 
@@ -8268,7 +8268,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1899]
+    (const void *)&gInstructions[1902]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = 
@@ -8285,7 +8285,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1901]
+    (const void *)&gInstructions[1904]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = 
@@ -8302,7 +8302,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1903]
+    (const void *)&gInstructions[1906]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = 
@@ -8319,13 +8319,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1908]
+    (const void *)&gInstructions[1911]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1912]
+    (const void *)&gInstructions[1915]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = 
@@ -8351,13 +8351,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1910]
+    (const void *)&gInstructions[1913]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1911]
+    (const void *)&gInstructions[1914]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = 
@@ -8383,7 +8383,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1913]
+    (const void *)&gInstructions[1916]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = 
@@ -8400,7 +8400,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1915]
+    (const void *)&gInstructions[1918]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = 
@@ -8417,7 +8417,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1944]
+    (const void *)&gInstructions[1947]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = 
@@ -8434,7 +8434,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1946]
+    (const void *)&gInstructions[1949]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = 
@@ -8451,7 +8451,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1950]
+    (const void *)&gInstructions[1953]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = 
@@ -8468,7 +8468,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1954]
+    (const void *)&gInstructions[1957]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = 
@@ -8485,7 +8485,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1956]
+    (const void *)&gInstructions[1959]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = 
@@ -8511,7 +8511,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1960]
+    (const void *)&gInstructions[1963]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = 
@@ -8528,7 +8528,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2040]
+    (const void *)&gInstructions[2043]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = 
@@ -8565,7 +8565,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2084]
+    (const void *)&gInstructions[2087]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = 
@@ -8582,7 +8582,7 @@ const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2085]
+    (const void *)&gInstructions[2088]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = 
@@ -8619,7 +8619,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2106]
+    (const void *)&gInstructions[2109]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = 
@@ -8636,7 +8636,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2117]
+    (const void *)&gInstructions[2120]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = 
@@ -8653,7 +8653,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2119]
+    (const void *)&gInstructions[2122]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = 
@@ -8670,7 +8670,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2131]
+    (const void *)&gInstructions[2134]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = 
@@ -8687,7 +8687,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2133]
+    (const void *)&gInstructions[2136]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = 
@@ -8704,7 +8704,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2207]
+    (const void *)&gInstructions[2210]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = 
@@ -8721,7 +8721,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2209]
+    (const void *)&gInstructions[2212]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = 
@@ -8738,7 +8738,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2214]
+    (const void *)&gInstructions[2217]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = 
@@ -8755,7 +8755,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2217]
+    (const void *)&gInstructions[2220]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = 
@@ -8781,13 +8781,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2224]
+    (const void *)&gInstructions[2227]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2225]
+    (const void *)&gInstructions[2228]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = 
@@ -8813,13 +8813,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2228]
+    (const void *)&gInstructions[2231]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2229]
+    (const void *)&gInstructions[2232]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = 
@@ -8834,13 +8834,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2232]
+    (const void *)&gInstructions[2235]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2233]
+    (const void *)&gInstructions[2236]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = 
@@ -8855,7 +8855,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2294]
+    (const void *)&gInstructions[2297]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = 
@@ -8870,13 +8870,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2313]
+    (const void *)&gInstructions[2316]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2317]
+    (const void *)&gInstructions[2320]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = 
@@ -8891,7 +8891,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2327]
+    (const void *)&gInstructions[2330]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = 
@@ -8932,7 +8932,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2248]
+    (const void *)&gInstructions[2251]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = 
@@ -8949,7 +8949,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2285]
+    (const void *)&gInstructions[2288]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = 
@@ -8964,13 +8964,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2287]
+    (const void *)&gInstructions[2290]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2289]
+    (const void *)&gInstructions[2292]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = 
@@ -8987,7 +8987,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2295]
+    (const void *)&gInstructions[2298]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = 
@@ -9013,13 +9013,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2298]
+    (const void *)&gInstructions[2301]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2300]
+    (const void *)&gInstructions[2303]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = 
@@ -9034,13 +9034,13 @@ const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2331]
+    (const void *)&gInstructions[2334]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2333]
+    (const void *)&gInstructions[2336]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = 
@@ -9081,7 +9081,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2301]
+    (const void *)&gInstructions[2304]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = 
@@ -9107,19 +9107,19 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2309]
+    (const void *)&gInstructions[2312]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2323]
+    (const void *)&gInstructions[2326]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2342]
+    (const void *)&gInstructions[2345]
 };
 
 const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = 
@@ -9151,7 +9151,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2310]
+    (const void *)&gInstructions[2313]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = 
@@ -9168,13 +9168,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2314]
+    (const void *)&gInstructions[2317]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2318]
+    (const void *)&gInstructions[2321]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = 
@@ -9200,7 +9200,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2324]
+    (const void *)&gInstructions[2327]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = 
@@ -9217,7 +9217,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2328]
+    (const void *)&gInstructions[2331]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = 
@@ -9243,7 +9243,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2334]
+    (const void *)&gInstructions[2337]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = 
@@ -9269,7 +9269,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2343]
+    (const void *)&gInstructions[2346]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = 
@@ -9286,7 +9286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2346]
+    (const void *)&gInstructions[2349]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = 
@@ -9303,7 +9303,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2348]
+    (const void *)&gInstructions[2351]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = 
@@ -9329,7 +9329,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2350]
+    (const void *)&gInstructions[2353]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = 
@@ -9355,7 +9355,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2352]
+    (const void *)&gInstructions[2355]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = 
@@ -9372,7 +9372,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2354]
+    (const void *)&gInstructions[2357]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = 
@@ -9389,7 +9389,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2356]
+    (const void *)&gInstructions[2359]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = 
@@ -9406,7 +9406,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2358]
+    (const void *)&gInstructions[2361]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = 
@@ -9423,7 +9423,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2360]
+    (const void *)&gInstructions[2363]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = 
@@ -9440,7 +9440,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2373]
+    (const void *)&gInstructions[2376]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = 
@@ -9457,7 +9457,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2375]
+    (const void *)&gInstructions[2378]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = 
@@ -9483,7 +9483,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2377]
+    (const void *)&gInstructions[2380]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = 
@@ -9509,7 +9509,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2379]
+    (const void *)&gInstructions[2382]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = 
@@ -9526,7 +9526,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2381]
+    (const void *)&gInstructions[2384]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = 
@@ -9543,7 +9543,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2383]
+    (const void *)&gInstructions[2386]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = 
@@ -9569,7 +9569,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2385]
+    (const void *)&gInstructions[2388]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = 
@@ -9595,7 +9595,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2387]
+    (const void *)&gInstructions[2390]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = 
@@ -9612,13 +9612,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2390]
+    (const void *)&gInstructions[2393]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2391]
+    (const void *)&gInstructions[2394]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = 
@@ -9644,7 +9644,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2448]
+    (const void *)&gInstructions[2451]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = 
@@ -9659,7 +9659,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2450]
+    (const void *)&gInstructions[2453]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = 
@@ -9685,7 +9685,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2452]
+    (const void *)&gInstructions[2455]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = 
@@ -9700,7 +9700,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2454]
+    (const void *)&gInstructions[2457]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = 
@@ -9715,7 +9715,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2456]
+    (const void *)&gInstructions[2459]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = 
@@ -9730,7 +9730,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2458]
+    (const void *)&gInstructions[2461]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = 
@@ -9756,7 +9756,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2461]
+    (const void *)&gInstructions[2464]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = 
@@ -9771,7 +9771,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2463]
+    (const void *)&gInstructions[2466]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = 
@@ -9786,7 +9786,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2465]
+    (const void *)&gInstructions[2468]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = 
@@ -9801,7 +9801,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2467]
+    (const void *)&gInstructions[2470]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = 
@@ -9827,7 +9827,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2471]
+    (const void *)&gInstructions[2474]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = 
@@ -9842,7 +9842,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2473]
+    (const void *)&gInstructions[2476]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = 
@@ -9868,7 +9868,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2475]
+    (const void *)&gInstructions[2478]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = 
@@ -9883,7 +9883,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2477]
+    (const void *)&gInstructions[2480]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = 
@@ -9909,7 +9909,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2479]
+    (const void *)&gInstructions[2482]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = 
@@ -9924,7 +9924,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2481]
+    (const void *)&gInstructions[2484]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = 
@@ -9950,7 +9950,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2483]
+    (const void *)&gInstructions[2486]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = 
@@ -9965,7 +9965,7 @@ const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w =
 const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2485]
+    (const void *)&gInstructions[2488]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = 
@@ -10254,13 +10254,13 @@ const ND_TABLE_OPCODE gEvexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1351]
+    (const void *)&gInstructions[1353]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1352]
+    (const void *)&gInstructions[1354]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = 
@@ -10286,7 +10286,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1420]
+    (const void *)&gInstructions[1422]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = 
@@ -10312,7 +10312,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1466]
+    (const void *)&gInstructions[1468]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = 
@@ -10338,13 +10338,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1485]
+    (const void *)&gInstructions[1487]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1487]
+    (const void *)&gInstructions[1489]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = 
@@ -10370,13 +10370,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1486]
+    (const void *)&gInstructions[1488]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1488]
+    (const void *)&gInstructions[1490]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = 
@@ -10413,13 +10413,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1490]
+    (const void *)&gInstructions[1492]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1492]
+    (const void *)&gInstructions[1494]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = 
@@ -10445,13 +10445,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1491]
+    (const void *)&gInstructions[1493]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1493]
+    (const void *)&gInstructions[1495]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = 
@@ -10488,7 +10488,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1494]
+    (const void *)&gInstructions[1496]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = 
@@ -10505,7 +10505,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1495]
+    (const void *)&gInstructions[1497]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = 
@@ -10542,13 +10542,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1498]
+    (const void *)&gInstructions[1500]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1499]
+    (const void *)&gInstructions[1501]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = 
@@ -10574,13 +10574,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1500]
+    (const void *)&gInstructions[1502]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1501]
+    (const void *)&gInstructions[1503]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = 
@@ -10606,13 +10606,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1662]
+    (const void *)&gInstructions[1664]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1663]
+    (const void *)&gInstructions[1665]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = 
@@ -10638,13 +10638,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1664]
+    (const void *)&gInstructions[1666]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1665]
+    (const void *)&gInstructions[1667]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = 
@@ -10670,13 +10670,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1690]
+    (const void *)&gInstructions[1692]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1691]
+    (const void *)&gInstructions[1693]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = 
@@ -10702,13 +10702,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1692]
+    (const void *)&gInstructions[1694]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1693]
+    (const void *)&gInstructions[1695]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = 
@@ -10734,7 +10734,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1694]
+    (const void *)&gInstructions[1696]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = 
@@ -10760,7 +10760,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1696]
+    (const void *)&gInstructions[1698]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = 
@@ -10786,13 +10786,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1705]
+    (const void *)&gInstructions[1707]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1707]
+    (const void *)&gInstructions[1709]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = 
@@ -10818,13 +10818,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1706]
+    (const void *)&gInstructions[1708]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1708]
+    (const void *)&gInstructions[1710]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = 
@@ -10861,13 +10861,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1710]
+    (const void *)&gInstructions[1712]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1712]
+    (const void *)&gInstructions[1714]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = 
@@ -10893,13 +10893,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1711]
+    (const void *)&gInstructions[1713]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1713]
+    (const void *)&gInstructions[1715]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = 
@@ -10936,7 +10936,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1714]
+    (const void *)&gInstructions[1716]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = 
@@ -10953,7 +10953,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1715]
+    (const void *)&gInstructions[1717]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = 
@@ -10990,7 +10990,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1905]
+    (const void *)&gInstructions[1908]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = 
@@ -11007,7 +11007,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1938]
+    (const void *)&gInstructions[1941]
 };
 
 const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = 
@@ -11024,13 +11024,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1942]
+    (const void *)&gInstructions[1945]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1969]
+    (const void *)&gInstructions[1972]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = 
@@ -11056,13 +11056,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1943]
+    (const void *)&gInstructions[1946]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1964]
+    (const void *)&gInstructions[1967]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = 
@@ -11088,13 +11088,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1965]
+    (const void *)&gInstructions[1968]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1968]
+    (const void *)&gInstructions[1971]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = 
@@ -11120,13 +11120,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1966]
+    (const void *)&gInstructions[1969]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1967]
+    (const void *)&gInstructions[1970]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = 
@@ -11152,7 +11152,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2000]
+    (const void *)&gInstructions[2007]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = 
@@ -11178,7 +11178,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2004]
+    (const void *)&gInstructions[2011]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = 
@@ -11204,7 +11204,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2013]
+    (const void *)&gInstructions[2016]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = 
@@ -11230,7 +11230,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2019]
+    (const void *)&gInstructions[2022]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = 
@@ -11256,7 +11256,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2032]
+    (const void *)&gInstructions[2035]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = 
@@ -11273,7 +11273,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2033]
+    (const void *)&gInstructions[2036]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = 
@@ -11310,13 +11310,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2036]
+    (const void *)&gInstructions[2039]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2038]
+    (const void *)&gInstructions[2041]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_16_01_00_w = 
@@ -11353,7 +11353,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2041]
+    (const void *)&gInstructions[2044]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = 
@@ -11370,7 +11370,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2042]
+    (const void *)&gInstructions[2045]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = 
@@ -11407,7 +11407,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2076]
+    (const void *)&gInstructions[2079]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = 
@@ -11424,7 +11424,7 @@ const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2077]
+    (const void *)&gInstructions[2080]
 };
 
 const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = 
@@ -11461,13 +11461,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2080]
+    (const void *)&gInstructions[2083]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2082]
+    (const void *)&gInstructions[2085]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_w = 
@@ -11504,13 +11504,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2268]
+    (const void *)&gInstructions[2270]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2269]
+    (const void *)&gInstructions[2271]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = 
@@ -11536,7 +11536,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2273]
+    (const void *)&gInstructions[2275]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = 
@@ -11562,13 +11562,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2276]
+    (const void *)&gInstructions[2279]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2277]
+    (const void *)&gInstructions[2280]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = 
@@ -11594,7 +11594,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2281]
+    (const void *)&gInstructions[2284]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = 
@@ -11620,13 +11620,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2362]
+    (const void *)&gInstructions[2365]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2363]
+    (const void *)&gInstructions[2366]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = 
@@ -11652,13 +11652,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2392]
+    (const void *)&gInstructions[2395]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2393]
+    (const void *)&gInstructions[2396]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = 
@@ -11684,13 +11684,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2394]
+    (const void *)&gInstructions[2397]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2395]
+    (const void *)&gInstructions[2398]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = 
@@ -11716,13 +11716,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2406]
+    (const void *)&gInstructions[2409]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2407]
+    (const void *)&gInstructions[2410]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = 
@@ -11748,13 +11748,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2408]
+    (const void *)&gInstructions[2411]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2409]
+    (const void *)&gInstructions[2412]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = 
@@ -11780,7 +11780,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2410]
+    (const void *)&gInstructions[2413]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = 
@@ -11806,7 +11806,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2411]
+    (const void *)&gInstructions[2414]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = 
@@ -11832,7 +11832,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2412]
+    (const void *)&gInstructions[2415]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = 
@@ -11858,7 +11858,7 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2413]
+    (const void *)&gInstructions[2416]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = 
@@ -11884,13 +11884,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2444]
+    (const void *)&gInstructions[2447]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2445]
+    (const void *)&gInstructions[2448]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = 
@@ -11916,13 +11916,13 @@ const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp =
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2446]
+    (const void *)&gInstructions[2449]
 };
 
 const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2447]
+    (const void *)&gInstructions[2450]
 };
 
 const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = 
diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h
index c22784d..d5f00c1 100644
--- a/bddisasm/include/table_root.h
+++ b/bddisasm/include/table_root.h
@@ -94,19 +94,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1182]
+    (const void *)&gInstructions[1184]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1277]
+    (const void *)&gInstructions[1279]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2529]
+    (const void *)&gInstructions[2532]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = 
@@ -157,19 +157,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1183]
+    (const void *)&gInstructions[1185]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1278]
+    (const void *)&gInstructions[1280]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2530]
+    (const void *)&gInstructions[2533]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = 
@@ -220,19 +220,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1184]
+    (const void *)&gInstructions[1186]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1279]
+    (const void *)&gInstructions[1281]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2531]
+    (const void *)&gInstructions[2534]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = 
@@ -283,19 +283,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1185]
+    (const void *)&gInstructions[1187]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1280]
+    (const void *)&gInstructions[1282]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2532]
+    (const void *)&gInstructions[2535]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = 
@@ -328,13 +328,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2497]
+    (const void *)&gInstructions[2500]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2498]
+    (const void *)&gInstructions[2501]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = 
@@ -731,7 +731,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[385]
+    (const void *)&gInstructions[387]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = 
@@ -748,7 +748,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[429]
+    (const void *)&gInstructions[431]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = 
@@ -774,7 +774,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[433]
+    (const void *)&gInstructions[435]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = 
@@ -800,7 +800,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[434]
+    (const void *)&gInstructions[436]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = 
@@ -1590,13 +1590,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[996]
+    (const void *)&gInstructions[997]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[997]
+    (const void *)&gInstructions[998]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = 
@@ -1613,13 +1613,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1002]
+    (const void *)&gInstructions[1003]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1003]
+    (const void *)&gInstructions[1004]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = 
@@ -1636,13 +1636,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1004]
+    (const void *)&gInstructions[1005]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1005]
+    (const void *)&gInstructions[1006]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = 
@@ -1659,13 +1659,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1006]
+    (const void *)&gInstructions[1007]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1007]
+    (const void *)&gInstructions[1008]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = 
@@ -1682,7 +1682,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1060]
+    (const void *)&gInstructions[1061]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = 
@@ -1699,7 +1699,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1214]
+    (const void *)&gInstructions[1216]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = 
@@ -1716,7 +1716,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1215]
+    (const void *)&gInstructions[1217]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = 
@@ -1733,7 +1733,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1216]
+    (const void *)&gInstructions[1218]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = 
@@ -1750,7 +1750,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1218]
+    (const void *)&gInstructions[1220]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = 
@@ -1767,7 +1767,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1219]
+    (const void *)&gInstructions[1221]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = 
@@ -1784,7 +1784,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1220]
+    (const void *)&gInstructions[1222]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = 
@@ -1801,13 +1801,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2499]
+    (const void *)&gInstructions[2502]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2500]
+    (const void *)&gInstructions[2503]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = 
@@ -2269,7 +2269,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[383]
+    (const void *)&gInstructions[385]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = 
@@ -2286,7 +2286,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[384]
+    (const void *)&gInstructions[386]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = 
@@ -2303,7 +2303,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[418]
+    (const void *)&gInstructions[420]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = 
@@ -2320,7 +2320,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[419]
+    (const void *)&gInstructions[421]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = 
@@ -2689,7 +2689,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1149]
+    (const void *)&gInstructions[1151]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = 
@@ -2706,7 +2706,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1150]
+    (const void *)&gInstructions[1152]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = 
@@ -2723,7 +2723,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1151]
+    (const void *)&gInstructions[1153]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = 
@@ -2740,7 +2740,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1152]
+    (const void *)&gInstructions[1154]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = 
@@ -2757,7 +2757,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1217]
+    (const void *)&gInstructions[1219]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = 
@@ -3253,7 +3253,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1314]
+    (const void *)&gInstructions[1316]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = 
@@ -3482,7 +3482,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1254]
+    (const void *)&gInstructions[1256]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = 
@@ -3520,37 +3520,43 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[431]
+    (const void *)&gInstructions[433]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1242]
+    (const void *)&gInstructions[1244]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1257]
+    (const void *)&gInstructions[1259]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1736]
+    (const void *)&gInstructions[1738]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1737]
+    (const void *)&gInstructions[1739]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1748]
+    (const void *)&gInstructions[1750]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[1751]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = 
@@ -3558,7 +3564,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
     ND_ILUT_MAN_PREFIX,
     { 
         /* 00 */ (const void *)&gRootTable_root_0f_01_reg_03_01_None_leaf,
-        /* 01 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_0f_01_reg_03_01_66_leaf,
         /* 02 */ (const void *)&gRootTable_root_0f_01_reg_03_01_F3_leaf,
         /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_01_F2_leaf,
     }
@@ -3567,19 +3573,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1747]
+    (const void *)&gInstructions[1749]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1853]
+    (const void *)&gInstructions[1856]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1854]
+    (const void *)&gInstructions[1857]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = 
@@ -3606,19 +3612,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[432]
+    (const void *)&gInstructions[434]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1134]
+    (const void *)&gInstructions[1136]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1135]
+    (const void *)&gInstructions[1137]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = 
@@ -3675,19 +3681,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1021]
+    (const void *)&gInstructions[1022]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1097]
+    (const void *)&gInstructions[1099]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1312]
+    (const void *)&gInstructions[1314]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = 
@@ -3704,19 +3710,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1120]
+    (const void *)&gInstructions[1122]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1129]
+    (const void *)&gInstructions[1131]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1288]
+    (const void *)&gInstructions[1290]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = 
@@ -3754,7 +3760,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1735]
+    (const void *)&gInstructions[1737]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = 
@@ -3771,7 +3777,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2520]
+    (const void *)&gInstructions[2523]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = 
@@ -3788,7 +3794,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2521]
+    (const void *)&gInstructions[2524]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = 
@@ -3805,7 +3811,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2548]
+    (const void *)&gInstructions[2551]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = 
@@ -3822,7 +3828,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2553]
+    (const void *)&gInstructions[2556]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = 
@@ -3888,25 +3894,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1733]
+    (const void *)&gInstructions[1735]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1746]
+    (const void *)&gInstructions[1748]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1852]
+    (const void *)&gInstructions[1855]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1864]
+    (const void *)&gInstructions[1867]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = 
@@ -3927,13 +3933,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[566]
+    (const void *)&gInstructions[568]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1118]
+    (const void *)&gInstructions[1120]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = 
@@ -3950,7 +3956,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1175]
+    (const void *)&gInstructions[1177]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = 
@@ -3967,19 +3973,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1194]
+    (const void *)&gInstructions[1196]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1210]
+    (const void *)&gInstructions[1212]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2552]
+    (const void *)&gInstructions[2555]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = 
@@ -3996,7 +4002,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2495]
+    (const void *)&gInstructions[2498]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = 
@@ -4013,7 +4019,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2535]
+    (const void *)&gInstructions[2538]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = 
@@ -4045,7 +4051,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1248]
+    (const void *)&gInstructions[1250]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = 
@@ -4066,31 +4072,31 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[430]
+    (const void *)&gInstructions[432]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[561]
+    (const void *)&gInstructions[563]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[563]
+    (const void *)&gInstructions[565]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[566]
+    (const void *)&gInstructions[568]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1158]
+    (const void *)&gInstructions[1160]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = 
@@ -4107,19 +4113,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1213]
+    (const void *)&gInstructions[1215]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1241]
+    (const void *)&gInstructions[1243]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1247]
+    (const void *)&gInstructions[1249]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = 
@@ -4348,13 +4354,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2544]
+    (const void *)&gInstructions[2547]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2545]
+    (const void *)&gInstructions[2548]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = 
@@ -4381,34 +4387,72 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix =
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[377]
 };
 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_rexw_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[378]
+};
+
+const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = 
+{
+    ND_ILUT_AUXILIARY,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_None_leaf,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_rexw_leaf,
+        /* 03 */ NULL,
+        /* 04 */ NULL,
+        /* 05 */ NULL,
+    }
+};
+
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_leaf,
+        /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_auxiliary,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[378]
+    (const void *)&gInstructions[379]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_rexw_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[380]
+};
+
+const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = 
+{
+    ND_ILUT_AUXILIARY,
+    { 
+        /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_None_leaf,
+        /* 01 */ NULL,
+        /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_rexw_leaf,
+        /* 03 */ NULL,
+        /* 04 */ NULL,
+        /* 05 */ NULL,
+    }
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix = 
 {
     ND_ILUT_MAN_PREFIX,
     { 
-        /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_leaf,
+        /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_auxiliary,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
@@ -4418,7 +4462,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[553]
+    (const void *)&gInstructions[555]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = 
@@ -4435,19 +4479,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1061]
+    (const void *)&gInstructions[1062]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2540]
+    (const void *)&gInstructions[2543]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2541]
+    (const void *)&gInstructions[2544]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = 
@@ -4477,7 +4521,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1259]
+    (const void *)&gInstructions[1261]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = 
@@ -4494,13 +4538,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2536]
+    (const void *)&gInstructions[2539]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2537]
+    (const void *)&gInstructions[2540]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = 
@@ -4545,13 +4589,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[412]
+    (const void *)&gInstructions[414]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[413]
+    (const void *)&gInstructions[415]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = 
@@ -4570,7 +4614,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[559]
+    (const void *)&gInstructions[561]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = 
@@ -4593,19 +4637,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1313]
+    (const void *)&gInstructions[1315]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1321]
+    (const void *)&gInstructions[1323]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1322]
+    (const void *)&gInstructions[1324]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = 
@@ -4628,7 +4672,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1212]
+    (const void *)&gInstructions[1214]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = 
@@ -4645,7 +4689,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1061]
+    (const void *)&gInstructions[1062]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = 
@@ -4662,7 +4706,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1114]
+    (const void *)&gInstructions[1116]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = 
@@ -4692,7 +4736,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1115]
+    (const void *)&gInstructions[1117]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = 
@@ -4722,7 +4766,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2492]
+    (const void *)&gInstructions[2495]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = 
@@ -4752,7 +4796,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2493]
+    (const void *)&gInstructions[2496]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = 
@@ -4980,19 +5024,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1734]
+    (const void *)&gInstructions[1736]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1849]
+    (const void *)&gInstructions[1852]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1865]
+    (const void *)&gInstructions[1868]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = 
@@ -5009,7 +5053,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1850]
+    (const void *)&gInstructions[1853]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = 
@@ -5026,13 +5070,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2538]
+    (const void *)&gInstructions[2541]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2539]
+    (const void *)&gInstructions[2542]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = 
@@ -5062,13 +5106,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2542]
+    (const void *)&gInstructions[2545]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2543]
+    (const void *)&gInstructions[2546]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = 
@@ -5098,13 +5142,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2546]
+    (const void *)&gInstructions[2549]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2547]
+    (const void *)&gInstructions[2550]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = 
@@ -5149,19 +5193,19 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1117]
+    (const void *)&gInstructions[1119]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1123]
+    (const void *)&gInstructions[1125]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1124]
+    (const void *)&gInstructions[1126]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = 
@@ -5178,13 +5222,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1121]
+    (const void *)&gInstructions[1123]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1122]
+    (const void *)&gInstructions[1124]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = 
@@ -5641,7 +5685,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_rexw_None_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_rexw_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1127]
+    (const void *)&gInstructions[1129]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_01_rexw_auxiliary = 
@@ -5660,7 +5704,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_01_rexw_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_reg_01_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1126]
+    (const void *)&gInstructions[1128]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_reg_01_auxiliary = 
@@ -5760,13 +5804,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[420]
+    (const void *)&gInstructions[422]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1851]
+    (const void *)&gInstructions[1854]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = 
@@ -5783,7 +5827,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1285]
+    (const void *)&gInstructions[1287]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = 
@@ -5817,13 +5861,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[421]
+    (const void *)&gInstructions[423]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1863]
+    (const void *)&gInstructions[1866]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = 
@@ -5840,7 +5884,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1863]
+    (const void *)&gInstructions[1866]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = 
@@ -5866,7 +5910,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1153]
+    (const void *)&gInstructions[1155]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = 
@@ -5900,7 +5944,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[382]
+    (const void *)&gInstructions[384]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = 
@@ -5917,7 +5961,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2496]
+    (const void *)&gInstructions[2499]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = 
@@ -5936,13 +5980,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[386]
+    (const void *)&gInstructions[388]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[387]
+    (const void *)&gInstructions[389]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = 
@@ -5959,7 +6003,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1287]
+    (const void *)&gInstructions[1289]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = 
@@ -5987,13 +6031,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[389]
+    (const void *)&gInstructions[391]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[390]
+    (const void *)&gInstructions[392]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = 
@@ -6010,7 +6054,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1159]
+    (const void *)&gInstructions[1161]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = 
@@ -6038,49 +6082,49 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[393]
+    (const void *)&gInstructions[395]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[428]
+    (const void *)&gInstructions[430]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[438]
+    (const void *)&gInstructions[440]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[440]
+    (const void *)&gInstructions[442]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[444]
+    (const void *)&gInstructions[446]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[446]
+    (const void *)&gInstructions[448]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[451]
+    (const void *)&gInstructions[453]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[564]
+    (const void *)&gInstructions[566]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = 
@@ -6092,25 +6136,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1243]
+    (const void *)&gInstructions[1245]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1268]
+    (const void *)&gInstructions[1270]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1478]
+    (const void *)&gInstructions[1480]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1479]
+    (const void *)&gInstructions[1481]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = 
@@ -6131,13 +6175,13 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[451]
+    (const void *)&gInstructions[453]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[564]
+    (const void *)&gInstructions[566]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = 
@@ -6149,25 +6193,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1244]
+    (const void *)&gInstructions[1246]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1269]
+    (const void *)&gInstructions[1271]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1478]
+    (const void *)&gInstructions[1480]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1479]
+    (const void *)&gInstructions[1481]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = 
@@ -6197,13 +6241,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[452]
+    (const void *)&gInstructions[454]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[976]
+    (const void *)&gInstructions[977]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = 
@@ -6222,85 +6266,85 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[455]
+    (const void *)&gInstructions[457]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[457]
+    (const void *)&gInstructions[459]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[459]
+    (const void *)&gInstructions[461]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[461]
+    (const void *)&gInstructions[463]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[463]
+    (const void *)&gInstructions[465]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[465]
+    (const void *)&gInstructions[467]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[467]
+    (const void *)&gInstructions[469]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[469]
+    (const void *)&gInstructions[471]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[471]
+    (const void *)&gInstructions[473]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[473]
+    (const void *)&gInstructions[475]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[476]
+    (const void *)&gInstructions[478]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[478]
+    (const void *)&gInstructions[480]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[550]
+    (const void *)&gInstructions[552]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[551]
+    (const void *)&gInstructions[553]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = 
@@ -6315,7 +6359,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[552]
+    (const void *)&gInstructions[554]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = 
@@ -6341,7 +6385,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[560]
+    (const void *)&gInstructions[562]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = 
@@ -6356,7 +6400,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[562]
+    (const void *)&gInstructions[564]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = 
@@ -6368,56 +6412,6 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod =
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_None_leaf = 
-{
-    ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[567]
-};
-
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_64_leaf = 
-{
-    ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1289]
-};
-
-const ND_TABLE_AUXILIARY gRootTable_root_0f_05_auxiliary = 
-{
-    ND_ILUT_AUXILIARY,
-    { 
-        /* 00 */ (const void *)&gRootTable_root_0f_05_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ (const void *)&gRootTable_root_0f_05_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-    }
-};
-
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_None_leaf = 
-{
-    ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[568]
-};
-
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_64_leaf = 
-{
-    ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1292]
-};
-
-const ND_TABLE_AUXILIARY gRootTable_root_0f_07_auxiliary = 
-{
-    ND_ILUT_AUXILIARY,
-    { 
-        /* 00 */ (const void *)&gRootTable_root_0f_07_None_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ (const void *)&gRootTable_root_0f_07_64_leaf,
-        /* 04 */ NULL,
-        /* 05 */ NULL,
-    }
-};
-
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
@@ -6591,7 +6585,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2549]
+    (const void *)&gInstructions[2552]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = 
@@ -6623,7 +6617,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2550]
+    (const void *)&gInstructions[2553]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = 
@@ -6889,7 +6883,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1246]
+    (const void *)&gInstructions[1248]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = 
@@ -6911,16 +6905,16 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf =
     (const void *)&gInstructions[650]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[663]
+    (const void *)&gInstructions[658]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[665]
+    (const void *)&gInstructions[664]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = 
@@ -6949,7 +6943,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[665]
+    (const void *)&gInstructions[658]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = 
@@ -7094,13 +7088,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[658]
+    (const void *)&gInstructions[659]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[660]
+    (const void *)&gInstructions[661]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = 
@@ -7123,7 +7117,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[662]
+    (const void *)&gInstructions[663]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = 
@@ -7155,13 +7149,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[659]
+    (const void *)&gInstructions[660]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[661]
+    (const void *)&gInstructions[662]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = 
@@ -7187,7 +7181,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[664]
+    (const void *)&gInstructions[665]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = 
@@ -7545,49 +7539,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[982]
+    (const void *)&gInstructions[983]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[983]
+    (const void *)&gInstructions[984]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[984]
+    (const void *)&gInstructions[985]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[985]
+    (const void *)&gInstructions[986]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[986]
+    (const void *)&gInstructions[987]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[987]
+    (const void *)&gInstructions[988]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[992]
+    (const void *)&gInstructions[993]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[993]
+    (const void *)&gInstructions[994]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = 
@@ -7704,25 +7698,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_07_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[988]
+    (const void *)&gInstructions[989]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[989]
+    (const void *)&gInstructions[990]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[990]
+    (const void *)&gInstructions[991]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[991]
+    (const void *)&gInstructions[992]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_0f_18_mem_modrmreg = 
@@ -8172,25 +8166,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf =
     (const void *)&gInstructions[878]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[879]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[880]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[881]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[882]
@@ -8265,7 +8259,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1059]
+    (const void *)&gInstructions[1060]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = 
@@ -9033,13 +9027,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[980]
+    (const void *)&gInstructions[981]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[981]
+    (const void *)&gInstructions[982]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = 
@@ -9056,13 +9050,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[994]
+    (const void *)&gInstructions[995]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[995]
+    (const void *)&gInstructions[996]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = 
@@ -9079,25 +9073,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[998]
+    (const void *)&gInstructions[999]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[999]
+    (const void *)&gInstructions[1000]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1000]
+    (const void *)&gInstructions[1001]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1001]
+    (const void *)&gInstructions[1002]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = 
@@ -9114,13 +9108,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1008]
+    (const void *)&gInstructions[1009]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1009]
+    (const void *)&gInstructions[1010]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = 
@@ -9137,13 +9131,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1022]
+    (const void *)&gInstructions[1023]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1023]
+    (const void *)&gInstructions[1024]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = 
@@ -9160,13 +9154,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1030]
+    (const void *)&gInstructions[1031]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1031]
+    (const void *)&gInstructions[1032]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = 
@@ -9207,13 +9201,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1010]
+    (const void *)&gInstructions[1011]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1011]
+    (const void *)&gInstructions[1012]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = 
@@ -9230,7 +9224,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1012]
+    (const void *)&gInstructions[1013]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = 
@@ -9247,13 +9241,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1013]
+    (const void *)&gInstructions[1014]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1014]
+    (const void *)&gInstructions[1015]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = 
@@ -9270,7 +9264,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1034]
+    (const void *)&gInstructions[1035]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = 
@@ -9287,13 +9281,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1035]
+    (const void *)&gInstructions[1036]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1036]
+    (const void *)&gInstructions[1037]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = 
@@ -9334,13 +9328,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1015]
+    (const void *)&gInstructions[1016]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1016]
+    (const void *)&gInstructions[1017]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = 
@@ -9357,13 +9351,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1017]
+    (const void *)&gInstructions[1018]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1018]
+    (const void *)&gInstructions[1019]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = 
@@ -9380,13 +9374,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1026]
+    (const void *)&gInstructions[1027]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1027]
+    (const void *)&gInstructions[1028]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = 
@@ -9403,13 +9397,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1039]
+    (const void *)&gInstructions[1040]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1040]
+    (const void *)&gInstructions[1041]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = 
@@ -9450,13 +9444,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1019]
+    (const void *)&gInstructions[1020]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1020]
+    (const void *)&gInstructions[1021]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = 
@@ -9473,13 +9467,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1024]
+    (const void *)&gInstructions[1025]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1025]
+    (const void *)&gInstructions[1026]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = 
@@ -9496,13 +9490,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1028]
+    (const void *)&gInstructions[1029]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1029]
+    (const void *)&gInstructions[1030]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = 
@@ -9519,13 +9513,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1032]
+    (const void *)&gInstructions[1033]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1033]
+    (const void *)&gInstructions[1034]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = 
@@ -9542,13 +9536,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1037]
+    (const void *)&gInstructions[1038]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1038]
+    (const void *)&gInstructions[1039]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = 
@@ -9565,13 +9559,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1041]
+    (const void *)&gInstructions[1042]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1042]
+    (const void *)&gInstructions[1043]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = 
@@ -9588,13 +9582,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1043]
+    (const void *)&gInstructions[1044]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1044]
+    (const void *)&gInstructions[1045]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = 
@@ -9611,13 +9605,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1045]
+    (const void *)&gInstructions[1046]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1046]
+    (const void *)&gInstructions[1047]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = 
@@ -9634,13 +9628,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1047]
+    (const void *)&gInstructions[1048]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1048]
+    (const void *)&gInstructions[1049]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = 
@@ -9657,13 +9651,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1049]
+    (const void *)&gInstructions[1050]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1050]
+    (const void *)&gInstructions[1051]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = 
@@ -9680,13 +9674,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1051]
+    (const void *)&gInstructions[1052]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1052]
+    (const void *)&gInstructions[1053]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = 
@@ -9703,13 +9697,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1053]
+    (const void *)&gInstructions[1054]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1054]
+    (const void *)&gInstructions[1055]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = 
@@ -9726,13 +9720,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1055]
+    (const void *)&gInstructions[1056]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1056]
+    (const void *)&gInstructions[1057]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = 
@@ -9749,13 +9743,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1057]
+    (const void *)&gInstructions[1058]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1058]
+    (const void *)&gInstructions[1059]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = 
@@ -9772,13 +9766,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1062]
+    (const void *)&gInstructions[1063]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1063]
+    (const void *)&gInstructions[1064]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = 
@@ -9795,13 +9789,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1064]
+    (const void *)&gInstructions[1065]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1065]
+    (const void *)&gInstructions[1066]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = 
@@ -9818,7 +9812,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1066]
+    (const void *)&gInstructions[1067]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = 
@@ -9835,13 +9829,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1067]
+    (const void *)&gInstructions[1068]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1068]
+    (const void *)&gInstructions[1069]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = 
@@ -9858,13 +9852,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1069]
+    (const void *)&gInstructions[1070]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1070]
+    (const void *)&gInstructions[1071]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = 
@@ -9881,13 +9875,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1071]
+    (const void *)&gInstructions[1072]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1072]
+    (const void *)&gInstructions[1073]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = 
@@ -9904,7 +9898,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1073]
+    (const void *)&gInstructions[1074]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = 
@@ -9921,13 +9915,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1074]
+    (const void *)&gInstructions[1075]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1075]
+    (const void *)&gInstructions[1076]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = 
@@ -9944,25 +9938,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1076]
+    (const void *)&gInstructions[1077]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1077]
+    (const void *)&gInstructions[1078]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1098]
+    (const void *)&gInstructions[1100]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1099]
+    (const void *)&gInstructions[1101]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = 
@@ -9979,13 +9973,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1106]
+    (const void *)&gInstructions[1108]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1107]
+    (const void *)&gInstructions[1109]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = 
@@ -10002,19 +9996,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1116]
+    (const void *)&gInstructions[1118]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1119]
+    (const void *)&gInstructions[1121]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1125]
+    (const void *)&gInstructions[1127]
 };
 
 const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = 
@@ -10033,13 +10027,13 @@ const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1128]
+    (const void *)&gInstructions[1130]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1154]
+    (const void *)&gInstructions[1156]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = 
@@ -10067,19 +10061,19 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1155]
+    (const void *)&gInstructions[1157]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1156]
+    (const void *)&gInstructions[1158]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1157]
+    (const void *)&gInstructions[1159]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = 
@@ -10096,133 +10090,133 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1195]
+    (const void *)&gInstructions[1197]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1196]
+    (const void *)&gInstructions[1198]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1197]
+    (const void *)&gInstructions[1199]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1198]
+    (const void *)&gInstructions[1200]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1199]
+    (const void *)&gInstructions[1201]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1200]
+    (const void *)&gInstructions[1202]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1201]
+    (const void *)&gInstructions[1203]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1202]
+    (const void *)&gInstructions[1204]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1203]
+    (const void *)&gInstructions[1205]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1204]
+    (const void *)&gInstructions[1206]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1205]
+    (const void *)&gInstructions[1207]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1206]
+    (const void *)&gInstructions[1208]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1207]
+    (const void *)&gInstructions[1209]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1208]
+    (const void *)&gInstructions[1210]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1209]
+    (const void *)&gInstructions[1211]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1211]
+    (const void *)&gInstructions[1213]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1227]
+    (const void *)&gInstructions[1229]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1228]
+    (const void *)&gInstructions[1230]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1236]
+    (const void *)&gInstructions[1238]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1237]
+    (const void *)&gInstructions[1239]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1239]
+    (const void *)&gInstructions[1241]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1240]
+    (const void *)&gInstructions[1242]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = 
@@ -10239,25 +10233,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1250]
+    (const void *)&gInstructions[1252]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1251]
+    (const void *)&gInstructions[1253]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1252]
+    (const void *)&gInstructions[1254]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1253]
+    (const void *)&gInstructions[1255]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = 
@@ -10274,25 +10268,25 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1281]
+    (const void *)&gInstructions[1283]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1282]
+    (const void *)&gInstructions[1284]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1283]
+    (const void *)&gInstructions[1285]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1284]
+    (const void *)&gInstructions[1286]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = 
@@ -10309,7 +10303,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1286]
+    (const void *)&gInstructions[1288]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = 
@@ -10334,28 +10328,40 @@ const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor =
     }
 };
 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[1291]
+};
+
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1290]
+    (const void *)&gInstructions[1292]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1291]
+    (const void *)&gInstructions[1293]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[1294]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1316]
+    (const void *)&gInstructions[1318]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1317]
+    (const void *)&gInstructions[1319]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = 
@@ -10372,31 +10378,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1318]
+    (const void *)&gInstructions[1320]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1319]
+    (const void *)&gInstructions[1321]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1320]
+    (const void *)&gInstructions[1322]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1323]
+    (const void *)&gInstructions[1325]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1324]
+    (const void *)&gInstructions[1326]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = 
@@ -10413,13 +10419,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1325]
+    (const void *)&gInstructions[1327]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1326]
+    (const void *)&gInstructions[1328]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = 
@@ -10433,51 +10439,53 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_NP_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2490]
+    (const void *)&gInstructions[2493]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_F3_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2491]
+    (const void *)&gInstructions[2494]
 };
 
-const ND_TABLE_MPREFIX gRootTable_root_0f_09_mprefix = 
+const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = 
 {
-    ND_ILUT_MAN_PREFIX,
+    ND_ILUT_AUXILIARY,
     { 
-        /* 00 */ (const void *)&gRootTable_root_0f_09_NP_leaf,
+        /* 00 */ (const void *)&gRootTable_root_0f_09_None_leaf,
         /* 01 */ NULL,
-        /* 02 */ (const void *)&gRootTable_root_0f_09_F3_leaf,
+        /* 02 */ NULL,
         /* 03 */ NULL,
+        /* 04 */ (const void *)&gRootTable_root_0f_09_aF3_leaf,
+        /* 05 */ NULL,
     }
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2494]
+    (const void *)&gInstructions[2497]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2502]
+    (const void *)&gInstructions[2505]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2503]
+    (const void *)&gInstructions[2506]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2515]
+    (const void *)&gInstructions[2518]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = 
@@ -10509,7 +10517,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2516]
+    (const void *)&gInstructions[2519]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = 
@@ -10541,7 +10549,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2517]
+    (const void *)&gInstructions[2520]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = 
@@ -10573,7 +10581,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2518]
+    (const void *)&gInstructions[2521]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = 
@@ -10605,7 +10613,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2519]
+    (const void *)&gInstructions[2522]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = 
@@ -10637,7 +10645,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2551]
+    (const void *)&gInstructions[2554]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_00_modrmrm = 
@@ -10682,13 +10690,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2533]
+    (const void *)&gInstructions[2536]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2534]
+    (const void *)&gInstructions[2537]
 };
 
 const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = 
@@ -10711,11 +10719,11 @@ const ND_TABLE_OPCODE gRootTable_root_0f_opcode =
         /* 02 */ (const void *)&gRootTable_root_0f_02_modrmmod,
         /* 03 */ (const void *)&gRootTable_root_0f_03_modrmmod,
         /* 04 */ NULL,
-        /* 05 */ (const void *)&gRootTable_root_0f_05_auxiliary,
+        /* 05 */ (const void *)&gRootTable_root_0f_05_leaf,
         /* 06 */ (const void *)&gRootTable_root_0f_06_leaf,
-        /* 07 */ (const void *)&gRootTable_root_0f_07_auxiliary,
+        /* 07 */ (const void *)&gRootTable_root_0f_07_leaf,
         /* 08 */ (const void *)&gRootTable_root_0f_08_leaf,
-        /* 09 */ (const void *)&gRootTable_root_0f_09_mprefix,
+        /* 09 */ (const void *)&gRootTable_root_0f_09_auxiliary,
         /* 0a */ (const void *)&gRootTable_root_0f_0a_leaf,
         /* 0b */ (const void *)&gRootTable_root_0f_0b_leaf,
         /* 0c */ NULL,
@@ -11104,25 +11112,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[411]
+    (const void *)&gInstructions[413]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[450]
+    (const void *)&gInstructions[452]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[454]
+    (const void *)&gInstructions[456]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1092]
+    (const void *)&gInstructions[1093]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = 
@@ -11155,19 +11163,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[411]
+    (const void *)&gInstructions[413]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[450]
+    (const void *)&gInstructions[452]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1092]
+    (const void *)&gInstructions[1093]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = 
@@ -11504,7 +11512,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[410]
+    (const void *)&gInstructions[412]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = 
@@ -11531,13 +11539,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[391]
+    (const void *)&gInstructions[393]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[396]
+    (const void *)&gInstructions[398]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = 
@@ -11561,13 +11569,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1303]
+    (const void *)&gInstructions[1305]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1304]
+    (const void *)&gInstructions[1306]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = 
@@ -11594,13 +11602,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[392]
+    (const void *)&gInstructions[394]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[397]
+    (const void *)&gInstructions[399]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = 
@@ -11624,13 +11632,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1305]
+    (const void *)&gInstructions[1307]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1306]
+    (const void *)&gInstructions[1308]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = 
@@ -11693,13 +11701,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[379]
+    (const void *)&gInstructions[381]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[380]
+    (const void *)&gInstructions[382]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = 
@@ -11801,7 +11809,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[381]
+    (const void *)&gInstructions[383]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = 
@@ -13001,103 +13009,103 @@ const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[388]
+    (const void *)&gInstructions[390]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[394]
+    (const void *)&gInstructions[396]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[395]
+    (const void *)&gInstructions[397]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[398]
+    (const void *)&gInstructions[400]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[399]
+    (const void *)&gInstructions[401]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[400]
+    (const void *)&gInstructions[402]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[401]
+    (const void *)&gInstructions[403]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[402]
+    (const void *)&gInstructions[404]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[403]
+    (const void *)&gInstructions[405]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[404]
+    (const void *)&gInstructions[406]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[405]
+    (const void *)&gInstructions[407]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[406]
+    (const void *)&gInstructions[408]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[407]
+    (const void *)&gInstructions[409]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[408]
+    (const void *)&gInstructions[410]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[409]
+    (const void *)&gInstructions[411]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[414]
+    (const void *)&gInstructions[416]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[415]
+    (const void *)&gInstructions[417]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = 
@@ -13116,13 +13124,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[416]
+    (const void *)&gInstructions[418]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[417]
+    (const void *)&gInstructions[419]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = 
@@ -13141,13 +13149,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[422]
+    (const void *)&gInstructions[424]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[423]
+    (const void *)&gInstructions[425]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = 
@@ -13179,43 +13187,43 @@ const ND_TABLE_DSIZE gRootTable_root_6d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[424]
+    (const void *)&gInstructions[426]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[425]
+    (const void *)&gInstructions[427]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[426]
+    (const void *)&gInstructions[428]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[427]
+    (const void *)&gInstructions[429]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[435]
+    (const void *)&gInstructions[437]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[436]
+    (const void *)&gInstructions[438]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[437]
+    (const void *)&gInstructions[439]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_cf_dsize = 
@@ -13234,31 +13242,31 @@ const ND_TABLE_DSIZE gRootTable_root_cf_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[439]
+    (const void *)&gInstructions[441]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[441]
+    (const void *)&gInstructions[443]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[442]
+    (const void *)&gInstructions[444]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[443]
+    (const void *)&gInstructions[445]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[475]
+    (const void *)&gInstructions[477]
 };
 
 const ND_TABLE_ASIZE gRootTable_root_e3_asize = 
@@ -13275,115 +13283,115 @@ const ND_TABLE_ASIZE gRootTable_root_e3_asize =
 const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[445]
+    (const void *)&gInstructions[447]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[447]
+    (const void *)&gInstructions[449]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[448]
+    (const void *)&gInstructions[450]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[449]
+    (const void *)&gInstructions[451]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[453]
+    (const void *)&gInstructions[455]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[456]
+    (const void *)&gInstructions[458]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[458]
+    (const void *)&gInstructions[460]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[460]
+    (const void *)&gInstructions[462]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[462]
+    (const void *)&gInstructions[464]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[464]
+    (const void *)&gInstructions[466]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[466]
+    (const void *)&gInstructions[468]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[468]
+    (const void *)&gInstructions[470]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[470]
+    (const void *)&gInstructions[472]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[472]
+    (const void *)&gInstructions[474]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[474]
+    (const void *)&gInstructions[476]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[477]
+    (const void *)&gInstructions[479]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[479]
+    (const void *)&gInstructions[481]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[549]
+    (const void *)&gInstructions[551]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[554]
+    (const void *)&gInstructions[556]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = 
@@ -13398,7 +13406,7 @@ const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[556]
+    (const void *)&gInstructions[558]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = 
@@ -13413,13 +13421,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod =
 const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[557]
+    (const void *)&gInstructions[559]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[558]
+    (const void *)&gInstructions[560]
 };
 
 const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = 
@@ -13778,7 +13786,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2501]
+    (const void *)&gInstructions[2504]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = 
@@ -13850,7 +13858,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2504]
+    (const void *)&gInstructions[2507]
 };
 
 const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = 
@@ -14020,7 +14028,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf =
 const ND_TABLE_INSTRUCTION gRootTable_root_90_rex_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2507]
+    (const void *)&gInstructions[2510]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = 
@@ -14271,28 +14279,47 @@ const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg =
     }
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_61_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[975]
 };
 
+const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[976]
+};
+
+const ND_TABLE_DSIZE gRootTable_root_61_dsize = 
+{
+    ND_ILUT_DSIZE,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_61_ds16_leaf,
+        /* 02 */ (const void *)&gRootTable_root_61_ds32_leaf,
+        /* 03 */ NULL,
+        /* 04 */ NULL,
+        /* 05 */ NULL,
+    }
+};
+
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[977]
+    (const void *)&gInstructions[978]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[978]
+    (const void *)&gInstructions[979]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[979]
+    (const void *)&gInstructions[980]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9d_dsize = 
@@ -14311,109 +14338,128 @@ const ND_TABLE_DSIZE gRootTable_root_9d_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1078]
+    (const void *)&gInstructions[1079]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1079]
+    (const void *)&gInstructions[1080]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1080]
+    (const void *)&gInstructions[1081]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1081]
+    (const void *)&gInstructions[1082]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1082]
+    (const void *)&gInstructions[1083]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1083]
+    (const void *)&gInstructions[1084]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1084]
+    (const void *)&gInstructions[1085]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1085]
+    (const void *)&gInstructions[1086]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1086]
+    (const void *)&gInstructions[1087]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1087]
+    (const void *)&gInstructions[1088]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1088]
+    (const void *)&gInstructions[1089]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1089]
+    (const void *)&gInstructions[1090]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1090]
+    (const void *)&gInstructions[1091]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1091]
+    (const void *)&gInstructions[1092]
 };
 
-const ND_TABLE_INSTRUCTION gRootTable_root_60_leaf = 
+const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1093]
+    (const void *)&gInstructions[1094]
+};
+
+const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[1095]
+};
+
+const ND_TABLE_DSIZE gRootTable_root_60_dsize = 
+{
+    ND_ILUT_DSIZE,
+    { 
+        /* 00 */ NULL,
+        /* 01 */ (const void *)&gRootTable_root_60_ds16_leaf,
+        /* 02 */ (const void *)&gRootTable_root_60_ds32_leaf,
+        /* 03 */ NULL,
+        /* 04 */ NULL,
+        /* 05 */ NULL,
+    }
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1094]
+    (const void *)&gInstructions[1096]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1095]
+    (const void *)&gInstructions[1097]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1096]
+    (const void *)&gInstructions[1098]
 };
 
 const ND_TABLE_DSIZE gRootTable_root_9c_dsize = 
@@ -14432,49 +14478,49 @@ const ND_TABLE_DSIZE gRootTable_root_9c_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1100]
+    (const void *)&gInstructions[1102]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1108]
+    (const void *)&gInstructions[1110]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1136]
+    (const void *)&gInstructions[1138]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1142]
+    (const void *)&gInstructions[1144]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1161]
+    (const void *)&gInstructions[1163]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1168]
+    (const void *)&gInstructions[1170]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1221]
+    (const void *)&gInstructions[1223]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1230]
+    (const void *)&gInstructions[1232]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = 
@@ -14495,49 +14541,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1101]
+    (const void *)&gInstructions[1103]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1109]
+    (const void *)&gInstructions[1111]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1137]
+    (const void *)&gInstructions[1139]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1143]
+    (const void *)&gInstructions[1145]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1162]
+    (const void *)&gInstructions[1164]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1169]
+    (const void *)&gInstructions[1171]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1222]
+    (const void *)&gInstructions[1224]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1231]
+    (const void *)&gInstructions[1233]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = 
@@ -14558,49 +14604,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1102]
+    (const void *)&gInstructions[1104]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1110]
+    (const void *)&gInstructions[1112]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1138]
+    (const void *)&gInstructions[1140]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1144]
+    (const void *)&gInstructions[1146]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1163]
+    (const void *)&gInstructions[1165]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1170]
+    (const void *)&gInstructions[1172]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1223]
+    (const void *)&gInstructions[1225]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1232]
+    (const void *)&gInstructions[1234]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = 
@@ -14621,49 +14667,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1103]
+    (const void *)&gInstructions[1105]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1111]
+    (const void *)&gInstructions[1113]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1139]
+    (const void *)&gInstructions[1141]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1145]
+    (const void *)&gInstructions[1147]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1164]
+    (const void *)&gInstructions[1166]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1171]
+    (const void *)&gInstructions[1173]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1224]
+    (const void *)&gInstructions[1226]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1233]
+    (const void *)&gInstructions[1235]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = 
@@ -14684,49 +14730,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1104]
+    (const void *)&gInstructions[1106]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1112]
+    (const void *)&gInstructions[1114]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1140]
+    (const void *)&gInstructions[1142]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1146]
+    (const void *)&gInstructions[1148]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1165]
+    (const void *)&gInstructions[1167]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1172]
+    (const void *)&gInstructions[1174]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1225]
+    (const void *)&gInstructions[1227]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1234]
+    (const void *)&gInstructions[1236]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = 
@@ -14747,49 +14793,49 @@ const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1105]
+    (const void *)&gInstructions[1107]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1113]
+    (const void *)&gInstructions[1115]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1141]
+    (const void *)&gInstructions[1143]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1147]
+    (const void *)&gInstructions[1149]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1166]
+    (const void *)&gInstructions[1168]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1173]
+    (const void *)&gInstructions[1175]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1226]
+    (const void *)&gInstructions[1228]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1235]
+    (const void *)&gInstructions[1237]
 };
 
 const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = 
@@ -14810,85 +14856,85 @@ const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg =
 const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1130]
+    (const void *)&gInstructions[1132]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1131]
+    (const void *)&gInstructions[1133]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1132]
+    (const void *)&gInstructions[1134]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1133]
+    (const void *)&gInstructions[1135]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1160]
+    (const void *)&gInstructions[1162]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1167]
+    (const void *)&gInstructions[1169]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1176]
+    (const void *)&gInstructions[1178]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1177]
+    (const void *)&gInstructions[1179]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1178]
+    (const void *)&gInstructions[1180]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1179]
+    (const void *)&gInstructions[1181]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1180]
+    (const void *)&gInstructions[1182]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1181]
+    (const void *)&gInstructions[1183]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1186]
+    (const void *)&gInstructions[1188]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1187]
+    (const void *)&gInstructions[1189]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = 
@@ -14907,13 +14953,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1188]
+    (const void *)&gInstructions[1190]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1189]
+    (const void *)&gInstructions[1191]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = 
@@ -14932,13 +14978,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1190]
+    (const void *)&gInstructions[1192]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1191]
+    (const void *)&gInstructions[1193]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = 
@@ -14957,13 +15003,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1192]
+    (const void *)&gInstructions[1194]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1193]
+    (const void *)&gInstructions[1195]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = 
@@ -14995,31 +15041,31 @@ const ND_TABLE_DSIZE gRootTable_root_af_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1255]
+    (const void *)&gInstructions[1257]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1256]
+    (const void *)&gInstructions[1258]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1258]
+    (const void *)&gInstructions[1260]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1260]
+    (const void *)&gInstructions[1262]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1261]
+    (const void *)&gInstructions[1263]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = 
@@ -15038,13 +15084,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1262]
+    (const void *)&gInstructions[1264]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1263]
+    (const void *)&gInstructions[1265]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = 
@@ -15063,13 +15109,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1264]
+    (const void *)&gInstructions[1266]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1265]
+    (const void *)&gInstructions[1267]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = 
@@ -15088,13 +15134,13 @@ const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary =
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1266]
+    (const void *)&gInstructions[1268]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1267]
+    (const void *)&gInstructions[1269]
 };
 
 const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = 
@@ -15126,163 +15172,163 @@ const ND_TABLE_DSIZE gRootTable_root_ab_dsize =
 const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1271]
+    (const void *)&gInstructions[1273]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1272]
+    (const void *)&gInstructions[1274]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1273]
+    (const void *)&gInstructions[1275]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1274]
+    (const void *)&gInstructions[1276]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1275]
+    (const void *)&gInstructions[1277]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1276]
+    (const void *)&gInstructions[1278]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1299]
+    (const void *)&gInstructions[1301]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1300]
+    (const void *)&gInstructions[1302]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1301]
+    (const void *)&gInstructions[1303]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1302]
+    (const void *)&gInstructions[1304]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2489]
+    (const void *)&gInstructions[2492]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2505]
+    (const void *)&gInstructions[2508]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2506]
+    (const void *)&gInstructions[2509]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2508]
+    (const void *)&gInstructions[2511]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2509]
+    (const void *)&gInstructions[2512]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2510]
+    (const void *)&gInstructions[2513]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2511]
+    (const void *)&gInstructions[2514]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2512]
+    (const void *)&gInstructions[2515]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2513]
+    (const void *)&gInstructions[2516]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2514]
+    (const void *)&gInstructions[2517]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2522]
+    (const void *)&gInstructions[2525]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2523]
+    (const void *)&gInstructions[2526]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2524]
+    (const void *)&gInstructions[2527]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2525]
+    (const void *)&gInstructions[2528]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2526]
+    (const void *)&gInstructions[2529]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2527]
+    (const void *)&gInstructions[2530]
 };
 
 const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2528]
+    (const void *)&gInstructions[2531]
 };
 
 const ND_TABLE_OPCODE gRootTable_root_opcode = 
@@ -15385,8 +15431,8 @@ const ND_TABLE_OPCODE gRootTable_root_opcode =
         /* 5d */ (const void *)&gRootTable_root_5d_leaf,
         /* 5e */ (const void *)&gRootTable_root_5e_leaf,
         /* 5f */ (const void *)&gRootTable_root_5f_leaf,
-        /* 60 */ (const void *)&gRootTable_root_60_leaf,
-        /* 61 */ (const void *)&gRootTable_root_61_leaf,
+        /* 60 */ (const void *)&gRootTable_root_60_dsize,
+        /* 61 */ (const void *)&gRootTable_root_61_dsize,
         /* 62 */ (const void *)&gRootTable_root_62_modrmmod,
         /* 63 */ (const void *)&gRootTable_root_63_auxiliary,
         /* 64 */ NULL,
diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h
index 0fd4377..0784764 100644
--- a/bddisasm/include/table_vex.h
+++ b/bddisasm/include/table_vex.h
@@ -49,7 +49,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1174]
+    (const void *)&gInstructions[1176]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = 
@@ -66,7 +66,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1229]
+    (const void *)&gInstructions[1231]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = 
@@ -83,7 +83,7 @@ const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1238]
+    (const void *)&gInstructions[1240]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = 
@@ -250,7 +250,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[555]
+    (const void *)&gInstructions[557]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = 
@@ -291,7 +291,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1309]
+    (const void *)&gInstructions[1311]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = 
@@ -356,7 +356,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1270]
+    (const void *)&gInstructions[1272]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = 
@@ -406,7 +406,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1311]
+    (const void *)&gInstructions[1313]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = 
@@ -495,7 +495,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1294]
+    (const void *)&gInstructions[1296]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = 
@@ -541,7 +541,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1295]
+    (const void *)&gInstructions[1297]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = 
@@ -576,7 +576,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1296]
+    (const void *)&gInstructions[1298]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = 
@@ -611,7 +611,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1297]
+    (const void *)&gInstructions[1299]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = 
@@ -646,7 +646,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1298]
+    (const void *)&gInstructions[1300]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = 
@@ -692,7 +692,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1307]
+    (const void *)&gInstructions[1309]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = 
@@ -727,7 +727,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1308]
+    (const void *)&gInstructions[1310]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = 
@@ -762,7 +762,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1310]
+    (const void *)&gInstructions[1312]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = 
@@ -808,7 +808,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1342]
+    (const void *)&gInstructions[1344]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = 
@@ -825,7 +825,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1344]
+    (const void *)&gInstructions[1346]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = 
@@ -842,7 +842,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1346]
+    (const void *)&gInstructions[1348]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = 
@@ -859,7 +859,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1348]
+    (const void *)&gInstructions[1350]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = 
@@ -876,7 +876,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1349]
+    (const void *)&gInstructions[1351]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = 
@@ -904,7 +904,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1367]
+    (const void *)&gInstructions[1369]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = 
@@ -950,7 +950,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1373]
+    (const void *)&gInstructions[1375]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = 
@@ -996,7 +996,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1380]
+    (const void *)&gInstructions[1382]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = 
@@ -1022,7 +1022,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1382]
+    (const void *)&gInstructions[1384]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = 
@@ -1048,7 +1048,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1413]
+    (const void *)&gInstructions[1415]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = 
@@ -1063,7 +1063,7 @@ const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1414]
+    (const void *)&gInstructions[1416]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = 
@@ -1100,13 +1100,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1503]
+    (const void *)&gInstructions[1505]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1505]
+    (const void *)&gInstructions[1507]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = 
@@ -1132,13 +1132,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1507]
+    (const void *)&gInstructions[1509]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1509]
+    (const void *)&gInstructions[1511]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = 
@@ -1164,13 +1164,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1511]
+    (const void *)&gInstructions[1513]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1513]
+    (const void *)&gInstructions[1515]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = 
@@ -1193,35 +1193,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1515]
+    (const void *)&gInstructions[1517]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1517]
+    (const void *)&gInstructions[1519]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_a9_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_a9_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_a9_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_a9_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_a9_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_a9_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_a9_01_01_leaf,
     }
 };
 
@@ -1230,7 +1219,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_a9_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_a9_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -1239,13 +1228,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1519]
+    (const void *)&gInstructions[1521]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1521]
+    (const void *)&gInstructions[1523]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = 
@@ -1268,35 +1257,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1523]
+    (const void *)&gInstructions[1525]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1525]
+    (const void *)&gInstructions[1527]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_b9_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_b9_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_b9_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_b9_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_b9_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_b9_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_b9_01_01_leaf,
     }
 };
 
@@ -1305,7 +1283,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_b9_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_b9_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -1314,13 +1292,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1535]
+    (const void *)&gInstructions[1537]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1537]
+    (const void *)&gInstructions[1539]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = 
@@ -1346,13 +1324,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_96_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1539]
+    (const void *)&gInstructions[1541]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1541]
+    (const void *)&gInstructions[1543]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = 
@@ -1378,13 +1356,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1543]
+    (const void *)&gInstructions[1545]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1545]
+    (const void *)&gInstructions[1547]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = 
@@ -1410,13 +1388,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1551]
+    (const void *)&gInstructions[1553]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1553]
+    (const void *)&gInstructions[1555]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = 
@@ -1442,13 +1420,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1555]
+    (const void *)&gInstructions[1557]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1557]
+    (const void *)&gInstructions[1559]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = 
@@ -1474,13 +1452,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1559]
+    (const void *)&gInstructions[1561]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1561]
+    (const void *)&gInstructions[1563]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = 
@@ -1503,35 +1481,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1563]
+    (const void *)&gInstructions[1565]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1565]
+    (const void *)&gInstructions[1567]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_ab_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_ab_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_ab_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_ab_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_ab_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_ab_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_ab_01_01_leaf,
     }
 };
 
@@ -1540,7 +1507,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_ab_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_ab_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -1549,13 +1516,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1567]
+    (const void *)&gInstructions[1569]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1569]
+    (const void *)&gInstructions[1571]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = 
@@ -1578,35 +1545,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1571]
+    (const void *)&gInstructions[1573]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1573]
+    (const void *)&gInstructions[1575]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_bb_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_bb_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_bb_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_bb_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_bb_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_bb_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_bb_01_01_leaf,
     }
 };
 
@@ -1615,7 +1571,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_bb_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_bb_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -1624,13 +1580,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1575]
+    (const void *)&gInstructions[1577]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1577]
+    (const void *)&gInstructions[1579]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = 
@@ -1656,13 +1612,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_97_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1579]
+    (const void *)&gInstructions[1581]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1581]
+    (const void *)&gInstructions[1583]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = 
@@ -1688,13 +1644,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1583]
+    (const void *)&gInstructions[1585]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1585]
+    (const void *)&gInstructions[1587]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = 
@@ -1720,13 +1676,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1599]
+    (const void *)&gInstructions[1601]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1601]
+    (const void *)&gInstructions[1603]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = 
@@ -1752,13 +1708,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1603]
+    (const void *)&gInstructions[1605]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1605]
+    (const void *)&gInstructions[1607]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = 
@@ -1784,13 +1740,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1607]
+    (const void *)&gInstructions[1609]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1609]
+    (const void *)&gInstructions[1611]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = 
@@ -1813,35 +1769,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1611]
+    (const void *)&gInstructions[1613]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1613]
+    (const void *)&gInstructions[1615]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_ad_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_ad_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_ad_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_ad_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_ad_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_ad_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_ad_01_01_leaf,
     }
 };
 
@@ -1850,7 +1795,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_ad_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_ad_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -1859,13 +1804,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1615]
+    (const void *)&gInstructions[1617]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1617]
+    (const void *)&gInstructions[1619]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = 
@@ -1888,35 +1833,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1619]
+    (const void *)&gInstructions[1621]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1621]
+    (const void *)&gInstructions[1623]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_bd_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_bd_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_bd_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_bd_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_bd_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_bd_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_bd_01_01_leaf,
     }
 };
 
@@ -1925,7 +1859,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_bd_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_bd_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -1934,13 +1868,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1631]
+    (const void *)&gInstructions[1633]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1633]
+    (const void *)&gInstructions[1635]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = 
@@ -1963,35 +1897,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1635]
+    (const void *)&gInstructions[1637]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1637]
+    (const void *)&gInstructions[1639]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_9f_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_9f_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_9f_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_9f_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_9f_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_9f_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_9f_01_01_leaf,
     }
 };
 
@@ -2000,7 +1923,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_9f_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_9f_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -2009,13 +1932,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1639]
+    (const void *)&gInstructions[1641]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1641]
+    (const void *)&gInstructions[1643]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = 
@@ -2038,35 +1961,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1643]
+    (const void *)&gInstructions[1645]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1645]
+    (const void *)&gInstructions[1647]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_af_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_af_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_af_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_af_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_af_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_af_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_af_01_01_leaf,
     }
 };
 
@@ -2075,7 +1987,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_af_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_af_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -2084,13 +1996,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_af_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1647]
+    (const void *)&gInstructions[1649]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1649]
+    (const void *)&gInstructions[1651]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = 
@@ -2113,35 +2025,24 @@ const ND_TABLE_VEX_PP gVexTable_root_02_be_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1651]
+    (const void *)&gInstructions[1653]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1653]
+    (const void *)&gInstructions[1655]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_02_bf_01_00_w = 
+const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_02_bf_01_00_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_02_bf_01_00_01_leaf,
-    }
-};
-
-const ND_TABLE_VEX_L gVexTable_root_02_bf_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_02_bf_01_00_w,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_02_bf_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_02_bf_01_01_leaf,
     }
 };
 
@@ -2150,7 +2051,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_02_bf_01_l,
+        /* 01 */ (const void *)&gVexTable_root_02_bf_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -2159,13 +2060,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1671]
+    (const void *)&gInstructions[1673]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1673]
+    (const void *)&gInstructions[1675]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = 
@@ -2200,13 +2101,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1683]
+    (const void *)&gInstructions[1685]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1685]
+    (const void *)&gInstructions[1687]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = 
@@ -2241,7 +2142,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1699]
+    (const void *)&gInstructions[1701]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = 
@@ -2267,7 +2168,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1721]
+    (const void *)&gInstructions[1723]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = 
@@ -2302,7 +2203,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1722]
+    (const void *)&gInstructions[1724]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = 
@@ -2337,7 +2238,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1723]
+    (const void *)&gInstructions[1725]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = 
@@ -2372,7 +2273,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1724]
+    (const void *)&gInstructions[1726]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = 
@@ -2407,7 +2308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1807]
+    (const void *)&gInstructions[1810]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = 
@@ -2433,7 +2334,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1875]
+    (const void *)&gInstructions[1878]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = 
@@ -2450,7 +2351,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1877]
+    (const void *)&gInstructions[1880]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = 
@@ -2467,7 +2368,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1880]
+    (const void *)&gInstructions[1883]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = 
@@ -2484,7 +2385,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1886]
+    (const void *)&gInstructions[1889]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = 
@@ -2501,7 +2402,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1926]
+    (const void *)&gInstructions[1929]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = 
@@ -2527,7 +2428,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1929]
+    (const void *)&gInstructions[1932]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = 
@@ -2553,7 +2454,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1934]
+    (const void *)&gInstructions[1937]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = 
@@ -2579,7 +2480,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1937]
+    (const void *)&gInstructions[1940]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = 
@@ -2605,7 +2506,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1949]
+    (const void *)&gInstructions[1952]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = 
@@ -2622,7 +2523,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1959]
+    (const void *)&gInstructions[1962]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = 
@@ -2639,7 +2540,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_37_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1992]
+    (const void *)&gInstructions[1995]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = 
@@ -2676,7 +2577,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_36_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2001]
+    (const void *)&gInstructions[2008]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = 
@@ -2702,7 +2603,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2005]
+    (const void *)&gInstructions[2012]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = 
@@ -2728,7 +2629,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2017]
+    (const void *)&gInstructions[2020]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = 
@@ -2765,13 +2666,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2047]
+    (const void *)&gInstructions[2050]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2049]
+    (const void *)&gInstructions[2052]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = 
@@ -2806,13 +2707,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2051]
+    (const void *)&gInstructions[2054]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2053]
+    (const void *)&gInstructions[2056]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = 
@@ -2847,7 +2748,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2057]
+    (const void *)&gInstructions[2060]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = 
@@ -2864,7 +2765,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2059]
+    (const void *)&gInstructions[2062]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = 
@@ -2881,7 +2782,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_03_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2066]
+    (const void *)&gInstructions[2069]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = 
@@ -2898,7 +2799,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2069]
+    (const void *)&gInstructions[2072]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = 
@@ -2926,7 +2827,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2071]
+    (const void *)&gInstructions[2074]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = 
@@ -2943,7 +2844,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2073]
+    (const void *)&gInstructions[2076]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = 
@@ -2960,7 +2861,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_07_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2074]
+    (const void *)&gInstructions[2077]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = 
@@ -2977,7 +2878,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_05_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2105]
+    (const void *)&gInstructions[2108]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = 
@@ -2994,13 +2895,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_04_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2108]
+    (const void *)&gInstructions[2111]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2110]
+    (const void *)&gInstructions[2113]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = 
@@ -3035,13 +2936,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2109]
+    (const void *)&gInstructions[2112]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2111]
+    (const void *)&gInstructions[2114]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = 
@@ -3076,7 +2977,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2113]
+    (const void *)&gInstructions[2116]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = 
@@ -3093,7 +2994,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2115]
+    (const void *)&gInstructions[2118]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = 
@@ -3110,7 +3011,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2122]
+    (const void *)&gInstructions[2125]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = 
@@ -3127,7 +3028,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2125]
+    (const void *)&gInstructions[2128]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = 
@@ -3144,7 +3045,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2127]
+    (const void *)&gInstructions[2130]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = 
@@ -3161,7 +3062,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2129]
+    (const void *)&gInstructions[2132]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = 
@@ -3178,7 +3079,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2136]
+    (const void *)&gInstructions[2139]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = 
@@ -3195,7 +3096,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2139]
+    (const void *)&gInstructions[2142]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = 
@@ -3212,13 +3113,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2160]
+    (const void *)&gInstructions[2163]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2161]
+    (const void *)&gInstructions[2164]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = 
@@ -3246,13 +3147,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2163]
+    (const void *)&gInstructions[2166]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2164]
+    (const void *)&gInstructions[2167]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = 
@@ -3280,13 +3181,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2166]
+    (const void *)&gInstructions[2169]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2167]
+    (const void *)&gInstructions[2170]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = 
@@ -3314,13 +3215,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2169]
+    (const void *)&gInstructions[2172]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2170]
+    (const void *)&gInstructions[2173]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = 
@@ -3348,13 +3249,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_25_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2172]
+    (const void *)&gInstructions[2175]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2173]
+    (const void *)&gInstructions[2176]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = 
@@ -3382,13 +3283,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_23_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2175]
+    (const void *)&gInstructions[2178]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2176]
+    (const void *)&gInstructions[2179]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = 
@@ -3416,13 +3317,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_24_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2186]
+    (const void *)&gInstructions[2189]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2187]
+    (const void *)&gInstructions[2190]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = 
@@ -3450,13 +3351,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2189]
+    (const void *)&gInstructions[2192]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2190]
+    (const void *)&gInstructions[2193]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = 
@@ -3484,13 +3385,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2192]
+    (const void *)&gInstructions[2195]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2193]
+    (const void *)&gInstructions[2196]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = 
@@ -3518,13 +3419,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2195]
+    (const void *)&gInstructions[2198]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2196]
+    (const void *)&gInstructions[2199]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = 
@@ -3552,13 +3453,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_35_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2198]
+    (const void *)&gInstructions[2201]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2199]
+    (const void *)&gInstructions[2202]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = 
@@ -3586,13 +3487,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2201]
+    (const void *)&gInstructions[2204]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2202]
+    (const void *)&gInstructions[2205]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = 
@@ -3620,7 +3521,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_34_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2204]
+    (const void *)&gInstructions[2207]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = 
@@ -3637,7 +3538,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2206]
+    (const void *)&gInstructions[2209]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = 
@@ -3654,7 +3555,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2212]
+    (const void *)&gInstructions[2215]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = 
@@ -3671,7 +3572,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2283]
+    (const void *)&gInstructions[2286]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = 
@@ -3688,7 +3589,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_00_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2291]
+    (const void *)&gInstructions[2294]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = 
@@ -3705,7 +3606,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2292]
+    (const void *)&gInstructions[2295]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = 
@@ -3722,7 +3623,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2293]
+    (const void *)&gInstructions[2296]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = 
@@ -3739,13 +3640,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2305]
+    (const void *)&gInstructions[2308]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2307]
+    (const void *)&gInstructions[2310]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = 
@@ -3771,7 +3672,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2320]
+    (const void *)&gInstructions[2323]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = 
@@ -3797,13 +3698,13 @@ const ND_TABLE_VEX_PP gVexTable_root_02_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2338]
+    (const void *)&gInstructions[2341]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2340]
+    (const void *)&gInstructions[2343]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = 
@@ -3829,7 +3730,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2364]
+    (const void *)&gInstructions[2367]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = 
@@ -3846,7 +3747,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2469]
+    (const void *)&gInstructions[2472]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = 
@@ -3872,7 +3773,7 @@ const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2470]
+    (const void *)&gInstructions[2473]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = 
@@ -4182,7 +4083,7 @@ const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1249]
+    (const void *)&gInstructions[1251]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = 
@@ -4263,13 +4164,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1719]
+    (const void *)&gInstructions[1721]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2460]
+    (const void *)&gInstructions[2463]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = 
@@ -4310,13 +4211,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[480]
+    (const void *)&gInstructions[482]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[481]
+    (const void *)&gInstructions[483]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = 
@@ -4351,13 +4252,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[482]
+    (const void *)&gInstructions[484]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[483]
+    (const void *)&gInstructions[485]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = 
@@ -4403,13 +4304,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[484]
+    (const void *)&gInstructions[486]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[485]
+    (const void *)&gInstructions[487]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = 
@@ -4444,13 +4345,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[490]
+    (const void *)&gInstructions[492]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[491]
+    (const void *)&gInstructions[493]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = 
@@ -4496,13 +4397,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[486]
+    (const void *)&gInstructions[488]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[487]
+    (const void *)&gInstructions[489]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = 
@@ -4537,13 +4438,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[488]
+    (const void *)&gInstructions[490]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[489]
+    (const void *)&gInstructions[491]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = 
@@ -4589,7 +4490,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[492]
+    (const void *)&gInstructions[494]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = 
@@ -4635,7 +4536,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[493]
+    (const void *)&gInstructions[495]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = 
@@ -4681,13 +4582,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_49_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[494]
+    (const void *)&gInstructions[496]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[499]
+    (const void *)&gInstructions[501]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = 
@@ -4713,13 +4614,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[495]
+    (const void *)&gInstructions[497]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[500]
+    (const void *)&gInstructions[502]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = 
@@ -4754,13 +4655,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[504]
+    (const void *)&gInstructions[506]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[509]
+    (const void *)&gInstructions[511]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = 
@@ -4786,13 +4687,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[505]
+    (const void *)&gInstructions[507]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[510]
+    (const void *)&gInstructions[512]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = 
@@ -4838,13 +4739,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_90_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[496]
+    (const void *)&gInstructions[498]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[501]
+    (const void *)&gInstructions[503]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = 
@@ -4879,13 +4780,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[506]
+    (const void *)&gInstructions[508]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[511]
+    (const void *)&gInstructions[513]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = 
@@ -4931,7 +4832,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_91_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[497]
+    (const void *)&gInstructions[499]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = 
@@ -4966,13 +4867,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[502]
+    (const void *)&gInstructions[504]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[507]
+    (const void *)&gInstructions[509]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = 
@@ -5007,7 +4908,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[512]
+    (const void *)&gInstructions[514]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = 
@@ -5053,7 +4954,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_92_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[498]
+    (const void *)&gInstructions[500]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = 
@@ -5088,13 +4989,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[503]
+    (const void *)&gInstructions[505]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[508]
+    (const void *)&gInstructions[510]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = 
@@ -5129,7 +5030,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[513]
+    (const void *)&gInstructions[515]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = 
@@ -5175,13 +5076,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_93_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[514]
+    (const void *)&gInstructions[516]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[515]
+    (const void *)&gInstructions[517]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = 
@@ -5216,13 +5117,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[516]
+    (const void *)&gInstructions[518]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[517]
+    (const void *)&gInstructions[519]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = 
@@ -5268,13 +5169,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[518]
+    (const void *)&gInstructions[520]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[519]
+    (const void *)&gInstructions[521]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = 
@@ -5309,13 +5210,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[520]
+    (const void *)&gInstructions[522]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[525]
+    (const void *)&gInstructions[527]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = 
@@ -5361,13 +5262,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_45_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[521]
+    (const void *)&gInstructions[523]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[522]
+    (const void *)&gInstructions[524]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = 
@@ -5402,13 +5303,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[523]
+    (const void *)&gInstructions[525]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[524]
+    (const void *)&gInstructions[526]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = 
@@ -5454,13 +5355,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_98_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[534]
+    (const void *)&gInstructions[536]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[535]
+    (const void *)&gInstructions[537]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = 
@@ -5495,13 +5396,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[536]
+    (const void *)&gInstructions[538]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[537]
+    (const void *)&gInstructions[539]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = 
@@ -5547,7 +5448,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_99_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[538]
+    (const void *)&gInstructions[540]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = 
@@ -5582,13 +5483,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[539]
+    (const void *)&gInstructions[541]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[540]
+    (const void *)&gInstructions[542]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = 
@@ -5634,13 +5535,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[541]
+    (const void *)&gInstructions[543]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[542]
+    (const void *)&gInstructions[544]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = 
@@ -5675,13 +5576,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[543]
+    (const void *)&gInstructions[545]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[544]
+    (const void *)&gInstructions[546]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = 
@@ -5727,13 +5628,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_46_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[545]
+    (const void *)&gInstructions[547]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[546]
+    (const void *)&gInstructions[548]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = 
@@ -5768,13 +5669,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[547]
+    (const void *)&gInstructions[549]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[548]
+    (const void *)&gInstructions[550]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = 
@@ -5820,25 +5721,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_47_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1332]
+    (const void *)&gInstructions[1334]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1334]
+    (const void *)&gInstructions[1336]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1336]
+    (const void *)&gInstructions[1338]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1338]
+    (const void *)&gInstructions[1340]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = 
@@ -5855,13 +5756,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_58_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1339]
+    (const void *)&gInstructions[1341]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1340]
+    (const void *)&gInstructions[1342]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = 
@@ -5878,13 +5779,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1354]
+    (const void *)&gInstructions[1356]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1356]
+    (const void *)&gInstructions[1358]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = 
@@ -5901,13 +5802,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_55_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1358]
+    (const void *)&gInstructions[1360]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1360]
+    (const void *)&gInstructions[1362]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = 
@@ -5924,25 +5825,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_54_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1384]
+    (const void *)&gInstructions[1386]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1387]
+    (const void *)&gInstructions[1388]
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1389]
+    (const void *)&gInstructions[1390]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1390]
+    (const void *)&gInstructions[1392]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = 
@@ -5959,13 +5860,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1392]
+    (const void *)&gInstructions[1394]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1394]
+    (const void *)&gInstructions[1396]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = 
@@ -5982,13 +5883,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1398]
+    (const void *)&gInstructions[1400]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1399]
+    (const void *)&gInstructions[1401]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = 
@@ -6005,13 +5906,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1405]
+    (const void *)&gInstructions[1407]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1444]
+    (const void *)&gInstructions[1446]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = 
@@ -6028,19 +5929,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1401]
+    (const void *)&gInstructions[1403]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1416]
+    (const void *)&gInstructions[1418]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1449]
+    (const void *)&gInstructions[1451]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = 
@@ -6057,13 +5958,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1407]
+    (const void *)&gInstructions[1409]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1408]
+    (const void *)&gInstructions[1410]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = 
@@ -6080,13 +5981,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1418]
+    (const void *)&gInstructions[1420]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1419]
+    (const void *)&gInstructions[1421]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = 
@@ -6103,13 +6004,13 @@ const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1431]
+    (const void *)&gInstructions[1433]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1439]
+    (const void *)&gInstructions[1441]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = 
@@ -6126,13 +6027,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1429]
+    (const void *)&gInstructions[1431]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1441]
+    (const void *)&gInstructions[1443]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = 
@@ -6149,13 +6050,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1435]
+    (const void *)&gInstructions[1437]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1437]
+    (const void *)&gInstructions[1439]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = 
@@ -6172,13 +6073,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1454]
+    (const void *)&gInstructions[1456]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1457]
+    (const void *)&gInstructions[1459]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = 
@@ -6195,25 +6096,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1468]
+    (const void *)&gInstructions[1470]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1470]
+    (const void *)&gInstructions[1472]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1472]
+    (const void *)&gInstructions[1474]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1474]
+    (const void *)&gInstructions[1476]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = 
@@ -6230,13 +6131,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1700]
+    (const void *)&gInstructions[1702]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1701]
+    (const void *)&gInstructions[1703]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = 
@@ -6253,13 +6154,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1702]
+    (const void *)&gInstructions[1704]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1703]
+    (const void *)&gInstructions[1705]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = 
@@ -6276,7 +6177,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1718]
+    (const void *)&gInstructions[1720]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = 
@@ -6302,7 +6203,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1720]
+    (const void *)&gInstructions[1722]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = 
@@ -6339,25 +6240,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1726]
+    (const void *)&gInstructions[1728]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1728]
+    (const void *)&gInstructions[1730]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1730]
+    (const void *)&gInstructions[1732]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1732]
+    (const void *)&gInstructions[1734]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = 
@@ -6374,25 +6275,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1739]
+    (const void *)&gInstructions[1741]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1741]
+    (const void *)&gInstructions[1743]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1743]
+    (const void *)&gInstructions[1745]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1745]
+    (const void *)&gInstructions[1747]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = 
@@ -6409,13 +6310,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1751]
+    (const void *)&gInstructions[1754]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1755]
+    (const void *)&gInstructions[1758]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = 
@@ -6432,13 +6333,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_28_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1752]
+    (const void *)&gInstructions[1755]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1756]
+    (const void *)&gInstructions[1759]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = 
@@ -6455,13 +6356,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_29_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1759]
+    (const void *)&gInstructions[1762]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1816]
+    (const void *)&gInstructions[1819]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_w = 
@@ -6498,13 +6399,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1760]
+    (const void *)&gInstructions[1763]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1817]
+    (const void *)&gInstructions[1820]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_w = 
@@ -6530,7 +6431,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1818]
+    (const void *)&gInstructions[1821]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = 
@@ -6558,13 +6459,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1764]
+    (const void *)&gInstructions[1767]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1765]
+    (const void *)&gInstructions[1768]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = 
@@ -6581,7 +6482,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_03_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1783]
+    (const void *)&gInstructions[1786]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = 
@@ -6598,7 +6499,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1800]
+    (const void *)&gInstructions[1803]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = 
@@ -6624,7 +6525,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1796]
+    (const void *)&gInstructions[1799]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = 
@@ -6650,7 +6551,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1831]
+    (const void *)&gInstructions[1834]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = 
@@ -6667,13 +6568,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_12_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1766]
+    (const void *)&gInstructions[1769]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1772]
+    (const void *)&gInstructions[1775]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = 
@@ -6690,13 +6591,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1767]
+    (const void *)&gInstructions[1770]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1773]
+    (const void *)&gInstructions[1776]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = 
@@ -6713,7 +6614,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1786]
+    (const void *)&gInstructions[1789]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = 
@@ -6739,7 +6640,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1790]
+    (const void *)&gInstructions[1793]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = 
@@ -6756,7 +6657,7 @@ const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1793]
+    (const void *)&gInstructions[1796]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = 
@@ -6782,7 +6683,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1829]
+    (const void *)&gInstructions[1832]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = 
@@ -6799,7 +6700,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_16_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1787]
+    (const void *)&gInstructions[1790]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = 
@@ -6825,7 +6726,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1791]
+    (const void *)&gInstructions[1794]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = 
@@ -6862,7 +6763,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1797]
+    (const void *)&gInstructions[1800]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = 
@@ -6888,7 +6789,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1801]
+    (const void *)&gInstructions[1804]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = 
@@ -6925,7 +6826,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_13_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1802]
+    (const void *)&gInstructions[1805]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = 
@@ -6940,7 +6841,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1803]
+    (const void *)&gInstructions[1806]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = 
@@ -6966,7 +6867,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_50_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1805]
+    (const void *)&gInstructions[1808]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = 
@@ -6992,7 +6893,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1809]
+    (const void *)&gInstructions[1812]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = 
@@ -7007,7 +6908,7 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1811]
+    (const void *)&gInstructions[1814]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = 
@@ -7033,7 +6934,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1819]
+    (const void *)&gInstructions[1822]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = 
@@ -7061,13 +6962,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1824]
+    (const void *)&gInstructions[1827]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1825]
+    (const void *)&gInstructions[1828]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = 
@@ -7082,13 +6983,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1836]
+    (const void *)&gInstructions[1839]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1837]
+    (const void *)&gInstructions[1840]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = 
@@ -7103,13 +7004,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1842]
+    (const void *)&gInstructions[1845]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1846]
+    (const void *)&gInstructions[1849]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = 
@@ -7126,13 +7027,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_10_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1826]
+    (const void *)&gInstructions[1829]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1827]
+    (const void *)&gInstructions[1830]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = 
@@ -7147,13 +7048,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1838]
+    (const void *)&gInstructions[1841]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1839]
+    (const void *)&gInstructions[1842]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = 
@@ -7168,13 +7069,13 @@ const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1843]
+    (const void *)&gInstructions[1846]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1847]
+    (const void *)&gInstructions[1850]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = 
@@ -7191,25 +7092,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_11_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1856]
+    (const void *)&gInstructions[1859]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1858]
+    (const void *)&gInstructions[1861]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1860]
+    (const void *)&gInstructions[1863]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1862]
+    (const void *)&gInstructions[1865]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = 
@@ -7226,13 +7127,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_59_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1867]
+    (const void *)&gInstructions[1870]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1869]
+    (const void *)&gInstructions[1872]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = 
@@ -7249,7 +7150,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_56_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1882]
+    (const void *)&gInstructions[1885]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = 
@@ -7266,7 +7167,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1884]
+    (const void *)&gInstructions[1887]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = 
@@ -7283,7 +7184,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1888]
+    (const void *)&gInstructions[1891]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = 
@@ -7300,7 +7201,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_67_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1890]
+    (const void *)&gInstructions[1893]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = 
@@ -7317,7 +7218,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1892]
+    (const void *)&gInstructions[1895]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = 
@@ -7334,7 +7235,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1894]
+    (const void *)&gInstructions[1897]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = 
@@ -7351,7 +7252,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1896]
+    (const void *)&gInstructions[1899]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = 
@@ -7368,7 +7269,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1898]
+    (const void *)&gInstructions[1901]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = 
@@ -7385,7 +7286,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1900]
+    (const void *)&gInstructions[1903]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = 
@@ -7402,7 +7303,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1902]
+    (const void *)&gInstructions[1905]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = 
@@ -7419,7 +7320,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1904]
+    (const void *)&gInstructions[1907]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = 
@@ -7436,7 +7337,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1907]
+    (const void *)&gInstructions[1910]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = 
@@ -7453,7 +7354,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_db_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1909]
+    (const void *)&gInstructions[1912]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = 
@@ -7470,7 +7371,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1914]
+    (const void *)&gInstructions[1917]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = 
@@ -7487,7 +7388,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1916]
+    (const void *)&gInstructions[1919]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = 
@@ -7504,7 +7405,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1945]
+    (const void *)&gInstructions[1948]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = 
@@ -7521,7 +7422,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_74_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1947]
+    (const void *)&gInstructions[1950]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = 
@@ -7538,7 +7439,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_76_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1951]
+    (const void *)&gInstructions[1954]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = 
@@ -7555,7 +7456,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_75_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1955]
+    (const void *)&gInstructions[1958]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = 
@@ -7572,7 +7473,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_64_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1957]
+    (const void *)&gInstructions[1960]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = 
@@ -7589,7 +7490,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_66_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1961]
+    (const void *)&gInstructions[1964]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = 
@@ -7603,26 +7504,17 @@ const ND_TABLE_VEX_PP gVexTable_root_01_65_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2043]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_01_c5_01_reg_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2046]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_w,
+        /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
@@ -7649,52 +7541,34 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2086]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_01_c4_01_mem_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2089]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_w,
+        /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2087]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_01_c4_01_reg_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2090]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_w,
+        /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
@@ -7724,7 +7598,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2107]
+    (const void *)&gInstructions[2110]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = 
@@ -7741,7 +7615,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2118]
+    (const void *)&gInstructions[2121]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = 
@@ -7758,7 +7632,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2120]
+    (const void *)&gInstructions[2123]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = 
@@ -7775,7 +7649,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_de_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2132]
+    (const void *)&gInstructions[2135]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = 
@@ -7792,7 +7666,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2134]
+    (const void *)&gInstructions[2137]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = 
@@ -7809,7 +7683,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_da_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2148]
+    (const void *)&gInstructions[2151]
 };
 
 const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = 
@@ -7835,7 +7709,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2208]
+    (const void *)&gInstructions[2211]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = 
@@ -7852,7 +7726,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2210]
+    (const void *)&gInstructions[2213]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = 
@@ -7869,7 +7743,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2215]
+    (const void *)&gInstructions[2218]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = 
@@ -7886,7 +7760,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2218]
+    (const void *)&gInstructions[2221]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = 
@@ -7903,7 +7777,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2223]
+    (const void *)&gInstructions[2226]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = 
@@ -7920,7 +7794,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2249]
+    (const void *)&gInstructions[2252]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = 
@@ -7937,19 +7811,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2286]
+    (const void *)&gInstructions[2289]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2288]
+    (const void *)&gInstructions[2291]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2290]
+    (const void *)&gInstructions[2293]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = 
@@ -7966,19 +7840,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_70_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2296]
+    (const void *)&gInstructions[2299]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2315]
+    (const void *)&gInstructions[2318]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2329]
+    (const void *)&gInstructions[2332]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = 
@@ -8019,7 +7893,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_72_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2297]
+    (const void *)&gInstructions[2300]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = 
@@ -8036,25 +7910,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2299]
+    (const void *)&gInstructions[2302]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2302]
+    (const void *)&gInstructions[2305]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2332]
+    (const void *)&gInstructions[2335]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2335]
+    (const void *)&gInstructions[2338]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = 
@@ -8095,7 +7969,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_73_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2303]
+    (const void *)&gInstructions[2306]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = 
@@ -8112,19 +7986,19 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2311]
+    (const void *)&gInstructions[2314]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2325]
+    (const void *)&gInstructions[2328]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2344]
+    (const void *)&gInstructions[2347]
 };
 
 const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = 
@@ -8165,7 +8039,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_71_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2312]
+    (const void *)&gInstructions[2315]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = 
@@ -8182,7 +8056,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2316]
+    (const void *)&gInstructions[2319]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = 
@@ -8199,7 +8073,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2326]
+    (const void *)&gInstructions[2329]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = 
@@ -8216,7 +8090,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2330]
+    (const void *)&gInstructions[2333]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = 
@@ -8233,7 +8107,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2336]
+    (const void *)&gInstructions[2339]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = 
@@ -8250,7 +8124,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2345]
+    (const void *)&gInstructions[2348]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = 
@@ -8267,7 +8141,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2347]
+    (const void *)&gInstructions[2350]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = 
@@ -8284,7 +8158,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2349]
+    (const void *)&gInstructions[2352]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = 
@@ -8301,7 +8175,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2351]
+    (const void *)&gInstructions[2354]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = 
@@ -8318,7 +8192,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2353]
+    (const void *)&gInstructions[2356]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = 
@@ -8335,7 +8209,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2355]
+    (const void *)&gInstructions[2358]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = 
@@ -8352,7 +8226,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2357]
+    (const void *)&gInstructions[2360]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = 
@@ -8369,7 +8243,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2359]
+    (const void *)&gInstructions[2362]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = 
@@ -8386,7 +8260,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2361]
+    (const void *)&gInstructions[2364]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = 
@@ -8403,7 +8277,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2374]
+    (const void *)&gInstructions[2377]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = 
@@ -8420,7 +8294,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2376]
+    (const void *)&gInstructions[2379]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = 
@@ -8437,7 +8311,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2378]
+    (const void *)&gInstructions[2381]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = 
@@ -8454,7 +8328,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2380]
+    (const void *)&gInstructions[2383]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = 
@@ -8471,7 +8345,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2382]
+    (const void *)&gInstructions[2385]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = 
@@ -8488,7 +8362,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2384]
+    (const void *)&gInstructions[2387]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = 
@@ -8505,7 +8379,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2386]
+    (const void *)&gInstructions[2389]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = 
@@ -8522,7 +8396,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2388]
+    (const void *)&gInstructions[2391]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = 
@@ -8539,7 +8413,7 @@ const ND_TABLE_VEX_PP gVexTable_root_01_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2389]
+    (const void *)&gInstructions[2392]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = 
@@ -8556,13 +8430,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2404]
+    (const void *)&gInstructions[2407]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2405]
+    (const void *)&gInstructions[2408]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = 
@@ -8579,13 +8453,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_53_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2426]
+    (const void *)&gInstructions[2429]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2427]
+    (const void *)&gInstructions[2430]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = 
@@ -8602,13 +8476,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_52_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2449]
+    (const void *)&gInstructions[2452]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2451]
+    (const void *)&gInstructions[2454]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = 
@@ -8625,25 +8499,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2453]
+    (const void *)&gInstructions[2456]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2455]
+    (const void *)&gInstructions[2458]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2457]
+    (const void *)&gInstructions[2460]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2459]
+    (const void *)&gInstructions[2462]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = 
@@ -8660,25 +8534,25 @@ const ND_TABLE_VEX_PP gVexTable_root_01_51_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2462]
+    (const void *)&gInstructions[2465]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2464]
+    (const void *)&gInstructions[2467]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2466]
+    (const void *)&gInstructions[2469]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2468]
+    (const void *)&gInstructions[2471]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = 
@@ -8695,13 +8569,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2472]
+    (const void *)&gInstructions[2475]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2474]
+    (const void *)&gInstructions[2477]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = 
@@ -8718,13 +8592,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2476]
+    (const void *)&gInstructions[2479]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2478]
+    (const void *)&gInstructions[2481]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = 
@@ -8741,13 +8615,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2480]
+    (const void *)&gInstructions[2483]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2482]
+    (const void *)&gInstructions[2485]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = 
@@ -8764,13 +8638,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2484]
+    (const void *)&gInstructions[2487]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2486]
+    (const void *)&gInstructions[2489]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = 
@@ -8787,13 +8661,13 @@ const ND_TABLE_VEX_PP gVexTable_root_01_57_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2487]
+    (const void *)&gInstructions[2490]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2488]
+    (const void *)&gInstructions[2491]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = 
@@ -9084,13 +8958,13 @@ const ND_TABLE_OPCODE gVexTable_root_01_opcode =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[526]
+    (const void *)&gInstructions[528]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[529]
+    (const void *)&gInstructions[531]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = 
@@ -9136,13 +9010,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_32_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[527]
+    (const void *)&gInstructions[529]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[528]
+    (const void *)&gInstructions[530]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = 
@@ -9188,13 +9062,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_33_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[530]
+    (const void *)&gInstructions[532]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[533]
+    (const void *)&gInstructions[535]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = 
@@ -9240,13 +9114,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_30_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[531]
+    (const void *)&gInstructions[533]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[532]
+    (const void *)&gInstructions[534]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = 
@@ -9292,7 +9166,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_31_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1148]
+    (const void *)&gInstructions[1150]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = 
@@ -9320,7 +9194,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1350]
+    (const void *)&gInstructions[1352]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = 
@@ -9348,7 +9222,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_df_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1363]
+    (const void *)&gInstructions[1365]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = 
@@ -9365,7 +9239,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1364]
+    (const void *)&gInstructions[1366]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = 
@@ -9382,7 +9256,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1365]
+    (const void *)&gInstructions[1367]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = 
@@ -9408,7 +9282,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1366]
+    (const void *)&gInstructions[1368]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = 
@@ -9434,7 +9308,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1421]
+    (const void *)&gInstructions[1423]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = 
@@ -9449,7 +9323,7 @@ const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1422]
+    (const void *)&gInstructions[1424]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = 
@@ -9486,7 +9360,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1476]
+    (const void *)&gInstructions[1478]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = 
@@ -9514,7 +9388,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_41_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1477]
+    (const void *)&gInstructions[1479]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = 
@@ -9531,7 +9405,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_40_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1484]
+    (const void *)&gInstructions[1486]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = 
@@ -9568,7 +9442,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_19_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1489]
+    (const void *)&gInstructions[1491]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = 
@@ -9605,7 +9479,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_39_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1496]
+    (const void *)&gInstructions[1498]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = 
@@ -9622,7 +9496,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1497]
+    (const void *)&gInstructions[1499]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = 
@@ -9659,13 +9533,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_17_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1526]
+    (const void *)&gInstructions[1528]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1527]
+    (const void *)&gInstructions[1529]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = 
@@ -9691,13 +9565,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_69_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1528]
+    (const void *)&gInstructions[1530]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1529]
+    (const void *)&gInstructions[1531]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = 
@@ -9723,13 +9597,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_68_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1530]
+    (const void *)&gInstructions[1532]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1531]
+    (const void *)&gInstructions[1533]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = 
@@ -9755,13 +9629,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1532]
+    (const void *)&gInstructions[1534]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1533]
+    (const void *)&gInstructions[1535]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = 
@@ -9787,13 +9661,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1546]
+    (const void *)&gInstructions[1548]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1547]
+    (const void *)&gInstructions[1549]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = 
@@ -9819,13 +9693,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1548]
+    (const void *)&gInstructions[1550]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1549]
+    (const void *)&gInstructions[1551]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = 
@@ -9851,13 +9725,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1586]
+    (const void *)&gInstructions[1588]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1587]
+    (const void *)&gInstructions[1589]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = 
@@ -9883,13 +9757,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1588]
+    (const void *)&gInstructions[1590]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1589]
+    (const void *)&gInstructions[1591]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = 
@@ -9915,13 +9789,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1590]
+    (const void *)&gInstructions[1592]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1591]
+    (const void *)&gInstructions[1593]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = 
@@ -9947,13 +9821,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1592]
+    (const void *)&gInstructions[1594]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1593]
+    (const void *)&gInstructions[1595]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = 
@@ -9979,13 +9853,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1594]
+    (const void *)&gInstructions[1596]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1595]
+    (const void *)&gInstructions[1597]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = 
@@ -10011,13 +9885,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1596]
+    (const void *)&gInstructions[1598]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1597]
+    (const void *)&gInstructions[1599]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = 
@@ -10043,13 +9917,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1622]
+    (const void *)&gInstructions[1624]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1623]
+    (const void *)&gInstructions[1625]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = 
@@ -10075,13 +9949,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_79_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1624]
+    (const void *)&gInstructions[1626]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1625]
+    (const void *)&gInstructions[1627]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = 
@@ -10107,13 +9981,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_78_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1626]
+    (const void *)&gInstructions[1628]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1627]
+    (const void *)&gInstructions[1629]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = 
@@ -10139,13 +10013,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1628]
+    (const void *)&gInstructions[1630]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1629]
+    (const void *)&gInstructions[1631]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = 
@@ -10171,13 +10045,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1654]
+    (const void *)&gInstructions[1656]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1655]
+    (const void *)&gInstructions[1657]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = 
@@ -10203,13 +10077,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1656]
+    (const void *)&gInstructions[1658]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1657]
+    (const void *)&gInstructions[1659]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = 
@@ -10235,13 +10109,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1658]
+    (const void *)&gInstructions[1660]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1659]
+    (const void *)&gInstructions[1661]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = 
@@ -10267,13 +10141,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1660]
+    (const void *)&gInstructions[1662]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1661]
+    (const void *)&gInstructions[1663]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = 
@@ -10299,7 +10173,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1695]
+    (const void *)&gInstructions[1697]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = 
@@ -10325,7 +10199,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1697]
+    (const void *)&gInstructions[1699]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = 
@@ -10351,7 +10225,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1704]
+    (const void *)&gInstructions[1706]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = 
@@ -10388,7 +10262,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_18_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1709]
+    (const void *)&gInstructions[1711]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = 
@@ -10425,7 +10299,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_38_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1716]
+    (const void *)&gInstructions[1718]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = 
@@ -10442,7 +10316,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1717]
+    (const void *)&gInstructions[1719]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = 
@@ -10479,7 +10353,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_21_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1848]
+    (const void *)&gInstructions[1851]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = 
@@ -10496,7 +10370,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_42_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1906]
+    (const void *)&gInstructions[1909]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = 
@@ -10513,7 +10387,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1917]
+    (const void *)&gInstructions[1920]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = 
@@ -10539,7 +10413,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_02_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1922]
+    (const void *)&gInstructions[1925]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = 
@@ -10565,7 +10439,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1923]
+    (const void *)&gInstructions[1926]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = 
@@ -10579,21 +10453,10 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1939]
-};
-
-const ND_TABLE_VEX_L gVexTable_root_03_44_01_l = 
-{
-    ND_ILUT_VEX_L,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_03_44_01_00_leaf,
-        /* 01 */ NULL,
-        /* 02 */ NULL,
-        /* 03 */ NULL,
-    }
+    (const void *)&gInstructions[1942]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = 
@@ -10601,7 +10464,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp =
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_03_44_01_l,
+        /* 01 */ (const void *)&gVexTable_root_03_44_01_leaf,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -10610,7 +10473,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_44_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1952]
+    (const void *)&gInstructions[1955]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = 
@@ -10638,7 +10501,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_61_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1953]
+    (const void *)&gInstructions[1956]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = 
@@ -10666,7 +10529,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_60_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1962]
+    (const void *)&gInstructions[1965]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = 
@@ -10694,7 +10557,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_63_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1963]
+    (const void *)&gInstructions[1966]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = 
@@ -10722,7 +10585,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_62_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1988]
+    (const void *)&gInstructions[1991]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = 
@@ -10759,7 +10622,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_06_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1989]
+    (const void *)&gInstructions[1992]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = 
@@ -10793,117 +10656,117 @@ const ND_TABLE_VEX_PP gVexTable_root_03_46_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
     (const void *)&gInstructions[2002]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2003]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_05_01_00_leaf,
-        /* 01 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_03_49_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_03_49_01_01_leaf,
     }
 };
 
-const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = 
+const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = 
 {
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_03_05_01_w,
+        /* 01 */ (const void *)&gVexTable_root_03_49_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2006]
+    (const void *)&gInstructions[2004]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = 
+{
+    ND_ILUT_INSTRUCTION,
+    (const void *)&gInstructions[2005]
+};
+
+const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_04_01_00_leaf,
-        /* 01 */ NULL,
+        /* 00 */ (const void *)&gVexTable_root_03_48_01_00_leaf,
+        /* 01 */ (const void *)&gVexTable_root_03_48_01_01_leaf,
     }
 };
 
-const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = 
+const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = 
 {
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_03_04_01_w,
+        /* 01 */ (const void *)&gVexTable_root_03_48_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = 
-{
-    ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2007]
-};
-
-const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2008]
+    (const void *)&gInstructions[2009]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = 
+const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_49_01_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_03_49_01_01_leaf,
+        /* 00 */ (const void *)&gVexTable_root_03_05_01_00_leaf,
+        /* 01 */ NULL,
     }
 };
 
-const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = 
+const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = 
 {
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_03_49_01_w,
+        /* 01 */ (const void *)&gVexTable_root_03_05_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = 
-{
-    ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2009]
-};
-
-const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2010]
+    (const void *)&gInstructions[2013]
 };
 
-const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = 
+const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = 
 {
     ND_ILUT_VEX_W,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_48_01_00_leaf,
-        /* 01 */ (const void *)&gVexTable_root_03_48_01_01_leaf,
+        /* 00 */ (const void *)&gVexTable_root_03_04_01_00_leaf,
+        /* 01 */ NULL,
     }
 };
 
-const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = 
+const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = 
 {
     ND_ILUT_VEX_PP,
     { 
         /* 00 */ NULL,
-        /* 01 */ (const void *)&gVexTable_root_03_48_01_w,
+        /* 01 */ (const void *)&gVexTable_root_03_04_01_w,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
@@ -10912,7 +10775,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_48_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2014]
+    (const void *)&gInstructions[2017]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = 
@@ -10949,7 +10812,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_01_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2020]
+    (const void *)&gInstructions[2023]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = 
@@ -10983,52 +10846,34 @@ const ND_TABLE_VEX_PP gVexTable_root_03_00_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2034]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_03_14_01_mem_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2037]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_w,
+        /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2035]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_03_14_01_reg_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2038]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_w,
+        /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
@@ -11058,13 +10903,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_14_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2037]
+    (const void *)&gInstructions[2040]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2039]
+    (const void *)&gInstructions[2042]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_16_01_00_w = 
@@ -11098,52 +10943,34 @@ const ND_TABLE_VEX_PP gVexTable_root_03_16_pp =
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2044]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_03_15_01_mem_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2047]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_w,
+        /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
     }
 };
 
-const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_00_leaf = 
+const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2045]
-};
-
-const ND_TABLE_VEX_W gVexTable_root_03_15_01_reg_00_w = 
-{
-    ND_ILUT_VEX_W,
-    { 
-        /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_00_leaf,
-        /* 01 */ NULL,
-    }
+    (const void *)&gInstructions[2048]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = 
 {
     ND_ILUT_VEX_L,
     { 
-        /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_w,
+        /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_leaf,
         /* 01 */ NULL,
         /* 02 */ NULL,
         /* 03 */ NULL,
@@ -11173,7 +11000,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_15_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2078]
+    (const void *)&gInstructions[2081]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = 
@@ -11190,7 +11017,7 @@ const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2079]
+    (const void *)&gInstructions[2082]
 };
 
 const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = 
@@ -11227,13 +11054,13 @@ const ND_TABLE_VEX_PP gVexTable_root_03_20_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2081]
+    (const void *)&gInstructions[2084]
 };
 
 const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2083]
+    (const void *)&gInstructions[2086]
 };
 
 const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_w = 
@@ -11270,7 +11097,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_22_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2414]
+    (const void *)&gInstructions[2417]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = 
@@ -11287,7 +11114,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_09_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2415]
+    (const void *)&gInstructions[2418]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = 
@@ -11304,7 +11131,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_08_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2416]
+    (const void *)&gInstructions[2419]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = 
@@ -11321,7 +11148,7 @@ const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp =
 const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2417]
+    (const void *)&gInstructions[2420]
 };
 
 const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = 
diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h
index 9d0901e..027565b 100644
--- a/bddisasm/include/table_xop.h
+++ b/bddisasm/include/table_xop.h
@@ -330,13 +330,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1293]
+    (const void *)&gInstructions[1295]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1315]
+    (const void *)&gInstructions[1317]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = 
@@ -384,13 +384,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[565]
+    (const void *)&gInstructions[567]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1245]
+    (const void *)&gInstructions[1247]
 };
 
 const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = 
@@ -420,127 +420,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1666]
+    (const void *)&gInstructions[1668]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1667]
+    (const void *)&gInstructions[1669]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1668]
+    (const void *)&gInstructions[1670]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1669]
+    (const void *)&gInstructions[1671]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2054]
+    (const void *)&gInstructions[2057]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2055]
+    (const void *)&gInstructions[2058]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2056]
+    (const void *)&gInstructions[2059]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2058]
+    (const void *)&gInstructions[2061]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2060]
+    (const void *)&gInstructions[2063]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2061]
+    (const void *)&gInstructions[2064]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2062]
+    (const void *)&gInstructions[2065]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2063]
+    (const void *)&gInstructions[2066]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2064]
+    (const void *)&gInstructions[2067]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2065]
+    (const void *)&gInstructions[2068]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2067]
+    (const void *)&gInstructions[2070]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2068]
+    (const void *)&gInstructions[2071]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2070]
+    (const void *)&gInstructions[2073]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2072]
+    (const void *)&gInstructions[2075]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2075]
+    (const void *)&gInstructions[2078]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2237]
+    (const void *)&gInstructions[2240]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2238]
+    (const void *)&gInstructions[2241]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_90_w = 
@@ -555,13 +555,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2240]
+    (const void *)&gInstructions[2243]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2241]
+    (const void *)&gInstructions[2244]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_92_w = 
@@ -576,13 +576,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2243]
+    (const void *)&gInstructions[2246]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2244]
+    (const void *)&gInstructions[2247]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_93_w = 
@@ -597,13 +597,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2246]
+    (const void *)&gInstructions[2249]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2247]
+    (const void *)&gInstructions[2250]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_91_w = 
@@ -618,13 +618,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2254]
+    (const void *)&gInstructions[2257]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2255]
+    (const void *)&gInstructions[2258]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_98_w = 
@@ -639,13 +639,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2256]
+    (const void *)&gInstructions[2259]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2257]
+    (const void *)&gInstructions[2260]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9a_w = 
@@ -660,13 +660,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2258]
+    (const void *)&gInstructions[2261]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2259]
+    (const void *)&gInstructions[2262]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_9b_w = 
@@ -681,13 +681,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2260]
+    (const void *)&gInstructions[2263]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2261]
+    (const void *)&gInstructions[2264]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_99_w = 
@@ -702,13 +702,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2262]
+    (const void *)&gInstructions[2265]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2263]
+    (const void *)&gInstructions[2266]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_94_w = 
@@ -720,16 +720,16 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
     }
 };
 
-const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = 
+const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2264]
+    (const void *)&gInstructions[2267]
 };
 
-const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = 
+const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2265]
+    (const void *)&gInstructions[2278]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_95_w = 
@@ -741,16 +741,16 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
     }
 };
 
-const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = 
+const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2266]
+    (const void *)&gInstructions[2268]
 };
 
-const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = 
+const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2267]
+    (const void *)&gInstructions[2269]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_96_w = 
@@ -765,13 +765,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2274]
+    (const void *)&gInstructions[2276]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2275]
+    (const void *)&gInstructions[2277]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_09_97_w = 
@@ -1049,13 +1049,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1940]
+    (const void *)&gInstructions[1943]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1941]
+    (const void *)&gInstructions[1944]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a2_w = 
@@ -1070,133 +1070,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1970]
+    (const void *)&gInstructions[1973]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1971]
+    (const void *)&gInstructions[1974]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1976]
+    (const void *)&gInstructions[1979]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1977]
+    (const void *)&gInstructions[1980]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1978]
+    (const void *)&gInstructions[1981]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1979]
+    (const void *)&gInstructions[1982]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1980]
+    (const void *)&gInstructions[1983]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[1981]
+    (const void *)&gInstructions[1984]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2090]
+    (const void *)&gInstructions[2093]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2091]
+    (const void *)&gInstructions[2094]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2092]
+    (const void *)&gInstructions[2095]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2093]
+    (const void *)&gInstructions[2096]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2094]
+    (const void *)&gInstructions[2097]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2095]
+    (const void *)&gInstructions[2098]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2096]
+    (const void *)&gInstructions[2099]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2097]
+    (const void *)&gInstructions[2100]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2098]
+    (const void *)&gInstructions[2101]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2099]
+    (const void *)&gInstructions[2102]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2100]
+    (const void *)&gInstructions[2103]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2101]
+    (const void *)&gInstructions[2104]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2226]
+    (const void *)&gInstructions[2229]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2227]
+    (const void *)&gInstructions[2230]
 };
 
 const ND_TABLE_VEX_W gXopTable_root_08_a3_w = 
@@ -1211,25 +1211,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2236]
+    (const void *)&gInstructions[2239]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2239]
+    (const void *)&gInstructions[2242]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2242]
+    (const void *)&gInstructions[2245]
 };
 
 const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = 
 {
     ND_ILUT_INSTRUCTION,
-    (const void *)&gInstructions[2245]
+    (const void *)&gInstructions[2248]
 };
 
 const ND_TABLE_OPCODE gXopTable_root_08_opcode = 
diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/tabledefs.h
index 6395a4f..e5791bf 100644
--- a/bddisasm/include/tabledefs.h
+++ b/bddisasm/include/tabledefs.h
@@ -413,6 +413,9 @@ typedef enum _ND_OPERAND_TYPE_SPEC
     ND_OPT_MEM_SHSP,
     ND_OPT_MEM_SHS0,
 
+    // Special immediates.
+    ND_OPT_Im2z,
+
     // Misc CR/XCR/MSR/SYS registers.
     ND_OPT_CR_0,
     ND_OPT_SYS_IDTR,
diff --git a/bddisasm_test/avx/avx2gather_64.result b/bddisasm_test/avx/avx2gather_64.result
index 349a3c4..626cf41 100644
--- a/bddisasm_test/avx/avx2gather_64.result
+++ b/bddisasm_test/avx/avx2gather_64.result
@@ -1,4 +1,4 @@
-0000000000000000 c4e2919294fb00100000            VGATHERDPD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
+0000000000000000 c4e2919294fb00100000            VGATHERDPD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -16,7 +16,7 @@
                 VSIB index size: 4, VSIB element size: 8, VSIB element count: 2
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-000000000000000A c4e2119294fb00100000            VGATHERDPS xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
+000000000000000A c4e2119294fb00100000            VGATHERDPS xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -34,7 +34,7 @@
                 VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-0000000000000014 c4e2919394fb00100000            VGATHERQPD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
+0000000000000014 c4e2919394fb00100000            VGATHERQPD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -52,7 +52,7 @@
                 VSIB index size: 8, VSIB element size: 8, VSIB element count: 2
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-000000000000001E c4e2119394fb00100000            VGATHERQPS xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
+000000000000001E c4e2119394fb00100000            VGATHERQPS xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -70,7 +70,7 @@
                 VSIB index size: 8, VSIB element size: 4, VSIB element count: 2
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-0000000000000028 c4e2159394cb00100000            VGATHERQPS xmm2, xmmword ptr [rbx+ymm1*8+0x1000], xmm13
+0000000000000028 c4e2159394cb00100000            VGATHERQPS xmm2, dword ptr [rbx+ymm1*8+0x1000], xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -88,7 +88,7 @@
                 VSIB index size: 8, VSIB element size: 4, VSIB element count: 4
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-0000000000000032 c4e2119094fb00100000            VPGATHERDD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
+0000000000000032 c4e2119094fb00100000            VPGATHERDD xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -106,7 +106,7 @@
                 VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-000000000000003C c4e2919094fb00100000            VPGATHERDQ xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
+000000000000003C c4e2919094fb00100000            VPGATHERDQ xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -124,7 +124,7 @@
                 VSIB index size: 4, VSIB element size: 8, VSIB element count: 2
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-0000000000000046 c4e2119194fb00100000            VPGATHERQD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
+0000000000000046 c4e2119194fb00100000            VPGATHERQD xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -142,7 +142,7 @@
                 VSIB index size: 8, VSIB element size: 4, VSIB element count: 2
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-0000000000000050 c4e2159194cb00100000            VPGATHERQD xmm2, xmmword ptr [rbx+ymm1*8+0x1000], xmm13
+0000000000000050 c4e2159194cb00100000            VPGATHERQD xmm2, dword ptr [rbx+ymm1*8+0x1000], xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
@@ -160,7 +160,7 @@
                 VSIB index size: 8, VSIB element size: 4, VSIB element count: 4
         Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
-000000000000005A c4e2919194fb00100000            VPGATHERQQ xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
+000000000000005A c4e2919194fb00100000            VPGATHERQQ xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
         Exception class: SSE/VEX, exception type: 12
diff --git a/bddisasm_test/avx/avx_64.result b/bddisasm_test/avx/avx_64.result
index 74eeb88..fb8acd8 100644
--- a/bddisasm_test/avx/avx_64.result
+++ b/bddisasm_test/avx/avx_64.result
@@ -20609,7 +20609,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -20627,7 +20627,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -20802,7 +20802,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -20908,7 +20908,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -31299,7 +31299,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -31863,7 +31863,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -32761,7 +32761,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
diff --git a/bddisasm_test/avx512/avx512bw_64.result b/bddisasm_test/avx512/avx512bw_64.result
index 843f2b0..8b8e934 100644
--- a/bddisasm_test/avx512/avx512bw_64.result
+++ b/bddisasm_test/avx512/avx512bw_64.result
@@ -31928,7 +31928,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -31946,7 +31946,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -31998,7 +31998,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -32104,7 +32104,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E9NF
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53354,7 +53354,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53374,7 +53374,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53394,7 +53394,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53431,7 +53431,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53447,11 +53447,11 @@
                 Segment: 3, Base: 3, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004905 62b115287174db080a              VPSLLW    ymm13, ymmword ptr [rbx+r11*8+0x80], 0x0a
+0000000000004905 62b115287174db080a              VPSLLW    ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53467,11 +53467,11 @@
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-000000000000490E 62b115287174dbf80a              VPSLLW    ymm13, ymmword ptr [rbx+r11*8-0x80], 0x0a
+000000000000490E 62b115287174dbf80a              VPSLLW    ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53491,7 +53491,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53510,7 +53510,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53526,11 +53526,11 @@
                 Segment: 3, Base: 3, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004925 62b13d407174db040a              VPSLLW    zmm24, zmmword ptr [rbx+r11*8+0x40], 0x0a
+0000000000004925 62b13d407174db040a              VPSLLW    zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -53546,11 +53546,11 @@
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-000000000000492E 62b13d407174dbfc0a              VPSLLW    zmm24, zmmword ptr [rbx+r11*8-0x40], 0x0a
+000000000000492E 62b13d407174dbfc0a              VPSLLW    zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55571,7 +55571,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55591,7 +55591,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55611,7 +55611,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55648,7 +55648,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55664,11 +55664,11 @@
                 Segment: 3, Base: 3, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004C02 62b115287164db080a              VPSRAW    ymm13, ymmword ptr [rbx+r11*8+0x80], 0x0a
+0000000000004C02 62b115287164db080a              VPSRAW    ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55684,11 +55684,11 @@
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004C0B 62b115287164dbf80a              VPSRAW    ymm13, ymmword ptr [rbx+r11*8-0x80], 0x0a
+0000000000004C0B 62b115287164dbf80a              VPSRAW    ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55708,7 +55708,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55727,7 +55727,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55743,11 +55743,11 @@
                 Segment: 3, Base: 3, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004C22 62b13d407164db040a              VPSRAW    zmm24, zmmword ptr [rbx+r11*8+0x40], 0x0a
+0000000000004C22 62b13d407164db040a              VPSRAW    zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -55763,11 +55763,11 @@
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004C2B 62b13d407164dbfc0a              VPSRAW    zmm24, zmmword ptr [rbx+r11*8-0x40], 0x0a
+0000000000004C2B 62b13d407164dbfc0a              VPSRAW    zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58011,7 +58011,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58031,7 +58031,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58051,7 +58051,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58088,7 +58088,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58104,11 +58104,11 @@
                 Segment: 3, Base: 3, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004F5C 62b115287154db080a              VPSRLW    ymm13, ymmword ptr [rbx+r11*8+0x80], 0x0a
+0000000000004F5C 62b115287154db080a              VPSRLW    ymm13, ymmword ptr [rbx+r11*8+0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58124,11 +58124,11 @@
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004F65 62b115287154dbf80a              VPSRLW    ymm13, ymmword ptr [rbx+r11*8-0x80], 0x0a
+0000000000004F65 62b115287154dbf80a              VPSRLW    ymm13, ymmword ptr [rbx+r11*8-0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58148,7 +58148,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58167,7 +58167,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58183,11 +58183,11 @@
                 Segment: 3, Base: 3, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004F7C 62b13d407154db040a              VPSRLW    zmm24, zmmword ptr [rbx+r11*8+0x40], 0x0a
+0000000000004F7C 62b13d407154db040a              VPSRLW    zmm24, zmmword ptr [rbx+r11*8+0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -58203,11 +58203,11 @@
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
         Operand: 3, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
 
-0000000000004F85 62b13d407154dbfc0a              VPSRLW    zmm24, zmmword ptr [rbx+r11*8-0x40], 0x0a
+0000000000004F85 62b13d407154dbfc0a              VPSRLW    zmm24, zmmword ptr [rbx+r11*8-0x100], 0x0a
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
-        EVEX Tuple Type: Mem 128
+        EVEX Tuple Type: Full Mem
         Exception class: EVEX, exception type: E4.nb
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
diff --git a/bddisasm_test/avx512/avx512dq_64.result b/bddisasm_test/avx512/avx512dq_64.result
index 78f740a..18547dc 100644
--- a/bddisasm_test/avx512/avx512dq_64.result
+++ b/bddisasm_test/avx512/avx512dq_64.result
@@ -9693,7 +9693,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9711,7 +9711,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9730,7 +9730,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9746,11 +9746,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 2 times
 
-0000000000000CD6 62b1fd087954db10                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x80]
+0000000000000CD6 62b1fd087954db10                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9765,11 +9765,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, 
 
-0000000000000CDE 62b1fd087954dbf0                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x80]
+0000000000000CDE 62b1fd087954dbf0                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9788,7 +9788,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9807,7 +9807,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9827,7 +9827,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9844,11 +9844,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 2 times
 
-0000000000000CF8 62b1fd0d7954db10                VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8+0x80]
+0000000000000CF8 62b1fd0d7954db10                VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9864,11 +9864,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, 
 
-0000000000000D00 62b1fd0d7954dbf0                VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8-0x80]
+0000000000000D00 62b1fd0d7954dbf0                VCVTPD2UQQ xmm2{k5}, xmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9888,7 +9888,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9907,7 +9907,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9927,7 +9927,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9944,11 +9944,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 2 times
 
-0000000000000D1A 62b1fd887954db10                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x80]
+0000000000000D1A 62b1fd887954db10                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9964,11 +9964,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, 
 
-0000000000000D22 62b1fd887954dbf0                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x80]
+0000000000000D22 62b1fd887954dbf0                VCVTPD2UQQ xmm2, xmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -9988,7 +9988,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10008,7 +10008,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10029,7 +10029,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10047,11 +10047,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 2 times
 
-0000000000000D3C 62b1fd8d7954db10                VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x80]
+0000000000000D3C 62b1fd8d7954db10                VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10068,11 +10068,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000010, 
 
-0000000000000D44 62b1fd8d7954dbf0                VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x80]
+0000000000000D44 62b1fd8d7954dbf0                VCVTPD2UQQ xmm2{k5}{z}, xmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10093,7 +10093,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10111,7 +10111,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10130,7 +10130,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10146,11 +10146,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 4 times
 
-0000000000000D5E 62a1fd287944db08                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x80]
+0000000000000D5E 62a1fd287944db08                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10165,11 +10165,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
 
-0000000000000D66 62a1fd287944dbf8                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x80]
+0000000000000D66 62a1fd287944dbf8                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10188,7 +10188,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10207,7 +10207,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10227,7 +10227,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10244,11 +10244,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 4 times
 
-0000000000000D80 62a1fd2d7944db08                VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8+0x80]
+0000000000000D80 62a1fd2d7944db08                VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10264,11 +10264,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
 
-0000000000000D88 62a1fd2d7944dbf8                VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8-0x80]
+0000000000000D88 62a1fd2d7944dbf8                VCVTPD2UQQ ymm16{k5}, ymmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10288,7 +10288,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10307,7 +10307,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10327,7 +10327,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10344,11 +10344,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 4 times
 
-0000000000000DA2 62a1fda87944db08                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x80]
+0000000000000DA2 62a1fda87944db08                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10364,11 +10364,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
 
-0000000000000DAA 62a1fda87944dbf8                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x80]
+0000000000000DAA 62a1fda87944dbf8                VCVTPD2UQQ ymm16, ymmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10388,7 +10388,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10408,7 +10408,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10429,7 +10429,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10447,11 +10447,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 4 times
 
-0000000000000DC4 62a1fdad7944db08                VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x80]
+0000000000000DC4 62a1fdad7944db08                VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10468,11 +10468,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000008, 
 
-0000000000000DCC 62a1fdad7944dbf8                VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x80]
+0000000000000DCC 62a1fdad7944dbf8                VCVTPD2UQQ ymm16{k5}{z}, ymmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10493,7 +10493,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10511,7 +10511,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10529,7 +10529,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10548,7 +10548,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10564,11 +10564,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 8 times
 
-0000000000000DEC 6221fd487944db04                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x80]
+0000000000000DEC 6221fd487944db04                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10583,11 +10583,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
 
-0000000000000DF4 6221fd487944dbfc                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x80]
+0000000000000DF4 6221fd487944dbfc                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10606,7 +10606,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10625,7 +10625,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10644,7 +10644,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10664,7 +10664,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10681,11 +10681,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 8 times
 
-0000000000000E14 6221fd4d7944db04                VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8+0x80]
+0000000000000E14 6221fd4d7944db04                VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10701,11 +10701,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
 
-0000000000000E1C 6221fd4d7944dbfc                VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8-0x80]
+0000000000000E1C 6221fd4d7944dbfc                VCVTPD2UQQ zmm24{k5}, zmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10725,7 +10725,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10744,7 +10744,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10763,7 +10763,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10783,7 +10783,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10800,11 +10800,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 8 times
 
-0000000000000E3C 6221fdc87944db04                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x80]
+0000000000000E3C 6221fdc87944db04                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10820,11 +10820,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
 
-0000000000000E44 6221fdc87944dbfc                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x80]
+0000000000000E44 6221fdc87944dbfc                VCVTPD2UQQ zmm24, zmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10844,7 +10844,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10864,7 +10864,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10884,7 +10884,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10905,7 +10905,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10923,11 +10923,11 @@
                 Segment: 3, Base: 3, 
                 Decorator: Broadcast 8 bytes element 8 times
 
-0000000000000E64 6221fdcd7944db04                VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x80]
+0000000000000E64 6221fdcd7944db04                VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8+0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -10944,11 +10944,11 @@
         Operand: 2, Acc:  R-,  Type:     Memory, Size: 64, RawSize: 64, Encoding: M, Compressed displacement: yes, 
                 Segment: 3, Base: 3, Index: 11 * 8, Displacement: 0x0000000000000004, 
 
-0000000000000E6C 6221fdcd7944dbfc                VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x80]
+0000000000000E6C 6221fdcd7944dbfc                VCVTPD2UQQ zmm24{k5}{z}, zmmword ptr [rbx+r11*8-0x100]
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512DQ, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
-        EVEX Tuple Type: Half
+        EVEX Tuple Type: Full
         Exception class: EVEX, exception type: E2
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
diff --git a/bddisasm_test/avx512/avx512pf_64.result b/bddisasm_test/avx512/avx512pf_64.result
index bcf562e..6b805f5 100644
--- a/bddisasm_test/avx512/avx512pf_64.result
+++ b/bddisasm_test/avx512/avx512pf_64.result
@@ -1,4 +1,4 @@
-0000000000000000 62f2fd45c68ccb00100000          VGATHERPF0DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5}
+0000000000000000 62f2fd45c68ccb00100000          VGATHERPF0DPD qword ptr [rbx+ymm17*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -18,7 +18,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-000000000000000B 62b27d45c68cdb00100000          VGATHERPF0DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+000000000000000B 62b27d45c68cdb00100000          VGATHERPF0DPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -38,7 +38,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000016 62b2fd45c78cdb00100000          VGATHERPF0QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+0000000000000016 62b2fd45c78cdb00100000          VGATHERPF0QPD qword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -58,7 +58,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000021 62b27d45c78cdb00100000          VGATHERPF0QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5}
+0000000000000021 62b27d45c78cdb00100000          VGATHERPF0QPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -78,7 +78,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-000000000000002C 62f2fd45c694cb00100000          VGATHERPF1DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5}
+000000000000002C 62f2fd45c694cb00100000          VGATHERPF1DPD qword ptr [rbx+ymm17*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -98,7 +98,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000037 62b27d45c694db00100000          VGATHERPF1DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+0000000000000037 62b27d45c694db00100000          VGATHERPF1DPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -118,7 +118,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000042 62b2fd45c794db00100000          VGATHERPF1QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+0000000000000042 62b2fd45c794db00100000          VGATHERPF1QPD qword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -138,7 +138,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-000000000000004D 62b27d45c794db00100000          VGATHERPF1QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5}
+000000000000004D 62b27d45c794db00100000          VGATHERPF1QPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: GATHER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -158,7 +158,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000058 62f2fd45c6accb00100000          VSCATTERPF0DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5}
+0000000000000058 62f2fd45c6accb00100000          VSCATTERPF0DPD qword ptr [rbx+ymm17*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -178,7 +178,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000063 62b27d45c6acdb00100000          VSCATTERPF0DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+0000000000000063 62b27d45c6acdb00100000          VSCATTERPF0DPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -198,7 +198,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-000000000000006E 62b2fd45c7acdb00100000          VSCATTERPF0QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+000000000000006E 62b2fd45c7acdb00100000          VSCATTERPF0QPD qword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -218,7 +218,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000079 62b27d45c7acdb00100000          VSCATTERPF0QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5}
+0000000000000079 62b27d45c7acdb00100000          VSCATTERPF0QPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -238,7 +238,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-0000000000000084 62f2fd45c6b4cb00100000          VSCATTERPF1DPD zmmword ptr [rbx+ymm17*8+0x1000]{k5}
+0000000000000084 62f2fd45c6b4cb00100000          VSCATTERPF1DPD qword ptr [rbx+ymm17*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -258,7 +258,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-000000000000008F 62b27d45c6b4db00100000          VSCATTERPF1DPS zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+000000000000008F 62b27d45c6b4db00100000          VSCATTERPF1DPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -278,7 +278,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-000000000000009A 62b2fd45c7b4db00100000          VSCATTERPF1QPD zmmword ptr [rbx+zmm27*8+0x1000]{k5}
+000000000000009A 62b2fd45c7b4db00100000          VSCATTERPF1QPD qword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
@@ -298,7 +298,7 @@
                 Decorator: Mask k5
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 5, RegCount: 1
 
-00000000000000A5 62b27d45c7b4db00100000          VSCATTERPF1QPS ymmword ptr [rbx+zmm27*8+0x1000]{k5}
+00000000000000A5 62b27d45c7b4db00100000          VSCATTERPF1QPS dword ptr [rbx+zmm27*8+0x1000]{k5}
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: AVX512PF, Ins cat: SCATTER, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 26
diff --git a/bddisasm_test/avx512/avx512vbmi_64.result b/bddisasm_test/avx512/avx512vbmi_64.result
index bcd5263..2a7ff1f 100644
--- a/bddisasm_test/avx512/avx512vbmi_64.result
+++ b/bddisasm_test/avx512/avx512vbmi_64.result
@@ -2,7 +2,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -20,7 +20,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -38,7 +38,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -56,7 +56,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -75,7 +75,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -94,7 +94,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -109,11 +109,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 64, RawSize: 64, Encoding: R, RegType:           Vector, RegSize: 64, RegId: 24, RegCount: 1
 
-0000000000000024 62b27d086354db40                VPCOMPRESSB xmmword ptr [rbx+r11*8+0x100], xmm2
+0000000000000024 62b27d086354db40                VPCOMPRESSB xmmword ptr [rbx+r11*8+0x40], xmm2
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -128,11 +128,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
 
-000000000000002C 62a27d286344db40                VPCOMPRESSB ymmword ptr [rbx+r11*8+0x100], ymm16
+000000000000002C 62a27d286344db40                VPCOMPRESSB ymmword ptr [rbx+r11*8+0x40], ymm16
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -147,11 +147,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 16, RegCount: 1
 
-0000000000000034 62227d486344db40                VPCOMPRESSB zmmword ptr [rbx+r11*8+0x100], zmm24
+0000000000000034 62227d486344db40                VPCOMPRESSB zmmword ptr [rbx+r11*8+0x40], zmm24
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -166,11 +166,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 64, RawSize: 64, Encoding: R, RegType:           Vector, RegSize: 64, RegId: 24, RegCount: 1
 
-000000000000003C 62b27d086354dbc0                VPCOMPRESSB xmmword ptr [rbx+r11*8-0x100], xmm2
+000000000000003C 62b27d086354dbc0                VPCOMPRESSB xmmword ptr [rbx+r11*8-0x40], xmm2
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -185,11 +185,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
 
-0000000000000044 62a27d286344dbc0                VPCOMPRESSB ymmword ptr [rbx+r11*8-0x100], ymm16
+0000000000000044 62a27d286344dbc0                VPCOMPRESSB ymmword ptr [rbx+r11*8-0x40], ymm16
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -204,11 +204,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 16, RegCount: 1
 
-000000000000004C 62227d486344dbc0                VPCOMPRESSB zmmword ptr [rbx+r11*8-0x100], zmm24
+000000000000004C 62227d486344dbc0                VPCOMPRESSB zmmword ptr [rbx+r11*8-0x40], zmm24
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -227,7 +227,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -245,7 +245,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -263,7 +263,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -281,7 +281,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -300,7 +300,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -319,7 +319,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -334,11 +334,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 64, RawSize: 64, Encoding: R, RegType:           Vector, RegSize: 64, RegId: 24, RegCount: 1
 
-0000000000000078 62b2fd086354db20                VPCOMPRESSW xmmword ptr [rbx+r11*8+0x100], xmm2
+0000000000000078 62b2fd086354db20                VPCOMPRESSW xmmword ptr [rbx+r11*8+0x40], xmm2
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -353,11 +353,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
 
-0000000000000080 62a2fd286344db20                VPCOMPRESSW ymmword ptr [rbx+r11*8+0x100], ymm16
+0000000000000080 62a2fd286344db20                VPCOMPRESSW ymmword ptr [rbx+r11*8+0x40], ymm16
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -372,11 +372,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 16, RegCount: 1
 
-0000000000000088 6222fd486344db20                VPCOMPRESSW zmmword ptr [rbx+r11*8+0x100], zmm24
+0000000000000088 6222fd486344db20                VPCOMPRESSW zmmword ptr [rbx+r11*8+0x40], zmm24
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -391,11 +391,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 64, RawSize: 64, Encoding: R, RegType:           Vector, RegSize: 64, RegId: 24, RegCount: 1
 
-0000000000000090 62b2fd086354dbe0                VPCOMPRESSW xmmword ptr [rbx+r11*8-0x100], xmm2
+0000000000000090 62b2fd086354dbe0                VPCOMPRESSW xmmword ptr [rbx+r11*8-0x40], xmm2
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -410,11 +410,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
 
-0000000000000098 62a2fd286344dbe0                VPCOMPRESSW ymmword ptr [rbx+r11*8-0x100], ymm16
+0000000000000098 62a2fd286344dbe0                VPCOMPRESSW ymmword ptr [rbx+r11*8-0x40], ymm16
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -429,11 +429,11 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size: 32, RawSize: 32, Encoding: R, RegType:           Vector, RegSize: 32, RegId: 16, RegCount: 1
 
-00000000000000A0 6222fd486344dbe0                VPCOMPRESSW zmmword ptr [rbx+r11*8-0x100], zmm24
+00000000000000A0 6222fd486344dbe0                VPCOMPRESSW zmmword ptr [rbx+r11*8-0x40], zmm24
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3440,7 +3440,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3458,7 +3458,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3477,7 +3477,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3496,7 +3496,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3516,7 +3516,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3534,7 +3534,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3553,7 +3553,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3572,7 +3572,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3592,7 +3592,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3610,7 +3610,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3629,7 +3629,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3648,7 +3648,7 @@
         DSIZE: 32, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 8 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3668,7 +3668,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3686,7 +3686,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3705,7 +3705,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3724,7 +3724,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 128
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3744,7 +3744,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3762,7 +3762,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3781,7 +3781,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3800,7 +3800,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 256
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3820,7 +3820,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3838,7 +3838,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3857,7 +3857,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
@@ -3876,7 +3876,7 @@
         DSIZE: 64, ASIZE: 64, VLEN: 512
         ISA Set: AVX512VBMI2, Ins cat: AVX512VBMI, CET tracked: no
         CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 6
-        EVEX Tuple Type: Tuple 1 Scalar
+        EVEX Tuple Type: Tuple 1 scalar, 16 bit
         Exception class: EVEX, exception type: E4
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
diff --git a/bddisasm_test/basic/basic1_64.result b/bddisasm_test/basic/basic1_64.result
index 367f572..8f24ac3 100644
--- a/bddisasm_test/basic/basic1_64.result
+++ b/bddisasm_test/basic/basic1_64.result
@@ -473,7 +473,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-0000000000000054 480500000010                    ADD       rax, 0x10000000
+0000000000000054 480500000010                    ADD       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -965,7 +965,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-00000000000000AE 482d00000010                    SUB       rax, 0x10000000
+00000000000000AE 482d00000010                    SUB       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -1457,7 +1457,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-0000000000000108 481500000010                    ADC       rax, 0x10000000
+0000000000000108 481500000010                    ADC       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -1949,7 +1949,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-0000000000000162 481d00000010                    SBB       rax, 0x10000000
+0000000000000162 481d00000010                    SBB       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -2441,7 +2441,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-00000000000001BC 482500000010                    AND       rax, 0x10000000
+00000000000001BC 482500000010                    AND       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: LOGIC, CET tracked: no
         FLAGS access
@@ -2933,7 +2933,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-0000000000000216 480d00000010                    OR        rax, 0x10000000
+0000000000000216 480d00000010                    OR        rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: LOGIC, CET tracked: no
         FLAGS access
@@ -3425,7 +3425,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-0000000000000270 483500000010                    XOR       rax, 0x10000000
+0000000000000270 483500000010                    XOR       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: LOGIC, CET tracked: no
         FLAGS access
@@ -3917,7 +3917,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:  General Purpose, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-00000000000002CA 483d00000010                    CMP       rax, 0x10000000
+00000000000002CA 483d00000010                    CMP       rax, 0x0000000010000000
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -3951,7 +3951,7 @@
         Operand: 1, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  4, Encoding: I
         Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
 
-00000000000002D5 48a901000000                    TEST      rax, 0x00000001
+00000000000002D5 48a901000000                    TEST      rax, 0x0000000000000001
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: LOGIC, CET tracked: no
         FLAGS access
@@ -4056,7 +4056,7 @@
         Operand: 1, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  4, Encoding: I
         Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
 
-00000000000002EF 48f70301000000                  TEST      qword ptr [rbx], 0x00000001
+00000000000002EF 48f70301000000                  TEST      qword ptr [rbx], 0x0000000000000001
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: LOGIC, CET tracked: no
         FLAGS access
@@ -8157,7 +8157,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  1, RawSize:  1, Encoding: S, RegType:  General Purpose, RegSize:  1, RegId: 1, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-00000000000005C8 666bc164                        IMUL      ax, cx, 0x64
+00000000000005C8 666bc164                        IMUL      ax, cx, 0x0064
         DSIZE: 16, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8175,7 +8175,7 @@
         Operand: 2, Acc:  R-,  Type:  Immediate, Size:  2, RawSize:  1, Encoding: I
         Operand: 3, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:            Flags, RegSize:  2, RegId: 0, RegCount: 1
 
-00000000000005CC 666b0364                        IMUL      ax, word ptr [rbx], 0x64
+00000000000005CC 666b0364                        IMUL      ax, word ptr [rbx], 0x0064
         DSIZE: 16, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8194,7 +8194,7 @@
         Operand: 2, Acc:  R-,  Type:  Immediate, Size:  2, RawSize:  1, Encoding: I
         Operand: 3, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:            Flags, RegSize:  2, RegId: 0, RegCount: 1
 
-00000000000005D0 6bc164                          IMUL      eax, ecx, 0x64
+00000000000005D0 6bc164                          IMUL      eax, ecx, 0x00000064
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8212,7 +8212,7 @@
         Operand: 2, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  1, Encoding: I
         Operand: 3, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
 
-00000000000005D3 6b0364                          IMUL      eax, dword ptr [rbx], 0x64
+00000000000005D3 6b0364                          IMUL      eax, dword ptr [rbx], 0x00000064
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8231,7 +8231,7 @@
         Operand: 2, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  1, Encoding: I
         Operand: 3, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
 
-00000000000005D6 486bc164                        IMUL      rax, rcx, 0x64
+00000000000005D6 486bc164                        IMUL      rax, rcx, 0x0000000000000064
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8249,7 +8249,7 @@
         Operand: 2, Acc:  R-,  Type:  Immediate, Size:  8, RawSize:  1, Encoding: I
         Operand: 3, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-00000000000005DA 486b0364                        IMUL      rax, qword ptr [rbx], 0x64
+00000000000005DA 486b0364                        IMUL      rax, qword ptr [rbx], 0x0000000000000064
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8935,7 +8935,7 @@
         Operand: 1, Acc:  R-,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:  General Purpose, RegSize:  2, RegId: 0, RegCount: 1
         Operand: 2, Acc:  R-,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:            Flags, RegSize:  2, RegId: 0, RegCount: 1
 
-0000000000000615 f04883870010000001              LOCK ADD  qword ptr [rdi+0x1000], 0x01
+0000000000000615 f04883870010000001              LOCK ADD  qword ptr [rdi+0x1000], 0x0000000000000001
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8953,7 +8953,7 @@
         Operand: 1, Acc:  R-,  Type:  Immediate, Size:  8, RawSize:  1, Encoding: I
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:            Flags, RegSize:  8, RegId: 0, RegCount: 1
 
-000000000000061E f2f0830001                      XACQUIRE LOCK ADD dword ptr [rax], 0x01
+000000000000061E f2f0830001                      XACQUIRE LOCK ADD dword ptr [rax], 0x00000001
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -8971,7 +8971,7 @@
         Operand: 1, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  1, Encoding: I
         Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
 
-0000000000000623 f3f04883acfe00f0ffff02          XRELEASE LOCK SUB qword ptr [rsi+rdi*8-0x1000], 0x02
+0000000000000623 f3f04883acfe00f0ffff02          XRELEASE LOCK SUB qword ptr [rsi+rdi*8-0x1000], 0x0000000000000002
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
diff --git a/bddisasm_test/basic/branch_32.result b/bddisasm_test/basic/branch_32.result
index 027fb33..aeceb32 100644
--- a/bddisasm_test/basic/branch_32.result
+++ b/bddisasm_test/basic/branch_32.result
@@ -655,7 +655,7 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: yes, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  2, Encoding: I
+        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  2, RawSize:  2, Encoding: I
         Operand: 1, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 4, RegCount: 1
         Operand: 3, Acc:  R-,  Type:     Memory, Size:  4, RawSize:  4, Encoding: S, Stack: yes, 
@@ -692,7 +692,7 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  2, Encoding: I
+        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  2, RawSize:  2, Encoding: I
         Operand: 1, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 1, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
         Operand: 3, Acc:  R-,  Type:     Memory, Size:  8, RawSize:  8, Encoding: S, Stack: yes, 
diff --git a/bddisasm_test/basic/branch_64.result b/bddisasm_test/basic/branch_64.result
index ce49fed..fadd0b0 100644
--- a/bddisasm_test/basic/branch_64.result
+++ b/bddisasm_test/basic/branch_64.result
@@ -447,7 +447,7 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: yes, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  8, RawSize:  2, Encoding: I
+        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  2, RawSize:  2, Encoding: I
         Operand: 1, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:               IP, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 4, RegCount: 1
         Operand: 3, Acc:  R-,  Type:     Memory, Size:  8, RawSize:  8, Encoding: S, Stack: yes, 
@@ -484,7 +484,7 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  4, RawSize:  2, Encoding: I
+        Operand: 0, Acc:  R-,  Type:  Immediate, Size:  2, RawSize:  2, Encoding: I
         Operand: 1, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 1, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
         Operand: 3, Acc:  R-,  Type:     Memory, Size:  8, RawSize:  8, Encoding: S, Stack: yes, 
@@ -542,8 +542,8 @@
                 Entire register
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
-                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
-                SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
diff --git a/bddisasm_test/basic/fpu_64.result b/bddisasm_test/basic/fpu_64.result
index ef7457b..6f88189 100644
--- a/bddisasm_test/basic/fpu_64.result
+++ b/bddisasm_test/basic/fpu_64.result
@@ -1834,7 +1834,7 @@
         Operand: 1, Acc:  RW,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:           System, RegSize:  2, RegId: 2, RegCount: 1
 
-00000000000000D8 ddd7                            FST       st0, st7
+00000000000000D8 ddd7                            FST       st7, st0
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: X87, Ins cat: X87_ALU, CET tracked: no
         FPU flags access
@@ -1847,11 +1847,11 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
-        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:           System, RegSize:  2, RegId: 2, RegCount: 1
 
-00000000000000DA dddf                            FSTP      st0, st7
+00000000000000DA dddf                            FSTP      st7, st0
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: X87, Ins cat: X87_ALU, CET tracked: no
         FPU flags access
@@ -1864,8 +1864,8 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
-        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:           System, RegSize:  2, RegId: 2, RegCount: 1
 
 00000000000000DC dde7                            FUCOM     st0, st7
@@ -2357,7 +2357,7 @@
         Operand: 1, Acc:  RW,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:           System, RegSize:  2, RegId: 2, RegCount: 1
 
-0000000000000114 dddf                            FSTP      st0, st7
+0000000000000114 dddf                            FSTP      st7, st0
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: X87, Ins cat: X87_ALU, CET tracked: no
         FPU flags access
@@ -2370,11 +2370,11 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
-        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:           System, RegSize:  2, RegId: 2, RegCount: 1
 
-0000000000000116 dddf                            FSTP      st0, st7
+0000000000000116 dddf                            FSTP      st7, st0
         DSIZE: 32, ASIZE: 64, VLEN: -
         ISA Set: X87, Ins cat: X87_ALU, CET tracked: no
         FPU flags access
@@ -2387,8 +2387,8 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
-        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 10, RawSize: 10, Encoding: M, RegType:               FP, RegSize: 10, RegId: 7, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 10, RawSize: 10, Encoding: S, RegType:               FP, RegSize: 10, RegId: 0, RegCount: 1
         Operand: 2, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:           System, RegSize:  2, RegId: 2, RegCount: 1
 
 0000000000000118 dfe0                            FNSTSW    ax
diff --git a/bddisasm_test/basic/stack_16.result b/bddisasm_test/basic/stack_16.result
index c65fbae..4843ee3 100644
--- a/bddisasm_test/basic/stack_16.result
+++ b/bddisasm_test/basic/stack_16.result
@@ -58,7 +58,7 @@
         Operand: 1, Acc:  R-,  Type:     Memory, Size:  4, RawSize:  4, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-0000000000000006 6a7f                            PUSH      0x7f
+0000000000000006 6a7f                            PUSH      0x007f
         DSIZE: 16, ASIZE: 16, VLEN: -
         ISA Set: I86, Ins cat: PUSH, CET tracked: no
         Valid modes
diff --git a/bddisasm_test/basic/stack_32.result b/bddisasm_test/basic/stack_32.result
index 0d5494b..5fdeae1 100644
--- a/bddisasm_test/basic/stack_32.result
+++ b/bddisasm_test/basic/stack_32.result
@@ -58,7 +58,7 @@
         Operand: 1, Acc:  R-,  Type:     Memory, Size:  4, RawSize:  4, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-0000000000000006 666a7f                          PUSH      0x7f
+0000000000000006 666a7f                          PUSH      0x007f
         DSIZE: 16, ASIZE: 32, VLEN: -
         ISA Set: I86, Ins cat: PUSH, CET tracked: no
         Valid modes
@@ -401,7 +401,7 @@
         Operand: 1, Acc:  R-,  Type:     Memory, Size:  4, RawSize:  4, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-0000000000000039 60                              PUSHA
+0000000000000039 60                              PUSHAD
         DSIZE: 32, ASIZE: 32, VLEN: -
         ISA Set: I386, Ins cat: PUSH, CET tracked: no
         Valid modes
@@ -412,11 +412,11 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 0, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
         Operand: 1, Acc:  -W,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-000000000000003A 61                              POPA
+000000000000003A 61                              POPAD
         DSIZE: 32, ASIZE: 32, VLEN: -
         ISA Set: I386, Ins cat: POP, CET tracked: no
         Valid modes
@@ -427,11 +427,11 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
         Operand: 1, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-000000000000003B 60                              PUSHA
+000000000000003B 60                              PUSHAD
         DSIZE: 32, ASIZE: 32, VLEN: -
         ISA Set: I386, Ins cat: PUSH, CET tracked: no
         Valid modes
@@ -442,11 +442,11 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 0, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
         Operand: 1, Acc:  -W,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-000000000000003C 61                              POPA
+000000000000003C 61                              POPAD
         DSIZE: 32, ASIZE: 32, VLEN: -
         ISA Set: I386, Ins cat: POP, CET tracked: no
         Valid modes
@@ -457,7 +457,7 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
         Operand: 1, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
diff --git a/bddisasm_test/basic/stack_64.result b/bddisasm_test/basic/stack_64.result
index 5a08930..b50d8f1 100644
--- a/bddisasm_test/basic/stack_64.result
+++ b/bddisasm_test/basic/stack_64.result
@@ -58,7 +58,7 @@
         Operand: 1, Acc:  R-,  Type:     Memory, Size:  8, RawSize:  8, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-0000000000000006 666a7f                          PUSH      0x7f
+0000000000000006 666a7f                          PUSH      0x007f
         DSIZE: 16, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: PUSH, CET tracked: no
         Valid modes
@@ -73,7 +73,7 @@
         Operand: 1, Acc:  -W,  Type:     Memory, Size:  2, RawSize:  2, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-0000000000000009 68ff7f0000                      PUSH      0x00007fff
+0000000000000009 68ff7f0000                      PUSH      0x0000000000007fff
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: PUSH, CET tracked: no
         Valid modes
@@ -88,7 +88,7 @@
         Operand: 1, Acc:  -W,  Type:     Memory, Size:  8, RawSize:  8, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-000000000000000E 68ffffff7f                      PUSH      0x7fffffff
+000000000000000E 68ffffff7f                      PUSH      0x000000007fffffff
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: PUSH, CET tracked: no
         Valid modes
diff --git a/bddisasm_test/basic/tsx_64.result b/bddisasm_test/basic/tsx_64.result
index c287a43..3d25ef2 100644
--- a/bddisasm_test/basic/tsx_64.result
+++ b/bddisasm_test/basic/tsx_64.result
@@ -11,7 +11,7 @@
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
         Operand: 0, Acc:  R-,  Type:     Offset, Size:  4, RawSize:  4, Encoding: D
-        Operand: 1, Acc:  RW,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:               IP, RegSize:  8, RegId: 0, RegCount: 1
         Operand: 2, Acc:  --,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
 
 0000000000000006 0f01d6                          XTEST
diff --git a/bddisasm_test/simd/sse2_64.result b/bddisasm_test/simd/sse2_64.result
index a6ebf14..6b39984 100644
--- a/bddisasm_test/simd/sse2_64.result
+++ b/bddisasm_test/simd/sse2_64.result
@@ -1905,7 +1905,7 @@
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
         Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
-        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 13, RegCount: 1
 
 0000000000000246 f2410fe6fd                      CVTPD2DQ  xmm7, xmm13
         DSIZE: 32, ASIZE: 64, VLEN: 128
@@ -4275,7 +4275,7 @@
         Operand: 1, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
                 Segment: 3, Base: 3, 
 
-00000000000004A7 f30fe63b                        CVTDQ2PD  xmm7, xmmword ptr [rbx]
+00000000000004A7 f30fe63b                        CVTDQ2PD  xmm7, qword ptr [rbx]
         DSIZE: 32, ASIZE: 64, VLEN: 128
         ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
         CPUID leaf: 0x00000001, reg: edx, bit: 26
@@ -4289,7 +4289,7 @@
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
         Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 7, RegCount: 1
-        Operand: 1, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, 
+        Operand: 1, Acc:  R-,  Type:     Memory, Size:  8, RawSize:  8, Encoding: M, 
                 Segment: 3, Base: 3, 
 
 00000000000004AB f20fe63b                        CVTPD2DQ  xmm7, xmmword ptr [rbx]
diff --git a/bddisasm_test/special/invalid_32.result b/bddisasm_test/special/invalid_32.result
index 63d09f7..e3eb293 100644
--- a/bddisasm_test/special/invalid_32.result
+++ b/bddisasm_test/special/invalid_32.result
@@ -112,18 +112,30 @@
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
 
-000000000000000B 0f05                            LOADALL
+000000000000000B 0f05                            SYSCALL
         DSIZE: 32, ASIZE: 32, VLEN: -
-        ISA Set: I486REAL, Ins cat: UNDOC, CET tracked: no
+        ISA Set: AMD, Ins cat: SYSCALL, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 11
+        FLAGS access
+                Entire register
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741695, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741694, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741692, RegCount: 1
+        Operand: 3, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 2, RegCount: 1
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 1, RegCount: 1
+        Operand: 5, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 11, RegCount: 1
+        Operand: 6, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 7, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 8, Acc:  RW,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 9, Acc:  RW,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:              SSP, RegSize:  4, RegId: 0, RegCount: 1
 
 000000000000000D 90                              NOP
         DSIZE: 32, ASIZE: 32, VLEN: -
@@ -221,18 +233,28 @@
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
 
-0000000000000015 0f07                            LOADALLD
+0000000000000015 0f07                            SYSRET
         DSIZE: 32, ASIZE: 32, VLEN: -
-        ISA Set: I486REAL, Ins cat: UNDOC, CET tracked: no
+        ISA Set: AMD, Ins cat: SYSRET, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 11
+        FLAGS access
+                Entire register
         Valid modes
-                R0: yes, R1: yes, R2: yes, R3: yes
+                R0: yes, R1: no, R2: no, R3: no
                 Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
-                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741695, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 2, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 11, RegCount: 1
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 5, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 6, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 7, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:              SSP, RegSize:  4, RegId: 0, RegCount: 1
 
 0000000000000017 90                              NOP
         DSIZE: 32, ASIZE: 32, VLEN: -
diff --git a/bddisasm_test/special/long_64.result b/bddisasm_test/special/long_64.result
index 6a442bb..fcb12bb 100644
--- a/bddisasm_test/special/long_64.result
+++ b/bddisasm_test/special/long_64.result
@@ -1,4 +1,4 @@
-0000000000000000 f2f0654b8184f7ffffff7fbdbdbdbd  XACQUIRE LOCK ADD qword ptr gs:[r15+r14*8+0x7fffffff], 0xbdbdbdbd
+0000000000000000 f2f0654b8184f7ffffff7fbdbdbdbd  XACQUIRE LOCK ADD qword ptr gs:[r15+r14*8+0x7fffffff], 0xffffffffbdbdbdbd
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
@@ -113,7 +113,7 @@
                 BND: no, BHINT: no, DNT: no
 
 0000000000000017 66                              db 0x66 (0x80000003)
-0000000000000018 f2f0654b8184f7ffffff7fbdbdbdbd  XACQUIRE LOCK ADD qword ptr gs:[r15+r14*8+0x7fffffff], 0xbdbdbdbd
+0000000000000018 f2f0654b8184f7ffffff7fbdbdbdbd  XACQUIRE LOCK ADD qword ptr gs:[r15+r14*8+0x7fffffff], 0xffffffffbdbdbdbd
         DSIZE: 64, ASIZE: 64, VLEN: -
         ISA Set: I86, Ins cat: ARITH, CET tracked: no
         FLAGS access
diff --git a/bddisasm_test/special/only_32.result b/bddisasm_test/special/only_32.result
index be07ae8..eea8352 100644
--- a/bddisasm_test/special/only_32.result
+++ b/bddisasm_test/special/only_32.result
@@ -239,7 +239,7 @@
         Operand: 2, Acc:  RW,  Type:   Register, Size:  1, RawSize:  1, Encoding: S, RegType:  General Purpose, RegSize:  1, RegId: 4, RegCount: 1
         Operand: 3, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
 
-0000000000000014 60                              PUSHA
+0000000000000014 60                              PUSHAD
         DSIZE: 32, ASIZE: 32, VLEN: -
         ISA Set: I386, Ins cat: PUSH, CET tracked: no
         Valid modes
@@ -250,11 +250,11 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 0, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
         Operand: 1, Acc:  -W,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
-0000000000000015 61                              POPA
+0000000000000015 61                              POPAD
         DSIZE: 32, ASIZE: 32, VLEN: -
         ISA Set: I386, Ins cat: POP, CET tracked: no
         Valid modes
@@ -265,7 +265,7 @@
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
                 BND: no, BHINT: no, DNT: no
-        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 0, Acc:  -W,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
         Operand: 1, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
                 Segment: 2, Base: 4, 
 
diff --git a/bddisasm_test/special/only_64.result b/bddisasm_test/special/only_64.result
index 243c144..0b4ad7e 100644
--- a/bddisasm_test/special/only_64.result
+++ b/bddisasm_test/special/only_64.result
@@ -62,8 +62,8 @@
                 Entire register
         Valid modes
                 R0: yes, R1: yes, R2: yes, R3: yes
-                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
-                SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
@@ -87,8 +87,8 @@
                 Entire register
         Valid modes
                 R0: yes, R1: no, R2: no, R3: no
-                Real: no, V8086: no, Prot: no, Compat: no, Long: yes
-                SMM: no, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
         Valid prefixes
                 REP: no, REPcc: no, LOCK: no
                 HLE: no, XACQUIRE only: no, XRELEASE only: no
diff --git a/bddisasm_test/special/regressions_32 b/bddisasm_test/special/regressions_32
new file mode 100644
index 0000000..716a8af
--- /dev/null
+++ b/bddisasm_test/special/regressions_32
@@ -0,0 +1 @@
+f``faa&‚Àä&&ófÇøó¤'NmÄá:Ê
\ No newline at end of file
diff --git a/bddisasm_test/special/regressions_32.asm b/bddisasm_test/special/regressions_32.asm
new file mode 100644
index 0000000..393fb6c
--- /dev/null
+++ b/bddisasm_test/special/regressions_32.asm
@@ -0,0 +1,19 @@
+    bits 32
+
+    db 0x66
+    pusha
+    pushad
+    db 0x66
+    popa
+    popad
+    
+    db 0x26, 0x82, 0xc0, 0xe4                   ; add al, 0xe4
+    db 0x26, 0x0f, 0x05                         ; syscall - even though SDM states it's invalid, it works in 32 bit
+    db 0x26, 0x0f, 0x07                         ; sysret - even though SDM states it's invalid, it works in 32 bit
+    
+    db 0xf3, 0x66, 0x0f, 0xc7, 0xf8             ; rdpid eax - reg is 32 bit in 16/32 bit mode, 64 bit in 64 bit mode
+    
+    db 0xf3, 0x0f, 0x1b, 0x05, 0xa4, 0x27, 0x4e, 0x6d   ; bndmk bnd0, [0x6d4e27a4] - Works on 32, #UD in 64 bit mode if RIP relative.
+    
+    db 0xc4, 0xe1, 0x3a, 0x10, 0xca             ; vmovss xmm1, xmm0, xmm2 - bit 3 of vex.vvvv is ingored in 32 bit mode.
+    
\ No newline at end of file
diff --git a/bddisasm_test/special/regressions_32.result b/bddisasm_test/special/regressions_32.result
new file mode 100644
index 0000000..97b4b55
--- /dev/null
+++ b/bddisasm_test/special/regressions_32.result
@@ -0,0 +1,173 @@
+0000000000000000 6660                            PUSHA
+        DSIZE: 16, ASIZE: 32, VLEN: -
+        ISA Set: I386, Ins cat: PUSH, CET tracked: no
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:  General Purpose, RegSize:  2, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:     Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, 
+                Segment: 2, Base: 4, 
+
+0000000000000002 60                              PUSHAD
+        DSIZE: 32, ASIZE: 32, VLEN: -
+        ISA Set: I386, Ins cat: PUSH, CET tracked: no
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
+        Operand: 1, Acc:  -W,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
+                Segment: 2, Base: 4, 
+
+0000000000000003 6661                            POPA
+        DSIZE: 16, ASIZE: 32, VLEN: -
+        ISA Set: I386, Ins cat: POP, CET tracked: no
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  2, RawSize:  2, Encoding: S, RegType:  General Purpose, RegSize:  2, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, 
+                Segment: 2, Base: 4, 
+
+0000000000000005 61                              POPAD
+        DSIZE: 32, ASIZE: 32, VLEN: -
+        ISA Set: I386, Ins cat: POP, CET tracked: no
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
+        Operand: 1, Acc:  R-,  Type:     Memory, Size: 32, RawSize: 32, Encoding: S, Stack: yes, 
+                Segment: 2, Base: 4, 
+
+0000000000000006 2682c0e4                        ADD       al, 0xe4
+        DSIZE: 32, ASIZE: 32, VLEN: -
+        ISA Set: I86, Ins cat: ARITH, CET tracked: no
+        FLAGS access
+                CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, 
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: no
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: yes
+                HLE: yes, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  RW,  Type:   Register, Size:  1, RawSize:  1, Encoding: M, RegType:  General Purpose, RegSize:  1, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: I
+        Operand: 2, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000000A 260f05                          SYSCALL
+        DSIZE: 32, ASIZE: 32, VLEN: -
+        ISA Set: AMD, Ins cat: SYSCALL, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 11
+        FLAGS access
+                Entire register
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741695, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741694, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741692, RegCount: 1
+        Operand: 3, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 2, RegCount: 1
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 1, RegCount: 1
+        Operand: 5, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 11, RegCount: 1
+        Operand: 6, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 7, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 8, Acc:  RW,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 9, Acc:  RW,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:              SSP, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000000D 260f07                          SYSRET
+        DSIZE: 32, ASIZE: 32, VLEN: -
+        ISA Set: AMD, Ins cat: SYSRET, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 11
+        FLAGS access
+                Entire register
+        Valid modes
+                R0: yes, R1: no, R2: no, R3: no
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: no, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741695, RegCount: 1
+        Operand: 1, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 2, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:  General Purpose, RegSize:  8, RegId: 11, RegCount: 1
+        Operand: 4, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:          Segment, RegSize:  4, RegId: 1, RegCount: 1
+        Operand: 5, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:               IP, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 6, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:            Flags, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 7, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:              SSP, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000010 f3660fc7f8                      RDPID     eax
+        DSIZE: 16, ASIZE: 32, VLEN: -
+        ISA Set: RDPID, Ins cat: RDPID, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ecx, bit: 22
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  4, RawSize:  4, Encoding: M, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:   Model Specific, RegSize:  8, RegId: -1073741565, RegCount: 1
+
+0000000000000015 f30f1b05a4274e6d                BNDMK     bnd0, dword ptr [0x6d4e27a4]
+        DSIZE: 32, ASIZE: 32, VLEN: -
+        ISA Set: MPX, Ins cat: MPX, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size:  8, RawSize:  8, Encoding: R, RegType:            Bound, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size:  4, RawSize:  4, Encoding: M, 
+                Segment: 3, Displacement: 0x000000006d4e27a4, 
+
+000000000000001D c4e13a10ca                      VMOVSS    xmm1, xmm0, xmm2
+        DSIZE: 32, ASIZE: 32, VLEN: 128
+        ISA Set: AVX, Ins cat: DATAXFER, CET tracked: no
+        CPUID leaf: 0x00000001, reg: ecx, bit: 28
+        Exception class: SSE/VEX, exception type: 5
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size:  4, RawSize:  4, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
+
diff --git a/bddisasm_test/special/regressions_64 b/bddisasm_test/special/regressions_64
new file mode 100644
index 0000000..9dbeb27
Binary files /dev/null and b/bddisasm_test/special/regressions_64 differ
diff --git a/bddisasm_test/special/regressions_64.asm b/bddisasm_test/special/regressions_64.asm
new file mode 100644
index 0000000..ed8f3ce
--- /dev/null
+++ b/bddisasm_test/special/regressions_64.asm
@@ -0,0 +1,13 @@
+    bits 64
+    
+    db 0x66, 0x26, 0xc7, 0xf8, 0xff, 0x7f           ; xbegin 0x800000000002d877
+    db 0x26, 0xc7, 0xf8, 0x00, 0x00, 0x00, 0x00     ; xbegin 0x8000000000025b1a
+    db 0x66, 0x0f, 0x01, 0xd9                       ; vmmcall
+    db 0x67, 0x48, 0x0f, 0x1a, 0x44, 0x25, 0x7f     ; bndldx bnd0, [rbp+0x7f]
+    db 0x26, 0x48, 0x0f, 0xae, 0x04, 0x48           ; fxsave64 [rax+rcx*2]
+    db 0x26, 0x48, 0x0f, 0xae, 0x0c, 0x48           ; fxrstor64 [rax+rcx*2]
+    db 0x26, 0xc4, 0xe3, 0x71, 0x48, 0xc2, 0x30     ; vpermil2ps xmm0, xmm1, xmm2, xmm3, 0x0
+    db 0x26, 0xc4, 0xe3, 0x71, 0x49, 0xc2, 0x30     ; vpermil2pd xmm0, xmm1, xmm2, xmm3, 0x0
+    db 0xc4, 0xe3, 0x69, 0x4a, 0xcb, 0x08           ; vblendvps xmm1, xmm2, xmm3, xmm0
+    db 0xc4, 0xe3, 0x69, 0x68, 0xcb, 0x08           ; vfmaddps xmm1, xmm2, xmm3, xmm0 
+    db 0x62, 0xf2, 0x7d, 0x09, 0xa0, 0x04, 0x40     ; vpscatterdd dword ptr [rax+xmm0*2], k1, xmm0    
\ No newline at end of file
diff --git a/bddisasm_test/special/regressions_64.result b/bddisasm_test/special/regressions_64.result
new file mode 100644
index 0000000..d8db31b
--- /dev/null
+++ b/bddisasm_test/special/regressions_64.result
@@ -0,0 +1,187 @@
+0000000000000000 6626c7f8ff7f                    XBEGIN    0x8005
+        DSIZE: 16, ASIZE: 64, VLEN: -
+        ISA Set: TSX, Ins cat: COND_BR, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 11
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Offset, Size:  2, RawSize:  2, Encoding: D
+        Operand: 1, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:               IP, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  --,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+
+0000000000000006 26c7f800000000                  XBEGIN    0xd
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: TSX, Ins cat: COND_BR, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 11
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Offset, Size:  4, RawSize:  4, Encoding: D
+        Operand: 1, Acc:  RW,  Type:   Register, Size:  8, RawSize:  8, Encoding: S, RegType:               IP, RegSize:  8, RegId: 0, RegCount: 1
+        Operand: 2, Acc:  --,  Type:   Register, Size:  4, RawSize:  4, Encoding: S, RegType:  General Purpose, RegSize:  4, RegId: 0, RegCount: 1
+
+000000000000000D 660f01d9                        VMMCALL
+        DSIZE: 32, ASIZE: 64, VLEN: -
+        ISA Set: SVM, Ins cat: SYSTEM, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 2
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+
+0000000000000011 67480f1a44257f                  BNDLDX    bnd0, [rbp+0x7f]
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: MPX, Ins cat: MPX, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 14
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:            Bound, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:     Memory, Size:  0, RawSize:  0, Encoding: M, Address Generator: yes, MIB Addressing: yes, 
+                Base: 5, Displacement: 0x000000000000007f, 
+
+0000000000000018 26480fae0448                    FXSAVE64  [rax+rcx*2]
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: FXSAVE, Ins cat: SSE, CET tracked: no
+        CPUID leaf: 0x00000001, reg: edx, bit: 24
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:     Memory, Size: 512, RawSize: 512, Encoding: M, 
+                Segment: 3, Base: 0, Index: 1 * 2, 
+        Operand: 1, Acc:  R-,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
+
+000000000000001E 26480fae0c48                    FXRSTOR64 [rax+rcx*2]
+        DSIZE: 64, ASIZE: 64, VLEN: -
+        ISA Set: FXSAVE, Ins cat: SSE, CET tracked: no
+        CPUID leaf: 0x00000001, reg: edx, bit: 24
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  R-,  Type:     Memory, Size: 512, RawSize: 512, Encoding: M, 
+                Segment: 3, Base: 0, Index: 1 * 2, 
+        Operand: 1, Acc:  -W,  Type:       Bank, Size: -1, RawSize: -1, Encoding: S
+
+0000000000000024 26c4e37148c230                  VPERMIL2PS xmm0, xmm1, xmm2, xmm3, 0x00
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: XOP, Ins cat: XOP, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 11
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: L, RegType:           Vector, RegSize: 16, RegId: 3, RegCount: 1
+        Operand: 4, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: L
+
+000000000000002B 26c4e37149c230                  VPERMIL2PD xmm0, xmm1, xmm2, xmm3, 0x00
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: XOP, Ins cat: XOP, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 11
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: L, RegType:           Vector, RegSize: 16, RegId: 3, RegCount: 1
+        Operand: 4, Acc:  R-,  Type:  Immediate, Size:  1, RawSize:  1, Encoding: L
+
+0000000000000032 c4e3694acb08                    VBLENDVPS xmm1, xmm2, xmm3, xmm0
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVX, Ins cat: AVX, CET tracked: no
+        CPUID leaf: 0x00000001, reg: ecx, bit: 28
+        Exception class: SSE/VEX, exception type: 4
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 3, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: L, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+
+0000000000000038 c4e36968cb08                    VFMADDPS  xmm1, xmm2, xmm3, xmm0
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
+        CPUID leaf: 0x80000001, reg: ecx, bit: 16
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 1, RegCount: 1
+        Operand: 1, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: V, RegType:           Vector, RegSize: 16, RegId: 2, RegCount: 1
+        Operand: 2, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: M, RegType:           Vector, RegSize: 16, RegId: 3, RegCount: 1
+        Operand: 3, Acc:  R-,  Type:   Register, Size: 16, RawSize: 16, Encoding: L, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+
+000000000000003E 62f27d09a00440                  VPSCATTERDD dword ptr [rax+xmm0*2]{k1}, xmm0
+        DSIZE: 32, ASIZE: 64, VLEN: 128
+        ISA Set: AVX512F, Ins cat: SCATTER, CET tracked: no
+        CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
+        EVEX Tuple Type: Tuple 1 Scalar
+        Exception class: EVEX, exception type: E12
+        Valid modes
+                R0: yes, R1: yes, R2: yes, R3: yes
+                Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
+                SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
+        Valid prefixes
+                REP: no, REPcc: no, LOCK: no
+                HLE: no, XACQUIRE only: no, XRELEASE only: no
+                BND: no, BHINT: no, DNT: no
+        Operand: 0, Acc:  -W,  Type:     Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes, 
+                Segment: 3, Base: 0, Index: 0 * 2, 
+                VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
+                Decorator: Mask k1
+        Operand: 1, Acc:  R-,  Type:   Register, Size:  8, RawSize:  8, Encoding: A, RegType:             Mask, RegSize:  8, RegId: 1, RegCount: 1
+        Operand: 2, Acc:  RW,  Type:   Register, Size: 16, RawSize: 16, Encoding: R, RegType:           Vector, RegSize: 16, RegId: 0, RegCount: 1
+
diff --git a/bdshemu_test/basic/test_64_basic05.result b/bdshemu_test/basic/test_64_basic05.result
index 59151a4..ad279d3 100644
--- a/bdshemu_test/basic/test_64_basic05.result
+++ b/bdshemu_test/basic/test_64_basic05.result
@@ -9,7 +9,7 @@ Emulating: 0x0000000000200000 LEA       rbp, [rel 0x200000]
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200007 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200007 SUB       rbp, 0x01
+Emulating: 0x0000000000200007 SUB       rbp, 0x0000000000000001
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x00000000001fffff RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_basic09.result b/bdshemu_test/basic/test_64_basic09.result
index 18ba9e1..933deb4 100644
--- a/bdshemu_test/basic/test_64_basic09.result
+++ b/bdshemu_test/basic/test_64_basic09.result
@@ -3,7 +3,7 @@
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200000 MOV       rax, 0xfffffff0
+Emulating: 0x0000000000200000 MOV       rax, 0xfffffffffffffff0
         RAX = 0xfffffffffffffff0 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_branch1.result b/bdshemu_test/basic/test_64_branch1.result
index ec74268..ae757a4 100644
--- a/bdshemu_test/basic/test_64_branch1.result
+++ b/bdshemu_test/basic/test_64_branch1.result
@@ -9,7 +9,7 @@ Emulating: 0x0000000000200000 MOV       eax, 0xffffffff
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200005 ADD       eax, 0x01
+Emulating: 0x0000000000200005 ADD       eax, 0x00000001
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_branch2.result b/bdshemu_test/basic/test_64_branch2.result
index a06d124..4ab90f5 100644
--- a/bdshemu_test/basic/test_64_branch2.result
+++ b/bdshemu_test/basic/test_64_branch2.result
@@ -9,7 +9,7 @@ Emulating: 0x0000000000200000 MOV       eax, 0xffffffff
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200005 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200005 ADD       eax, 0x01
+Emulating: 0x0000000000200005 ADD       eax, 0x00000001
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_flags.result b/bdshemu_test/basic/test_64_flags.result
index c16ef81..49cce25 100644
--- a/bdshemu_test/basic/test_64_flags.result
+++ b/bdshemu_test/basic/test_64_flags.result
@@ -15,7 +15,7 @@ Emulating: 0x0000000000200002 MOV       eax, 0xffffffff
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200007 RFLAGS = 0x0000000000000246
-Emulating: 0x0000000000200007 ADD       eax, 0x01
+Emulating: 0x0000000000200007 ADD       eax, 0x00000001
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
@@ -33,13 +33,13 @@ Emulating: 0x000000000020000c MOV       eax, 0xffffffff
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200011 RFLAGS = 0x0000000000000246
-Emulating: 0x0000000000200011 ADD       eax, 0x01
+Emulating: 0x0000000000200011 ADD       eax, 0x00000001
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200014 RFLAGS = 0x0000000000000247
-Emulating: 0x0000000000200014 ADC       eax, 0x00
+Emulating: 0x0000000000200014 ADC       eax, 0x00000000
         RAX = 0x0000000000000001 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
@@ -51,13 +51,13 @@ Emulating: 0x0000000000200017 XOR       eax, eax
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200019 RFLAGS = 0x0000000000000246
-Emulating: 0x0000000000200019 SUB       eax, 0x01
+Emulating: 0x0000000000200019 SUB       eax, 0x00000001
         RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x000000000020001c RFLAGS = 0x0000000000000286
-Emulating: 0x000000000020001c SBB       eax, 0x00
+Emulating: 0x000000000020001c SBB       eax, 0x00000000
         RAX = 0x00000000ffffffff RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_loadrip02.result b/bdshemu_test/basic/test_64_loadrip02.result
index a186a08..fd65bd5 100644
--- a/bdshemu_test/basic/test_64_loadrip02.result
+++ b/bdshemu_test/basic/test_64_loadrip02.result
@@ -15,7 +15,7 @@ Emulating: 0x0000000000200002 FXSAVE    [rsp]
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200006 ADD       rsp, 0x08
+Emulating: 0x0000000000200006 ADD       rsp, 0x0000000000000008
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101008 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_mov.result b/bdshemu_test/basic/test_64_mov.result
index 45b3489..30316b7 100644
--- a/bdshemu_test/basic/test_64_mov.result
+++ b/bdshemu_test/basic/test_64_mov.result
@@ -15,7 +15,7 @@ Emulating: 0x0000000000200002 MOV       al, 0x12
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200004 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200004 MOV       rcx, 0xffffffff
+Emulating: 0x0000000000200004 MOV       rcx, 0xffffffffffffffff
         RAX = 0x000000000000bd12 RCX = 0xffffffffffffffff RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
@@ -75,7 +75,7 @@ Emulating: 0x0000000000200027 XCHG      eax, ebx
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200028 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200028 MOV       qword ptr [rsp], 0xffffffff
+Emulating: 0x0000000000200028 MOV       qword ptr [rsp], 0xffffffffffffffff
         RAX = 0x0000000009abcdef RCX = 0x000000000000ffff RDX = 0x0000000000000000 RBX = 0x0000000012345678
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/basic/test_64_string.result b/bdshemu_test/basic/test_64_string.result
index bb4eec0..d71bcf7 100644
--- a/bdshemu_test/basic/test_64_string.result
+++ b/bdshemu_test/basic/test_64_string.result
@@ -45,13 +45,13 @@ Emulating: 0x0000000000200012 MOVSD
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200013 RFLAGS = 0x0000000000000202
-Emulating: 0x0000000000200013 SUB       rsi, 0x08
+Emulating: 0x0000000000200013 SUB       rsi, 0x0000000000000008
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x0000000000200087
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
         R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
         RIP = 0x0000000000200017 RFLAGS = 0x0000000000000206
-Emulating: 0x0000000000200017 SUB       rdi, 0x08
+Emulating: 0x0000000000200017 SUB       rdi, 0x0000000000000008
         RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
         RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x000000000020005f RDI = 0x000000000020007f
         R8  = 0x0000000000000000 R9  = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
diff --git a/bdshemu_test/test_all.py b/bdshemu_test/test_all.py
index adc7482..a5b1125 100644
--- a/bdshemu_test/test_all.py
+++ b/bdshemu_test/test_all.py
@@ -47,6 +47,24 @@ def test_dir(dir):
         os.remove(f)
     for f in glob.glob('%s\\*.temp' % dir):
         os.remove(f)
+        
+def regenerate(dir): 
+    for f in glob.glob('%s\\*' % dir):
+        if -1 == f.find('.'):
+            if 0 < f.find('_16'):
+                mod = '-b16'
+            elif 0 < f.find('_32'):
+                mod = '-b32'
+            else:
+                mod = '-b64'
+            if 0 < f.find('_r0'):
+                mod += ' -k'
+                
+            print('    * Regenerating test case %s...' % f)
+            os.system('disasm -exi -shemu %s -f %s >%s.result' % (mod, f, f))
+                            
+    for f in glob.glob('%s\\*_decoded.bin' % dir):
+        os.remove(f)        
 
 for dn in glob.glob("*"):
     if not os.path.isdir(dn):
diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c
index aa6b1b3..5b44214 100644
--- a/disasmtool/disasmtool.c
+++ b/disasmtool/disasmtool.c
@@ -292,7 +292,6 @@ const char* category_to_string(
     case ND_CAT_SYSTEM:               return "SYSTEM";
     case ND_CAT_UD:                   return "UD";
     case ND_CAT_UNCOND_BR:            return "UNCOND_BR";
-    case ND_CAT_UNDOC:                return "UNDOC";
     case ND_CAT_UNKNOWN:              return "UNKNOWN";
     case ND_CAT_VAES:                 return "VAES";
     case ND_CAT_VFMA:                 return "VFMA";
diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp
index 8d5d52e..3d815eb 100644
--- a/disasmtool_lix/dumpers.cpp
+++ b/disasmtool_lix/dumpers.cpp
@@ -332,8 +332,6 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_LLDT: return "lldt";
     case ND_INS_LLWPCB: return "llwpcb";
     case ND_INS_LMSW: return "lmsw";
-    case ND_INS_LOADALL: return "loadall";
-    case ND_INS_LOADALLD: return "loadalld";
     case ND_INS_LODS: return "lods";
     case ND_INS_LOOP: return "loop";
     case ND_INS_LOOPNZ: return "loopnz";
@@ -1121,8 +1119,6 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
     case ND_INS_VPERMI2W: return "vpermi2w";
     case ND_INS_VPERMILPD: return "vpermilpd";
     case ND_INS_VPERMILPS: return "vpermilps";
-    case ND_INS_VPERMILzz2PD: return "vpermilzz2pd";
-    case ND_INS_VPERMILzz2PS: return "vpermilzz2ps";
     case ND_INS_VPERMPD: return "vpermpd";
     case ND_INS_VPERMPS: return "vpermps";
     case ND_INS_VPERMQ: return "vpermq";
@@ -1562,7 +1558,6 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
     case ND_CAT_SYSTEM: return "system";
     case ND_CAT_UD: return "ud";
     case ND_CAT_UNCOND_BR: return "uncond_br";
-    case ND_CAT_UNDOC: return "undoc";
     case ND_CAT_UNKNOWN: return "unknown";
     case ND_CAT_VAES: return "vaes";
     case ND_CAT_VFMA: return "vfma";
diff --git a/inc/bddisasm.h b/inc/bddisasm.h
index 4248f2b..fef44a3 100644
--- a/inc/bddisasm.h
+++ b/inc/bddisasm.h
@@ -176,6 +176,8 @@ typedef uint32_t ND_REG_SIZE;
 #define ND_FLAG_NO_RIP_REL          0x02000000  // The instruction doesn't work with RIP relative addressing.
 #define ND_FLAG_NO66                0x04000000  // The 0x66 prefix is not accepted by the instruction.
 #define ND_FLAG_SIBMEM              0x08000000  // sibmem addressing is used (Intel AMX instructions).
+#define ND_FLAG_I67                 0x10000000  // Ignore the 0x67 prefix in 64 bit mode (Intel MPX instructions).
+#define ND_FLAG_IER                 0x20000000  // Ignore EVEX embedded rounding.
 
 
 //
diff --git a/inc/constants.h b/inc/constants.h
index df07792..b414fc6 100644
--- a/inc/constants.h
+++ b/inc/constants.h
@@ -245,7 +245,9 @@ typedef enum _ND_INS_CLASS
     ND_INS_FXAM,
     ND_INS_FXCH,
     ND_INS_FXRSTOR,
+    ND_INS_FXRSTOR64,
     ND_INS_FXSAVE,
+    ND_INS_FXSAVE64,
     ND_INS_FXTRACT,
     ND_INS_FYL2X,
     ND_INS_FYL2XP1,
@@ -319,8 +321,6 @@ typedef enum _ND_INS_CLASS
     ND_INS_LLDT,
     ND_INS_LLWPCB,
     ND_INS_LMSW,
-    ND_INS_LOADALL,
-    ND_INS_LOADALLD,
     ND_INS_LODS,
     ND_INS_LOOP,
     ND_INS_LOOPNZ,
@@ -357,6 +357,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_MOVDQ2Q,
     ND_INS_MOVDQA,
     ND_INS_MOVDQU,
+    ND_INS_MOVHLPS,
     ND_INS_MOVHPD,
     ND_INS_MOVHPS,
     ND_INS_MOVLHPS,
@@ -461,6 +462,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_PFMUL,
     ND_INS_PFNACC,
     ND_INS_PFPNACC,
+    ND_INS_PFRCP,
     ND_INS_PFRCPIT1,
     ND_INS_PFRCPIT2,
     ND_INS_PFRCPV,
@@ -519,6 +521,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_PMULUDQ,
     ND_INS_POP,
     ND_INS_POPA,
+    ND_INS_POPAD,
     ND_INS_POPCNT,
     ND_INS_POPF,
     ND_INS_POR,
@@ -572,6 +575,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_PUNPCKLWD,
     ND_INS_PUSH,
     ND_INS_PUSHA,
+    ND_INS_PUSHAD,
     ND_INS_PUSHF,
     ND_INS_PVALIDATE,
     ND_INS_PXOR,
@@ -1106,10 +1110,10 @@ typedef enum _ND_INS_CLASS
     ND_INS_VPERMI2PS,
     ND_INS_VPERMI2Q,
     ND_INS_VPERMI2W,
+    ND_INS_VPERMIL2PD,
+    ND_INS_VPERMIL2PS,
     ND_INS_VPERMILPD,
     ND_INS_VPERMILPS,
-    ND_INS_VPERMILzz2PD,
-    ND_INS_VPERMILzz2PS,
     ND_INS_VPERMPD,
     ND_INS_VPERMPS,
     ND_INS_VPERMQ,
@@ -1272,6 +1276,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_VPSHAQ,
     ND_INS_VPSHAW,
     ND_INS_VPSHLB,
+    ND_INS_VPSHLD,
     ND_INS_VPSHLDD,
     ND_INS_VPSHLDQ,
     ND_INS_VPSHLDVD,
@@ -1279,6 +1284,7 @@ typedef enum _ND_INS_CLASS
     ND_INS_VPSHLDVW,
     ND_INS_VPSHLDW,
     ND_INS_VPSHLQ,
+    ND_INS_VPSHLW,
     ND_INS_VPSHRDD,
     ND_INS_VPSHRDQ,
     ND_INS_VPSHRDVD,
@@ -1664,7 +1670,6 @@ typedef enum _ND_INS_TYPE
     ND_CAT_SYSTEM,
     ND_CAT_UD,
     ND_CAT_UNCOND_BR,
-    ND_CAT_UNDOC,
     ND_CAT_UNKNOWN,
     ND_CAT_VAES,
     ND_CAT_VFMA,
diff --git a/inc/version.h b/inc/version.h
index 982c964..ebe2944 100644
--- a/inc/version.h
+++ b/inc/version.h
@@ -6,7 +6,7 @@
 #define _DISASM_VER_H_
 
 #define DISASM_VERSION_MAJOR        1
-#define DISASM_VERSION_MINOR        25
-#define DISASM_VERSION_REVISION     2
+#define DISASM_VERSION_MINOR        26
+#define DISASM_VERSION_REVISION     0
 
 #endif // _DISASM_VER_H_
diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py
index fbce3ad..111f7fc 100644
--- a/isagenerator/disasmlib.py
+++ b/isagenerator/disasmlib.py
@@ -43,6 +43,8 @@ valid_attributes = {
     'PREFIX',       # Prefix.
     'SERIAL',       # Instruction is serializing.
     'SIBMEM',       # Instruction uses sibmem addressing (AMX instructions).
+    'I67',          # Ignore the address size override (0x67) prefix in 64 bit mode.
+    'IER',          # Ignore embedded rounding for the instruction.
 }
 
 #
@@ -126,6 +128,7 @@ valid_optype = [
     'rT',           # The reg field inside modrm encodes a TMM register (AMX extension).
     'mT',           # The rm field inside modrm encodes a TMM register (AMX extension).
     'vT',           # The v field inside vex encodes a TMM register (AMX extension).
+    'm2zI',         # Bits [1,0] of the immediate byte which selects the fourth register.
 ]
 
 # Operand sizes.
@@ -236,6 +239,7 @@ valid_impops = {# register      size
     'aDI'      : ('rDI',        'asz'), # DI, EDI, or RDI register, depending on address size.
     'R11'      : ('rR11',       'q'),   # R11 register.
     'rIP'      : ('rIP',        'v'),   # IP, EIP or RIP, depending on op size.
+    'yIP'      : ('rIP',        'yf'),  # EIP in 16/32 bit mode, or RIP in 64 bit mode.
     '1'        : ('1',          'b'),   # Constant 1.
     'XMM0'     : ('XMM0',       'dq'),  # XMM0 register.
     'ST(0)'    : ('ST(0)',      'ft'),  # ST(0) register.
diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py
index d69f543..e7e7c80 100644
--- a/isagenerator/generate_tables.py
+++ b/isagenerator/generate_tables.py
@@ -40,6 +40,8 @@ flags = {
     'CETT'     : 'ND_FLAG_CETT',
     'SERIAL'   : 'ND_FLAG_SERIAL',
     'SIBMEM'   : 'ND_FLAG_SIBMEM',
+    'I67'      : 'ND_FLAG_I67',
+    'IER'      : 'ND_FLAG_IER',
 }
 
 prefixes_map = {
@@ -139,6 +141,9 @@ optype = {
     'SHS'      : 'ND_OPT_MEM_SHS',
     'SHS0'     : 'ND_OPT_MEM_SHS0',
     'SHSP'     : 'ND_OPT_MEM_SHSP',
+
+    # Special immediates.
+    'm2zI'     : 'ND_OPT_Im2z',
     
     # System registers, MSRs, XCRs, etc.
     'GDTR'     : 'ND_OPT_SYS_GDTR',
diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_0F.dat
index b9dceb6..c45f227 100644
--- a/isagenerator/instructions/table_0F.dat
+++ b/isagenerator/instructions/table_0F.dat
@@ -51,6 +51,7 @@ CLZERO         nil           rAX                       [            0x0F 0x01 /0
 RDPRU          nil           EAX,EDX,ECX,Fv            [            0x0F 0x01 /0xFD]           s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0
 VMRUN          nil           rAX                       [            0x0F 0x01 /0xD8]           s:SVM, t:SYSTEM, w:R, m:VMXROOT
 VMMCALL        nil           nil                       [            0x0F 0x01 /0xD9]           s:SVM, t:SYSTEM, m:VMX
+VMMCALL        nil           nil                       [       0x66 0x0F 0x01 /0xD9]           s:SVM, t:SYSTEM, m:VMX
 VMGEXIT        nil           nil                       [       0xF3 0x0F 0x01 /0xD9]           s:SVM, t:SYSTEM, m:VMX
 VMGEXIT        nil           nil                       [       0xF2 0x0F 0x01 /0xD9]           s:SVM, t:SYSTEM, m:VMX
 VMLOAD         nil           rAX                       [            0x0F 0x01 /0xDA]           s:SVM, t:SYSTEM, w:R, m:VMXROOT
@@ -70,14 +71,14 @@ LAR            Gv,Mw         Fv                        [            0x0F 0x02 /r
 LAR            Gv,Rz         Fv                        [            0x0F 0x02 /r:reg]          s:I286PROT, t:SYSTEM, w:CW|R|W, f:ZF=m, m:NOREAL
 LSL            Gv,Mw         Fv                        [            0x0F 0x03 /r:mem]          s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL
 LSL            Gv,Rz         Fv                        [            0x0F 0x03 /r:reg]          s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL
-LOADALL        nil           BANK                      [            0x0F 0x05]                 s:I486REAL, t:UNDOC, w:R
-SYSCALL        nil           STAR,LSTAR,FMASK,SS,RCX,R11,CS,rIP,Fv,SSP [        o64 0x0F 0x05] s:AMD, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW|RW, a:F64, i:FSC, m:O64|NOSGX
+#LOADALL        nil           BANK                      [            0x0F 0x05]                s:I486REAL, t:UNDOC, w:R
+SYSCALL        nil           STAR,LSTAR,FMASK,SS,RCX,R11,CS,rIP,Fv,SSP [        0x0F 0x05]     s:AMD, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW|RW, a:F64, i:FSC, m:NOSGX
 CLTS           nil           CR0                       [            0x0F 0x06]                 s:I286REAL, t:SYSTEM, w:W, m:KERNEL|NOV86
-LOADALLD       nil           BANK                      [            0x0F 0x07]                 s:I486REAL, t:UNDOC, w:R
-SYSRET         nil           STAR,SS,rCX,R11,CS,rIP,Fv,SSP [        o64 0x0F 0x07]             s:AMD, t:SYSRET, w:R|W|R|R|W|W|W|W, i:FSC, m:KERNEL|O64
+#LOADALLD       nil           BANK                      [            0x0F 0x07]                s:I486REAL, t:UNDOC, w:R
+SYSRET         nil           STAR,SS,rCX,R11,CS,rIP,Fv,SSP [        0x0F 0x07]                 s:AMD, t:SYSRET, w:R|W|R|R|W|W|W|W, i:FSC, m:KERNEL
 INVD           nil           nil                       [            0x0F 0x08]                 s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86
-WBINVD         nil           nil                       [         NP 0x0F 0x09]                 s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86
-WBNOINVD       nil           nil                       [       0xF3 0x0F 0x09]                 s:WBNOINVD, t:WBNOINVD, m:KERNEL|NOV86
+WBINVD         nil           nil                       [            0x0F 0x09]                 s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86
+WBNOINVD       nil           nil                       [      a0xF3 0x0F 0x09]                 s:WBNOINVD, t:WBNOINVD, m:KERNEL|NOV86
 CL1INVMB       nil           nil                       [            0x0F 0x0A]                 s:SCC, t:SYSTEM
 UD2            nil           nil                       [            0x0F 0x0B]                 s:PPRO, t:MISC
 PREFETCHE      Mb            nil                       [            0x0F 0x0D /0:mem]          s:PREFETCH_NOP, t:PREFETCH, w:R
@@ -108,7 +109,7 @@ MOVUPS         Wps,Vps       nil                       [         NP 0x0F 0x11 /r
 MOVUPD         Wpd,Vpd       nil                       [       0x66 0x0F 0x11 /r]              s:SSE2, t:DATAXFER, w:W|R, e:4
 MOVSS          Wss,Vss       nil                       [       0xF3 0x0F 0x11 /r]              s:SSE, t:DATAXFER, w:W|R, e:5
 MOVSD          Wsd,Vsd       nil                       [       0xF2 0x0F 0x11 /r]              s:SSE2, t:DATAXFER, w:W|R, e:5
-MOVLPS         Vq,Wq         nil                       [         NP 0x0F 0x12 /r]              s:SSE, t:DATAXFER, w:W|R, e:5
+MOVHLPS        Vq,Wq         nil                       [         NP 0x0F 0x12 /r]              s:SSE, t:DATAXFER, w:W|R, e:5
 MOVLPD         Vsd,Mq        nil                       [       0x66 0x0F 0x12 /r:mem]          s:SSE2, t:DATAXFER, w:W|R, e:5
 MOVSLDUP       Vx,Wx         nil                       [       0xF3 0x0F 0x12 /r]              s:SSE3, t:DATAXFER, w:W|R, e:4
 MOVDDUP        Vdq,Wq        nil                       [       0xF2 0x0F 0x12 /r]              s:SSE3, t:DATAXFER, w:W|R, e:5
@@ -141,18 +142,18 @@ NOP            Ev            nil                       [            0x0F 0x19 /r
 # MPX instructions. According to the SDM, MPX instructions have 64 bit op & address size in 64 bit mode, no matter 
 # if 0x66 or 0x67 prefixes are used. 16 bit addressing cause #UD. However, these checks are not handled here (note
 # that Xed doesn't do those checks either).
-BNDLDX         rBl,Mmib      nil                       [            0x0F 0x1A /r:mem mib]      s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL
+BNDLDX         rBl,Mmib      nil                       [            0x0F 0x1A /r:mem mib]      s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL|I67
 NOP            Gv,Ev         nil                       [            0x0F 0x1A /r:reg]          s:PPRO, t:WIDENOP, w:R|R
-BNDMOV         rBl,mBl       nil                       [       0x66 0x0F 0x1A /r]              s:MPX, t:MPX, w:W|R, a:NOA16
-BNDCL          rBl,Ey        nil                       [       0xF3 0x0F 0x1A /r]              s:MPX, t:MPX, w:R|R, a:AG|F64
-BNDCU          rBl,Ey        nil                       [       0xF2 0x0F 0x1A /r]              s:MPX, t:MPX, w:R|R, a:AG|F64
+BNDMOV         rBl,mBl       nil                       [       0x66 0x0F 0x1A /r]              s:MPX, t:MPX, w:W|R, a:NOA16|I67
+BNDCL          rBl,Ey        nil                       [       0xF3 0x0F 0x1A /r]              s:MPX, t:MPX, w:R|R, a:AG|F64|I67
+BNDCU          rBl,Ey        nil                       [       0xF2 0x0F 0x1A /r]              s:MPX, t:MPX, w:R|R, a:AG|F64|I67
 
-BNDSTX         Mmib,rBl      nil                       [            0x0F 0x1B /r:mem mib]      s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL
+BNDSTX         Mmib,rBl      nil                       [            0x0F 0x1B /r:mem mib]      s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL|I67
 NOP            Gv,Ev         nil                       [            0x0F 0x1B /r:reg]          s:PPRO, t:WIDENOP, w:R|R
-BNDMOV         mBl,rBl       nil                       [       0x66 0x0F 0x1B /r]              s:MPX, t:MPX, w:W|R, a:NOA16
-BNDMK          rBl,My        nil                       [       0xF3 0x0F 0x1B /r:mem]          s:MPX, t:MPX, w:W|R, a:F64|NOA16|NORIPREL
+BNDMOV         mBl,rBl       nil                       [       0x66 0x0F 0x1B /r]              s:MPX, t:MPX, w:W|R, a:NOA16|I67
+BNDMK          rBl,My        nil                       [       0xF3 0x0F 0x1B /r:mem]          s:MPX, t:MPX, w:W|R, a:F64|NOA16|NORIPREL|I67
 NOP            Gv,Ev         nil                       [       0xF3 0x0F 0x1B /r:reg]          s:PPRO, t:WIDENOP, w:R|R
-BNDCN          rBl,Ey        nil                       [       0xF2 0x0F 0x1B /r]              s:MPX, t:MPX, w:R|R, a:AG|F64
+BNDCN          rBl,Ey        nil                       [       0xF2 0x0F 0x1B /r]              s:MPX, t:MPX, w:R|R, a:AG|F64|I67
 
 CLDEMOTE       Mb            nil                       [         NP 0x0F 0x1C /0:mem]          s:CLDEMOTE, t:CLDEMOTE, w:W
 NOP            Ev,Gv         nil                       [       0x66 0x0F 0x1C /0:mem]          s:PPRO, t:WIDENOP, w:R|R
@@ -428,7 +429,7 @@ SETNC          Eb            Fv                        [            0x0F 0x93 /r
 SETZ           Eb            Fv                        [            0x0F 0x94 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CZ,    a:COND
 SETNZ          Eb            Fv                        [            0x0F 0x95 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNZ,   a:COND
 SETBE          Eb            Fv                        [            0x0F 0x96 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CBE,   a:COND
-SETNB          Eb            Fv                        [            0x0F 0x97 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNBE,  a:COND
+SETNBE         Eb            Fv                        [            0x0F 0x97 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNBE,  a:COND
 SETS           Eb            Fv                        [            0x0F 0x98 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CS,    a:COND
 SETNS          Eb            Fv                        [            0x0F 0x99 /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CNS,   a:COND
 SETP           Eb            Fv                        [            0x0F 0x9A /r]              s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CP,    a:COND
@@ -465,7 +466,9 @@ SHRD           Ev,Gv,Ib      Fv                        [            0x0F 0xAC /r
 SHRD           Ev,Gv,CL      Fv                        [            0x0F 0xAD /r]              s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD
 
 FXSAVE         Mrx           BANK                      [         NP 0x0F 0xAE /0:mem]          s:FXSAVE, t:SSE, w:W|R
+FXSAVE64       Mrx           BANK                      [    rexw NP 0x0F 0xAE /0:mem]          s:FXSAVE, t:SSE, w:W|R
 FXRSTOR        Mrx           BANK                      [         NP 0x0F 0xAE /1:mem]          s:FXSAVE, t:SSE, w:R|W
+FXRSTOR64      Mrx           BANK                      [    rexw NP 0x0F 0xAE /1:mem]          s:FXSAVE, t:SSE, w:R|W
 LDMXCSR        Md            MXCSR                     [         NP 0x0F 0xAE /2:mem]          s:SSE, t:SSE, w:R|W
 STMXCSR        Md            MXCSR                     [         NP 0x0F 0xAE /3:mem]          s:SSE, t:SSE, w:W|R
 XSAVE          M?            EDX,EAX,XCR0,BANK         [         NP 0x0F 0xAE /4:mem]          s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R
@@ -554,7 +557,7 @@ RDRAND         Rv            Fv                        [            0x0F 0xC7 /6
 RDRAND         Rv            Fv                        [       0x66 0x0F 0xC7 /6:reg]          s:RDRAND, t:RDRAND, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0
 RDSEED         Rv            Fv                        [            0x0F 0xC7 /7:reg]          s:RDSEED, t:RDSEED, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0
 RDSEED         Rv            Fv                        [       0x66 0x0F 0xC7 /7:reg]          s:RDSEED, t:RDSEED, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0
-RDPID          Rv            TSCAUX                    [       0xF3 0x0F 0xC7 /7:reg]          s:RDPID, t:RDPID, w:W|R
+RDPID          Ryf           TSCAUX                    [       0xF3 0x0F 0xC7 /7:reg]          s:RDPID, t:RDPID, w:W|R
 
 BSWAP          Zv            nil                       [            0x0F 0xC8]                 s:I486REAL, t:DATAXFER, w:RW
 BSWAP          Zv            nil                       [            0x0F 0xC9]                 s:I486REAL, t:DATAXFER, w:RW
@@ -614,7 +617,7 @@ PMULHUW        Vx,Wx         nil                       [       0x66 0x0F 0xE4 /r
 PMULHW         Pq,Qq         nil                       [         NP 0x0F 0xE5 /r]              s:MMX, t:MMX, w:RW|R
 PMULHW         Vx,Wx         nil                       [       0x66 0x0F 0xE5 /r]              s:SSE2, t:SSE, w:RW|R, e:4
 CVTTPD2DQ      Vx,Wpd        nil                       [       0x66 0x0F 0xE6 /r]              s:SSE2, t:CONVERT, w:W|R, e:2
-CVTDQ2PD       Vx,Wpd        nil                       [       0xF3 0x0F 0xE6 /r]              s:SSE2, t:CONVERT, w:W|R, e:5
+CVTDQ2PD       Vx,Wq         nil                       [       0xF3 0x0F 0xE6 /r]              s:SSE2, t:CONVERT, w:W|R, e:5
 CVTPD2DQ       Vx,Wpd        nil                       [       0xF2 0x0F 0xE6 /r]              s:SSE2, t:CONVERT, w:W|R, e:2
 MOVNTQ         Mq,Pq         nil                       [         NP 0x0F 0xE7 /r:mem]          s:MMX, t:DATAXFER, w:W|R
 MOVNTDQ        Mx,Vx         nil                       [       0x66 0x0F 0xE7 /r:mem]          s:SSE2, t:DATAXFER, w:W|R, e:1
diff --git a/isagenerator/instructions/table_3dnow.dat b/isagenerator/instructions/table_3dnow.dat
index 131ebe7..ae6efea 100644
--- a/isagenerator/instructions/table_3dnow.dat
+++ b/isagenerator/instructions/table_3dnow.dat
@@ -10,7 +10,7 @@ PFNACC         Pq,Qq         nil           [0x0F 0x0F /r 0x8A]         s:3DNOW,
 PFPNACC        Pq,Qq         nil           [0x0F 0x0F /r 0x8E]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
 PFCMPGE        Pq,Qq         nil           [0x0F 0x0F /r 0x90]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
 PFMIN          Pq,Qq         nil           [0x0F 0x0F /r 0x94]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
-PFMIN          Pq,Qq         nil           [0x0F 0x0F /r 0x96]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
+PFRCP          Pq,Qq         nil           [0x0F 0x0F /r 0x96]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
 PFRSQRT        Pq,Qq         nil           [0x0F 0x0F /r 0x97]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
 PFSUB          Pq,Qq         nil           [0x0F 0x0F /r 0x9A]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
 PFADD          Pq,Qq         nil           [0x0F 0x0F /r 0x9E]         s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW
diff --git a/isagenerator/instructions/table_base.dat b/isagenerator/instructions/table_base.dat
index 72135db..eb5842a 100644
--- a/isagenerator/instructions/table_base.dat
+++ b/isagenerator/instructions/table_base.dat
@@ -110,8 +110,10 @@ POP            Zv            Kv                [            0x5E]          s:I86
 POP            Zv            Kv                [            0x5F]          s:I86, t:POP,  w:W|R, a:D64 
 
 # 0x60 - 0x6F
-PUSHA          nil           BANK,Kv8          [            0x60]          s:I386, t:PUSH, w:R|W, m:NO64
-POPA           nil           BANK,Kv8          [            0x61]          s:I386, t:POP, w:W|R, m:NO64
+PUSHA          nil           BANK,Kv8          [       ds16 0x60]          s:I386, t:PUSH, w:R|W, m:NO64
+PUSHAD         nil           BANK,Kv8          [       ds32 0x60]          s:I386, t:PUSH, w:R|W, m:NO64
+POPA           nil           BANK,Kv8          [       ds16 0x61]          s:I386, t:POP, w:W|R, m:NO64
+POPAD          nil           BANK,Kv8          [       ds32 0x61]          s:I386, t:POP, w:W|R, m:NO64
 BOUND          Gv,Ma         nil               [            0x62 /r:mem]   s:I186, t:INTERRUPT, w:R|R, m:NO64
 ARPL           Ew,Gw         Fv                [            0x63 /r]       s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL|NO64
 MOVSXD         Gv,Ez         nil               [        o64 0x63 /r]       s:LONGMODE, t:DATAXFER, w:W|R, m:O64
@@ -174,14 +176,14 @@ SUB            Ev,Iz         Fv                [            0x81 /5 iz]    s:I86
 XOR            Ev,Iz         Fv                [            0x81 /6 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, p:HLE|LOCK
 CMP            Ev,Iz         Fv                [            0x81 /7 iz]    s:I86, t:ARITH, w:R|R|W,   f:ARITH,  a:OP2SEXO1
 
-ADD            Ev,Iz         Fv                [            0x82 /0 iz]    s:I86, t:ARITH, w:RW|R|W,  f:ARITH,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
-OR             Ev,Iz         Fv                [            0x82 /1 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
-ADC            Ev,Iz         Fv                [            0x82 /2 iz]    s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
-SBB            Ev,Iz         Fv                [            0x82 /3 iz]    s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
-AND            Ev,Iz         Fv                [            0x82 /4 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
-SUB            Ev,Iz         Fv                [            0x82 /5 iz]    s:I86, t:ARITH, w:RW|R|W,  f:ARITH,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
-XOR            Ev,Iz         Fv                [            0x82 /6 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
-CMP            Ev,Iz         Fv                [            0x82 /7 iz]    s:I86, t:ARITH, w:R|R|W,   f:ARITH,  a:OP2SEXO1, m:NO64
+ADD            Eb,Ib         Fv                [            0x82 /0 iz]    s:I86, t:ARITH, w:RW|R|W,  f:ARITH,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
+OR             Eb,Ib         Fv                [            0x82 /1 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
+ADC            Eb,Ib         Fv                [            0x82 /2 iz]    s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
+SBB            Eb,Ib         Fv                [            0x82 /3 iz]    s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
+AND            Eb,Ib         Fv                [            0x82 /4 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
+SUB            Eb,Ib         Fv                [            0x82 /5 iz]    s:I86, t:ARITH, w:RW|R|W,  f:ARITH,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
+XOR            Eb,Ib         Fv                [            0x82 /6 iz]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, m:NO64, p:HLE|LOCK
+CMP            Eb,Ib         Fv                [            0x82 /7 iz]    s:I86, t:ARITH, w:R|R|W,   f:ARITH,  a:OP2SEXO1, m:NO64
 
 ADD            Ev,Ib         Fv                [            0x83 /0 ib]    s:I86, t:ARITH, w:RW|R|W,  f:ARITH,  a:OP2SEXO1, p:HLE|LOCK
 OR             Ev,Ib         Fv                [            0x83 /1 ib]    s:I86, t:LOGIC, w:RW|R|W,  f:LOGIC,  a:OP2SEXO1, p:HLE|LOCK
@@ -324,17 +326,17 @@ SHL            Ev,Ib         Fv                [            0xC1 /4 ib]    s:I86
 SHR            Ev,Ib         Fv                [            0xC1 /5 ib]    s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
 SAL            Ev,Ib         Fv                [            0xC1 /6 ib]    s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
 SAR            Ev,Ib         Fv                [            0xC1 /7 ib]    s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
-RETN           Iw            rIP,sSP,Kv,SHS1   [            0xC2 iw]       s:I86, t:RET, w:R|W|W|R|R, a:F64|OP1SEXDW, p:BND
+RETN           Iw            rIP,sSP,Kv,SHS1   [            0xC2 iw]       s:I86, t:RET, w:R|W|W|R|R, a:F64, p:BND
 RETN           nil           rIP,Kv,SHS1       [            0xC3]          s:I86, t:RET, w:W|R|R, a:F64, p:BND
 LES            Gz,Mp         ES                [            0xC4 /r:mem]   s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX
 LDS            Gz,Mp         DS                [            0xC5 /r:mem]   s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX
 MOV            Eb,Ib         nil               [            0xC6 /0 ib]    s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL
 XABORT         Ib            EAX               [            0xC6 /0xF8 ib] s:TSX, t:UNCOND_BR, w:R|RCW, i:RTM, m:NOTSX
 MOV            Ev,Iz         nil               [            0xC7 /0 iz]    s:I86, t:DATAXFER, w:W|R, a:OP2SEXO1, p:XRELEASE|HLEWOL
-XBEGIN         Jz            rIP,EAX           [            0xC7 /0xF8 cz] s:TSX, t:COND_BR, w:R|RW|CW, i:RTM
+XBEGIN         Jz            yIP,EAX           [            0xC7 /0xF8 cz] s:TSX, t:COND_BR, w:R|RW|CW, i:RTM
 ENTER          Iw,Ib         rBP,sSP,Kv        [            0xC8 iw ib]    s:I186, t:MISC, w:R|R|RW|RW|W
 LEAVE          nil           sBP,rBP,rSP,Kv    [            0xC9]          s:I186, t:MISC, w:R|RW|RW|R, a:D64
-RETF           Iw            CS,rIP,Kv2,SHS2   [            0xCA iw]       s:I86, t:RET, a:OP1SEXDW, w:R|W|W|R|R
+RETF           Iw            CS,rIP,Kv2,SHS2   [            0xCA iw]       s:I86, t:RET, w:R|W|W|R|R
 RETF           nil           CS,rIP,Kv2,SHS2   [            0xCB]          s:I86, t:RET, w:W|W|R|R
 INT3           nil           CS,rIP,Kv3,Fv,SHS3 [           0xCC]          s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, f:INT, m:NOSGX
 INT            Ib            CS,rIP,Kv3,Fv,SHS3 [           0xCD ib]       s:I86, t:INTERRUPT, w:R|RW|RW|RW|W|W, f:INT, m:NOSGX
diff --git a/isagenerator/instructions/table_evex1.dat b/isagenerator/instructions/table_evex1.dat
index f6a81b3..3748adb 100644
--- a/isagenerator/instructions/table_evex1.dat
+++ b/isagenerator/instructions/table_evex1.dat
@@ -39,7 +39,7 @@ VMOVAPD              Vn{K}{z},Wn                  nil       [evex m:1 p:1 l:x w:
 VMOVAPS              Wn{K}{z},Vn                  nil       [evex m:1 p:0 l:x w:0 0x29 /r]             s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
 VMOVAPD              Wn{K}{z},Vn                  nil       [evex m:1 p:1 l:x w:1 0x29 /r]             s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
 VCVTSI2SS            Vdq,Hdq{er},Ey               nil       [evex m:1 p:2 l:i w:x 0x2A /r]             s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
-VCVTSI2SD            Vdq,Hdq{er},Ey               nil       [evex m:1 p:3 l:i w:0 0x2A /r]             s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R
+VCVTSI2SD            Vdq,Hdq,Ey                   nil       [evex m:1 p:3 l:i w:0 0x2A /r]             s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER
 VCVTSI2SD            Vdq,Hdq{er},Ey               nil       [evex m:1 p:3 l:i w:1 0x2A /r]             s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
 VMOVNTPS             Mn,Vn                        nil       [evex m:1 p:0 l:x w:0 0x2B /r:mem]         s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
 VMOVNTPD             Mn,Vn                        nil       [evex m:1 p:1 l:x w:1 0x2B /r:mem]         s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
@@ -126,9 +126,9 @@ VMOVDQU16            Vn{K}{z},Wn                  nil       [evex m:1 p:3 l:x w:
 VPSHUFD              Vn{K}{z},Wn|B32,Ib           nil       [evex m:1 p:1 l:x w:0 0x70 /r ib]          s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
 VPSHUFHW             Vn{K}{z},Wn,Ib               nil       [evex m:1 p:2 l:x w:i 0x70 /r ib]          s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
 VPSHUFLW             Vn{K}{z},Wn,Ib               nil       [evex m:1 p:3 l:x w:i 0x70 /r ib]          s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
-VPSRLW               Hn{K}{z},Wn,Ib               nil       [evex m:1 p:1 l:x w:i 0x71 /2 ib]          s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R
-VPSRAW               Hn{K}{z},Wn,Ib               nil       [evex m:1 p:1 l:x w:i 0x71 /4 ib]          s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R
-VPSLLW               Hn{K}{z},Wn,Ib               nil       [evex m:1 p:1 l:x w:i 0x71 /6 ib]          s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R
+VPSRLW               Hn{K}{z},Wn,Ib               nil       [evex m:1 p:1 l:x w:i 0x71 /2 ib]          s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
+VPSRAW               Hn{K}{z},Wn,Ib               nil       [evex m:1 p:1 l:x w:i 0x71 /4 ib]          s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
+VPSLLW               Hn{K}{z},Wn,Ib               nil       [evex m:1 p:1 l:x w:i 0x71 /6 ib]          s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
 VPRORD               Hn{K}{z},Wn|B32,Ib           nil       [evex m:1 p:1 l:x w:0 0x72 /0 ib]          s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
 VPRORQ               Hn{K}{z},Wn|B64,Ib           nil       [evex m:1 p:1 l:x w:1 0x72 /0 ib]          s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
 VPROLD               Hn{K}{z},Wn|B32,Ib           nil       [evex m:1 p:1 l:x w:0 0x72 /1 ib]          s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
@@ -153,19 +153,19 @@ VCVTTSD2USI          Gy,Wsd{sae}                  nil       [evex m:1 p:3 l:i w:
 VCVTPS2UDQ           Vn{K}{z},Wn|B32{er}          nil       [evex m:1 p:0 l:x w:0 0x79 /r]             s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTPD2UDQ           Vh{K}{z},Wn|B64{er}          nil       [evex m:1 p:0 l:x w:1 0x79 /r]             s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTPS2UQQ           Vn{K}{z},Wh|B32{er}          nil       [evex m:1 p:1 l:x w:0 0x79 /r]             s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
-VCVTPD2UQQ           Vn{K}{z},Wn|B64{er}          nil       [evex m:1 p:1 l:x w:1 0x79 /r]             s:AVX512DQ, t:CONVERT, l:hv, e:E2, w:W|R|R
+VCVTPD2UQQ           Vn{K}{z},Wn|B64{er}          nil       [evex m:1 p:1 l:x w:1 0x79 /r]             s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTSS2USI           Gy,Wss{er}                   nil       [evex m:1 p:2 l:i w:x 0x79 /r]             s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
 VCVTSD2USI           Gy,Wsd{er}                   nil       [evex m:1 p:3 l:i w:x 0x79 /r]             s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
 VCVTTPS2QQ           Vn{K}{z},Wh|B32{sae}         nil       [evex m:1 p:1 l:x w:0 0x7A /r]             s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
 VCVTTPD2QQ           Vn{K}{z},Wn|B64{sae}         nil       [evex m:1 p:1 l:x w:1 0x7A /r]             s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
-VCVTUDQ2PD           Vn{K}{z},Wh|B32              nil       [evex m:1 p:2 l:x w:0 0x7A /r]             s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R
+VCVTUDQ2PD           Vn{K}{z},Wh|B32              nil       [evex m:1 p:2 l:x w:0 0x7A /r]             s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
 VCVTUQQ2PD           Vn{K}{z},Wn|B64{er}          nil       [evex m:1 p:2 l:x w:1 0x7A /r]             s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTUDQ2PS           Vn{K}{z},Wn|B32{er}          nil       [evex m:1 p:3 l:x w:0 0x7A /r]             s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTUQQ2PS           Vh{K}{z},Wn|B64{er}          nil       [evex m:1 p:3 l:x w:1 0x7A /r]             s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTPS2QQ            Vn{K}{z},Wh|B32{er}          nil       [evex m:1 p:1 l:x w:0 0x7B /r]             s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
 VCVTPD2QQ            Vn{K}{z},Wn|B64{er}          nil       [evex m:1 p:1 l:x w:1 0x7B /r]             s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTUSI2SS           Vss,Hss{er},Ey               nil       [evex m:1 p:2 l:i w:x 0x7B /r]             s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
-VCVTUSI2SD           Vdq,Hdq{er},Ey               nil       [evex m:1 p:3 l:i w:0 0x7B /r]             s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R
+VCVTUSI2SD           Vdq,Hdq,Ey                   nil       [evex m:1 p:3 l:i w:0 0x7B /r]             s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER
 VCVTUSI2SD           Vdq,Hdq{er},Ey               nil       [evex m:1 p:3 l:i w:1 0x7B /r]             s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
 VMOVD                Ey,Vdq                       nil       [evex m:1 p:1 l:0 w:0 0x7E /r]             s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
 VMOVQ                Ey,Vdq                       nil       [evex m:1 p:1 l:0 w:1 0x7E /r]             s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
@@ -190,8 +190,8 @@ VCMPPS               rKq{K},Hn,Wn|B32{sae},Ib     nil       [evex m:1 p:0 l:x w:
 VCMPPD               rKq{K},Hn,Wn|B64{sae},Ib     nil       [evex m:1 p:1 l:x w:1 0xC2 /r ib]          s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
 VCMPSS               rKq{K},Hdq,Wss{sae},Ib       nil       [evex m:1 p:2 l:x w:0 0xC2 /r ib]          s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
 VCMPSD               rKq{K},Hdq,Wsd{sae},Ib       nil       [evex m:1 p:3 l:x w:1 0xC2 /r ib]          s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
-VPINSRW              Vdq,Hdq,Mw,Ib                nil       [evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
-VPINSRW              Vdq,Hdq,Rv,Ib                nil       [evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
+VPINSRW              Vdq,Hdq,Mw,Ib                nil       [evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R
+VPINSRW              Vdq,Hdq,Rv,Ib                nil       [evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R
 VPEXTRW              Gy,Udq,Ib                    nil       [evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
 VSHUFPS              Vn{K}{z},Hn,Wn|B32,Ib        nil       [evex m:1 p:0 l:x w:0 0xC6 /r ib]          s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
 VSHUFPD              Vn{K}{z},Hn,Wn|B64,Ib        nil       [evex m:1 p:1 l:x w:1 0xC6 /r ib]          s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
@@ -223,7 +223,7 @@ VPAVGW               Vn{K}{z},Hn,Wn               nil       [evex m:1 p:1 l:x w:
 VPMULHUW             Vn{K}{z},Hn,Wn               nil       [evex m:1 p:1 l:x w:i 0xE4 /r]             s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
 VPMULHW              Vn{K}{z},Hn,Wn               nil       [evex m:1 p:1 l:x w:i 0xE5 /r]             s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
 VCVTTPD2DQ           Vh{K}{z},Wn|B64{sae}         nil       [evex m:1 p:1 l:x w:1 0xE6 /r]             s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
-VCVTDQ2PD            Vn{K}{z},Wh|B32              nil       [evex m:1 p:2 l:x w:0 0xE6 /r]             s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R
+VCVTDQ2PD            Vn{K}{z},Wh|B32              nil       [evex m:1 p:2 l:x w:0 0xE6 /r]             s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
 VCVTQQ2PD            Vn{K}{z},Wn|B64{er}          nil       [evex m:1 p:2 l:x w:1 0xE6 /r]             s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
 VCVTPD2DQ            Vh{K}{z},Wn|B64{er}          nil       [evex m:1 p:3 l:x w:1 0xE6 /r]             s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
 VMOVNTDQ             Mn,Vn                        nil       [evex m:1 p:1 l:x w:0 0xE7 /r:mem]         s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
diff --git a/isagenerator/instructions/table_evex2.dat b/isagenerator/instructions/table_evex2.dat
index 01c875a..22b20f7 100644
--- a/isagenerator/instructions/table_evex2.dat
+++ b/isagenerator/instructions/table_evex2.dat
@@ -152,10 +152,10 @@ VBROADCASTI32X8      Voq{K}{z},Mqq                nil       [evex m:2 p:1 l:2 w:
 VBROADCASTI64X4      Voq{K}{z},Mqq                nil       [evex m:2 p:1 l:2 w:1 0x5B /r:mem]         s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R
 
 # 0x60 - 0x6F
-VPEXPANDB            Vn{K}{z},Wn                  nil       [evex m:2 p:1 l:x w:0 0x62 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s, e:E4, w:W|R|R
-VPEXPANDW            Vn{K}{z},Wn                  nil       [evex m:2 p:1 l:x w:1 0x62 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s, e:E4, w:W|R|R
-VPCOMPRESSB          Wn{K}{z},Vn                  nil       [evex m:2 p:1 l:x w:0 0x63 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s, a:NOMZ, e:E4, w:W|R|R
-VPCOMPRESSW          Wn{K}{z},Vn                  nil       [evex m:2 p:1 l:x w:1 0x63 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s, a:NOMZ, e:E4, w:W|R|R
+VPEXPANDB            Vn{K}{z},Wn                  nil       [evex m:2 p:1 l:x w:0 0x62 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s8, e:E4, w:W|R|R
+VPEXPANDW            Vn{K}{z},Wn                  nil       [evex m:2 p:1 l:x w:1 0x62 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s16, e:E4, w:W|R|R
+VPCOMPRESSB          Wn{K}{z},Vn                  nil       [evex m:2 p:1 l:x w:0 0x63 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s8, a:NOMZ, e:E4, w:W|R|R
+VPCOMPRESSW          Wn{K}{z},Vn                  nil       [evex m:2 p:1 l:x w:1 0x63 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:t1s16, a:NOMZ, e:E4, w:W|R|R
 VPBLENDMD            Vn{K}{z},Hn,Wn|B32           nil       [evex m:2 p:1 l:x w:0 0x64 /r]             s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R
 VPBLENDMQ            Vn{K}{z},Hn,Wn|B64           nil       [evex m:2 p:1 l:x w:1 0x64 /r]             s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R
 VBLENDMPS            Vn{K}{z},Hn,Wn|B32           nil       [evex m:2 p:1 l:x w:0 0x65 /r]             s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R
@@ -171,7 +171,7 @@ VPSHLDVW             Vn{K}{z},Hn,Wn               nil       [evex m:2 p:1 l:x w:
 VPSHLDVD             Vn{K}{z},Hn,Wn|B32           nil       [evex m:2 p:1 l:x w:0 0x71 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
 VPSHLDVQ             Vn{K}{z},Hn,Wn|B64           nil       [evex m:2 p:1 l:x w:1 0x71 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
 VPSHRDVW             Vn{K}{z},Hn,Wn               nil       [evex m:2 p:1 l:x w:1 0x72 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R
-VCVTNEPS2BF16        Vh{K}{z},Wn                  nil       [evex m:2 p:2 l:x w:0 0x72 /r]             s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R
+VCVTNEPS2BF16        Vh{K}{z},Wn|B32              nil       [evex m:2 p:2 l:x w:0 0x72 /r]             s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R
 VCVTNE2PS2BF16       Vn{K}{z},Hn,Wn|B32           nil       [evex m:2 p:3 l:x w:0 0x72 /r]             s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R
 VPSHRDVD             Vn{K}{z},Hn,Wn|B32           nil       [evex m:2 p:1 l:x w:0 0x73 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
 VPSHRDVQ             Vn{K}{z},Hn,Wn|B64           nil       [evex m:2 p:1 l:x w:1 0x73 /r]             s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
diff --git a/isagenerator/instructions/table_evex3.dat b/isagenerator/instructions/table_evex3.dat
index 117b655..4effa4e 100644
--- a/isagenerator/instructions/table_evex3.dat
+++ b/isagenerator/instructions/table_evex3.dat
@@ -14,10 +14,10 @@ VRNDSCALESD          Vdq{K}{z},Hdq,Wsd{sae},Ib    nil       [evex m:3 p:1 l:i w:
 VPALIGNR             Vn{K}{z},Hn,Wn,Ib            nil       [evex m:3 p:1 l:x w:i 0x0F /r ib]          s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
 
 # 0x10 - 0x1F
-VPEXTRB              Mb,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x14 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
-VPEXTRB              Ry,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
-VPEXTRW              Mw,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x15 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
-VPEXTRW              Ry,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
+VPEXTRB              Mb,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x14 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R
+VPEXTRB              Ry,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R
+VPEXTRW              Mw,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x15 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R
+VPEXTRW              Ry,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R
 VPEXTRD              Ed,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:0 0x16 /r ib]          s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R
 VPEXTRQ              Eq,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:1 0x16 /r ib]          s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R
 VEXTRACTPS           Md,Vdq,Ib                    nil       [evex m:3 p:1 l:0 w:i 0x17 /r:mem ib]      s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
@@ -37,8 +37,8 @@ VPCMPD               rKq{K},Hn,Wn|B32,Ib          nil       [evex m:3 p:1 l:x w:
 VPCMPQ               rKq{K},Hn,Wn|B64,Ib          nil       [evex m:3 p:1 l:x w:1 0x1F /r ib]          s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
 
 # 0x20 - 0x2F
-VPINSRB              Vdq,Hdq,Mb,Ib                nil       [evex m:3 p:1 l:0 w:i 0x20 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
-VPINSRB              Vdq,Hdq,Rd,Ib                nil       [evex m:3 p:1 l:0 w:i 0x20 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
+VPINSRB              Vdq,Hdq,Mb,Ib                nil       [evex m:3 p:1 l:0 w:i 0x20 /r:mem ib]      s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
+VPINSRB              Vdq,Hdq,Rd,Ib                nil       [evex m:3 p:1 l:0 w:i 0x20 /r:reg ib]      s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
 VINSERTPS            Vdq,Hdq,Md,Ib                nil       [evex m:3 p:1 l:0 w:i 0x21 /r:mem ib]      s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
 VINSERTPS            Vdq,Hdq,Udq,Ib               nil       [evex m:3 p:1 l:0 w:i 0x21 /r:reg ib]      s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
 VPINSRD              Vdq,Hdq,Ed,Ib                nil       [evex m:3 p:1 l:0 w:0 0x22 /r ib]          s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
diff --git a/isagenerator/instructions/table_fpu.dat b/isagenerator/instructions/table_fpu.dat
index 8cb6864..590e538 100644
--- a/isagenerator/instructions/table_fpu.dat
+++ b/isagenerator/instructions/table_fpu.dat
@@ -108,8 +108,8 @@ FDIV           ST(0),Mfq     X87STATUS                   [0xDC /6:mem]         s
 FDIVR          ST(0),Mfq     X87STATUS                   [0xDC /7:mem]         s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
 FADD           ST(i),ST(0)   X87STATUS                   [0xDC /0:reg]         s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
 FMUL           ST(i),ST(0)   X87STATUS                   [0xDC /1:reg]         s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
-FCOM           ST(i),ST(0)   X87STATUS                   [0xDC /2:reg]         s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
-FCOMP          ST(i),ST(0)   X87STATUS                   [0xDC /3:reg]         s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
+FCOM           ST(0),ST(i)   X87STATUS                   [0xDC /2:reg]         s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
+FCOMP          ST(0),ST(i)   X87STATUS                   [0xDC /3:reg]         s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
 FSUBR          ST(i),ST(0)   X87STATUS                   [0xDC /4:reg]         s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
 FSUB           ST(i),ST(0)   X87STATUS                   [0xDC /5:reg]         s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
 FDIVR          ST(i),ST(0)   X87STATUS                   [0xDC /6:reg]         s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
@@ -126,8 +126,8 @@ FNSAVE         Mfs           X87CONTROL,X87TAG,X87STATUS [0xDD /6:mem]         s
 FNSTSW         Mw            X87STATUS                   [0xDD /7:mem]         s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u
 FFREE          ST(i)         X87TAG                      [0xDD /0:reg]         s:X87, t:X87_ALU, w:R|W, u:C0=u|C1=u|C2=u|C3=u
 FXCH           ST(0),ST(i)   X87STATUS                   [0xDD /1:reg]         s:X87, t:X87_ALU, w:W|R|W, u:C1=0
-FST            ST(0),ST(i)   X87STATUS                   [0xDD /2:reg]         s:X87, t:X87_ALU, w:W|R|W, u:C1=m
-FSTP           ST(0),ST(i)   X87STATUS                   [0xDD /3:reg]         s:X87, t:X87_ALU, w:W|R|W, u:C1=m
+FST            ST(i),ST(0)   X87STATUS                   [0xDD /2:reg]         s:X87, t:X87_ALU, w:W|R|W, u:C1=m
+FSTP           ST(i),ST(0)   X87STATUS                   [0xDD /3:reg]         s:X87, t:X87_ALU, w:W|R|W, u:C1=m
 FUCOM          ST(0),ST(i)   X87STATUS                   [0xDD /4:reg]         s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
 FUCOMP         ST(0),ST(i)   X87STATUS                   [0xDD /5:reg]         s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
 
diff --git a/isagenerator/instructions/table_vex1.dat b/isagenerator/instructions/table_vex1.dat
index 3909a2c..49ed280 100644
--- a/isagenerator/instructions/table_vex1.dat
+++ b/isagenerator/instructions/table_vex1.dat
@@ -238,13 +238,13 @@ CLEVICT1            M?                    nil               [vex m:1 p:2 0xAE /7
 # 0xB0 - 0xBF
 
 # 0xC0 - 0xCF
-VCMPSS              Vss,Hss,Wss,Ib        nil               [vex m:1 p:0 l:i w:i 0xC2 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:3
+VCMPPS              Vss,Hss,Wss,Ib        nil               [vex m:1 p:0 l:i w:i 0xC2 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:3
 VCMPPD              Vpd,Hpd,Wpd,Ib        nil               [vex m:1 p:1 l:x w:i 0xC2 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:3
 VCMPSS              Vss,Hss,Wss,Ib        nil               [vex m:1 p:2 l:i w:i 0xC2 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:3
 VCMPSD              Vsd,Hsd,Wsd,Ib        nil               [vex m:1 p:3 l:i w:i 0xC2 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:3
-VPINSRW             Vdq,Hdq,Mw,Ib         nil               [vex m:1 p:1 l:0 w:0 0xC4 /r:mem ib]    s:AVX, t:AVX, w:W|R|R|R, e:5
-VPINSRW             Vdq,Hdq,Ry,Ib         nil               [vex m:1 p:1 l:0 w:0 0xC4 /r:reg ib]    s:AVX, t:AVX, w:W|R|R|R, e:5
-VPEXTRW             Gy,Udq,Ib             nil               [vex m:1 p:1 l:0 w:0 0xC5 /r:reg ib]    s:AVX, t:AVX, w:W|R|R, e:5
+VPINSRW             Vdq,Hdq,Mw,Ib         nil               [vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib]    s:AVX, t:AVX, w:W|R|R|R, e:5
+VPINSRW             Vdq,Hdq,Rd,Ib         nil               [vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib]    s:AVX, t:AVX, w:W|R|R|R, e:5
+VPEXTRW             Gy,Udq,Ib             nil               [vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib]    s:AVX, t:AVX, w:W|R|R, e:5
 VSHUFPS             Vps,Hps,Wps,Ib        nil               [vex m:1 p:0 l:x w:i 0xC6 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:4
 VSHUFPD             Vpd,Hpd,Wpd,Ib        nil               [vex m:1 p:1 l:x w:i 0xC6 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:4
 
diff --git a/isagenerator/instructions/table_vex2.dat b/isagenerator/instructions/table_vex2.dat
index ef5f783..4df1342 100644
--- a/isagenerator/instructions/table_vex2.dat
+++ b/isagenerator/instructions/table_vex2.dat
@@ -132,20 +132,20 @@ VFMSUBADD132PS      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0
 VFMSUBADD132PD      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0x97 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMADD132PS         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0x98 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMADD132PD         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0x98 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFMADD132SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:x w:0 0x99 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFMADD132SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:x w:1 0x99 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMADD132SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0x99 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMADD132SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0x99 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFMSUB132PS         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0x9A /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMSUB132PD         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0x9A /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFMSUB132SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:x w:0 0x9B /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFMSUB132SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:x w:1 0x9B /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMSUB132SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0x9B /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMSUB132SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0x9B /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMADD132PS        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0x9C /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMADD132PD        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0x9C /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMADD132SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0x9D /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMADD132SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0x9D /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMSUB132PS        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0x9E /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMSUB132PD        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0x9E /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFNMSUB132SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0x9F /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFNMSUB132SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0x9F /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMSUB132SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0x9F /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMSUB132SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0x9F /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 
 # 0xA0 - 0xAF
 VFMADDSUB213PS      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xA6 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
@@ -154,20 +154,20 @@ VFMSUBADD213PS      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0
 VFMSUBADD213PD      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xA7 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMADD213PS         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xA8 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMADD213PD         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xA8 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFMADD213SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xA9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFMADD213SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xA9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMADD213SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xA9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMADD213SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xA9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFMSUB213PS         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xAA /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMSUB213PD         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xAA /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFMSUB213SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xAB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFMSUB213SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xAB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMSUB213SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xAB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMSUB213SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xAB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMADD213PS        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xAC /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMADD213PD        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xAC /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFNMADD213SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xAD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFNMADD213SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xAD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMADD213SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xAD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMADD213SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xAD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMSUB213PS        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xAE /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMSUB213PD        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xAE /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFNMSUB213SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xAF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFNMSUB213SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xAF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMSUB213SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xAF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMSUB213SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xAF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 
 # 0xB0 - 0xBF
 VFMADDSUB231PS      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xB6 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
@@ -176,20 +176,20 @@ VFMSUBADD231PS      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0
 VFMSUBADD231PD      Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xB7 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMADD231PS         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xB8 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMADD231PD         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xB8 /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFMADD231SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xB9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFMADD231SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xB9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMADD231SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xB9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMADD231SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xB9 /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFMSUB231PS         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xBA /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFMSUB231PD         Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xBA /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFMSUB231SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xBB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFMSUB231SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xBB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMSUB231SS         Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xBB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFMSUB231SD         Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xBB /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMADD231PS        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xBC /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMADD231PD        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xBC /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFNMADD231SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xBD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFNMADD231SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xBD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMADD231SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xBD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMADD231SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xBD /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VFNMSUB231PS        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xBE /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
 VFNMSUB231PD        Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:1 0xBE /r]           s:FMA, t:VFMA, w:RW|R|R, e:2
-VFNMSUB231SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:0 w:0 0xBF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
-VFNMSUB231SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:0 w:1 0xBF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMSUB231SS        Vdq,Hdq,Wss           nil               [vex m:2 p:1 l:i w:0 0xBF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
+VFNMSUB231SD        Vdq,Hdq,Wsd           nil               [vex m:2 p:1 l:i w:1 0xBF /r]           s:FMA, t:VFMA, w:RW|R|R, e:3
 VGF2P8MULB          Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:0 0xCF /r]           s:GFNI, t:GFNI, w:W|R|R
 VAESIMC             Vdq,Wdq               nil               [vex m:2 p:1 l:0 w:i 0xDB /r]           s:AES, t:AES, w:W|R, e:4
 VAESENC             Vx,Hx,Wx              nil               [vex m:2 p:1 l:x w:i 0xDC /r]           s:AES, t:AES, w:W|R|R, e:4
diff --git a/isagenerator/instructions/table_vex3.dat b/isagenerator/instructions/table_vex3.dat
index c6cb049..70100d3 100644
--- a/isagenerator/instructions/table_vex3.dat
+++ b/isagenerator/instructions/table_vex3.dat
@@ -17,10 +17,10 @@ VPBLENDW            Vx,Hx,Wx,Ib           nil               [vex m:3 p:1 l:x w:i
 VPALIGNR            Vx,Hx,Wx,Ib           nil               [vex m:3 p:1 l:x w:i 0x0F /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:4
 
 # 0x10 - 0x1F
-VPEXTRB             Mb,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:0 0x14 /r:mem ib]    s:AVX, t:AVX, w:W|R|R, e:5
-VPEXTRB             Ry,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:0 0x14 /r:reg ib]    s:AVX, t:AVX, w:W|R|R, e:5
-VPEXTRW             Mw,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:0 0x15 /r:mem ib]    s:AVX, t:AVX, w:W|R|R, e:5
-VPEXTRW             Ry,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:0 0x15 /r:reg ib]    s:AVX, t:AVX, w:W|R|R, e:5
+VPEXTRB             Mb,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:i 0x14 /r:mem ib]    s:AVX, t:AVX, w:W|R|R, e:5
+VPEXTRB             Rd,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:i 0x14 /r:reg ib]    s:AVX, t:AVX, w:W|R|R, e:5
+VPEXTRW             Mw,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:i 0x15 /r:mem ib]    s:AVX, t:AVX, w:W|R|R, e:5
+VPEXTRW             Rd,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:i 0x15 /r:reg ib]    s:AVX, t:AVX, w:W|R|R, e:5
 VPEXTRD             Ey,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:0 0x16 /r ib]        s:AVX, t:AVX, w:W|R|R, e:5
 VPEXTRQ             Ey,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:1 0x16 /r ib]        s:AVX, t:AVX, w:W|R|R, e:5
 VEXTRACTPS          Md,Vdq,Ib             nil               [vex m:3 p:1 l:0 w:i 0x17 /r:mem ib]    s:AVX, t:AVX, w:W|R|R, e:5
@@ -54,12 +54,12 @@ VEXTRACTI128        Wdq,Vqq,Ib            nil               [vex m:3 p:1 l:1 w:0
 VDPPS               Vx,Hx,Wx,Ib           nil               [vex m:3 p:1 l:x w:i 0x40 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:2
 VDPPD               Vdq,Hdq,Wdq,Ib        nil               [vex m:3 p:1 l:0 w:i 0x41 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:2
 VMPSADBW            Vx,Hx,Wx,Ib           nil               [vex m:3 p:1 l:x w:i 0x42 /r ib]        s:AVX, t:AVX, w:W|R|R|R, e:4
-VPCLMULQDQ          Vdq,Hdq,Wdq,Ib        nil               [vex m:3 p:1 l:0 w:i 0x44 /r ib]        s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4
+VPCLMULQDQ          Vx,Hx,Wx,Ib           nil               [vex m:3 p:1 l:x w:i 0x44 /r ib]        s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4
 VPERM2I128          Vqq,Hqq,Wqq,Ib        nil               [vex m:3 p:1 l:1 w:0 0x46 /r ib]        s:AVX2, t:AVX2, w:W|R|R|R, e:6
-VPERMILzz2PS        Vx,Hx,Wx,Lx,Ib        nil               [vex m:3 p:1 l:x w:0 0x48 /r ib]        s:XOP, t:XOP, w:W|R|R|R|R, e:4
-VPERMILzz2PS        Vx,Hx,Lx,Wx,Ib        nil               [vex m:3 p:1 l:x w:1 0x48 /r ib]        s:XOP, t:XOP, w:W|R|R|R|R, e:4
-VPERMILzz2PD        Vx,Hx,Wx,Lx,Ib        nil               [vex m:3 p:1 l:x w:0 0x49 /r ib]        s:XOP, t:XOP, w:W|R|R|R|R, e:4
-VPERMILzz2PD        Vx,Hx,Lx,Wx,Ib        nil               [vex m:3 p:1 l:x w:1 0x49 /r ib]        s:XOP, t:XOP, w:W|R|R|R|R, e:4
+VPERMIL2PS          Vx,Hx,Wx,Lx,m2zIb     nil               [vex m:3 p:1 l:x w:0 0x48 /r is4]       s:XOP, t:XOP, w:W|R|R|R|R, e:4
+VPERMIL2PS          Vx,Hx,Lx,Wx,m2zIb     nil               [vex m:3 p:1 l:x w:1 0x48 /r is4]       s:XOP, t:XOP, w:W|R|R|R|R, e:4
+VPERMIL2PD          Vx,Hx,Wx,Lx,m2zIb     nil               [vex m:3 p:1 l:x w:0 0x49 /r is4]       s:XOP, t:XOP, w:W|R|R|R|R, e:4
+VPERMIL2PD          Vx,Hx,Lx,Wx,m2zIb     nil               [vex m:3 p:1 l:x w:1 0x49 /r is4]       s:XOP, t:XOP, w:W|R|R|R|R, e:4
 VBLENDVPS           Vx,Hx,Wx,Lx           nil               [vex m:3 p:1 l:x w:0 0x4A /r is4]       s:AVX, t:AVX, w:W|R|R|R, e:4
 VBLENDVPD           Vx,Hx,Wx,Lx           nil               [vex m:3 p:1 l:x w:0 0x4B /r is4]       s:AVX, t:AVX, w:W|R|R|R, e:4
 VPBLENDVB           Vx,Hx,Wx,Lx           nil               [vex m:3 p:1 l:x w:0 0x4C /r is4]       s:AVX, t:AVX, w:W|R|R|R, e:4
diff --git a/isagenerator/instructions/table_xop.dat b/isagenerator/instructions/table_xop.dat
index 04292f5..f6d9af9 100644
--- a/isagenerator/instructions/table_xop.dat
+++ b/isagenerator/instructions/table_xop.dat
@@ -118,9 +118,9 @@ VPROTQ              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x93 /r]
 VPROTQ              Vdq,Hdq,Wdq           nil           [xop m:9 w:1 0x93 /r]       s:XOP, t:XOP, w:W|R|R
 VPSHLB              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x94 /r]       s:XOP, t:XOP, w:W|R|R
 VPSHLB              Vdq,Hdq,Wdq           nil           [xop m:9 w:1 0x94 /r]       s:XOP, t:XOP, w:W|R|R
-VPSHLB              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x95 /r]       s:XOP, t:XOP, w:W|R|R
+VPSHLW              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x95 /r]       s:XOP, t:XOP, w:W|R|R
 VPSHLB              Vdq,Hdq,Wdq           nil           [xop m:9 w:1 0x95 /r]       s:XOP, t:XOP, w:W|R|R
-VPSHLB              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x96 /r]       s:XOP, t:XOP, w:W|R|R
+VPSHLD              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x96 /r]       s:XOP, t:XOP, w:W|R|R
 VPSHLB              Vdq,Hdq,Wdq           nil           [xop m:9 w:1 0x96 /r]       s:XOP, t:XOP, w:W|R|R
 VPSHLQ              Vdq,Wdq,Hdq           nil           [xop m:9 w:0 0x97 /r]       s:XOP, t:XOP, w:W|R|R
 VPSHLQ              Vdq,Hdq,Wdq           nil           [xop m:9 w:1 0x97 /r]       s:XOP, t:XOP, w:W|R|R