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@ -1150,11 +1150,11 @@ ShemuGetOperandValue(
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break;
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break;
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case ND_REG_RIP:
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case ND_REG_RIP:
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Value->Value.Qwords[0] = ND_TRIM(Value->Size, Context->Registers.RegRip);
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Value->Value.Qwords[0] = ND_TRIM(op->Size, Context->Registers.RegRip);
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break;
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break;
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case ND_REG_FLG:
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case ND_REG_FLG:
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Value->Value.Qwords[0] = Context->Registers.RegFlags;
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Value->Value.Qwords[0] = ND_TRIM(op->Size, Context->Registers.RegFlags);
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break;
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break;
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case ND_REG_CR:
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case ND_REG_CR:
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@ -1244,7 +1244,7 @@ ShemuGetOperandValue(
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}
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}
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// Get the memory value.
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// Get the memory value.
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status = ShemuGetMemValue(Context, gla, Value->Size, Value->Value.Bytes);
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status = ShemuGetMemValue(Context, gla, MIN(op->Size, Value->Size), Value->Value.Bytes);
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if (SHEMU_SUCCESS != status)
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if (SHEMU_SUCCESS != status)
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{
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{
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return status;
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return status;
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@ -1335,8 +1335,17 @@ ShemuSetOperandValue(
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break;
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break;
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case ND_REG_SSE:
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case ND_REG_SSE:
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// Zero the register first.
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if (Context->Instruction.EncMode != ND_ENCM_LEGACY)
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nd_memzero(&Context->SseRegisters[op->Info.Register.Reg], ND_MAX_REGISTER_SIZE);
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{
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// Zero the entire register first, if we have a VEX/EVEX encoded instruction.
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nd_memzero(&Context->SseRegisters[op->Info.Register.Reg], ND_MAX_REGISTER_SIZE);
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}
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else
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{
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// Zero upper bits in the 128 bits register, if operand size is less than 16 bytes.
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// Upper bits in the YMM/ZMM register are preserved.
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nd_memzero(&Context->SseRegisters[op->Info.Register.Reg], 16);
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}
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// Copy the value.
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// Copy the value.
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shemu_memcpy(&Context->SseRegisters[op->Info.Register.Reg],
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shemu_memcpy(&Context->SseRegisters[op->Info.Register.Reg],
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Value->Value.Bytes,
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Value->Value.Bytes,
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@ -1358,14 +1367,22 @@ ShemuSetOperandValue(
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break;
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break;
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case ND_REG_RIP:
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case ND_REG_RIP:
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Context->Registers.RegRip = ND_TRIM(Value->Size, Value->Value.Qwords[0]);
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Context->Registers.RegRip = ND_TRIM(op->Size, Value->Value.Qwords[0]);
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break;
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break;
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case ND_REG_FLG:
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case ND_REG_FLG:
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Context->Registers.RegFlags = ND_TRIM(Value->Size, Value->Value.Qwords[0]);
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if (op->Size == 2)
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{
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*((ND_UINT16*)&Context->Registers.RegFlags) = Value->Value.Words[0];
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}
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else
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{
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Context->Registers.RegFlags = Value->Value.Qwords[0];
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}
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// Handle reserved bits.
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// Handle reserved bits.
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Context->Registers.RegFlags |= (1ULL << 1);
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Context->Registers.RegFlags |= (1ULL << 1);
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Context->Registers.RegFlags &= ~((1ULL << 3) | (1ULL << 5) | (1ULL << 15));
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Context->Registers.RegFlags &= ~((1ULL << 3) | (1ULL << 5) | (1ULL << 15));
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Context->Registers.RegFlags &= 0x3FFFFF;
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break;
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break;
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case ND_REG_CR:
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case ND_REG_CR:
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@ -2972,7 +2989,7 @@ check_far_branch:
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dst.Value.Bytes[11] = src.Value.Bytes[5];
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dst.Value.Bytes[11] = src.Value.Bytes[5];
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dst.Value.Bytes[10] = dst.Value.Bytes[5];
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dst.Value.Bytes[10] = dst.Value.Bytes[5];
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dst.Value.Bytes[9] = src.Value.Bytes[4];
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dst.Value.Bytes[9] = src.Value.Bytes[4];
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dst.Value.Bytes[8] = src.Value.Bytes[4];
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dst.Value.Bytes[8] = dst.Value.Bytes[4];
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dst.Value.Bytes[7] = src.Value.Bytes[3];
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dst.Value.Bytes[7] = src.Value.Bytes[3];
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dst.Value.Bytes[6] = dst.Value.Bytes[3];
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dst.Value.Bytes[6] = dst.Value.Bytes[3];
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dst.Value.Bytes[5] = src.Value.Bytes[2];
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dst.Value.Bytes[5] = src.Value.Bytes[2];
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