From 144baa51400fbcc965d67c1929148685979a59e2 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Wed, 29 Jul 2020 11:05:27 +0300 Subject: [PATCH] Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES. --- bddisasm/bddisasm.c | 176 ++-- bddisasm/include/instructions.h | 1448 +++++++++++++++---------------- bdshemu/bdshemu.c | 222 ++--- disasmtool/disasmtool.c | 4 +- disasmtool_lix/dumpers.cpp | 48 +- inc/cpuidflags.h | 194 ++--- inc/registers.h | 126 +-- inc/version.h | 4 +- isagenerator/generate_tables.py | 4 +- pydis/_pydis/pydis.c | 4 +- 10 files changed, 1115 insertions(+), 1115 deletions(-) diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c index 45262b6..31d8fec 100644 --- a/bddisasm/bddisasm.c +++ b/bddisasm/bddisasm.c @@ -912,7 +912,7 @@ NdFetchModrmAndSib( } // If needed, fetch the SIB. - if ((Instrux->ModRm.rm == REG_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16)) + if ((Instrux->ModRm.rm == NDR_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16)) { // At least one more byte must be available, for the sib. RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); @@ -1180,17 +1180,17 @@ NdGetSegOverride( switch (Instrux->Seg) { case ND_PREFIX_G2_SEG_CS: - return REG_CS; + return NDR_CS; case ND_PREFIX_G2_SEG_DS: - return REG_DS; + return NDR_DS; case ND_PREFIX_G2_SEG_ES: - return REG_ES; + return NDR_ES; case ND_PREFIX_G2_SEG_SS: - return REG_SS; + return NDR_SS; case ND_PREFIX_G2_SEG_FS: - return REG_FS; + return NDR_FS; case ND_PREFIX_G2_SEG_GS: - return REG_GS; + return NDR_GS; default: return DefaultSeg; } @@ -1714,7 +1714,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RAX; + operand->Info.Register.Reg = NDR_RAX; break; case ND_OPT_GPR_AH: @@ -1722,7 +1722,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = ND_SIZE_8BIT; - operand->Info.Register.Reg = REG_AH; + operand->Info.Register.Reg = NDR_AH; operand->Info.Register.IsHigh8 = true; break; @@ -1731,7 +1731,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RCX; + operand->Info.Register.Reg = NDR_RCX; break; case ND_OPT_GPR_rDX: @@ -1739,7 +1739,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RDX; + operand->Info.Register.Reg = NDR_RDX; break; case ND_OPT_GPR_rBX: @@ -1747,7 +1747,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RBX; + operand->Info.Register.Reg = NDR_RBX; break; case ND_OPT_GPR_rBP: @@ -1755,7 +1755,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RBP; + operand->Info.Register.Reg = NDR_RBP; break; case ND_OPT_GPR_rSP: @@ -1763,7 +1763,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RSP; + operand->Info.Register.Reg = NDR_RSP; break; case ND_OPT_GPR_rSI: @@ -1771,7 +1771,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RSI; + operand->Info.Register.Reg = NDR_RSI; break; case ND_OPT_GPR_rDI: @@ -1779,7 +1779,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_RDI; + operand->Info.Register.Reg = NDR_RDI; break; case ND_OPT_GPR_rR11: @@ -1787,7 +1787,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_R11; + operand->Info.Register.Reg = NDR_R11; break; case ND_OPT_SEG_CS: @@ -1795,7 +1795,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_CS; + operand->Info.Register.Reg = NDR_CS; break; case ND_OPT_SEG_SS: @@ -1803,7 +1803,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_SS; + operand->Info.Register.Reg = NDR_SS; break; case ND_OPT_SEG_DS: @@ -1811,7 +1811,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_DS; + operand->Info.Register.Reg = NDR_DS; break; case ND_OPT_SEG_ES: @@ -1819,7 +1819,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_ES; + operand->Info.Register.Reg = NDR_ES; break; case ND_OPT_SEG_FS: @@ -1827,7 +1827,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_FS; + operand->Info.Register.Reg = NDR_FS; break; case ND_OPT_SEG_GS: @@ -1835,7 +1835,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_GS; + operand->Info.Register.Reg = NDR_GS; break; case ND_OPT_FPU_ST0: @@ -1868,7 +1868,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_CR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_CR0; + operand->Info.Register.Reg = NDR_CR0; break; case ND_OPT_SYS_GDTR: @@ -1876,7 +1876,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_GDTR; + operand->Info.Register.Reg = NDR_GDTR; break; case ND_OPT_SYS_IDTR: @@ -1884,7 +1884,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_IDTR; + operand->Info.Register.Reg = NDR_IDTR; break; case ND_OPT_SYS_LDTR: @@ -1892,7 +1892,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_LDTR; + operand->Info.Register.Reg = NDR_LDTR; break; case ND_OPT_SYS_TR: @@ -1900,7 +1900,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = REG_TR; + operand->Info.Register.Reg = NDR_TR; break; case ND_OPT_X87_CONTROL: @@ -1908,7 +1908,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = ND_SIZE_16BIT; - operand->Info.Register.Reg = REG_X87_CONTROL; + operand->Info.Register.Reg = NDR_X87_CONTROL; break; case ND_OPT_X87_TAG: @@ -1916,7 +1916,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = ND_SIZE_16BIT; - operand->Info.Register.Reg = REG_X87_TAG; + operand->Info.Register.Reg = NDR_X87_TAG; break; case ND_OPT_X87_STATUS: @@ -1924,7 +1924,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; operand->Info.Register.Size = ND_SIZE_16BIT; - operand->Info.Register.Reg = REG_X87_STATUS; + operand->Info.Register.Reg = NDR_X87_STATUS; break; case ND_OPT_MXCSR: @@ -1964,7 +1964,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_TSC; + operand->Info.Register.Reg = NDR_IA32_TSC; break; case ND_OPT_MSR_TSCAUX: @@ -1972,7 +1972,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_TSC_AUX; + operand->Info.Register.Reg = NDR_IA32_TSC_AUX; break; case ND_OPT_MSR_SCS: @@ -1980,7 +1980,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_SYSENTER_CS; + operand->Info.Register.Reg = NDR_IA32_SYSENTER_CS; break; case ND_OPT_MSR_SESP: @@ -1988,7 +1988,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_SYSENTER_ESP; + operand->Info.Register.Reg = NDR_IA32_SYSENTER_ESP; break; case ND_OPT_MSR_SEIP: @@ -1996,7 +1996,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_SYSENTER_EIP; + operand->Info.Register.Reg = NDR_IA32_SYSENTER_EIP; break; case ND_OPT_MSR_STAR: @@ -2004,7 +2004,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_STAR; + operand->Info.Register.Reg = NDR_IA32_STAR; break; case ND_OPT_MSR_LSTAR: @@ -2012,7 +2012,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_LSTAR; + operand->Info.Register.Reg = NDR_IA32_LSTAR; break; case ND_OPT_MSR_FMASK: @@ -2020,7 +2020,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_FMASK; + operand->Info.Register.Reg = NDR_IA32_FMASK; break; case ND_OPT_MSR_FSBASE: @@ -2028,7 +2028,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_FS_BASE; + operand->Info.Register.Reg = NDR_IA32_FS_BASE; break; case ND_OPT_MSR_GSBASE: @@ -2036,7 +2036,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_GS_BASE; + operand->Info.Register.Reg = NDR_IA32_GS_BASE; break; case ND_OPT_MSR_KGSBASE: @@ -2044,7 +2044,7 @@ NdParseOperand( operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = REG_IA32_GS_BASE; + operand->Info.Register.Reg = NDR_IA32_GS_BASE; break; case ND_OPT_XCR: @@ -2071,7 +2071,7 @@ NdParseOperand( operand->Size = operand->RawSize = Instrux->WordLength; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = Instrux->WordLength; - operand->Info.Register.Reg = REG_EAX; + operand->Info.Register.Reg = NDR_EAX; operand->Info.Register.Count = 8; operand->Info.Register.IsBlock = true; } @@ -2181,7 +2181,7 @@ NdParseOperand( } // If CS is loaded - #UD. - if ((operand->Info.Register.Reg == REG_CS) && operand->Access.Write) + if ((operand->Info.Register.Reg == NDR_CS) && operand->Access.Write) { return ND_STATUS_CS_LOAD; } @@ -2225,10 +2225,10 @@ NdParseOperand( operand->Type = ND_OP_MEM; operand->Info.Memory.IsStack = true; operand->Info.Memory.HasBase = true; - operand->Info.Memory.Base = REG_RSP; + operand->Info.Memory.Base = NDR_RSP; operand->Info.Memory.BaseSize = szLut[Instrux->DefStack]; operand->Info.Memory.HasSeg = true; - operand->Info.Memory.Seg = REG_SS; + operand->Info.Memory.Seg = NDR_SS; Instrux->StackWords = (uint8_t)(operand->Size / Instrux->WordLength); Instrux->StackAccess |= operand->Access.Access; } @@ -2414,7 +2414,7 @@ NdParseOperand( operand->Info.Memory.DispSize = Instrux->MoffsetLength; operand->Info.Memory.Disp = Instrux->Moffset; operand->Info.Memory.HasSeg = true; - operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); Offset = Instrux->Length; } @@ -2447,58 +2447,58 @@ memory: operand->Info.Memory.HasBase = true; operand->Info.Memory.HasIndex = true; operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = REG_BX; - operand->Info.Memory.Index = REG_SI; + operand->Info.Memory.Base = NDR_BX; + operand->Info.Memory.Index = NDR_SI; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; break; case 1: // [bx + di] operand->Info.Memory.HasBase = true; operand->Info.Memory.HasIndex = true; operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = REG_BX; - operand->Info.Memory.Index = REG_DI; + operand->Info.Memory.Base = NDR_BX; + operand->Info.Memory.Index = NDR_DI; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; break; case 2: // [bp + si] operand->Info.Memory.HasBase = true; operand->Info.Memory.HasIndex = true; operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = REG_BP; - operand->Info.Memory.Index = REG_SI; + operand->Info.Memory.Base = NDR_BP; + operand->Info.Memory.Index = NDR_SI; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_SS; + operand->Info.Memory.Seg = NDR_SS; break; case 3: // [bp + di] operand->Info.Memory.HasBase = true; operand->Info.Memory.HasIndex = true; operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = REG_BP; - operand->Info.Memory.Index = REG_DI; + operand->Info.Memory.Base = NDR_BP; + operand->Info.Memory.Index = NDR_DI; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_SS; + operand->Info.Memory.Seg = NDR_SS; break; case 4: // [si] operand->Info.Memory.HasBase = true; - operand->Info.Memory.Base = REG_SI; + operand->Info.Memory.Base = NDR_SI; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; break; case 5: // [di] operand->Info.Memory.HasBase = true; - operand->Info.Memory.Base = REG_DI; + operand->Info.Memory.Base = NDR_DI; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; break; case 6: // [bp] @@ -2506,22 +2506,22 @@ memory: { // If mod is not zero, than we have "[bp + displacement]". operand->Info.Memory.HasBase = true; - operand->Info.Memory.Base = REG_BP; + operand->Info.Memory.Base = NDR_BP; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_SS; + operand->Info.Memory.Seg = NDR_SS; } else { // If mod is zero, than we only have a displacement that is used to directly address mem. - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; } break; case 7: // [bx] operand->Info.Memory.HasBase = true; - operand->Info.Memory.Base = REG_BX; + operand->Info.Memory.Base = NDR_BX; operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; break; } @@ -2535,12 +2535,12 @@ memory: uint8_t defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT); // Implicit segment is DS. - operand->Info.Memory.Seg = REG_DS; + operand->Info.Memory.Seg = NDR_DS; if (Instrux->HasSib) { // Check for base. - if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == REG_RBP)) + if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == NDR_RBP)) { // Mod is mem without displacement and base reg is RBP -> no base reg used. // Note that this addressing mode is not RIP relative. @@ -2551,14 +2551,14 @@ memory: operand->Info.Memory.BaseSize = defsize; operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->Sib.base); - if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP)) + if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP)) { - operand->Info.Memory.Seg = REG_SS; + operand->Info.Memory.Seg = NDR_SS; } } // Check for index. - if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != REG_RSP) || ND_HAS_VSIB(Instrux)) + if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != NDR_RSP) || ND_HAS_VSIB(Instrux)) { // Index * Scale is present. operand->Info.Memory.HasIndex = true; @@ -2576,7 +2576,7 @@ memory: } else { - if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == REG_RBP)) + if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == NDR_RBP)) { // // RIP relative addressing addresses a memory region relative to the current RIP; However, @@ -2599,9 +2599,9 @@ memory: operand->Info.Memory.BaseSize = defsize; operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP)) + if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP)) { - operand->Info.Memory.Seg = REG_SS; + operand->Info.Memory.Seg = NDR_SS; } } } @@ -2802,16 +2802,16 @@ memory: operand->Info.Memory.HasBase = true; operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; operand->Info.Memory.HasSeg = true; - operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? REG_RSI : REG_RDI)); + operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? NDR_RSI : NDR_RDI)); operand->Info.Memory.IsString = (ND_OPT_X == opt || ND_OPT_Y == opt); // DS:rSI supports segment overriding. ES:rDI does not. if (opt == ND_OPT_Y) { - operand->Info.Memory.Seg = REG_ES; + operand->Info.Memory.Seg = NDR_ES; } else { - operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); } break; @@ -2823,11 +2823,11 @@ memory: operand->Info.Memory.HasIndex = true; operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; operand->Info.Memory.IndexSize = ND_SIZE_8BIT; // Always 1 Byte. - operand->Info.Memory.Base = REG_RBX; // Always rBX. - operand->Info.Memory.Index = REG_AL; // Always AL. + operand->Info.Memory.Base = NDR_RBX; // Always rBX. + operand->Info.Memory.Index = NDR_AL; // Always AL. operand->Info.Memory.Scale = 1; // Always 1. operand->Info.Memory.HasSeg = true; - operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; case ND_OPT_MEM_SHS: @@ -2960,7 +2960,7 @@ memory: operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; operand->Info.Memory.HasSeg = true; - operand->Info.Memory.Seg = REG_ES; + operand->Info.Memory.Seg = NDR_ES; break; case ND_OPT_mM: @@ -2970,7 +2970,7 @@ memory: operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.m << 3) | Instrux->ModRm.rm); operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; operand->Info.Memory.HasSeg = true; - operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS); + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; case ND_OPT_rT: @@ -4632,8 +4632,8 @@ NdToText( return ND_STATUS_INVALID_INSTRUX; } - if ((ND_CODE_64 != Instrux->DefCode) || (REG_FS == pOp->Info.Memory.Seg) || - (REG_GS == pOp->Info.Memory.Seg)) + if ((ND_CODE_64 != Instrux->DefCode) || (NDR_FS == pOp->Info.Memory.Seg) || + (NDR_GS == pOp->Info.Memory.Seg)) { res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Memory.Seg]); RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW); @@ -4957,8 +4957,8 @@ NdGetFullAccessMap( if (pOp->Info.Memory.IsStack) { AccessMap->StackAccess |= pOp->Access.Access; - AccessMap->GprAccess[REG_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE; - AccessMap->SegAccess[REG_SS] |= ND_ACCESS_READ; + AccessMap->GprAccess[NDR_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE; + AccessMap->SegAccess[NDR_SS] |= ND_ACCESS_READ; } else { diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index 581c1bc..cbdd7fe 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -12,10 +12,10 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_AAA, ND_CAT_DECIMAL, ND_SET_I86, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_AF, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -29,9 +29,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -46,9 +46,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -62,10 +62,10 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 3, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_AF, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -78,8 +78,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -94,8 +94,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -110,8 +110,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -126,8 +126,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -142,8 +142,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -158,8 +158,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -174,8 +174,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -190,8 +190,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -206,8 +206,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -222,8 +222,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -239,7 +239,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, { @@ -255,7 +255,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -271,7 +271,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -287,7 +287,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -303,7 +303,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -319,7 +319,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -335,7 +335,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -351,7 +351,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -367,7 +367,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -383,7 +383,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -399,7 +399,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -505,7 +505,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, { @@ -626,9 +626,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -642,9 +642,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -658,9 +658,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -674,9 +674,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -690,9 +690,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -706,9 +706,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -722,9 +722,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -738,9 +738,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -754,9 +754,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -770,9 +770,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -786,9 +786,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -863,7 +863,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -879,9 +879,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, - 0|REG_RFLAG_ZF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF, + 0|NDR_RFLAG_ZF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -1066,9 +1066,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF, - 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -1097,9 +1097,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, - 0|REG_RFLAG_CF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF, - 0|REG_RFLAG_ZF|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -1113,9 +1113,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF, - 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -1264,9 +1264,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -1280,9 +1280,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -1408,9 +1408,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -1424,9 +1424,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -1440,9 +1440,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -1456,9 +1456,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -1472,9 +1472,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -1488,9 +1488,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -1504,9 +1504,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -1520,9 +1520,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -1536,9 +1536,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF, - 0|REG_RFLAG_OF|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -1684,7 +1684,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, 0, - 0|REG_RFLAG_AC, + 0|NDR_RFLAG_AC, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -1698,7 +1698,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -1712,7 +1712,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -1810,7 +1810,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, 0, - 0|REG_RFLAG_IF, + 0|NDR_RFLAG_IF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, @@ -1822,9 +1822,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_OF|REG_RFLAG_SF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -1879,7 +1879,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, { @@ -1892,7 +1892,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 80, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -1908,7 +1908,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 81, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -1924,7 +1924,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 82, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -1940,7 +1940,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 83, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -1956,7 +1956,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 84, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -1972,7 +1972,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 85, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -1988,7 +1988,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 86, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -2004,7 +2004,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 87, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -2020,7 +2020,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -2036,7 +2036,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -2052,7 +2052,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -2068,7 +2068,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -2084,7 +2084,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -2100,7 +2100,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -2116,7 +2116,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -2132,7 +2132,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -2149,7 +2149,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2165,7 +2165,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2181,7 +2181,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2197,7 +2197,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2213,7 +2213,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2229,7 +2229,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2245,7 +2245,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2261,7 +2261,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2277,7 +2277,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2293,7 +2293,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2340,8 +2340,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2358,8 +2358,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2393,8 +2393,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2411,8 +2411,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2430,8 +2430,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2448,8 +2448,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2483,8 +2483,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2501,8 +2501,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2521,7 +2521,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2538,7 +2538,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -2555,7 +2555,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -2574,7 +2574,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -2593,7 +2593,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -2609,7 +2609,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -3104,10 +3104,10 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 138, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|REG_RFLAG_CF|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF, - 0|REG_RFLAG_OF, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF, + 0|NDR_RFLAG_OF, + 0|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -3119,10 +3119,10 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 139, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|REG_RFLAG_CF|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_OF, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_OF, + 0|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -3135,7 +3135,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3150,7 +3150,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3165,7 +3165,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3180,7 +3180,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3195,7 +3195,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3210,7 +3210,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3225,7 +3225,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3240,7 +3240,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3255,7 +3255,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3270,7 +3270,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -3300,8 +3300,8 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), @@ -3318,8 +3318,8 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -3533,9 +3533,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), @@ -3549,9 +3549,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), @@ -3783,7 +3783,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 168, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -3800,7 +3800,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 169, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -3817,7 +3817,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 170, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -3834,7 +3834,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 171, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -3851,7 +3851,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 172, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -3868,7 +3868,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 173, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -3885,7 +3885,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 174, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -3902,7 +3902,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 175, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -3984,9 +3984,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), @@ -4001,9 +4001,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), @@ -5760,9 +5760,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), @@ -5777,9 +5777,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), @@ -6125,8 +6125,8 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), @@ -6143,8 +6143,8 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -6159,9 +6159,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -6175,9 +6175,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -6192,9 +6192,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -6209,9 +6209,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), @@ -6226,9 +6226,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -6242,7 +6242,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6258,7 +6258,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6274,7 +6274,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6290,7 +6290,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6307,7 +6307,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6322,7 +6322,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6337,7 +6337,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6352,7 +6352,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6367,7 +6367,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6382,7 +6382,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6397,7 +6397,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6412,7 +6412,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6427,7 +6427,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6442,7 +6442,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -6488,7 +6488,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6505,7 +6505,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6523,7 +6523,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6540,7 +6540,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6622,7 +6622,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6639,7 +6639,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -6657,8 +6657,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 278, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_VM, - 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0|NDR_RFLAG_VM, + 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { @@ -6676,8 +6676,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 279, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_VM, - 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0|NDR_RFLAG_VM, + 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { @@ -6693,8 +6693,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 280, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_VM, - 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0|NDR_RFLAG_VM, + 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { @@ -6711,8 +6711,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 281, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_VM, - 0|REG_RFLAG_VM|REG_RFLAG_IF|REG_RFLAG_NT|REG_RFLAG_AC|REG_RFLAG_RF|REG_RFLAG_TF, + 0|NDR_RFLAG_VM, + 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { @@ -6744,9 +6744,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -6820,9 +6820,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -6889,7 +6889,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -6905,7 +6905,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -6921,7 +6921,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -6937,7 +6937,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -6985,7 +6985,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -7001,7 +7001,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -7017,7 +7017,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -7033,7 +7033,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -7156,7 +7156,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -7172,7 +7172,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -7188,7 +7188,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -7204,7 +7204,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -7220,7 +7220,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -7236,7 +7236,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -7252,7 +7252,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -7268,7 +7268,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -7284,7 +7284,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -7300,7 +7300,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -7316,7 +7316,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -7332,7 +7332,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -7348,7 +7348,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -7364,7 +7364,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -7380,7 +7380,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -7396,7 +7396,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -7412,7 +7412,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -7428,7 +7428,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -7444,7 +7444,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -7460,7 +7460,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -7492,7 +7492,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -7508,7 +7508,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -7524,7 +7524,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -7540,7 +7540,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, ND_MOD_ANY, ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -8187,9 +8187,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -8203,9 +8203,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), @@ -8219,9 +8219,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), @@ -8235,9 +8235,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), @@ -8630,7 +8630,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 367, ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0, 0, 0, @@ -8646,7 +8646,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -8662,7 +8662,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -8905,7 +8905,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -8922,7 +8922,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -8940,7 +8940,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -8957,7 +8957,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -8975,7 +8975,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -8992,7 +8992,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -9010,7 +9010,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -9027,7 +9027,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -9062,7 +9062,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 389, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -9079,7 +9079,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 390, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -9097,7 +9097,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -9113,7 +9113,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -9192,9 +9192,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -9300,9 +9300,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -10693,7 +10693,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10711,7 +10711,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10760,7 +10760,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10778,7 +10778,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10827,7 +10827,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10845,7 +10845,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10894,7 +10894,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -10912,7 +10912,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -11083,9 +11083,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), @@ -11100,9 +11100,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -11225,7 +11225,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -11240,7 +11240,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -12038,9 +12038,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -12054,9 +12054,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -12070,9 +12070,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -12086,9 +12086,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -12102,9 +12102,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -12118,9 +12118,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -12134,9 +12134,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -12150,9 +12150,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -12166,9 +12166,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -12182,9 +12182,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -12227,7 +12227,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12243,7 +12243,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12259,7 +12259,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12275,7 +12275,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12291,7 +12291,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12308,7 +12308,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12326,7 +12326,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12343,7 +12343,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12361,7 +12361,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -12378,7 +12378,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|REG_RFLAG_DF|REG_RFLAG_IOPL|REG_RFLAG_VM, + 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, @@ -13166,9 +13166,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -13186,9 +13186,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -13311,9 +13311,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -13329,9 +13329,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -15151,9 +15151,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -15819,7 +15819,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, - 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { @@ -16404,9 +16404,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -16974,7 +16974,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 0, - 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF|REG_RFLAG_CF, + 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF, 0, 0, { @@ -17020,8 +17020,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17036,8 +17036,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17052,8 +17052,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17068,8 +17068,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17084,8 +17084,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17100,8 +17100,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17146,8 +17146,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17162,8 +17162,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17178,8 +17178,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17194,8 +17194,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17210,8 +17210,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17226,8 +17226,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17339,9 +17339,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -17356,9 +17356,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -17371,9 +17371,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -17386,9 +17386,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -17401,9 +17401,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -17563,7 +17563,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, - 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { @@ -17580,7 +17580,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, - 0|REG_RFLAG_OF|REG_RFLAG_ZF|REG_RFLAG_AF|REG_RFLAG_PF|REG_RFLAG_SF, + 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { @@ -17596,7 +17596,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17612,7 +17612,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17628,7 +17628,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17644,7 +17644,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17660,7 +17660,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17676,7 +17676,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17692,7 +17692,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17708,7 +17708,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17724,7 +17724,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17740,7 +17740,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17756,7 +17756,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17772,7 +17772,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { @@ -17943,9 +17943,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_OF|REG_RFLAG_SF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -17972,7 +17972,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0, 0, { @@ -17987,9 +17987,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18003,9 +18003,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18019,9 +18019,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18035,9 +18035,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18051,9 +18051,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18067,9 +18067,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18082,7 +18082,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 688, ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -18098,9 +18098,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18114,9 +18114,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18130,9 +18130,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18146,9 +18146,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18162,9 +18162,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18178,9 +18178,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18209,7 +18209,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 691, ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -18224,8 +18224,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18240,8 +18240,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18256,8 +18256,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18272,8 +18272,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18288,8 +18288,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18304,8 +18304,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18320,8 +18320,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18336,8 +18336,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18352,8 +18352,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18368,8 +18368,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18384,8 +18384,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18401,8 +18401,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18419,8 +18419,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18436,8 +18436,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18454,8 +18454,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18471,8 +18471,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18489,8 +18489,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18506,8 +18506,8 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, ND_MOD_ANY, ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_ZF|REG_RFLAG_DF, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -18538,7 +18538,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 698, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -18553,7 +18553,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 699, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -18568,7 +18568,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 700, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -18583,7 +18583,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -18598,7 +18598,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, @@ -18613,7 +18613,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, 0, 0, @@ -18628,7 +18628,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, @@ -18643,7 +18643,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_SF|REG_RFLAG_ZF|REG_RFLAG_OF, + 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, @@ -18658,7 +18658,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -18673,7 +18673,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -18688,7 +18688,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -18703,7 +18703,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 709, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -18718,7 +18718,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_OF, + 0|NDR_RFLAG_OF, 0, 0, 0, @@ -18733,7 +18733,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 711, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_PF, + 0|NDR_RFLAG_PF, 0, 0, 0, @@ -18748,7 +18748,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_SF, + 0|NDR_RFLAG_SF, 0, 0, 0, @@ -18778,7 +18778,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, 0, @@ -18930,9 +18930,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18946,9 +18946,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18962,9 +18962,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18978,9 +18978,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -18994,9 +18994,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19010,9 +19010,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19026,9 +19026,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -19043,9 +19043,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -19076,9 +19076,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19092,9 +19092,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19108,9 +19108,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19124,9 +19124,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19140,9 +19140,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19156,9 +19156,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -19172,9 +19172,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -19189,9 +19189,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, - 0|REG_RFLAG_CF|REG_RFLAG_AF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -19446,7 +19446,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 0, 0, - 0|REG_RFLAG_AC, + 0|NDR_RFLAG_AC, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -19460,7 +19460,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -19474,7 +19474,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -19502,7 +19502,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_IF, + 0|NDR_RFLAG_IF, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), @@ -19529,7 +19529,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 749, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19546,7 +19546,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 749, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19564,7 +19564,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 750, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19581,7 +19581,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 750, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19599,7 +19599,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 751, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19616,7 +19616,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 751, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19634,7 +19634,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19651,7 +19651,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, ND_MOD_ANY, ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_DF, + 0|NDR_RFLAG_DF, 0, 0, 0, @@ -19714,7 +19714,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19730,7 +19730,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19746,7 +19746,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19762,7 +19762,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19778,7 +19778,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19794,7 +19794,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19810,7 +19810,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19826,7 +19826,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19842,7 +19842,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -19858,7 +19858,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -20017,7 +20017,7 @@ const ND_INSTRUCTION gInstructions[2557] = 0, 0, 0, - 0|REG_RFLAG_IF, + 0|NDR_RFLAG_IF, { OP(ND_OPT_MSR_SCS, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_SESP, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), @@ -20171,9 +20171,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -20187,9 +20187,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -20203,9 +20203,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -20219,9 +20219,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -20235,9 +20235,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -20251,9 +20251,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -20267,9 +20267,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -20283,9 +20283,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -20386,9 +20386,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), @@ -20403,9 +20403,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -20434,7 +20434,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -20450,7 +20450,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -20510,9 +20510,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, - 0|REG_RFLAG_CF, + 0|NDR_RFLAG_CF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_mM, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -21654,7 +21654,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -21670,7 +21670,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -21686,7 +21686,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -21702,7 +21702,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -23034,7 +23034,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -23049,7 +23049,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, 0, { @@ -27273,9 +27273,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -27462,9 +27462,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -29073,9 +29073,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -29088,9 +29088,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -29103,9 +29103,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -29119,9 +29119,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -29293,9 +29293,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), @@ -29309,9 +29309,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, @@ -29323,9 +29323,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), @@ -30749,9 +30749,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -30769,9 +30769,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -30921,9 +30921,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -30939,9 +30939,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), @@ -37495,9 +37495,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), @@ -39234,9 +39234,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), @@ -39250,9 +39250,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), @@ -39266,7 +39266,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -39282,7 +39282,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -39298,7 +39298,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -39314,7 +39314,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_ZF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { @@ -39751,7 +39751,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -39767,7 +39767,7 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_ZF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { @@ -40065,9 +40065,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -40081,9 +40081,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -40097,9 +40097,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -40113,9 +40113,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), @@ -40129,9 +40129,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -40145,9 +40145,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -40161,9 +40161,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), @@ -40177,9 +40177,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -40193,9 +40193,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -40209,9 +40209,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, - 0|REG_RFLAG_PF|REG_RFLAG_ZF|REG_RFLAG_SF, - 0|REG_RFLAG_AF, - 0|REG_RFLAG_CF|REG_RFLAG_OF|REG_RFLAG_AF, + 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + 0|NDR_RFLAG_AF, + 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), @@ -40558,9 +40558,9 @@ const ND_INSTRUCTION gInstructions[2557] = ND_MOD_ANY, 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 0, - 0|REG_RFLAG_ZF, + 0|NDR_RFLAG_ZF, 0, - 0|REG_RFLAG_CF|REG_RFLAG_PF|REG_RFLAG_AF|REG_RFLAG_SF|REG_RFLAG_OF, + 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, diff --git a/bdshemu/bdshemu.c b/bdshemu/bdshemu.c index 23a487f..c27c17a 100644 --- a/bdshemu/bdshemu.c +++ b/bdshemu/bdshemu.c @@ -321,60 +321,60 @@ ShemuSetFlags( // PF set if the first bytes has an even number of 1 bits. if ((pfArr[Dst & 0xF] + pfArr[(Dst >> 4) & 0xF]) % 2 == 0) { - Context->Registers.RegFlags |= REG_RFLAG_PF; + Context->Registers.RegFlags |= NDR_RFLAG_PF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_PF; + Context->Registers.RegFlags &= ~NDR_RFLAG_PF; } // ZF set if the result is zero. if (Dst == 0) { - Context->Registers.RegFlags |= REG_RFLAG_ZF; + Context->Registers.RegFlags |= NDR_RFLAG_ZF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_ZF; + Context->Registers.RegFlags &= ~NDR_RFLAG_ZF; } // SF is set if the sign flag is set. if (ND_GET_SIGN(Size, Dst) != 0) { - Context->Registers.RegFlags |= REG_RFLAG_SF; + Context->Registers.RegFlags |= NDR_RFLAG_SF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_SF; + Context->Registers.RegFlags &= ~NDR_RFLAG_SF; } // OF and CF are handled differently for some instructions. if (FM_LOGIC == FlagsMode) { // OF and CF are cleared on logic instructions. - Context->Registers.RegFlags &= ~(REG_RFLAG_OF | REG_RFLAG_CF); + Context->Registers.RegFlags &= ~(NDR_RFLAG_OF | NDR_RFLAG_CF); } else if (FM_SHL == FlagsMode) { // CF is the last bit shifted out of the destination. if (ND_GET_BIT(Src1, (Size * 8) - Src2)) { - Context->Registers.RegFlags |= REG_RFLAG_CF; + Context->Registers.RegFlags |= NDR_RFLAG_CF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_CF; + Context->Registers.RegFlags &= ~NDR_RFLAG_CF; } if (Src2 == 1) { if (ND_GET_BIT(Size * 8 - 1, Dst) ^ ND_GET_BIT(Src1, (Size * 8) - Src2)) { - Context->Registers.RegFlags |= REG_RFLAG_OF; + Context->Registers.RegFlags |= NDR_RFLAG_OF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_OF; + Context->Registers.RegFlags &= ~NDR_RFLAG_OF; } } } @@ -383,22 +383,22 @@ ShemuSetFlags( // CF is the last bit shifted out of the destination. if (ND_GET_BIT(Src1, Src2 - 1)) { - Context->Registers.RegFlags |= REG_RFLAG_CF; + Context->Registers.RegFlags |= NDR_RFLAG_CF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_CF; + Context->Registers.RegFlags &= ~NDR_RFLAG_CF; } if (Src2 == 1) { if (ND_GET_BIT(Size * 8 - 1, Dst)) { - Context->Registers.RegFlags |= REG_RFLAG_OF; + Context->Registers.RegFlags |= NDR_RFLAG_OF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_OF; + Context->Registers.RegFlags &= ~NDR_RFLAG_OF; } } } @@ -407,29 +407,29 @@ ShemuSetFlags( // CF is the last bit shifted out of the destination. if (ND_GET_BIT(Src1, Src2 - 1)) { - Context->Registers.RegFlags |= REG_RFLAG_CF; + Context->Registers.RegFlags |= NDR_RFLAG_CF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_CF; + Context->Registers.RegFlags &= ~NDR_RFLAG_CF; } - Context->Registers.RegFlags &= ~REG_RFLAG_OF; + Context->Registers.RegFlags &= ~NDR_RFLAG_OF; } else { // Set CF. if ((FM_SUB == FlagsMode) && (Src1 < Src2)) { - Context->Registers.RegFlags |= REG_RFLAG_CF; + Context->Registers.RegFlags |= NDR_RFLAG_CF; } else if ((FM_ADD == FlagsMode) && (Dst < Src1)) { - Context->Registers.RegFlags |= REG_RFLAG_CF; + Context->Registers.RegFlags |= NDR_RFLAG_CF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_CF; + Context->Registers.RegFlags &= ~NDR_RFLAG_CF; } // Set OF. @@ -438,11 +438,11 @@ ShemuSetFlags( if ((ND_GET_SIGN(Size, Src1) && !ND_GET_SIGN(Size, Src2) && !ND_GET_SIGN(Size, Dst)) || (!ND_GET_SIGN(Size, Src1) && ND_GET_SIGN(Size, Src2) && ND_GET_SIGN(Size, Dst))) { - Context->Registers.RegFlags |= REG_RFLAG_OF; + Context->Registers.RegFlags |= NDR_RFLAG_OF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_OF; + Context->Registers.RegFlags &= ~NDR_RFLAG_OF; } } else if (FM_ADD == FlagsMode) @@ -450,11 +450,11 @@ ShemuSetFlags( if (ND_GET_SIGN(Size, Src1) == ND_GET_SIGN(Size, Src2) && ND_GET_SIGN(Size, Src1) != ND_GET_SIGN(Size, Dst)) { - Context->Registers.RegFlags |= REG_RFLAG_OF; + Context->Registers.RegFlags |= NDR_RFLAG_OF; } else { - Context->Registers.RegFlags &= ~REG_RFLAG_OF; + Context->Registers.RegFlags &= ~NDR_RFLAG_OF; } } } @@ -473,99 +473,99 @@ ShemuEvalCondition( switch (ConditionCode) { case ND_COND_OVERFLOW: // O - if (GET_FLAG(Context, REG_RFLAG_OF) == 1) + if (GET_FLAG(Context, NDR_RFLAG_OF) == 1) { return true; } break; case ND_COND_NOT(ND_COND_OVERFLOW): // NO - if (GET_FLAG(Context, REG_RFLAG_OF) == 0) + if (GET_FLAG(Context, NDR_RFLAG_OF) == 0) { return true; } break; case ND_COND_CARRY: // C/B/NAE - if (GET_FLAG(Context, REG_RFLAG_CF) == 1) + if (GET_FLAG(Context, NDR_RFLAG_CF) == 1) { return true; } break; case ND_COND_NOT(ND_COND_CARRY): // NC/NB/AE - if (GET_FLAG(Context, REG_RFLAG_CF) == 0) + if (GET_FLAG(Context, NDR_RFLAG_CF) == 0) { return true; } break; case ND_COND_ZERO: // E/Z - if (GET_FLAG(Context, REG_RFLAG_ZF) == 1) + if (GET_FLAG(Context, NDR_RFLAG_ZF) == 1) { return true; } break; case ND_COND_NOT(ND_COND_ZERO): // NE/NZ - if (GET_FLAG(Context, REG_RFLAG_ZF) == 0) + if (GET_FLAG(Context, NDR_RFLAG_ZF) == 0) { return true; } break; case ND_COND_BELOW_OR_EQUAL: // BE/NA - if ((GET_FLAG(Context, REG_RFLAG_CF) | (GET_FLAG(Context, REG_RFLAG_ZF))) == 1) + if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1) { return true; } break; case ND_COND_NOT(ND_COND_BELOW_OR_EQUAL): // A/NBE - if ((GET_FLAG(Context, REG_RFLAG_CF) | (GET_FLAG(Context, REG_RFLAG_ZF))) == 0) + if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0) { return true; } break; case ND_COND_SIGN: // S - if (GET_FLAG(Context, REG_RFLAG_SF) == 1) + if (GET_FLAG(Context, NDR_RFLAG_SF) == 1) { return true; } break; case ND_COND_NOT(ND_COND_SIGN): // NS - if (GET_FLAG(Context, REG_RFLAG_SF) == 0) + if (GET_FLAG(Context, NDR_RFLAG_SF) == 0) { return true; } break; case ND_COND_PARITY: // P - if (GET_FLAG(Context, REG_RFLAG_PF) == 1) + if (GET_FLAG(Context, NDR_RFLAG_PF) == 1) { return true; } break; case ND_COND_NOT(ND_COND_PARITY): // NP - if (GET_FLAG(Context, REG_RFLAG_PF) == 0) + if (GET_FLAG(Context, NDR_RFLAG_PF) == 0) { return true; } break; case ND_COND_LESS: // L/NGE - if ((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) == 1) + if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 1) { return true; } break; case ND_COND_NOT(ND_COND_LESS): // NL/GE - if ((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) == 0) + if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 0) { return true; } break; case ND_COND_LESS_OR_EQUAL: // LE/NG - if (((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) | - (GET_FLAG(Context, REG_RFLAG_ZF))) == 1) + if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) | + (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1) { return true; } break; case ND_COND_NOT(ND_COND_LESS_OR_EQUAL): // NLE/G - if (((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) | - (GET_FLAG(Context, REG_RFLAG_ZF))) == 0) + if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) | + (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0) { return true; } @@ -696,17 +696,17 @@ ShemuGetSegValue( { switch (Reg) { - case REG_ES: + case NDR_ES: return Context->Segments.Es.Selector; - case REG_CS: + case NDR_CS: return Context->Segments.Cs.Selector; - case REG_SS: + case NDR_SS: return Context->Segments.Ss.Selector; - case REG_DS: + case NDR_DS: return Context->Segments.Ds.Selector; - case REG_FS: + case NDR_FS: return Context->Segments.Fs.Selector; - case REG_GS: + case NDR_GS: return Context->Segments.Gs.Selector; } @@ -726,22 +726,22 @@ ShemuSetSegValue( { switch (Reg) { - case REG_ES: + case NDR_ES: Context->Segments.Es.Selector = Value; break; - case REG_CS: + case NDR_CS: Context->Segments.Cs.Selector = Value; break; - case REG_SS: + case NDR_SS: Context->Segments.Ss.Selector = Value; break; - case REG_DS: + case NDR_DS: Context->Segments.Ds.Selector = Value; break; - case REG_FS: + case NDR_FS: Context->Segments.Fs.Selector = Value; break; - case REG_GS: + case NDR_GS: Context->Segments.Gs.Selector = Value; break; } @@ -759,17 +759,17 @@ ShemuGetSegBase( { switch (Reg) { - case REG_ES: + case NDR_ES: return Context->Segments.Es.Base; - case REG_CS: + case NDR_CS: return Context->Segments.Cs.Base; - case REG_SS: + case NDR_SS: return Context->Segments.Ss.Base; - case REG_DS: + case NDR_DS: return Context->Segments.Ds.Base; - case REG_FS: + case NDR_FS: return Context->Segments.Fs.Base; - case REG_GS: + case NDR_GS: return Context->Segments.Gs.Base; } @@ -1084,19 +1084,19 @@ ShemuGetOperandValue( case ND_REG_CR: switch (op->Info.Register.Reg) { - case REG_CR0: + case NDR_CR0: Value->Value.Qwords[0] = Context->Registers.RegCr0; break; - case REG_CR2: + case NDR_CR2: Value->Value.Qwords[0] = Context->Registers.RegCr2; break; - case REG_CR3: + case NDR_CR3: Value->Value.Qwords[0] = Context->Registers.RegCr3; break; - case REG_CR4: + case NDR_CR4: Value->Value.Qwords[0] = Context->Registers.RegCr4; break; - case REG_CR8: + case NDR_CR8: Value->Value.Qwords[0] = Context->Registers.RegCr8; break; default: @@ -1163,11 +1163,11 @@ ShemuGetOperandValue( // If this is a stack access, we need to update the stack pointer. if (op->Info.Memory.IsStack) { - uint64_t regval = ShemuGetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), false); + uint64_t regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), false); regval += op->Size; - ShemuSetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), regval, false); + ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, false); } // If this is a string operation, make sure we update RSI/RDI. @@ -1175,7 +1175,7 @@ ShemuGetOperandValue( { uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false); - regval = GET_FLAG(Context, REG_RFLAG_DF) ? regval - op->Size : regval + op->Size; + regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size; ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false); } @@ -1260,19 +1260,19 @@ ShemuSetOperandValue( case ND_REG_CR: switch (op->Info.Register.Reg) { - case REG_CR0: + case NDR_CR0: Context->Registers.RegCr0 = Value->Value.Qwords[0]; break; - case REG_CR2: + case NDR_CR2: Context->Registers.RegCr2 = Value->Value.Qwords[0]; break; - case REG_CR3: + case NDR_CR3: Context->Registers.RegCr3 = Value->Value.Qwords[0]; break; - case REG_CR4: + case NDR_CR4: Context->Registers.RegCr4 = Value->Value.Qwords[0]; break; - case REG_CR8: + case NDR_CR8: Context->Registers.RegCr8 = Value->Value.Qwords[0]; break; default: @@ -1359,11 +1359,11 @@ ShemuSetOperandValue( // If this is a stack access, we need to update the stack pointer. if (op->Info.Memory.IsStack) { - uint64_t regval = ShemuGetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), false); + uint64_t regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), false); regval -= op->Size; - ShemuSetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), regval, false); + ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, false); } // If this is a string operation, make sure we update RSI/RDI. @@ -1371,7 +1371,7 @@ ShemuSetOperandValue( { uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false); - regval = GET_FLAG(Context, REG_RFLAG_DF) ? regval - op->Size : regval + op->Size; + regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size; ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false); } @@ -1660,12 +1660,12 @@ ShemuEmulate( { GET_OP(Context, 1, &src); SET_OP(Context, 0, &src); - SET_FLAG(Context, REG_RFLAG_ZF, 1); + SET_FLAG(Context, NDR_RFLAG_ZF, 1); } else { SET_OP(Context, 2, &dst); - SET_FLAG(Context, REG_RFLAG_ZF, 0); + SET_FLAG(Context, NDR_RFLAG_ZF, 0); } break; @@ -1676,7 +1676,7 @@ ShemuEmulate( if (ND_INS_ADC == Context->Instruction.Instruction) { - src.Value.Qwords[0] += GET_FLAG(Context, REG_RFLAG_CF); + src.Value.Qwords[0] += GET_FLAG(Context, NDR_RFLAG_CF); } res.Size = src.Size; @@ -1695,7 +1695,7 @@ ShemuEmulate( if (ND_INS_SBB == Context->Instruction.Instruction) { - src.Value.Qwords[0] += GET_FLAG(Context, REG_RFLAG_CF); + src.Value.Qwords[0] += GET_FLAG(Context, NDR_RFLAG_CF); } res.Size = src.Size; @@ -1864,31 +1864,31 @@ ShemuEmulate( while (tempcnt != 0) { tempCF = ND_MSB(dst.Size, dst.Value.Qwords[0]); - dst.Value.Qwords[0] = (dst.Value.Qwords[0] << 1) + GET_FLAG(Context, REG_RFLAG_CF); - SET_FLAG(Context, REG_RFLAG_CF, tempCF); + dst.Value.Qwords[0] = (dst.Value.Qwords[0] << 1) + GET_FLAG(Context, NDR_RFLAG_CF); + SET_FLAG(Context, NDR_RFLAG_CF, tempCF); tempcnt--; } if ((cnt & cntmask) == 1) { - SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - GET_FLAG(Context, REG_RFLAG_CF)); + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, NDR_RFLAG_CF)); } } else if (ND_INS_RCR == Context->Instruction.Instruction) { if ((cnt & cntmask) == 1) { - SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - GET_FLAG(Context, REG_RFLAG_CF)); + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, NDR_RFLAG_CF)); } while (tempcnt != 0) { tempCF = ND_LSB(dst.Size, dst.Value.Qwords[0]); dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) + - ((uint64_t)GET_FLAG(Context, REG_RFLAG_CF) << (dst.Size * 8 - 1)); - SET_FLAG(Context, REG_RFLAG_CF, tempCF); + ((uint64_t)GET_FLAG(Context, NDR_RFLAG_CF) << (dst.Size * 8 - 1)); + SET_FLAG(Context, NDR_RFLAG_CF, tempCF); tempcnt--; } } @@ -1903,13 +1903,13 @@ ShemuEmulate( if ((cnt & cntmask) != 0) { - SET_FLAG(Context, REG_RFLAG_CF, dst.Value.Qwords[0] & 1); + SET_FLAG(Context, NDR_RFLAG_CF, dst.Value.Qwords[0] & 1); } if ((cnt & cntmask) == 1) { - SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - GET_FLAG(Context, REG_RFLAG_CF)); + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, NDR_RFLAG_CF)); } } else // ND_INS_ROR @@ -1923,12 +1923,12 @@ ShemuEmulate( if ((cnt & cntmask) != 0) { - SET_FLAG(Context, REG_RFLAG_CF, ND_MSB(dst.Size, dst.Value.Qwords[0])); + SET_FLAG(Context, NDR_RFLAG_CF, ND_MSB(dst.Size, dst.Value.Qwords[0])); } if ((cnt & cntmask) == 1) { - SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ tempCF); + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ tempCF); } } @@ -1988,7 +1988,7 @@ ShemuEmulate( src.Value.Qwords[0] %= dst.Size * 8; // Store the bit inside CF. - SET_FLAG(Context, REG_RFLAG_CF, (dst.Value.Qwords[0] >> src.Value.Qwords[0]) & 1); + SET_FLAG(Context, NDR_RFLAG_CF, (dst.Value.Qwords[0] >> src.Value.Qwords[0]) & 1); if (ND_INS_BTS == Context->Instruction.Instruction) { @@ -2041,8 +2041,8 @@ ShemuEmulate( SET_OP(Context, 1, &rcx); if (rcx.Value.Qwords[0] > 0) { - if (((ND_INS_LOOPNZ == Context->Instruction.Instruction) && (0 == GET_FLAG(Context, REG_RFLAG_ZF))) || - ((ND_INS_LOOPZ == Context->Instruction.Instruction) && (0 != GET_FLAG(Context, REG_RFLAG_ZF))) || + if (((ND_INS_LOOPNZ == Context->Instruction.Instruction) && (0 == GET_FLAG(Context, NDR_RFLAG_ZF))) || + ((ND_INS_LOOPZ == Context->Instruction.Instruction) && (0 != GET_FLAG(Context, NDR_RFLAG_ZF))) || (ND_INS_LOOP == Context->Instruction.Instruction)) { // Modify the RIP if the branch is taken. @@ -2156,12 +2156,12 @@ ShemuEmulate( rcx.Value.Qwords[0]--; SET_OP(Context, 2, &rcx); - if (Context->Instruction.HasRepRepzXrelease && !GET_FLAG(Context, REG_RFLAG_ZF)) + if (Context->Instruction.HasRepRepzXrelease && !GET_FLAG(Context, NDR_RFLAG_ZF)) { break; } - if (Context->Instruction.HasRepnzXacquireBnd && GET_FLAG(Context, REG_RFLAG_ZF)) + if (Context->Instruction.HasRepnzXacquireBnd && GET_FLAG(Context, NDR_RFLAG_ZF)) { break; } @@ -2287,8 +2287,8 @@ ShemuEmulate( break; } - SET_FLAG(Context, REG_RFLAG_CF, cfof); - SET_FLAG(Context, REG_RFLAG_OF, cfof); + SET_FLAG(Context, NDR_RFLAG_CF, cfof); + SET_FLAG(Context, NDR_RFLAG_OF, cfof); } else { @@ -2318,8 +2318,8 @@ ShemuEmulate( break; } - SET_FLAG(Context, REG_RFLAG_CF, cfof); - SET_FLAG(Context, REG_RFLAG_OF, cfof); + SET_FLAG(Context, NDR_RFLAG_CF, cfof); + SET_FLAG(Context, NDR_RFLAG_OF, cfof); } break; @@ -2416,23 +2416,23 @@ ShemuEmulate( break; case ND_INS_CLD: - SET_FLAG(Context, REG_RFLAG_DF, 0); + SET_FLAG(Context, NDR_RFLAG_DF, 0); break; case ND_INS_STD: - SET_FLAG(Context, REG_RFLAG_DF, 1); + SET_FLAG(Context, NDR_RFLAG_DF, 1); break; case ND_INS_CLC: - SET_FLAG(Context, REG_RFLAG_CF, 0); + SET_FLAG(Context, NDR_RFLAG_CF, 0); break; case ND_INS_STC: - SET_FLAG(Context, REG_RFLAG_CF, 1); + SET_FLAG(Context, NDR_RFLAG_CF, 1); break; case ND_INS_CMC: - Context->Registers.RegFlags ^= REG_RFLAG_CF; + Context->Registers.RegFlags ^= NDR_RFLAG_CF; break; case ND_INS_STI: @@ -2441,7 +2441,7 @@ ShemuEmulate( return SHEMU_ABORT_NO_PRIVILEGE; } - SET_FLAG(Context, REG_RFLAG_IF, 1); + SET_FLAG(Context, NDR_RFLAG_IF, 1); break; case ND_INS_CLI: @@ -2450,7 +2450,7 @@ ShemuEmulate( return SHEMU_ABORT_NO_PRIVILEGE; } - SET_FLAG(Context, REG_RFLAG_IF, 0); + SET_FLAG(Context, NDR_RFLAG_IF, 0); break; case ND_INS_SAHF: @@ -2471,7 +2471,7 @@ ShemuEmulate( break; case ND_INS_SALC: - if (GET_FLAG(Context, REG_RFLAG_CF)) + if (GET_FLAG(Context, NDR_RFLAG_CF)) { *((uint8_t *)&Context->Registers.RegRax) = 0xFF; } diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c index dbd906d..fe927b2 100644 --- a/disasmtool/disasmtool.c +++ b/disasmtool/disasmtool.c @@ -34,7 +34,7 @@ typedef struct _DISASM_OPTIONS uint8_t Ring; // Ring - 0, 1, 2 or 3. uint8_t Vendor; // Proffered vendor. char *FileName; // Input file, if any. - size_t ShemuRegs[REG_R15 + 1]; + size_t ShemuRegs[NDR_R15 + 1]; BOOLEAN UseShemuRegs; } DISASM_OPTIONS, *PDISASM_OPTIONS; @@ -1439,7 +1439,7 @@ handle_shemu( ctx.Registers.RegRsp = 0x101000; ctx.IntbufSize = (DWORD)shellSize + STACK_SIZE; - ctx.Registers.RegFlags = REG_RFLAG_IF | 2; + ctx.Registers.RegFlags = NDR_RFLAG_IF | 2; ctx.Registers.RegRip = ctx.ShellcodeBase + offset; ctx.Segments.Cs.Selector = 0x10; diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp index e5e6f9c..1df4f8d 100644 --- a/disasmtool_lix/dumpers.cpp +++ b/disasmtool_lix/dumpers.cpp @@ -1764,36 +1764,36 @@ std::string reg_to_str(const int reg, const ND_REG_TYPE type) case ND_REG_GPR: switch (reg) { - case REG_RAX: return "rax"; - case REG_RCX: return "rcx"; - case REG_RDX: return "rdx"; - case REG_RBX: return "rbx"; - case REG_RSP: return "rsp"; - case REG_RBP: return "rbp"; - case REG_RSI: return "rsi"; - case REG_RDI: return "rdi"; - case REG_R8: return "r8"; - case REG_R9: return "r9"; - case REG_R10: return "r10"; - case REG_R11: return "r11"; - case REG_R12: return "r12"; - case REG_R13: return "r13"; - case REG_R14: return "r14"; - case REG_R15: return "r15"; + case NDR_RAX: return "rax"; + case NDR_RCX: return "rcx"; + case NDR_RDX: return "rdx"; + case NDR_RBX: return "rbx"; + case NDR_RSP: return "rsp"; + case NDR_RBP: return "rbp"; + case NDR_RSI: return "rsi"; + case NDR_RDI: return "rdi"; + case NDR_R8: return "r8"; + case NDR_R9: return "r9"; + case NDR_R10: return "r10"; + case NDR_R11: return "r11"; + case NDR_R12: return "r12"; + case NDR_R13: return "r13"; + case NDR_R14: return "r14"; + case NDR_R15: return "r15"; } return ""; case ND_REG_SEG: switch (reg) { - case REG_ES: return "es"; - case REG_CS: return "cs"; - case REG_SS: return "ss"; - case REG_DS: return "ds"; - case REG_FS: return "fs"; - case REG_GS: return "gs"; - case REG_INV6: return "inv6"; - case REG_INV7: return "inv7"; + case NDR_ES: return "es"; + case NDR_CS: return "cs"; + case NDR_SS: return "ss"; + case NDR_DS: return "ds"; + case NDR_FS: return "fs"; + case NDR_GS: return "gs"; + case NDR_INV6: return "inv6"; + case NDR_INV7: return "inv7"; } return ""; diff --git a/inc/cpuidflags.h b/inc/cpuidflags.h index 3b7aea7..bd1cbf9 100644 --- a/inc/cpuidflags.h +++ b/inc/cpuidflags.h @@ -7,102 +7,102 @@ #define ND_CFF(leaf, subleaf, reg, bit) ((uint64_t)(leaf) | ((uint64_t)((subleaf) & 0xFFFFFF) << 32) | ((uint64_t)(reg) << 56) | ((uint64_t)(bit) << 59)) -#define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 0) -#define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 5) -#define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 8) -#define ND_CFF_SEP ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 11) -#define ND_CFF_CMOV ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 15) -#define ND_CFF_CLFSH ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 19) -#define ND_CFF_MMX ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 23) -#define ND_CFF_FXSAVE ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 24) -#define ND_CFF_SSE ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 25) -#define ND_CFF_SSE2 ND_CFF(0x00000001, 0xFFFFFFFF, REG_EDX, 26) -#define ND_CFF_SSE3 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 0) -#define ND_CFF_PCLMULQDQ ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 1) -#define ND_CFF_MONITOR ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 3) -#define ND_CFF_VTX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 5) -#define ND_CFF_SMX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 6) -#define ND_CFF_SSSE3 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 9) -#define ND_CFF_FMA ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 12) -#define ND_CFF_SSE4 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 19) -#define ND_CFF_SSE42 ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 20) -#define ND_CFF_MOVBE ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 22) -#define ND_CFF_POPCNT ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 23) -#define ND_CFF_AES ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 25) -#define ND_CFF_XSAVE ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 26) -#define ND_CFF_AVX ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 28) -#define ND_CFF_F16C ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 29) -#define ND_CFF_RDRAND ND_CFF(0x00000001, 0xFFFFFFFF, REG_ECX, 30) -#define ND_CFF_RDWRFSGS ND_CFF(0x00000007, 0x00000000, REG_EBX, 0) -#define ND_CFF_SGX ND_CFF(0x00000007, 0x00000000, REG_EBX, 2) -#define ND_CFF_BMI1 ND_CFF(0x00000007, 0x00000000, REG_EBX, 3) -#define ND_CFF_HLE ND_CFF(0x00000007, 0x00000000, REG_EBX, 4) -#define ND_CFF_AVX2 ND_CFF(0x00000007, 0x00000000, REG_EBX, 5) -#define ND_CFF_BMI2 ND_CFF(0x00000007, 0x00000000, REG_EBX, 8) -#define ND_CFF_INVPCID ND_CFF(0x00000007, 0x00000000, REG_EBX, 10) -#define ND_CFF_RTM ND_CFF(0x00000007, 0x00000000, REG_EBX, 11) -#define ND_CFF_MPX ND_CFF(0x00000007, 0x00000000, REG_EBX, 14) -#define ND_CFF_AVX512F ND_CFF(0x00000007, 0x00000000, REG_EBX, 16) -#define ND_CFF_AVX512DQ ND_CFF(0x00000007, 0x00000000, REG_EBX, 17) -#define ND_CFF_RDSEED ND_CFF(0x00000007, 0x00000000, REG_EBX, 18) -#define ND_CFF_ADX ND_CFF(0x00000007, 0x00000000, REG_EBX, 19) -#define ND_CFF_SMAP ND_CFF(0x00000007, 0x00000000, REG_EBX, 20) -#define ND_CFF_AVX512IFMA ND_CFF(0x00000007, 0x00000000, REG_EBX, 21) -#define ND_CFF_PCOMMIT ND_CFF(0x00000007, 0x00000000, REG_EBX, 22) -#define ND_CFF_CLFSHOPT ND_CFF(0x00000007, 0x00000000, REG_EBX, 23) -#define ND_CFF_CLWB ND_CFF(0x00000007, 0x00000000, REG_EBX, 24) -#define ND_CFF_AVX512PF ND_CFF(0x00000007, 0x00000000, REG_EBX, 26) -#define ND_CFF_AVX512ER ND_CFF(0x00000007, 0x00000000, REG_EBX, 27) -#define ND_CFF_AVX512CD ND_CFF(0x00000007, 0x00000000, REG_EBX, 28) -#define ND_CFF_SHA ND_CFF(0x00000007, 0x00000000, REG_EBX, 29) -#define ND_CFF_AVX512BW ND_CFF(0x00000007, 0x00000000, REG_EBX, 30) -#define ND_CFF_PREFETCHWT1 ND_CFF(0x00000007, 0x00000000, REG_ECX, 0) -#define ND_CFF_AVX512VBMI ND_CFF(0x00000007, 0x00000000, REG_ECX, 1) -#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, REG_ECX, 3) -#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, REG_ECX, 5) -#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, REG_ECX, 6) -#define ND_CFF_CET_SS ND_CFF(0x00000007, 0x00000000, REG_ECX, 7) -#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 8) -#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, REG_ECX, 9) -#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 10) -#define ND_CFF_AVX512VNNI ND_CFF(0x00000007, 0x00000000, REG_ECX, 11) -#define ND_CFF_AVX512BITALG ND_CFF(0x00000007, 0x00000000, REG_ECX, 12) -#define ND_CFF_AVX512VPOPCNTDQ ND_CFF(0x00000007, 0x00000000, REG_ECX, 14) -#define ND_CFF_RDPID ND_CFF(0x00000007, 0x00000000, REG_ECX, 22) -#define ND_CFF_CLDEMOTE ND_CFF(0x00000007, 0x00000000, REG_ECX, 25) -#define ND_CFF_MOVDIRI ND_CFF(0x00000007, 0x00000000, REG_ECX, 27) -#define ND_CFF_MOVDIR64B ND_CFF(0x00000007, 0x00000000, REG_ECX, 28) -#define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, REG_ECX, 29) -#define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, REG_EDX, 2) -#define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, REG_EDX, 3) -#define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, REG_EDX, 8) -#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, REG_EDX, 14) -#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, REG_EDX, 16) -#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, REG_EDX, 18) -#define ND_CFF_CET_IBT ND_CFF(0x00000007, 0x00000000, REG_EDX, 20) -#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, REG_EDX, 22) -#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, REG_EDX, 24) -#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, REG_EDX, 25) -#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, REG_EAX, 5) -#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, REG_EAX, 0) -#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, REG_EAX, 1) -#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, REG_EAX, 3) -#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, REG_EBX, 4) -#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 2) -#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 5) -#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 6) -#define ND_CFF_PREFETCHW ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 8) -#define ND_CFF_FSC ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 11) -#define ND_CFF_XOP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 11) -#define ND_CFF_LWP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 15) -#define ND_CFF_FMA4 ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 16) -#define ND_CFF_TBM ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 21) -#define ND_CFF_INVLPGB ND_CFF(0x80000001, 0xFFFFFFFF, REG_EDX, 24) -#define ND_CFF_RDTSCP ND_CFF(0x80000001, 0xFFFFFFFF, REG_ECX, 27) -#define ND_CFF_3DNOW ND_CFF(0x80000001, 0xFFFFFFFF, REG_EDX, 31) -#define ND_CFF_WBNOINVD ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 9) -#define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 4) -#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, REG_EBX, 8) -#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, REG_EAX, 4) +#define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 0) +#define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 5) +#define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 8) +#define ND_CFF_SEP ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 11) +#define ND_CFF_CMOV ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 15) +#define ND_CFF_CLFSH ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 19) +#define ND_CFF_MMX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 23) +#define ND_CFF_FXSAVE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 24) +#define ND_CFF_SSE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 25) +#define ND_CFF_SSE2 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 26) +#define ND_CFF_SSE3 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 0) +#define ND_CFF_PCLMULQDQ ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 1) +#define ND_CFF_MONITOR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 3) +#define ND_CFF_VTX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 5) +#define ND_CFF_SMX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 6) +#define ND_CFF_SSSE3 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 9) +#define ND_CFF_FMA ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 12) +#define ND_CFF_SSE4 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 19) +#define ND_CFF_SSE42 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 20) +#define ND_CFF_MOVBE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 22) +#define ND_CFF_POPCNT ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 23) +#define ND_CFF_AES ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 25) +#define ND_CFF_XSAVE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 26) +#define ND_CFF_AVX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 28) +#define ND_CFF_F16C ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 29) +#define ND_CFF_RDRAND ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 30) +#define ND_CFF_RDWRFSGS ND_CFF(0x00000007, 0x00000000, NDR_EBX, 0) +#define ND_CFF_SGX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 2) +#define ND_CFF_BMI1 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 3) +#define ND_CFF_HLE ND_CFF(0x00000007, 0x00000000, NDR_EBX, 4) +#define ND_CFF_AVX2 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 5) +#define ND_CFF_BMI2 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 8) +#define ND_CFF_INVPCID ND_CFF(0x00000007, 0x00000000, NDR_EBX, 10) +#define ND_CFF_RTM ND_CFF(0x00000007, 0x00000000, NDR_EBX, 11) +#define ND_CFF_MPX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 14) +#define ND_CFF_AVX512F ND_CFF(0x00000007, 0x00000000, NDR_EBX, 16) +#define ND_CFF_AVX512DQ ND_CFF(0x00000007, 0x00000000, NDR_EBX, 17) +#define ND_CFF_RDSEED ND_CFF(0x00000007, 0x00000000, NDR_EBX, 18) +#define ND_CFF_ADX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 19) +#define ND_CFF_SMAP ND_CFF(0x00000007, 0x00000000, NDR_EBX, 20) +#define ND_CFF_AVX512IFMA ND_CFF(0x00000007, 0x00000000, NDR_EBX, 21) +#define ND_CFF_PCOMMIT ND_CFF(0x00000007, 0x00000000, NDR_EBX, 22) +#define ND_CFF_CLFSHOPT ND_CFF(0x00000007, 0x00000000, NDR_EBX, 23) +#define ND_CFF_CLWB ND_CFF(0x00000007, 0x00000000, NDR_EBX, 24) +#define ND_CFF_AVX512PF ND_CFF(0x00000007, 0x00000000, NDR_EBX, 26) +#define ND_CFF_AVX512ER ND_CFF(0x00000007, 0x00000000, NDR_EBX, 27) +#define ND_CFF_AVX512CD ND_CFF(0x00000007, 0x00000000, NDR_EBX, 28) +#define ND_CFF_SHA ND_CFF(0x00000007, 0x00000000, NDR_EBX, 29) +#define ND_CFF_AVX512BW ND_CFF(0x00000007, 0x00000000, NDR_EBX, 30) +#define ND_CFF_PREFETCHWT1 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 0) +#define ND_CFF_AVX512VBMI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 1) +#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, NDR_ECX, 3) +#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, NDR_ECX, 5) +#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 6) +#define ND_CFF_CET_SS ND_CFF(0x00000007, 0x00000000, NDR_ECX, 7) +#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 8) +#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, NDR_ECX, 9) +#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, NDR_ECX, 10) +#define ND_CFF_AVX512VNNI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 11) +#define ND_CFF_AVX512BITALG ND_CFF(0x00000007, 0x00000000, NDR_ECX, 12) +#define ND_CFF_AVX512VPOPCNTDQ ND_CFF(0x00000007, 0x00000000, NDR_ECX, 14) +#define ND_CFF_RDPID ND_CFF(0x00000007, 0x00000000, NDR_ECX, 22) +#define ND_CFF_CLDEMOTE ND_CFF(0x00000007, 0x00000000, NDR_ECX, 25) +#define ND_CFF_MOVDIRI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 27) +#define ND_CFF_MOVDIR64B ND_CFF(0x00000007, 0x00000000, NDR_ECX, 28) +#define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, NDR_ECX, 29) +#define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, NDR_EDX, 2) +#define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, NDR_EDX, 3) +#define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 8) +#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 14) +#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, NDR_EDX, 16) +#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, NDR_EDX, 18) +#define ND_CFF_CET_IBT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 20) +#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 22) +#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24) +#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25) +#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5) +#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0) +#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1) +#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3) +#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, NDR_EBX, 4) +#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 2) +#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 5) +#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 6) +#define ND_CFF_PREFETCHW ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 8) +#define ND_CFF_FSC ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 11) +#define ND_CFF_XOP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 11) +#define ND_CFF_LWP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 15) +#define ND_CFF_FMA4 ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 16) +#define ND_CFF_TBM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 21) +#define ND_CFF_INVLPGB ND_CFF(0x80000001, 0xFFFFFFFF, NDR_EDX, 24) +#define ND_CFF_RDTSCP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 27) +#define ND_CFF_3DNOW ND_CFF(0x80000001, 0xFFFFFFFF, NDR_EDX, 31) +#define ND_CFF_WBNOINVD ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 9) +#define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 4) +#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 8) +#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 4) #endif // CPUID_FLAGS_H diff --git a/inc/registers.h b/inc/registers.h index 6756186..22c12d9 100644 --- a/inc/registers.h +++ b/inc/registers.h @@ -10,139 +10,139 @@ // enum { - REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, - REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, + NDR_RAX, NDR_RCX, NDR_RDX, NDR_RBX, NDR_RSP, NDR_RBP, NDR_RSI, NDR_RDI, + NDR_R8, NDR_R9, NDR_R10, NDR_R11, NDR_R12, NDR_R13, NDR_R14, NDR_R15, }; enum { - REG_EAX, REG_ECX, REG_EDX, REG_EBX, REG_ESP, REG_EBP, REG_ESI, REG_EDI, - REG_R8D, REG_R9D, REG_R10D,REG_R11D,REG_R12D,REG_R13D,REG_R14D,REG_R15D, + NDR_EAX, NDR_ECX, NDR_EDX, NDR_EBX, NDR_ESP, NDR_EBP, NDR_ESI, NDR_EDI, + NDR_R8D, NDR_R9D, NDR_R10D,NDR_R11D,NDR_R12D,NDR_R13D,NDR_R14D,NDR_R15D, }; enum { - REG_AX, REG_CX, REG_DX, REG_BX, REG_SP, REG_BP, REG_SI, REG_DI, - REG_R8W, REG_R9W, REG_R10W,REG_R11W,REG_R12W,REG_R13W,REG_R14W,REG_R15W, + NDR_AX, NDR_CX, NDR_DX, NDR_BX, NDR_SP, NDR_BP, NDR_SI, NDR_DI, + NDR_R8W, NDR_R9W, NDR_R10W,NDR_R11W,NDR_R12W,NDR_R13W,NDR_R14W,NDR_R15W, }; enum { - REG_AL, REG_CL, REG_DL, REG_BL, REG_AH, REG_CH, REG_DH, REG_BH, + NDR_AL, NDR_CL, NDR_DL, NDR_BL, NDR_AH, NDR_CH, NDR_DH, NDR_BH, }; enum { - REG_AL64, REG_CL64, REG_DL64, REG_BL64, REG_SPL, REG_BPL, REG_SIL, REG_DIL, - REG_R8L, REG_R9L, REG_R10L, REG_R11L, REG_R12L, REG_R13L, REG_R14L, REG_R15L, + NDR_AL64, NDR_CL64, NDR_DL64, NDR_BL64, NDR_SPL, NDR_BPL, NDR_SIL, NDR_DIL, + NDR_R8L, NDR_R9L, NDR_R10L, NDR_R11L, NDR_R12L, NDR_R13L, NDR_R14L, NDR_R15L, }; enum { - REG_ES, REG_CS, REG_SS, REG_DS, REG_FS, REG_GS, REG_INV6, REG_INV7, + NDR_ES, NDR_CS, NDR_SS, NDR_DS, NDR_FS, NDR_GS, NDR_INV6, NDR_INV7, }; enum { - REG_CR0, REG_CR1, REG_CR2, REG_CR3, REG_CR4, REG_CR5, REG_CR6, REG_CR7, - REG_CR8, REG_CR9, REG_CR10, REG_CR11, REG_CR12, REG_CR13, REG_CR14, REG_CR15, + NDR_CR0, NDR_CR1, NDR_CR2, NDR_CR3, NDR_CR4, NDR_CR5, NDR_CR6, NDR_CR7, + NDR_CR8, NDR_CR9, NDR_CR10, NDR_CR11, NDR_CR12, NDR_CR13, NDR_CR14, NDR_CR15, }; enum { - REG_DR0, REG_DR1, REG_DR2, REG_DR3, REG_DR4, REG_DR5, REG_DR6, REG_DR7, - REG_DR8, REG_DR9, REG_DR10, REG_DR11, REG_DR12, REG_DR13, REG_DR14, REG_DR15, + NDR_DR0, NDR_DR1, NDR_DR2, NDR_DR3, NDR_DR4, NDR_DR5, NDR_DR6, NDR_DR7, + NDR_DR8, NDR_DR9, NDR_DR10, NDR_DR11, NDR_DR12, NDR_DR13, NDR_DR14, NDR_DR15, }; enum { - REG_TR0, REG_TR1, REG_TR2, REG_TR3, REG_TR4, REG_TR5, REG_TR6, REG_TR7, - REG_TR8, REG_TR9, REG_TR10, REG_TR11, REG_TR12, REG_TR13, REG_TR14, REG_TR15, + NDR_TR0, NDR_TR1, NDR_TR2, NDR_TR3, NDR_TR4, NDR_TR5, NDR_TR6, NDR_TR7, + NDR_TR8, NDR_TR9, NDR_TR10, NDR_TR11, NDR_TR12, NDR_TR13, NDR_TR14, NDR_TR15, }; enum { - REG_K0, REG_K1, REG_K2, REG_K3, REG_K4, REG_K5, REG_K6, REG_K7, + NDR_K0, NDR_K1, NDR_K2, NDR_K3, NDR_K4, NDR_K5, NDR_K6, NDR_K7, }; enum { - REG_BND0, REG_BND1, REG_BND2, REG_BND3, + NDR_BND0, NDR_BND1, NDR_BND2, NDR_BND3, }; enum { - REG_ST0, REG_ST1, REG_ST2, REG_ST3, REG_ST4, REG_ST5, REG_ST6, REG_ST7, + NDR_ST0, NDR_ST1, NDR_ST2, NDR_ST3, NDR_ST4, NDR_ST5, NDR_ST6, NDR_ST7, }; enum { - REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7, - REG_XMM8, REG_XMM9, REG_XMM10, REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15, - REG_XMM16, REG_XMM17, REG_XMM18, REG_XMM19, REG_XMM20, REG_XMM21, REG_XMM22, REG_XMM23, - REG_XMM24, REG_XMM25, REG_XMM26, REG_XMM27, REG_XMM28, REG_XMM29, REG_XMM30, REG_XMM31, + NDR_XMM0, NDR_XMM1, NDR_XMM2, NDR_XMM3, NDR_XMM4, NDR_XMM5, NDR_XMM6, NDR_XMM7, + NDR_XMM8, NDR_XMM9, NDR_XMM10, NDR_XMM11, NDR_XMM12, NDR_XMM13, NDR_XMM14, NDR_XMM15, + NDR_XMM16, NDR_XMM17, NDR_XMM18, NDR_XMM19, NDR_XMM20, NDR_XMM21, NDR_XMM22, NDR_XMM23, + NDR_XMM24, NDR_XMM25, NDR_XMM26, NDR_XMM27, NDR_XMM28, NDR_XMM29, NDR_XMM30, NDR_XMM31, }; enum { - REG_YMM0, REG_YMM1, REG_YMM2, REG_YMM3, REG_YMM4, REG_YMM5, REG_YMM6, REG_YMM7, - REG_YMM8, REG_YMM9, REG_YMM10, REG_YMM11, REG_YMM12, REG_YMM13, REG_YMM14, REG_YMM15, - REG_YMM16, REG_YMM17, REG_YMM18, REG_YMM19, REG_YMM20, REG_YMM21, REG_YMM22, REG_YMM23, - REG_YMM24, REG_YMM25, REG_YMM26, REG_YMM27, REG_YMM28, REG_YMM29, REG_YMM30, REG_YMM31, + NDR_YMM0, NDR_YMM1, NDR_YMM2, NDR_YMM3, NDR_YMM4, NDR_YMM5, NDR_YMM6, NDR_YMM7, + NDR_YMM8, NDR_YMM9, NDR_YMM10, NDR_YMM11, NDR_YMM12, NDR_YMM13, NDR_YMM14, NDR_YMM15, + NDR_YMM16, NDR_YMM17, NDR_YMM18, NDR_YMM19, NDR_YMM20, NDR_YMM21, NDR_YMM22, NDR_YMM23, + NDR_YMM24, NDR_YMM25, NDR_YMM26, NDR_YMM27, NDR_YMM28, NDR_YMM29, NDR_YMM30, NDR_YMM31, }; enum { - REG_ZMM0, REG_ZMM1, REG_ZMM2, REG_ZMM3, REG_ZMM4, REG_ZMM5, REG_ZMM6, REG_ZMM7, - REG_ZMM8, REG_ZMM9, REG_ZMM10, REG_ZMM11, REG_ZMM12, REG_ZMM13, REG_ZMM14, REG_ZMM15, - REG_ZMM16, REG_ZMM17, REG_ZMM18, REG_ZMM19, REG_ZMM20, REG_ZMM21, REG_ZMM22, REG_ZMM23, - REG_ZMM24, REG_ZMM25, REG_ZMM26, REG_ZMM27, REG_ZMM28, REG_ZMM29, REG_ZMM30, REG_ZMM31, + NDR_ZMM0, NDR_ZMM1, NDR_ZMM2, NDR_ZMM3, NDR_ZMM4, NDR_ZMM5, NDR_ZMM6, NDR_ZMM7, + NDR_ZMM8, NDR_ZMM9, NDR_ZMM10, NDR_ZMM11, NDR_ZMM12, NDR_ZMM13, NDR_ZMM14, NDR_ZMM15, + NDR_ZMM16, NDR_ZMM17, NDR_ZMM18, NDR_ZMM19, NDR_ZMM20, NDR_ZMM21, NDR_ZMM22, NDR_ZMM23, + NDR_ZMM24, NDR_ZMM25, NDR_ZMM26, NDR_ZMM27, NDR_ZMM28, NDR_ZMM29, NDR_ZMM30, NDR_ZMM31, }; enum { - REG_GDTR, REG_IDTR, REG_LDTR, REG_TR, + NDR_GDTR, NDR_IDTR, NDR_LDTR, NDR_TR, }; enum { - REG_X87_CONTROL, REG_X87_TAG, REG_X87_STATUS, + NDR_X87_CONTROL, NDR_X87_TAG, NDR_X87_STATUS, }; enum { - REG_XCR0, REG_XCR1, REG_XCR_ANY = 0xFF, + NDR_XCR0, NDR_XCR1, NDR_XCR_ANY = 0xFF, }; -#define REG_IA32_TSC 0x00000010 -#define REG_IA32_SYSENTER_CS 0x00000174 -#define REG_IA32_SYSENTER_ESP 0x00000175 -#define REG_IA32_SYSENTER_EIP 0x00000176 -#define REG_IA32_STAR 0xC0000081 -#define REG_IA32_LSTAR 0xC0000082 -#define REG_IA32_FMASK 0xC0000084 -#define REG_IA32_FS_BASE 0xC0000100 -#define REG_IA32_GS_BASE 0xC0000101 -#define REG_IA32_KERNEL_GS_BASE 0xC0000102 -#define REG_IA32_TSC_AUX 0xC0000103 -#define REG_MSR_ANY 0xFFFFFFFF +#define NDR_IA32_TSC 0x00000010 +#define NDR_IA32_SYSENTER_CS 0x00000174 +#define NDR_IA32_SYSENTER_ESP 0x00000175 +#define NDR_IA32_SYSENTER_EIP 0x00000176 +#define NDR_IA32_STAR 0xC0000081 +#define NDR_IA32_LSTAR 0xC0000082 +#define NDR_IA32_FMASK 0xC0000084 +#define NDR_IA32_FS_BASE 0xC0000100 +#define NDR_IA32_GS_BASE 0xC0000101 +#define NDR_IA32_KERNEL_GS_BASE 0xC0000102 +#define NDR_IA32_TSC_AUX 0xC0000103 +#define NDR_MSR_ANY 0xFFFFFFFF -#define REG_RFLAG_CF (1 << 0) -#define REG_RFLAG_PF (1 << 2) -#define REG_RFLAG_AF (1 << 4) -#define REG_RFLAG_ZF (1 << 6) -#define REG_RFLAG_SF (1 << 7) -#define REG_RFLAG_TF (1 << 8) -#define REG_RFLAG_IF (1 << 9) -#define REG_RFLAG_DF (1 << 10) -#define REG_RFLAG_OF (1 << 11) -#define REG_RFLAG_IOPL (3 << 12) -#define REG_RFLAG_NT (1 << 14) -#define REG_RFLAG_RF (1 << 16) -#define REG_RFLAG_VM (1 << 17) -#define REG_RFLAG_AC (1 << 18) -#define REG_RFLAG_VIF (1 << 19) -#define REG_RFLAG_VIP (1 << 20) -#define REG_RFLAG_ID (1 << 21) +#define NDR_RFLAG_CF (1 << 0) +#define NDR_RFLAG_PF (1 << 2) +#define NDR_RFLAG_AF (1 << 4) +#define NDR_RFLAG_ZF (1 << 6) +#define NDR_RFLAG_SF (1 << 7) +#define NDR_RFLAG_TF (1 << 8) +#define NDR_RFLAG_IF (1 << 9) +#define NDR_RFLAG_DF (1 << 10) +#define NDR_RFLAG_OF (1 << 11) +#define NDR_RFLAG_IOPL (3 << 12) +#define NDR_RFLAG_NT (1 << 14) +#define NDR_RFLAG_RF (1 << 16) +#define NDR_RFLAG_VM (1 << 17) +#define NDR_RFLAG_AC (1 << 18) +#define NDR_RFLAG_VIF (1 << 19) +#define NDR_RFLAG_VIP (1 << 20) +#define NDR_RFLAG_ID (1 << 21) #endif diff --git a/inc/version.h b/inc/version.h index d33017a..4a7e761 100644 --- a/inc/version.h +++ b/inc/version.h @@ -6,7 +6,7 @@ #define DISASM_VER_H #define DISASM_VERSION_MAJOR 1 -#define DISASM_VERSION_MINOR 26 -#define DISASM_VERSION_REVISION 3 +#define DISASM_VERSION_MINOR 27 +#define DISASM_VERSION_REVISION 0 #endif // DISASM_VER_H diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py index 1f005d3..9963ebe 100644 --- a/isagenerator/generate_tables.py +++ b/isagenerator/generate_tables.py @@ -540,7 +540,7 @@ def cdef_instruction(self): if m == '1' or m == '0': dst = dst + self.RevFlagsAccess['u'] for f in dst: - flg += '|REG_RFLAG_%s' % f.upper() + flg += '|NDR_RFLAG_%s' % f.upper() c += "\n %s," % flg # Add the instruction operands @@ -1202,7 +1202,7 @@ def generate_features(features, fname): f.write('\n') for c in features: - f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'REG_' + c.Reg, c.Bit)) + f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'NDR_' + c.Reg, c.Bit)) f.write('\n') diff --git a/pydis/_pydis/pydis.c b/pydis/_pydis/pydis.c index 6f0507d..46e0cf6 100644 --- a/pydis/_pydis/pydis.c +++ b/pydis/_pydis/pydis.c @@ -33,7 +33,7 @@ nd_vsnprintf_s(char *str, size_t sizeOfBuffer, size_t count, const char *format, return vsnprintf(str, count, format, args); } -int nd_memset(void *s, int c, size_t n) +void *nd_memset(void *s, int c, size_t n) { - memset(s, c, n); + return memset(s, c, n); }