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bddisasm/isagenerator/instructions/table_vex2.dat

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Typo fixes in the instruction tables. Added a reference to the git repo in the documentation.
2020-07-21 13:38:09 +00:00
# Mnemonic Explicit Operands Implicit Operands Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
Initial commit.
2020-07-21 08:19:18 +00:00
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x00 - 0x0F
VPSHUFB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x00 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHADDW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x01 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHADDD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x02 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHADDSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x03 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMADDUBSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x04 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHSUBW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x05 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHSUBD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x06 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHSUBSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x07 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSIGNB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x08 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSIGNW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x09 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSIGND Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x0A /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMULHRSW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x0B /r] s:AVX, t:AVX, w:W|R|R, e:4
VPERMILPS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x0C /r] s:AVX, t:AVX, w:W|R|R, e:4
VPERMILPD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x0D /r] s:AVX, t:AVX, w:W|R|R, e:4
VTESTPS Vx,Wx Fv [vex m:2 p:1 l:x w:0 0x0E /r] s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4
VTESTPD Vx,Wx Fv [vex m:2 p:1 l:x w:0 0x0F /r] s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4
# 0x10 - 0x1F
VCVTPH2PS Vdq,Wq nil [vex m:2 p:1 l:0 w:0 0x13 /r] s:F16C, t:CONVERT, w:W|R, e:11
VCVTPH2PS Vqq,Wdq nil [vex m:2 p:1 l:1 w:0 0x13 /r] s:F16C, t:CONVERT, w:W|R, e:11
VPERMPS Vqq,Hqq,Wqq nil [vex m:2 p:1 l:1 w:0 0x16 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
VPTEST Vx,Wx Fv [vex m:2 p:1 l:x w:i 0x17 /r] s:AVX, t:LOGICAL, w:R|R|W, f:VPTEST, e:4
VBROADCASTSS Vx,Wss nil [vex m:2 p:1 l:x w:0 0x18 /r] s:AVX, t:BROADCAST, w:W|R, e:6
VBROADCASTSD Vqq,Wsd nil [vex m:2 p:1 l:x w:0 0x19 /r] s:AVX, t:BROADCAST, w:W|R, e:6
VBROADCASTF128 Vqq,Mdq nil [vex m:2 p:1 l:1 w:0 0x1A /r:mem] s:AVX, t:BROADCAST, w:W|R, e:6
VPABSB Vx,Wx nil [vex m:2 p:1 l:x w:i 0x1C /r] s:AVX, t:AVX, w:W|R, e:4
VPABSW Vx,Wx nil [vex m:2 p:1 l:x w:i 0x1D /r] s:AVX, t:AVX, w:W|R, e:4
VPABSD Vx,Wx nil [vex m:2 p:1 l:x w:i 0x1E /r] s:AVX, t:AVX, w:W|R, e:4
# 0x20 - 0x2F
VPMOVSXBW Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x20 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVSXBW Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x20 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVSXBD Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x21 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVSXBD Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x21 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVSXBQ Vdq,Ww nil [vex m:2 p:1 l:0 w:i 0x22 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVSXBQ Vqq,Wd nil [vex m:2 p:1 l:1 w:i 0x22 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVSXWD Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x23 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVSXWD Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x23 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVSXWQ Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x24 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVSXWQ Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x24 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVSXDQ Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x25 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVSXDQ Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x25 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMULDQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x28 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPEQQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x29 /r] s:AVX, t:AVX, w:W|R|R, e:4
VMOVNTDQA Vx,Mx nil [vex m:2 p:1 l:x w:i 0x2A /r:mem] s:AVX, t:AVX, w:W|R, e:1
VPACKUSDW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x2B /r] s:AVX, t:AVX, w:W|R|R, e:4
VMASKMOVPS Vx,Hx,Mx nil [vex m:2 p:1 l:x w:0 0x2C /r:mem] s:AVX, t:AVX, w:W|R|R, e:6
VMASKMOVPD Vx,Hx,Mx nil [vex m:2 p:1 l:x w:0 0x2D /r:mem] s:AVX, t:AVX, w:W|R|R, e:6
VMASKMOVPS Mx,Hx,Vx nil [vex m:2 p:1 l:x w:0 0x2E /r:mem] s:AVX, t:AVX, w:W|R|R, e:6
VMASKMOVPD Mx,Hx,Vx nil [vex m:2 p:1 l:x w:0 0x2F /r:mem] s:AVX, t:AVX, w:W|R|R, e:6
# 0x30 - 0x3F
VPMOVZXBW Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x30 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVZXBW Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x30 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVZXBD Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x31 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVZXBD Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x31 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVZXBQ Vdq,Ww nil [vex m:2 p:1 l:0 w:i 0x32 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVZXBQ Vqq,Wd nil [vex m:2 p:1 l:1 w:i 0x32 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVZXWD Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x33 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVZXWD Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x33 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVZXWQ Vdq,Wd nil [vex m:2 p:1 l:0 w:i 0x34 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVZXWQ Vqq,Wq nil [vex m:2 p:1 l:1 w:i 0x34 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPMOVZXDQ Vdq,Wq nil [vex m:2 p:1 l:0 w:i 0x35 /r] s:AVX, t:AVX, w:W|R, e:5
VPMOVZXDQ Vqq,Wdq nil [vex m:2 p:1 l:1 w:i 0x35 /r] s:AVX2, t:AVX2, w:W|R, e:5
VPERMD Vqq,Hqq,Wqq nil [vex m:2 p:1 l:1 w:0 0x36 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
VPCMPGTQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x37 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMINSB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x38 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMINSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x39 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMINUW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3A /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMINUD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3B /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMAXSB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3C /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMAXSD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3D /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMAXUW Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3E /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMAXUD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x3F /r] s:AVX, t:AVX, w:W|R|R, e:4
# 0x40 - 0x4F
VPMULLD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0x40 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPHMINPOSUW Vdq,Wdq nil [vex m:2 p:1 l:0 w:i 0x41 /r] s:AVX, t:AVX, w:W|R, e:4
VPSRLVD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x45 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
VPSRLVQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x45 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
VPSRAVD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x46 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
VPSLLVD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x47 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
VPSLLVQ Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x47 /r] s:AVX2, t:AVX2, w:W|R|R, e:4
LDTILECFG Moq nil [vex m:2 p:0 l:0 w:0 0x49 /0:mem] s:AMXTILE, t:AMX, w:R, m:NOTSX|O64, e:AMX_E1
STTILECFG Moq nil [vex m:2 p:1 l:0 w:0 0x49 /0:mem] s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E2
TILELOADD rTt,Mt nil [vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem] s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
TILESTORED Mt,rTt nil [vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem] s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
TILELOADDT1 rTt,Mt nil [vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem] s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
TILERELEASE nil nil [vex m:2 p:0 l:0 w:0 0x49 /0xC0] s:AMXTILE, t:AMX, m:NOTSX|O64, e:AMX_E6
TILEZERO rTt nil [vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0] s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5
# 0x50 - 0x5F
VPBROADCASTD Vx,Wd nil [vex m:2 p:1 l:x w:0 0x58 /r] s:AVX2, t:BROADCAST, w:W|R, e:6
VPBROADCASTQ Vx,Wq nil [vex m:2 p:1 l:x w:0 0x59 /r] s:AVX2, t:BROADCAST, w:W|R, e:6
VBROADCASTI128 Vqq,Mdq nil [vex m:2 p:1 l:1 w:0 0x5A /r:mem] s:AVX2, t:BROADCAST, w:W|R, e:6
TDPBF16PS rTt,mTt,vTt nil [vex m:2 p:2 l:0 w:0 0x5C /r:reg] s:AMXBF16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
TDPBUUD rTt,mTt,vTt nil [vex m:2 p:0 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
TDPBUSD rTt,mTt,vTt nil [vex m:2 p:1 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
TDPBSUD rTt,mTt,vTt nil [vex m:2 p:2 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
TDPBSSD rTt,mTt,vTt nil [vex m:2 p:3 l:0 w:0 0x5E /r:reg] s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
# 0x60 - 0x6F
# 0x70 - 0x7F
VPBROADCASTB Vx,Wb nil [vex m:2 p:1 l:x w:0 0x78 /r] s:AVX2, t:BROADCAST, w:W|R, e:6
VPBROADCASTW Vx,Ww nil [vex m:2 p:1 l:x w:0 0x79 /r] s:AVX2, t:BROADCAST, w:W|R, e:6
# 0x80 - 0x8F
VPMASKMOVD Vx,Hx,Mx nil [vex m:2 p:1 l:x w:0 0x8C /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6
VPMASKMOVQ Vx,Hx,Mx nil [vex m:2 p:1 l:x w:1 0x8C /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6
VPMASKMOVD Mx,Hx,Vx nil [vex m:2 p:1 l:x w:0 0x8E /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6
VPMASKMOVQ Mx,Hx,Vx nil [vex m:2 p:1 l:x w:1 0x8E /r:mem] s:AVX2, t:AVX2, w:W|R|R, e:6
# 0x90 - 0x9F
VPGATHERDD Vx,Mvm32n,Hx nil [vex m:2 p:1 l:x w:0 0x90 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VPGATHERDQ Vx,Mvm32h,Hx nil [vex m:2 p:1 l:x w:1 0x90 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VPGATHERQD Vdq,Mvm64n,Hdq nil [vex m:2 p:1 l:x w:0 0x91 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VPGATHERQQ Vx,Mvm64n,Hx nil [vex m:2 p:1 l:x w:1 0x91 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VGATHERDPS Vx,Mvm32n,Hx nil [vex m:2 p:1 l:x w:0 0x92 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VGATHERDPD Vx,Mvm32h,Hx nil [vex m:2 p:1 l:x w:1 0x92 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VGATHERQPS Vdq,Mvm64n,Hdq nil [vex m:2 p:1 l:x w:0 0x93 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VGATHERQPD Vx,Mvm64n,Hx nil [vex m:2 p:1 l:x w:1 0x93 /r:mem vsib] s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
VFMADDSUB132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x96 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADDSUB132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x96 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUBADD132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x97 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUBADD132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x97 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADD132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x98 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADD132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x98 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFMADD132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0x99 /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFMADD132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0x99 /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFMSUB132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x9A /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUB132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x9A /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFMSUB132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0x9B /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFMSUB132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0x9B /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFNMADD132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x9C /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMADD132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x9C /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMADD132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0x9D /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMADD132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0x9D /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMSUB132PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0x9E /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMSUB132PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0x9E /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFNMSUB132SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0x9F /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMSUB132SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0x9F /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xA0 - 0xAF
VFMADDSUB213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xA6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADDSUB213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xA6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUBADD213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xA7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUBADD213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xA7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADD213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xA8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADD213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xA8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFMADD213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xA9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFMADD213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xA9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFMSUB213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xAA /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUB213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xAA /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFMSUB213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xAB /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFMSUB213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xAB /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFNMADD213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xAC /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMADD213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xAC /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFNMADD213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xAD /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMADD213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xAD /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFNMSUB213PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xAE /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMSUB213PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xAE /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFNMSUB213SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xAF /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMSUB213SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xAF /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xB0 - 0xBF
VFMADDSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADDSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB6 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUBADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUBADD231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB7 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xB8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMADD231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xB8 /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFMADD231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xB9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFMADD231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xB9 /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFMSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xBA /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFMSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xBA /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFMSUB231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xBB /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFMSUB231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xBB /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFNMADD231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xBC /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMADD231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xBC /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFNMADD231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xBD /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMADD231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xBD /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VFNMSUB231PS Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xBE /r] s:FMA, t:VFMA, w:RW|R|R, e:2
VFNMSUB231PD Vx,Hx,Wx nil [vex m:2 p:1 l:x w:1 0xBE /r] s:FMA, t:VFMA, w:RW|R|R, e:2
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VFNMSUB231SS Vdq,Hdq,Wss nil [vex m:2 p:1 l:i w:0 0xBF /r] s:FMA, t:VFMA, w:RW|R|R, e:3
VFNMSUB231SD Vdq,Hdq,Wsd nil [vex m:2 p:1 l:i w:1 0xBF /r] s:FMA, t:VFMA, w:RW|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VGF2P8MULB Vx,Hx,Wx nil [vex m:2 p:1 l:x w:0 0xCF /r] s:GFNI, t:GFNI, w:W|R|R
VAESIMC Vdq,Wdq nil [vex m:2 p:1 l:0 w:i 0xDB /r] s:AES, t:AES, w:W|R, e:4
VAESENC Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDC /r] s:AES, t:AES, w:W|R|R, e:4
VAESENCLAST Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDD /r] s:AES, t:AES, w:W|R|R, e:4
VAESDEC Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDE /r] s:AES, t:AES, w:W|R|R, e:4
VAESDECLAST Vx,Hx,Wx nil [vex m:2 p:1 l:x w:i 0xDF /r] s:AES, t:AES, w:W|R|R, e:4
# 0xF0 - 0xFF
ANDN Gy,By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF2 /r] s:BMI1, t:BMI1, w:W|R|R|W, f:CF=0|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13
BLSR By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /1] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13
BLSMSK By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /2] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=0|SF=m|OF=0, e:13
BLSI By,Ey Fv [vex m:2 p:0 l:0 w:x 0xF3 /3] s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13
BZHI Gy,Ey,By Fv [vex m:2 p:0 l:0 w:x 0xF5 /r] s:BMI2, t:BMI2, w:W|R|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13
PEXT Gy,By,Ey nil [vex m:2 p:2 l:0 w:x 0xF5 /r] s:BMI2, t:BMI2, w:W|R|R|W, e:13
PDEP Gy,By,Ey nil [vex m:2 p:3 l:0 w:x 0xF5 /r] s:BMI2, t:BMI2, w:W|R|R|W, e:13
MULX Gy,By,Ey yDX [vex m:2 p:3 l:0 w:x 0xF6 /r] s:BMI2, t:BMI2, w:W|W|R|R, e:13
BEXTR Gy,Ey,By Fv [vex m:2 p:0 l:0 w:x 0xF7 /r] s:BMI1, t:BMI1, w:W|R|R|W, f:CF=0|PF=u|AF=u|ZF=m|SF=u|OF=0, e:13
SHLX Gy,Ey,By nil [vex m:2 p:1 l:0 w:x 0xF7 /r] s:BMI2, t:BMI2, w:W|R|R, e:13
SARX Gy,Ey,By nil [vex m:2 p:2 l:0 w:x 0xF7 /r] s:BMI2, t:BMI2, w:W|R|R, e:13
SHRX Gy,Ey,By nil [vex m:2 p:3 l:0 w:x 0xF7 /r] s:BMI2, t:BMI2, w:W|R|R, e:13
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