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bddisasm/bddisasm_test/avx/avx2gather_64.result

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Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
0000000000000000 c4e2919294fb00100000 VGATHERDPD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 4, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
000000000000000A c4e2119294fb00100000 VGATHERDPS xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
0000000000000014 c4e2919394fb00100000 VGATHERQPD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 8, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
000000000000001E c4e2119394fb00100000 VGATHERQPS xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 8, VSIB element size: 4, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
0000000000000028 c4e2159394cb00100000 VGATHERQPS xmm2, dword ptr [rbx+ymm1*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 32, ASIZE: 64, VLEN: 256
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 1 * 8, Displacement: 0x0000000000001000,
VSIB index size: 8, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
0000000000000032 c4e2119094fb00100000 VPGATHERDD xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
000000000000003C c4e2919094fb00100000 VPGATHERDQ xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 4, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
0000000000000046 c4e2119194fb00100000 VPGATHERQD xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 8, VSIB element size: 4, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
0000000000000050 c4e2159194cb00100000 VPGATHERQD xmm2, dword ptr [rbx+ymm1*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 32, ASIZE: 64, VLEN: 256
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 1 * 8, Displacement: 0x0000000000001000,
VSIB index size: 8, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
000000000000005A c4e2919194fb00100000 VPGATHERQQ xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
Initial commit.
2020-07-21 08:19:18 +00:00
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM: yes, SGX: yes, TSX: yes, VMXRoot: yes, VMXNonRoot: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Added dedicated Prefetch operand access type. Internally, store the access type sepparately than the flags. Dump conditional operand accesses with exi option too.
2020-07-25 14:16:35 +00:00
Operand: 0, Acc: CRW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, VSIB Addressing: yes,
Segment: 3, Base: 3, Index: 7 * 8, Displacement: 0x0000000000001000,
VSIB index size: 8, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
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