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bddisasm/isagenerator/instructions/table_fpu.dat

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Initial commit.
2020-07-21 08:19:18 +00:00
# Mnemonic Explicit Implicit Operands Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0xD8 FPU instructions, mod mem
FADD ST(0),Mfd X87STATUS [0xD8 /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FMUL ST(0),Mfd X87STATUS [0xD8 /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FCOM ST(0),Mfd X87STATUS [0xD8 /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FCOMP ST(0),Mfd X87STATUS [0xD8 /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FSUB ST(0),Mfd X87STATUS [0xD8 /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FSUBR ST(0),Mfd X87STATUS [0xD8 /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIV ST(0),Mfd X87STATUS [0xD8 /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIVR ST(0),Mfd X87STATUS [0xD8 /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FADD ST(0),ST(i) X87STATUS [0xD8 /0:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FMUL ST(0),ST(i) X87STATUS [0xD8 /1:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FCOM ST(0),ST(i) X87STATUS [0xD8 /2:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FCOMP ST(0),ST(i) X87STATUS [0xD8 /3:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FSUB ST(0),ST(i) X87STATUS [0xD8 /4:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FSUBR ST(0),ST(i) X87STATUS [0xD8 /5:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIV ST(0),ST(i) X87STATUS [0xD8 /6:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIVR ST(0),ST(i) X87STATUS [0xD8 /7:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
# 0xD9
FLD ST(0),Mfd X87STATUS [0xD9 /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FST Mfd,ST(0) X87STATUS [0xD9 /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FSTP Mfd,ST(0) X87STATUS [0xD9 /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FLDENV Mfe X87STATUS [0xD9 /4:mem] s:X87, t:X87_ALU, w:R|W, u:C0=m|C1=m|C2=m|C3=m
FLDCW Mw X87CONTROL,X87STATUS [0xD9 /5:mem] s:X87, t:X87_ALU, w:R|W|W, u:C0=u|C1=u|C2=u|C3=u
FNSTENV Mfe X87STATUS [0xD9 /6:mem] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u
FNSTCW Mw X87CONTROL,X87STATUS [0xD9 /7:mem] s:X87, t:X87_ALU, w:W|R|W, u:C0=u|C1=u|C2=u|C3=u
FNOP nil nil [0xD9 /0xD0] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u
FCHS nil X87STATUS [0xD9 /0xE0] s:X87, t:X87_ALU, w:W, u:C1=0
FABS nil X87STATUS [0xD9 /0xE1] s:X87, t:X87_ALU, w:W, u:C1=0
FTST nil X87STATUS [0xD9 /0xE4] s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m
FXAM nil X87STATUS [0xD9 /0xE5] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m
FLD1 nil X87STATUS [0xD9 /0xE8] s:X87, t:X87_ALU, w:W, u:C1=m
FLDL2T nil X87STATUS [0xD9 /0xE9] s:X87, t:X87_ALU, w:W, u:C1=m
FLDL2E nil X87STATUS [0xD9 /0xEA] s:X87, t:X87_ALU, w:W, u:C1=m
FLDPI nil X87STATUS [0xD9 /0xEB] s:X87, t:X87_ALU, w:W, u:C1=m
FLDLG2 nil X87STATUS [0xD9 /0xEC] s:X87, t:X87_ALU, w:W, u:C1=m
FLDLN2 nil X87STATUS [0xD9 /0xED] s:X87, t:X87_ALU, w:W, u:C1=m
FLDZ nil X87STATUS [0xD9 /0xEE] s:X87, t:X87_ALU, w:W, u:C1=m
F2XM1 nil X87STATUS [0xD9 /0xF0] s:X87, t:X87_ALU, w:W, u:C1=m
FYL2X nil X87STATUS [0xD9 /0xF1] s:X87, t:X87_ALU, w:W, u:C1=m
FPTAN nil X87STATUS [0xD9 /0xF2] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m
FPATAN nil X87STATUS [0xD9 /0xF3] s:X87, t:X87_ALU, w:W, u:C1=m
FXTRACT nil X87STATUS [0xD9 /0xF4] s:X87, t:X87_ALU, w:W, u:C1=m
FPREM1 nil X87STATUS [0xD9 /0xF5] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m
FDECSTP nil X87STATUS [0xD9 /0xF6] s:X87, t:X87_ALU, w:W, u:C1=0
FINCSTP nil X87STATUS [0xD9 /0xF7] s:X87, t:X87_ALU, w:W, u:C1=0
FPREM nil X87STATUS [0xD9 /0xF8] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m
FYL2XP1 nil X87STATUS [0xD9 /0xF9] s:X87, t:X87_ALU, w:W, u:C1=m
FSQRT nil X87STATUS [0xD9 /0xFA] s:X87, t:X87_ALU, w:W, u:C1=m
FSINCOS nil X87STATUS [0xD9 /0xFB] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m
FRNDINT nil X87STATUS [0xD9 /0xFC] s:X87, t:X87_ALU, w:W, u:C1=m
FSCALE nil X87STATUS [0xD9 /0xFD] s:X87, t:X87_ALU, w:W, u:C1=m
FSIN nil X87STATUS [0xD9 /0xFE] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m
FCOS nil X87STATUS [0xD9 /0xFF] s:X87, t:X87_ALU, w:W, u:C1=m|C2=m
FLD ST(0),ST(i) X87STATUS [0xD9 /0:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FXCH ST(0),ST(i) X87STATUS [0xD9 /1:reg] s:X87, t:X87_ALU, w:RW|RW|W, u:C1=0
FSTPNCE ST(i),ST(0) X87STATUS [0xD9 /3:reg] s:X87, t:X87_ALU, w:W|R|W
# 0xDA
FIADD ST(0),Md X87STATUS [0xDA /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FIMUL ST(0),Md X87STATUS [0xDA /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FICOM ST(0),Md X87STATUS [0xDA /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
FICOMP ST(0),Md X87STATUS [0xDA /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
FISUB ST(0),Md X87STATUS [0xDA /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FISUBR ST(0),Md X87STATUS [0xDA /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FIDIV ST(0),Md X87STATUS [0xDA /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FIDIVR ST(0),Md X87STATUS [0xDA /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FUCOMPP nil X87STATUS [0xDA /0xE9] s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m
FCMOVB ST(0),ST(i) X87STATUS,Fv [0xDA /0:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t, u:C1=m
FCMOVE ST(0),ST(i) X87STATUS,Fv [0xDA /1:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:ZF=t, u:C1=m
FCMOVBE ST(0),ST(i) X87STATUS,Fv [0xDA /2:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t|ZF=t, u:C1=m
FCMOVU ST(0),ST(i) X87STATUS,Fv [0xDA /3:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:PF=t, u:C1=m
# 0xDB
FILD ST(0),Md X87STATUS [0xDB /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FISTTP Md,ST(0) X87STATUS [0xDB /1:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=0
FIST Md,ST(0) X87STATUS [0xDB /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FISTP Md,ST(0) X87STATUS [0xDB /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FLD ST(0),Mft X87STATUS [0xDB /5:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FSTP Mft,ST(0) X87STATUS [0xDB /7:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FNOP nil nil [0xDB /0xE0] s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u
FNDISI nil nil [0xDB /0xE1] s:X87, t:X87_ALU, w:W
FNCLEX nil X87STATUS [0xDB /0xE2] s:X87, t:X87_ALU, w:W
FNINIT nil X87CONTROL,X87TAG,X87STATUS [0xDB /0xE3] s:X87, t:X87_ALU, w:W|W|W, u:C0=0|C1=0|C2=0|C3=0
FNOP nil nil [0xDB /0xE4] s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u
FCMOVNB ST(0),ST(i) X87STATUS,Fv [0xDB /0:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t, u:C1=m
FCMOVNE ST(0),ST(i) X87STATUS,Fv [0xDB /1:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:ZF=t, u:C1=m
FCMOVNBE ST(0),ST(i) X87STATUS,Fv [0xDB /2:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t|ZF=t, u:C1=m
FCMOVNU ST(0),ST(i) X87STATUS,Fv [0xDB /3:reg] s:X87, t:X87_ALU, w:CW|R|RW|W, f:PF=t, u:C1=m
FUCOMI ST(0),ST(i) X87STATUS,Fv [0xDB /5:reg] s:X87, t:X87_ALU, w:R|R|RW|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m
FCOMI ST(0),ST(i) X87STATUS,Fv [0xDB /6:reg] s:X87, t:X87_ALU, w:R|R|RW|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m
# 0xDC
FADD ST(0),Mfq X87STATUS [0xDC /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FMUL ST(0),Mfq X87STATUS [0xDC /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FCOM ST(0),Mfq X87STATUS [0xDC /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FCOMP ST(0),Mfq X87STATUS [0xDC /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FSUB ST(0),Mfq X87STATUS [0xDC /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FSUBR ST(0),Mfq X87STATUS [0xDC /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIV ST(0),Mfq X87STATUS [0xDC /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIVR ST(0),Mfq X87STATUS [0xDC /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FADD ST(i),ST(0) X87STATUS [0xDC /0:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FMUL ST(i),ST(0) X87STATUS [0xDC /1:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
FCOM ST(0),ST(i) X87STATUS [0xDC /2:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
FCOMP ST(0),ST(i) X87STATUS [0xDC /3:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=0|C2=m|C3=m
Initial commit.
2020-07-21 08:19:18 +00:00
FSUBR ST(i),ST(0) X87STATUS [0xDC /4:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FSUB ST(i),ST(0) X87STATUS [0xDC /5:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIVR ST(i),ST(0) X87STATUS [0xDC /6:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIV ST(i),ST(0) X87STATUS [0xDC /7:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
# 0xDD
FLD ST(0),Mfq X87STATUS [0xDD /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FISTTP Mq,ST(0) X87STATUS [0xDD /1:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=0
FST Mfq,ST(0) X87STATUS [0xDD /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FSTP Mfq,ST(0) X87STATUS [0xDD /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FRSTOR Mfs X87CONTROL [0xDD /4:mem] s:X87, t:X87_ALU, w:R|W, u:C0=m|C1=m|C2=m|C3=m
FNSAVE Mfs X87CONTROL,X87TAG,X87STATUS [0xDD /6:mem] s:X87, t:X87_ALU, w:W|RW|RW|W, u:C0=0|C1=0|C2=0|C3=0
FNSTSW Mw X87STATUS [0xDD /7:mem] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u
FFREE ST(i) X87TAG [0xDD /0:reg] s:X87, t:X87_ALU, w:R|W, u:C0=u|C1=u|C2=u|C3=u
FXCH ST(0),ST(i) X87STATUS [0xDD /1:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=0
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
FST ST(i),ST(0) X87STATUS [0xDD /2:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FSTP ST(i),ST(0) X87STATUS [0xDD /3:reg] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
Initial commit.
2020-07-21 08:19:18 +00:00
FUCOM ST(0),ST(i) X87STATUS [0xDD /4:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
FUCOMP ST(0),ST(i) X87STATUS [0xDD /5:reg] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
# 0xDE
FIADD ST(0),Mw X87STATUS [0xDE /0:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FIMUL ST(0),Mw X87STATUS [0xDE /1:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FICOM ST(0),Mw X87STATUS [0xDE /2:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
FICOMP ST(0),Mw X87STATUS [0xDE /3:mem] s:X87, t:X87_ALU, w:R|R|W, u:C0=m|C1=m|C2=m|C3=m
FISUB ST(0),Mw X87STATUS [0xDE /4:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FISUBR ST(0),Mw X87STATUS [0xDE /5:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FIDIV ST(0),Mw X87STATUS [0xDE /6:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FIDIVR ST(0),Mw X87STATUS [0xDE /7:mem] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FCOMPP nil X87STATUS [0xDE /0xD9] s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m
FADDP ST(i),ST(0) X87STATUS [0xDE /0:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FMULP ST(i),ST(0) X87STATUS [0xDE /1:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FCOMP ST(0),ST(i) X87STATUS [0xDE /2:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C0=m|C1=0|C2=m|C3=m
FSUBRP ST(i),ST(0) X87STATUS [0xDE /4:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FSUBP ST(i),ST(0) X87STATUS [0xDE /5:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIVRP ST(i),ST(0) X87STATUS [0xDE /6:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
FDIVP ST(i),ST(0) X87STATUS [0xDE /7:reg] s:X87, t:X87_ALU, w:RW|R|W, u:C1=m
# 0xDF
FILD ST(0),Mw X87STATUS [0xDF /0:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FISTTP Mw,ST(0) X87STATUS [0xDF /1:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=0
FIST Mw,ST(0) X87STATUS [0xDF /2:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FISTP Mw,ST(0) X87STATUS [0xDF /3:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FBLD ST(0),Mfa X87STATUS [0xDF /4:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FILD ST(0),Mq X87STATUS [0xDF /5:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FBSTP Mfa,ST(0) X87STATUS [0xDF /6:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FISTP Mq,ST(0) X87STATUS [0xDF /7:mem] s:X87, t:X87_ALU, w:W|R|W, u:C1=m
FFREEP ST(i) X87TAG [0xDF /0:reg] s:X87, t:X87_ALU, w:R|W
FXCH ST(0),ST(i) X87TAG [0xDF /1:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=0
FSTP ST(i),ST(0) X87STATUS [0xDF /2:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=m
FSTP ST(i),ST(0) X87STATUS [0xDF /3:reg] s:X87, t:X87_ALU, w:R|W|W, u:C1=m
FNSTSW AX X87STATUS [0xDF /0xE0] s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u
FSTDW AX nil [0xDF /0xE1] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u
FSTSG AX nil [0xDF /0xE2] s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u
FUCOMIP ST(0),ST(i) X87STATUS,Fv [0xDF /5:reg] s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m
FCOMIP ST(0),ST(i) X87STATUS,Fv [0xDF /6:reg] s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m
FRINEAR nil nil [0xDF /0xFC] s:X87, t:X87_ALU
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