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bddisasm/bddisasm_test/x86/basic/snp_64.result

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Initial commit.
2020-07-21 08:19:18 +00:00
0000000000000000 f30f01fe RMPADJUST
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x8000001f, reg: eax, bit: 4
FLAGS access
PF: m, AF: m, ZF: m, SF: m, OF: m,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Multiple improvements - New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0. - Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions. - Fixed Do Not Track prefix recognition for CALL and JMP in long-mode. - Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load. - Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.
2021-08-31 10:37:50 +00:00
Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S,
Segment: 3, Base: 0,
Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1
Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
Initial commit.
2020-07-21 08:19:18 +00:00
0000000000000004 f20f01fe RMPUPDATE
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x8000001f, reg: eax, bit: 4
FLAGS access
PF: m, AF: m, ZF: m, SF: m, OF: m,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Multiple improvements - New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0. - Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions. - Fixed Do Not Track prefix recognition for CALL and JMP in long-mode. - Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load. - Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.
2021-08-31 10:37:50 +00:00
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: S,
Segment: 3, Base: 1,
Initial commit.
2020-07-21 08:19:18 +00:00
Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
0000000000000008 f30f01ff PSMASH
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x8000001f, reg: eax, bit: 4
FLAGS access
PF: m, AF: m, ZF: m, SF: m, OF: m,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
000000000000000C f20f01ff PVALIDATE
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x8000001f, reg: eax, bit: 4
FLAGS access
CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1
Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
Added support for AMD RMPQUERY instruction.
2022-10-27 09:37:02 +00:00
0000000000000010 f30f01fd RMPQUERY
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: SNP, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x8000001f, reg: eax, bit: 6
FLAGS access
PF: m, AF: m, ZF: m, SF: m, OF: m,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: S,
Segment: 3, Base: 0,
Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1
Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
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