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bddisasm/isagenerator/instructions/table_base.dat

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Initial commit.
2020-07-21 08:19:18 +00:00
# Mnemonic Explicit Implicit Encoding s:set, t:type, c:class, a:flags, p:prefixes, w:operands access, f:flags access, i:cpuid, m:valid cpu modes
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x00 - 0x0F
ADD Eb,Gb Fv [ 0x00 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK
ADD Ev,Gv Fv [ 0x01 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK
ADD Gb,Eb Fv [ 0x02 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH
ADD Gv,Ev Fv [ 0x03 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH
ADD AL,Ib Fv [ 0x04 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH
ADD rAX,Iz Fv [ 0x05 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1
PUSH ES Kv [ 0x06] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX
POP ES Kv [ 0x07] s:I86, t:POP, w:W|R, m:NO64|NOSGX
OR Eb,Gb Fv [ 0x08 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
OR Ev,Gv Fv [ 0x09 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
OR Gb,Eb Fv [ 0x0A /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
OR Gv,Ev Fv [ 0x0B /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
OR AL,Ib Fv [ 0x0C ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
OR rAX,Iz Fv [ 0x0D iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1
PUSH CS Kv [ 0x0E] s:I86, t:PUSH, w:R|R, m:NO64|NOSGX
# 0x10 - 0x1F
ADC Eb,Gb Fv [ 0x10 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK
ADC Ev,Gv Fv [ 0x11 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK
ADC Gb,Eb Fv [ 0x12 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC
ADC Gv,Ev Fv [ 0x13 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC
ADC AL,Ib Fv [ 0x14 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC
ADC rAX,Iz Fv [ 0x15 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1
PUSH SS Kv [ 0x16] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX
POP SS Kv [ 0x17] s:I86, t:POP, w:W|R, m:NO64|NOSGX
SBB Eb,Gb Fv [ 0x18 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK
SBB Ev,Gv Fv [ 0x19 /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK
SBB Gb,Eb Fv [ 0x1A /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC
SBB Gv,Ev Fv [ 0x1B /r] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC
SBB AL,Ib Fv [ 0x1C ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC
SBB rAX,Iz Fv [ 0x1D iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1
PUSH DS Kv [ 0x1E] s:I86, t:PUSH, w:R|W, m:NO64|NOSGX
POP DS Kv [ 0x1F] s:I86, t:POP, w:W|R, m:NO64|NOSGX
# 0x20 - 0x2F
AND Eb,Gb Fv [ 0x20 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
AND Ev,Gv Fv [ 0x21 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
AND Gb,Eb Fv [ 0x22 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
AND Gv,Ev Fv [ 0x23 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
AND AL,Ib Fv [ 0x24 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
AND rAX,Iz Fv [ 0x25 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1
es nil nil [ 0x26] s:UNKNOWN, t:UNKNOWN, a:PREFIX
DAA nil AL,Fv [ 0x27] s:I86, t:DECIMAL, w:RW|RW, f:DAAS, m:NO64
SUB Eb,Gb Fv [ 0x28 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK
SUB Ev,Gv Fv [ 0x29 /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK
SUB Gb,Eb Fv [ 0x2A /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH
SUB Gv,Ev Fv [ 0x2B /r] s:I86, t:ARITH, w:RW|R|W, f:ARITH
SUB AL,Ib Fv [ 0x2C ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH
SUB rAX,Iz Fv [ 0x2D iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1
cs nil nil [ 0x2E] s:UNKNOWN, t:UNKNOWN, a:PREFIX
BHNT nil nil [ 0x2E] s:UNKNOWN, t:UNKNOWN, a:PREFIX
DAS nil AL,Fv [ 0x2F] s:I86, t:DECIMAL, w:RW|RW, f:DAAS|SF=m, m:NO64
# 0x30 - 0x3F
XOR Eb,Gb Fv [ 0x30 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
XOR Ev,Gv Fv [ 0x31 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
XOR Gb,Eb Fv [ 0x32 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
XOR Gv,Ev Fv [ 0x33 /r] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
XOR AL,Ib Fv [ 0x34 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC
XOR rAX,Iz Fv [ 0x35 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1
ss nil nil [ 0x36] s:UNKNOWN, t:UNKNOWN, a:PREFIX
AAA nil AH,AL,Fv [ 0x37] s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64
CMP Eb,Gb Fv [ 0x38 /r] s:I86, t:ARITH, w:R|R|W, f:ARITH
CMP Ev,Gv Fv [ 0x39 /r] s:I86, t:ARITH, w:R|R|W, f:ARITH
CMP Gb,Eb Fv [ 0x3A /r] s:I86, t:ARITH, w:R|R|W, f:ARITH
CMP Gv,Ev Fv [ 0x3B /r] s:I86, t:ARITH, w:R|R|W, f:ARITH
CMP AL,Ib Fv [ 0x3C ib] s:I86, t:ARITH, w:R|R|W, f:ARITH
CMP rAX,Iz Fv [ 0x3D iz] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1
ds nil nil [ 0x3E] s:UNKNOWN, t:UNKNOWN, a:PREFIX
BHT nil nil [ 0x3E] s:UNKNOWN, t:UNKNOWN, a:PREFIX
AAS nil AH,AL,Fv [ 0x3F] s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64
# 0x40 - 0x4F
* INC/DEC do not modify the CF. * Fixed FXSAVE64, PUSHAD and POPAD emulation - when explicit mnemonics were added for them, emulation support was not added, thus causing emulation to stop when encountering one of these.
2020-08-19 16:14:22 +00:00
INC Zv Fv [ 0x40] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x41] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x42] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x43] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x44] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x45] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x46] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
INC Zv Fv [ 0x47] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x48] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x49] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x4A] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x4B] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x4C] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x4D] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x4E] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
DEC Zv Fv [ 0x4F] s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x50 - 0x5F
PUSH Zv Kv [ 0x50] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x51] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x52] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x53] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x54] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x55] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x56] s:I86, t:PUSH, w:R|W, a:D64
PUSH Zv Kv [ 0x57] s:I86, t:PUSH, w:R|W, a:D64
POP Zv Kv [ 0x58] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x59] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x5A] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x5B] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x5C] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x5D] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x5E] s:I86, t:POP, w:W|R, a:D64
POP Zv Kv [ 0x5F] s:I86, t:POP, w:W|R, a:D64
# 0x60 - 0x6F
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
PUSHA nil BANK,Kv8 [ ds16 0x60] s:I386, t:PUSH, w:R|W, m:NO64
PUSHAD nil BANK,Kv8 [ ds32 0x60] s:I386, t:PUSH, w:R|W, m:NO64
POPA nil BANK,Kv8 [ ds16 0x61] s:I386, t:POP, w:W|R, m:NO64
POPAD nil BANK,Kv8 [ ds32 0x61] s:I386, t:POP, w:W|R, m:NO64
Initial commit.
2020-07-21 08:19:18 +00:00
BOUND Gv,Ma nil [ 0x62 /r:mem] s:I186, t:INTERRUPT, w:R|R, m:NO64
ARPL Ew,Gw Fv [ 0x63 /r] s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL|NO64
MOVSXD Gv,Ez nil [ o64 0x63 /r] s:LONGMODE, t:DATAXFER, w:W|R, m:O64
fs nil nil [ 0x64] s:UNKNOWN, t:UNKNOWN, a:PREFIX
BHALT nil nil [ 0x64] s:UNKNOWN, t:UNKNOWN, a:PREFIX
gs nil nil [ 0x65] s:UNKNOWN, t:UNKNOWN, a:PREFIX
size nil nil [ 0x66] s:UNKNOWN, t:UNKNOWN, a:PREFIX
addr nil nil [ 0x67] s:UNKNOWN, t:UNKNOWN, a:PREFIX
PUSH Iz Kv [ 0x68 iz] s:I86, t:PUSH, w:R|W, a:D64|OP1SEXDW
IMUL Gv,Ev,Iz Fv [ 0x69 /r iz] s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SEXO1
PUSH Ib Kv [ 0x6A ib] s:I86, t:PUSH, w:R|W, a:D64|OP1SEXDW
IMUL Gv,Ev,Ib Fv [ 0x6B /r ib] s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SEXO1
INSB Yb,DX aDI,Fv [ 0x6C] s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX
INSB Yb,DX aCX,aDI,Fv [ rep 0x6C] s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX
INSW Yz,DX aDI,Fv [ ds16 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX
INSW Yz,DX aCX,aDI,Fv [ rep ds16 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX
INSD Yz,DX aDI,Fv [ 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX
INSD Yz,DX aCX,aDI,Fv [ rep 0x6D] s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX
OUTSB DX,Xb aSI,Fv [ 0x6E] s:I86, t:IOSTRINGOP, c:OUTS, w:R|R|RW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX
OUTSB DX,Xb aCX,aSI,Fv [ rep 0x6E] s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX
OUTSW DX,Xz aSI,Fv [ ds16 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|R|RW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX
OUTSW DX,Xz aCX,aSI,Fv [ rep ds16 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX
OUTSD DX,Xz aSI,Fv [ 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|R|RW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX
OUTSD DX,Xz aCX,aSI,Fv [ rep 0x6F] s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX
# 0x70 - 0x7F
Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. Bypass self-writes option in bdshemu - if set, bdshemu will not proceed to commit modifications made by the shellcode to itself.
2021-05-17 06:04:34 +00:00
JO Jb rIP,Fv [ 0x70 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CO, a:F64|COND, p:BND|BH
JNO Jb rIP,Fv [ 0x71 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNO, a:F64|COND, p:BND|BH
JC Jb rIP,Fv [ 0x72 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CC, a:F64|COND, p:BND|BH
JNC Jb rIP,Fv [ 0x73 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNC, a:F64|COND, p:BND|BH
JZ Jb rIP,Fv [ 0x74 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CZ, a:F64|COND, p:BND|BH
JNZ Jb rIP,Fv [ 0x75 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNZ, a:F64|COND, p:BND|BH
JBE Jb rIP,Fv [ 0x76 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CBE, a:F64|COND, p:BND|BH
JNBE Jb rIP,Fv [ 0x77 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNBE, a:F64|COND, p:BND|BH
JS Jb rIP,Fv [ 0x78 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CS, a:F64|COND, p:BND|BH
JNS Jb rIP,Fv [ 0x79 cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNS, a:F64|COND, p:BND|BH
JP Jb rIP,Fv [ 0x7A cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CP, a:F64|COND, p:BND|BH
JNP Jb rIP,Fv [ 0x7B cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNP, a:F64|COND, p:BND|BH
JL Jb rIP,Fv [ 0x7C cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CL, a:F64|COND, p:BND|BH
JNL Jb rIP,Fv [ 0x7D cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNL, a:F64|COND, p:BND|BH
JLE Jb rIP,Fv [ 0x7E cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CLE, a:F64|COND, p:BND|BH
JNLE Jb rIP,Fv [ 0x7F cb] s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNLE, a:F64|COND, p:BND|BH
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x80 - 0x8F
ADD Eb,Ib Fv [ 0x80 /0 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK
OR Eb,Ib Fv [ 0x80 /1 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
ADC Eb,Ib Fv [ 0x80 /2 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK
SBB Eb,Ib Fv [ 0x80 /3 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK
AND Eb,Ib Fv [ 0x80 /4 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
SUB Eb,Ib Fv [ 0x80 /5 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK
XOR Eb,Ib Fv [ 0x80 /6 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK
CMP Eb,Ib Fv [ 0x80 /7 ib] s:I86, t:ARITH, w:R|R|W, f:ARITH
ADD Ev,Iz Fv [ 0x81 /0 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK
OR Ev,Iz Fv [ 0x81 /1 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK
ADC Ev,Iz Fv [ 0x81 /2 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK
SBB Ev,Iz Fv [ 0x81 /3 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK
AND Ev,Iz Fv [ 0x81 /4 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK
SUB Ev,Iz Fv [ 0x81 /5 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK
XOR Ev,Iz Fv [ 0x81 /6 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK
CMP Ev,Iz Fv [ 0x81 /7 iz] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
ADD Eb,Ib Fv [ 0x82 /0 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, m:NO64, p:HLE|LOCK
OR Eb,Ib Fv [ 0x82 /1 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
ADC Eb,Ib Fv [ 0x82 /2 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
SBB Eb,Ib Fv [ 0x82 /3 iz] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
AND Eb,Ib Fv [ 0x82 /4 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
SUB Eb,Ib Fv [ 0x82 /5 iz] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, m:NO64, p:HLE|LOCK
XOR Eb,Ib Fv [ 0x82 /6 iz] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK
CMP Eb,Ib Fv [ 0x82 /7 iz] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1, m:NO64
Initial commit.
2020-07-21 08:19:18 +00:00
ADD Ev,Ib Fv [ 0x83 /0 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK
OR Ev,Ib Fv [ 0x83 /1 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK
ADC Ev,Ib Fv [ 0x83 /2 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK
SBB Ev,Ib Fv [ 0x83 /3 ib] s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK
AND Ev,Ib Fv [ 0x83 /4 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK
SUB Ev,Ib Fv [ 0x83 /5 ib] s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK
XOR Ev,Ib Fv [ 0x83 /6 ib] s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK
CMP Ev,Ib Fv [ 0x83 /7 ib] s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1
TEST Eb,Gb Fv [ 0x84 /r] s:I86, t:LOGIC, w:R|R|W, f:LOGIC
TEST Ev,Gv Fv [ 0x85 /r] s:I86, t:LOGIC, w:R|R|W, f:LOGIC
XCHG Eb,Gb nil [ 0x86 /r] s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL
XCHG Ev,Gv nil [ 0x87 /r] s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL
MOV Eb,Gb nil [ 0x88 /r] s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL
MOV Ev,Gv nil [ 0x89 /r] s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL
MOV Gb,Eb nil [ 0x8A /r] s:I86, t:DATAXFER, w:W|R
MOV Gv,Ev nil [ 0x8B /r] s:I86, t:DATAXFER, w:W|R
MOV Mw,Sw nil [ 0x8C /r:mem] s:I86, t:DATAXFER, w:W|R
MOV Rv,Sw nil [ 0x8C /r:reg] s:I86, t:DATAXFER, w:W|R
LEA Gv,M0 nil [ 0x8D /r:mem] s:I86, t:MISC, w:W|N, a:AG
MOV Sw,Mw nil [ 0x8E /r:mem] s:I86, t:DATAXFER, w:W|R
MOV Sw,Rv nil [ 0x8E /r:reg] s:I86, t:DATAXFER, w:W|R
POP Ev Kv [ 0x8F /0] s:I86, t:POP, w:W|R, a:D64
# 0x90 - 0x9F
NOP nil nil [ 0x90] s:I86, t:NOP,
PAUSE nil nil [ a0xF3 0x90] s:PAUSE, t:MISC, m:NOTSX
Fixed https://github.com/bitdefender/bddisasm/issues/34, https://github.com/bitdefender/bddisasm/issues/35, https://github.com/bitdefender/bddisasm/issues/36 and https://github.com/bitdefender/bddisasm/issues/37.
2021-01-11 09:10:04 +00:00
XCHG Zv,rAX nil [ rexb 0x90] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x91] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x92] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x93] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x94] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x95] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x96] s:I86, t:DATAXFER, w:RW|RW
XCHG Zv,rAX nil [ 0x97] s:I86, t:DATAXFER, w:RW|RW
Initial commit.
2020-07-21 08:19:18 +00:00
CBW nil AX,AL [ ds16 0x98] s:I386, t:CONVERT, w:W|R
CWDE nil EAX,AX [ ds32 0x98] s:I386, t:CONVERT, w:W|R
CDQE nil RAX,EAX [ ds64 0x98] s:I386, t:CONVERT, w:W|R
CWD nil DX,AX [ ds16 0x99] s:I386, t:CONVERT, w:W|R
CDQ nil EDX,EAX [ ds32 0x99] s:I386, t:CONVERT, w:W|R
CQO nil RDX,RAX [ ds64 0x99] s:I386, t:CONVERT, w:W|R
CALLF Ap CS,rIP,Kv2,SHS2 [ 0x9A cp] s:I86, t:CALL, c:CALLFD, w:R|RW|W|W|W, m:NO64|NOSGX
WAIT nil nil [ 0x9B] s:X87, t:X87_ALU
PUSHFW Fv Kv [ ds16 0x9C] s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64
PUSHFD Fv Kv [ ds32 0x9C] s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64
PUSHFQ Fv Kv [ dds64 0x9C] s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64
POPFW Fv Kv [ ds16 0x9D] s:I86, t:POP, c:POPF, w:W|R , a:D64
POPFD Fv Kv [ ds32 0x9D] s:I86, t:POP, c:POPF, w:W|R , a:D64
POPFQ Fv Kv [ dds64 0x9D] s:I86, t:POP, c:POPF, w:W|R , a:D64
SAHF nil AH,Fv [ 0x9E] s:I86, t:FLAGOP, w:R|W, f:CF=m|PF=m|AF=m|ZF=m|SF=m
LAHF nil AH,Fv [ 0x9F] s:I86, t:FLAGOP, w:W|R, f:CF=t|PF=t|AF=t|ZF=t|SF=t
# 0xA0 - 0xAF
MOV AL,Ob nil [ 0xA0] s:I86, t:DATAXFER, w:W|R
MOV rAX,Ov nil [ 0xA1] s:I86, t:DATAXFER, w:W|R
MOV Ob,AL nil [ 0xA2] s:I86, t:DATAXFER, w:W|R
MOV Ov,rAX nil [ 0xA3] s:I86, t:DATAXFER, w:W|R
MOVSB Yb,Xb aSI,aDI,Fv [ 0xA4] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSB Yb,Xb aCX,aSI,aDI,Fv [ rep 0xA4] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSW Yv,Xv aSI,aDI,Fv [ ds16 0xA5] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSW Yv,Xv aCX,aSI,aDI,Fv [ rep ds16 0xA5] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSD Yv,Xv aSI,aDI,Fv [ ds32 0xA5] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSD Yv,Xv aCX,aSI,aDI,Fv [ rep ds32 0xA5] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSQ Yv,Xv aSI,aDI,Fv [ ds64 0xA5] s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP
MOVSQ Yv,Xv aCX,aSI,aDI,Fv [ rep ds64 0xA5] s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
CMPSB Xb,Yb aSI,aDI,Fv [ 0xA6] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSB Xb,Yb aCX,aSI,aDI,Fv [ rep 0xA6] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSW Xv,Yv aSI,aDI,Fv [ ds16 0xA7] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSW Xv,Yv aCX,aSI,aDI,Fv [ rep ds16 0xA7] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSD Xv,Yv aSI,aDI,Fv [ ds32 0xA7] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSD Xv,Yv aCX,aSI,aDI,Fv [ rep ds32 0xA7] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSQ Xv,Yv aSI,aDI,Fv [ ds64 0xA7] s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
CMPSQ Xv,Yv aCX,aSI,aDI,Fv [ rep ds64 0xA7] s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
TEST AL,Ib Fv [ 0xA8 ib] s:I86, t:LOGIC, w:R|R|W, f:LOGIC
TEST rAX,Iz Fv [ 0xA9 iz] s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1
STOSB Yb,AL aDI,Fv [ 0xAA] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSB Yb,AL aCX,aDI,Fv [ rep 0xAA] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSW Yv,AX aDI,Fv [ ds16 0xAB] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSW Yv,AX aCX,aDI,Fv [ rep ds16 0xAB] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSD Yv,EAX aDI,Fv [ ds32 0xAB] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSD Yv,EAX aCX,aDI,Fv [ rep ds32 0xAB] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSQ Yv,RAX aDI,Fv [ ds64 0xAB] s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
STOSQ Yv,RAX aCX,aDI,Fv [ rep ds64 0xAB] s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP
LODSB AL,Xb aSI,Fv [ 0xAC] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
LODSB AL,Xb aCX,aSI,Fv [ rep 0xAC] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
LODSW AX,Xv aSI,Fv [ ds16 0xAD] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
LODSW AX,Xv aCX,aSI,Fv [ rep ds16 0xAD] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
LODSD EAX,Xv aSI,Fv [ ds32 0xAD] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
LODSD EAX,Xv aCX,aSI,Fv [ rep ds32 0xAD] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
LODSQ RAX,Xv aSI,Fv [ ds64 0xAD] s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP
LODSQ RAX,Xv aCX,aSI,Fv [ rep ds64 0xAD] s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP
SCASB AL,Yb aDI,Fv [ 0xAE] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
SCASB AL,Yb aCX,aDI,Fv [ rep 0xAE] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
SCASW AX,Yv aDI,Fv [ ds16 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
SCASW AX,Yv aCX,aDI,Fv [ rep ds16 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
SCASD EAX,Yv aDI,Fv [ ds32 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
SCASD EAX,Yv aCX,aDI,Fv [ rep ds32 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
SCASQ RAX,Yv aDI,Fv [ ds64 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC
SCASQ RAX,Yv aCX,aDI,Fv [ rep ds64 0xAF] s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC
# 0xB0 - 0xBF
MOV Zb,Ib nil [ 0xB0 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB1 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB2 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB3 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB4 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB5 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB6 ib] s:I86, t:DATAXFER, w:W|R
MOV Zb,Ib nil [ 0xB7 ib] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xB8 iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xB9 iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xBA iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xBB iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xBC iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xBD iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xBE iv] s:I86, t:DATAXFER, w:W|R
MOV Zv,Iv nil [ 0xBF iv] s:I86, t:DATAXFER, w:W|R
# 0xC0 - 0xCF
ROL Eb,Ib Fv [ 0xC0 /0 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT
ROR Eb,Ib Fv [ 0xC0 /1 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT
RCL Eb,Ib Fv [ 0xC0 /2 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
RCR Eb,Ib Fv [ 0xC0 /3 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
SHL Eb,Ib Fv [ 0xC0 /4 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SHR Eb,Ib Fv [ 0xC0 /5 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAL Eb,Ib Fv [ 0xC0 /6 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAR Eb,Ib Fv [ 0xC0 /7 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
ROL Ev,Ib Fv [ 0xC1 /0 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT
ROR Ev,Ib Fv [ 0xC1 /1 ib] s:I86, t:ROTATE, w:RW|R|W, f:ROT
RCL Ev,Ib Fv [ 0xC1 /2 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
RCR Ev,Ib Fv [ 0xC1 /3 ib] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
SHL Ev,Ib Fv [ 0xC1 /4 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SHR Ev,Ib Fv [ 0xC1 /5 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAL Ev,Ib Fv [ 0xC1 /6 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAR Ev,Ib Fv [ 0xC1 /7 ib] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
RETN Iw rIP,sSP,Kv,SHS1 [ 0xC2 iw] s:I86, t:RET, w:R|W|W|R|R, a:F64, p:BND
Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them.
2020-07-21 14:36:19 +00:00
RETN nil rIP,Kv,SHS1 [ 0xC3] s:I86, t:RET, w:W|R|R, a:F64, p:BND
Initial commit.
2020-07-21 08:19:18 +00:00
LES Gz,Mp ES [ 0xC4 /r:mem] s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX
LDS Gz,Mp DS [ 0xC5 /r:mem] s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX
MOV Eb,Ib nil [ 0xC6 /0 ib] s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL
Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup. Moved helper functions in bdhelpers.c. Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
2021-11-02 09:22:22 +00:00
XABORT Ib yIP,EAX [ 0xC6 /0xF8 ib] s:TSX, t:UNCOND_BR, w:R|W|RCW, i:RTM
Initial commit.
2020-07-21 08:19:18 +00:00
MOV Ev,Iz nil [ 0xC7 /0 iz] s:I86, t:DATAXFER, w:W|R, a:OP2SEXO1, p:XRELEASE|HLEWOL
Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. Bypass self-writes option in bdshemu - if set, bdshemu will not proceed to commit modifications made by the shellcode to itself.
2021-05-17 06:04:34 +00:00
XBEGIN Jz yIP,EAX [ 0xC7 /0xF8 cz] s:TSX, t:COND_BR, w:R|RCW|CW, i:RTM
D64 flag for ENTER instruction.
2020-11-07 10:12:28 +00:00
ENTER Iw,Ib rBP,sSP,Kv [ 0xC8 iw ib] s:I186, t:MISC, w:R|R|RW|RW|W, a:D64
Initial commit.
2020-07-21 08:19:18 +00:00
LEAVE nil sBP,rBP,rSP,Kv [ 0xC9] s:I186, t:MISC, w:R|RW|RW|R, a:D64
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
RETF Iw CS,rIP,Kv2,SHS2 [ 0xCA iw] s:I86, t:RET, w:R|W|W|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
RETF nil CS,rIP,Kv2,SHS2 [ 0xCB] s:I86, t:RET, w:W|W|R|R
Multiple improvements - New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0. - Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions. - Fixed Do Not Track prefix recognition for CALL and JMP in long-mode. - Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load. - Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.
2021-08-31 10:37:50 +00:00
INT3 nil CS,rIP,Kv3,Fv,SHS3 [ 0xCC] s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX
INT Ib CS,rIP,Kv3,Fv,SHS3 [ 0xCD ib] s:I86, t:INTERRUPT, w:R|RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX
INTO nil CS,rIP,Kv3,Fv,SHS3 [ 0xCE] s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NO64|NOSGX
Initial commit.
2020-07-21 08:19:18 +00:00
IRETW nil CS,rIP,Kv3,Fv,SHS3 [ ds16 0xCF] s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL
IRETD nil CS,rIP,Kv3,Fv,SHS3 [ ds32 0xCF] s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL
IRETQ nil CS,rIP,Kv3,Fv,SHS3 [ ds64 0xCF] s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL
# 0xD0 - 0xDF
ROL Eb,1 Fv [ 0xD0 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT
ROR Eb,1 Fv [ 0xD0 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT
RCL Eb,1 Fv [ 0xD0 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
RCR Eb,1 Fv [ 0xD0 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
SHL Eb,1 Fv [ 0xD0 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SHR Eb,1 Fv [ 0xD0 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAL Eb,1 Fv [ 0xD0 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAR Eb,1 Fv [ 0xD0 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
ROL Ev,1 Fv [ 0xD1 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT
ROR Ev,1 Fv [ 0xD1 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT
RCL Ev,1 Fv [ 0xD1 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
RCR Ev,1 Fv [ 0xD1 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
SHL Ev,1 Fv [ 0xD1 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SHR Ev,1 Fv [ 0xD1 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAL Ev,1 Fv [ 0xD1 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAR Ev,1 Fv [ 0xD1 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
ROL Eb,CL Fv [ 0xD2 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT
ROR Eb,CL Fv [ 0xD2 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT
RCL Eb,CL Fv [ 0xD2 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
RCR Eb,CL Fv [ 0xD2 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
SHL Eb,CL Fv [ 0xD2 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SHR Eb,CL Fv [ 0xD2 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAL Eb,CL Fv [ 0xD2 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAR Eb,CL Fv [ 0xD2 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
ROL Ev,CL Fv [ 0xD3 /0] s:I86, t:ROTATE, w:RW|R|W, f:ROT
ROR Ev,CL Fv [ 0xD3 /1] s:I86, t:ROTATE, w:RW|R|W, f:ROT
RCL Ev,CL Fv [ 0xD3 /2] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
RCR Ev,CL Fv [ 0xD3 /3] s:I86, t:ROTATE, w:RW|R|RW, f:ROTC
SHL Ev,CL Fv [ 0xD3 /4] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SHR Ev,CL Fv [ 0xD3 /5] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAL Ev,CL Fv [ 0xD3 /6] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
SAR Ev,CL Fv [ 0xD3 /7] s:I86, t:SHIFT, w:RW|R|W, f:SHIFT
AAM Ib AL,AH,Fv [ 0xD4 ib] s:I86, t:DECIMAL, w:R|RW|W|W, f:AADM, m:NO64
AAD Ib AL,AH,Fv [ 0xD5 ib] s:I86, t:DECIMAL, w:R|RW|RW|W, f:AADM, m:NO64
SALC nil AL,Fv [ 0xD6] s:I86, t:FLAGOP, w:W|R, f:CF=t
XLATB nil AL,pBXALb [ 0xD7] s:I86, t:MISC, w:W|R
# 0xE0 - 0xEF
Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. Bypass self-writes option in bdshemu - if set, bdshemu will not proceed to commit modifications made by the shellcode to itself.
2021-05-17 06:04:34 +00:00
LOOPNZ Jb aCX,rIP,Fv [ 0xE0 cb] s:I86, t:COND_BR, w:R|RW|CRCW|R, f:ZF=t, a:F64
LOOPZ Jb aCX,rIP,Fv [ 0xE1 cb] s:I86, t:COND_BR, w:R|RW|CRCW|R, f:ZF=t, a:F64
LOOP Jb aCX,rIP,Fv [ 0xE2 cb] s:I86, t:COND_BR, w:R|RW|CRCW|R, a:F64
JCXZ Jb aCX,rIP [ as16 0xE3 cb] s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64
JECXZ Jb aCX,rIP [ as32 0xE3 cb] s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64
JRCXZ Jb aCX,rIP [ as64 0xE3 cb] s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64
Initial commit.
2020-07-21 08:19:18 +00:00
IN AL,Ib Fv [ 0xE4 ib] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX
IN eAX,Ib Fv [ 0xE5 ib] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX
OUT Ib,AL Fv [ 0xE6 ib] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX
OUT Ib,eAX Fv [ 0xE7 ib] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX
Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them.
2020-07-21 14:36:19 +00:00
CALL Jz rIP,Kv,SHS1 [ 0xE8 cz] s:I86, t:CALL, c:CALLNR, w:R|RW|W|W, a:F64, p:BND
Initial commit.
2020-07-21 08:19:18 +00:00
JMP Jz rIP [ 0xE9 cz] s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64, p:BND
JMPF Ap CS,rIP [ 0xEA cp] s:I86, t:UNCOND_BR, c:JMPFD, w:R|W|W, m:NO64|NOSGX
JMP Jb rIP [ 0xEB cb] s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64, p:BND
IN AL,DX Fv [ 0xEC] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX
IN eAX,DX Fv [ 0xED] s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX
OUT DX,AL Fv [ 0xEE] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX
OUT DX,eAX Fv [ 0xEF] s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX
# 0xF0 - 0xFF
LOCK nil nil [ 0xF0] s:UNKNOWN, t:UNKNOWN, a:PREFIX
REPNZ nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX
XACQUIRE nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX
BND nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX
REPZ nil nil [ 0xF3] s:UNKNOWN, t:UNKNOWN, a:PREFIX
XRELEASE nil nil [ 0xF2] s:UNKNOWN, t:UNKNOWN, a:PREFIX
INT1 nil CS,rIP,Kv3,Fv [ 0xF1] s:I86, t:INTERRUPT, w:RW|RW|RW|W, f:INT, m:NOSGX
HLT nil nil [ 0xF4] s:I86, t:SYSTEM, m:KERNEL
CMC nil Fv [ 0xF5] s:I86, t:FLAGOP, w:RW, f:CF=m
TEST Eb,Ib Fv [ 0xF6 /0 ib] s:I86, t:LOGIC, w:R|R|W, f:LOGIC
TEST Eb,Ib Fv [ 0xF6 /1 ib] s:I86, t:LOGIC, w:R|R|W, f:LOGIC
NOT Eb nil [ 0xF6 /2] s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK
NEG Eb Fv [ 0xF6 /3] s:I86, t:LOGIC, w:RW|W, f:ARITH, p:HLE|LOCK
MUL Eb AL,AX,Fv [ 0xF6 /4] s:I86, t:ARITH, w:R|R|W|W, f:MUL
IMUL Eb AL,AX,Fv [ 0xF6 /5] s:I86, t:ARITH, w:R|R|W|W, f:MUL
DIV Eb AX,AL,AH,Fv [ 0xF6 /6] s:I86, t:ARITH, w:R|R|W|W|W, f:DIV
IDIV Eb AX,AL,AH,Fv [ 0xF6 /7] s:I86, t:ARITH, w:R|R|W|W|W, f:DIV
TEST Ev,Iz Fv [ 0xF7 /0 iz] s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1
TEST Ev,Iz Fv [ 0xF7 /1 iz] s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1
NOT Ev nil [ 0xF7 /2] s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK
NEG Ev Fv [ 0xF7 /3] s:I86, t:LOGIC, w:RW|W, f:ARITH, p:HLE|LOCK
MUL Ev rAX,rDX,Fv [ 0xF7 /4] s:I86, t:ARITH, w:R|RW|W|W, f:MUL
IMUL Ev rAX,rDX,Fv [ 0xF7 /5] s:I86, t:ARITH, w:R|RW|W|W, f:MUL
DIV Ev rAX,rDX,Fv [ 0xF7 /6] s:I86, t:ARITH, w:R|RW|RW|W, f:DIV
IDIV Ev rAX,rDX,Fv [ 0xF7 /7] s:I86, t:ARITH, w:R|RW|RW|W, f:DIV
CLC nil Fv [ 0xF8] s:I86, t:FLAGOP, w:W, f:CF=0
STC nil Fv [ 0xF9] s:I86, t:FLAGOP, w:W, f:CF=1
CLI nil Fv [ 0xFA] s:I86, t:FLAGOP, w:RW, f:IF=0
STI nil Fv [ 0xFB] s:I86, t:FLAGOP, w:RW, f:IF=1
CLD nil Fv [ 0xFC] s:I86, t:FLAGOP, w:W, f:DF=0
STD nil Fv [ 0xFD] s:I86, t:FLAGOP, w:W, f:DF=1
* INC/DEC do not modify the CF. * Fixed FXSAVE64, PUSHAD and POPAD emulation - when explicit mnemonics were added for them, emulation support was not added, thus causing emulation to stop when encountering one of these.
2020-08-19 16:14:22 +00:00
INC Eb Fv [ 0xFE /0] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK
DEC Eb Fv [ 0xFE /1] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK
INC Ev Fv [ 0xFF /0] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK
DEC Ev Fv [ 0xFF /1] s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK
Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them.
2020-07-21 14:36:19 +00:00
CALL Ev rIP,Kv,SHS1 [ 0xFF /2] s:I86, t:CALL, c:CALLNI, w:R|W|W|W, a:F64|CETT, p:BND|DNT
Initial commit.
2020-07-21 08:19:18 +00:00
CALLF Mp CS,rIP,Kv2,SHS2 [ 0xFF /3:mem] s:I86, t:CALL, c:CALLFI, w:R|W|W|W|W, a:CETT, m:NOSGX
JMP Ev rIP [ 0xFF /4] s:I86, t:UNCOND_BR, c:JMPNI, w:R|W, a:F64|CETT, p:BND|DNT
JMPF Mp CS,rIP [ 0xFF /5:mem] s:I86, t:UNCOND_BR, c:JMPFI, w:R|W|W, a:CETT, m:NOSGX
PUSH Ev Kv [ 0xFF /6] s:I86, t:PUSH, w:R|W, a:D64
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