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bddisasm/isagenerator/instructions/table_evex6.dat

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Switched from nil to n/a naming for absent operands, as it is more obvious.
2023-02-08 15:44:45 +00:00
#
# Copyright (c) 2020 Bitdefender
# SPDX-License-Identifier: Apache-2.0
#
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0x10 - 0x1F
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; n/a ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0x20 - 0x2F
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0x40 - 0x4F
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; n/a ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VRCPPH ; Vfv{K}{z},Wfv|B16 ; n/a ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
VRCPSH ; Vdq{K}{z},Hdq,Wsh ; n/a ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; n/a ; evex m:6 p:1 l:x w:0 0x4E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; n/a ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0x50 - 0x5F
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0x90 - 0x9F
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0xA0 - 0xAF
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0xB0 - 0xBF
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
# 0xD0 - 0xD7
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
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