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https://github.com/trezor/trezor-firmware.git
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208 lines
8.6 KiB
C
208 lines
8.6 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_sram.h
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* @author MCD Application Team
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* @version V1.5.2
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* @date 22-September-2016
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* @brief Header file of SRAM HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_SRAM_H
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#define __STM32F4xx_HAL_SRAM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
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#include "stm32f4xx_ll_fsmc.h"
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
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defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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#include "stm32f4xx_ll_fmc.h"
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
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defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
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defined(STM32F412Vx) || defined(STM32F412Rx)
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/** @addtogroup SRAM
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* @{
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*/
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/* Exported typedef ----------------------------------------------------------*/
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/** @defgroup SRAM_Exported_Types SRAM Exported Types
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* @{
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*/
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/**
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* @brief HAL SRAM State structures definition
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*/
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typedef enum
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{
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HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
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HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
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HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
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HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
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HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
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}HAL_SRAM_StateTypeDef;
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/**
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* @brief SRAM handle Structure definition
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*/
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typedef struct
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{
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FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
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FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
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FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
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HAL_LockTypeDef Lock; /*!< SRAM locking object */
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__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
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DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
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}SRAM_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
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* @{
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*/
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/** @brief Reset SRAM handle state
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* @param __HANDLE__: SRAM handle
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* @retval None
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*/
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#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup SRAM_Exported_Functions
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* @{
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*/
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/** @addtogroup SRAM_Exported_Functions_Group1
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* @{
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*/
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/* Initialization/de-initialization functions **********************************/
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HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
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HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
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void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
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void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
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void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
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void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Exported_Functions_Group2
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* @{
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*/
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/* I/O operation functions *****************************************************/
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HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Exported_Functions_Group3
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* @{
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*/
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/* SRAM Control functions ******************************************************/
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HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
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HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Exported_Functions_Group4
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* @{
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*/
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/* SRAM State functions *********************************************************/
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HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/**
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* @}
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*/
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
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STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
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STM32F412Vx || STM32F412Rx */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F4xx_HAL_SRAM_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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