mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-11-30 03:18:20 +00:00
99 lines
3.2 KiB
ArmAsm
99 lines
3.2 KiB
ArmAsm
.syntax unified
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.text
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.global memset_reg
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.type memset_reg, STT_FUNC
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memset_reg:
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// call with the following (note that the arguments are not validated prior to use):
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// r0 - address of first word to write (inclusive)
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// r1 - address of first word following the address in r0 to NOT write (exclusive)
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// r2 - word value to be written
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// both addresses in r0 and r1 needs to be divisible by 4!
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.L_loop_begin:
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str r2, [r0], 4 // store the word in r2 to the address in r0, post-indexed
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cmp r0, r1
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bne .L_loop_begin
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bx lr
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.global jump_to
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.type jump_to, STT_FUNC
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jump_to:
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mov r4, r0 // save input argument r0 (the address of the next stage's vector table) (r4 is callee save)
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// this subroutine re-points the exception handlers before the C code
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// that comprises them has been given a good environment to run.
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// therefore, this code needs to disable interrupts before the VTOR
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// update. then, the reset_handler of the next stage needs to re-enable interrupts.
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// the following prevents activation of all exceptions except Non-Maskable Interrupt (NMI).
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// according to "ARM Cortex-M Programming Guide to Memory Barrier Instructions" Application Note 321, section 4.8:
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// "there is no requirement to insert memory barrier instructions after CPSID".
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cpsid f
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// wipe memory at the end of the current stage of code
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bl clear_otg_hs_memory
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ldr r0, =ccmram_start // r0 - point to beginning of CCMRAM
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ldr r1, =ccmram_end // r1 - point to byte after the end of CCMRAM
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ldr r2, =0 // r2 - the word-sized value to be written
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bl memset_reg
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ldr r0, =sram_start // r0 - point to beginning of SRAM
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ldr r1, =sram_end // r1 - point to byte after the end of SRAM
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ldr r2, =0 // r2 - the word-sized value to be written
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bl memset_reg
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mov lr, r4
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// clear out the general purpose registers before the next stage's code can run (even the NMI exception handler)
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ldr r0, =0
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mov r1, r0
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mov r2, r0
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mov r3, r0
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mov r4, r0
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mov r5, r0
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mov r6, r0
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mov r7, r0
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mov r8, r0
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mov r9, r0
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mov r10, r0
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mov r11, r0
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mov r12, r0
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// give the next stage a fresh main stack pointer
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ldr r0, [lr] // set r0 to the main stack pointer in the next stage's vector table
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msr msp, r0 // give the next stage its main stack pointer
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// point to the next stage's exception handlers
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// AN321, section 4.11: "a memory barrier is not required after a VTOR update"
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.set SCB_VTOR, 0xE000ED08 // reference "Cortex-M4 Devices Generic User Guide" section 4.3
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ldr r0, =SCB_VTOR
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str lr, [r0]
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mov r0, r1 // zero out r0
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// go on to the next stage
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ldr lr, [lr, 4] // set lr to the next stage's reset_handler
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bx lr
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.global shutdown
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.type shutdown, STT_FUNC
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shutdown:
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cpsid f
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ldr r0, =0
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mov r1, r0
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mov r2, r0
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mov r3, r0
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mov r4, r0
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mov r5, r0
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mov r6, r0
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mov r7, r0
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mov r8, r0
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mov r9, r0
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mov r10, r0
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mov r11, r0
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mov r12, r0
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ldr lr, =0xffffffff
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ldr r0, =ccmram_start
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ldr r1, =ccmram_end
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// set to value in r2
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bl memset_reg
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ldr r0, =sram_start
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ldr r1, =sram_end
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// set to value in r2
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bl memset_reg
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bl clear_otg_hs_memory
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b . // loop forever
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.end
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