mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-11-30 11:28:21 +00:00
63 lines
1.9 KiB
ArmAsm
63 lines
1.9 KiB
ArmAsm
.syntax unified
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.text
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.global reset_handler
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.type reset_handler, STT_FUNC
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reset_handler:
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// The following loading of VTOR address only works if T1 bootloader was built with PRODUCTION=0
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// or the firmware was properly signed. All other variants end up in hard fault due to MPU
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// (cf mpu_config_firmware in legacy bootloader)
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#if TREZOR_MODEL == 1
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cpsid if
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ldr r0, =0xE000ED08 // r0 = VTOR address
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ldr r1, =0x08010400 // r1 = FLASH_APP_START
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str r1, [r0] // assign
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ldr r0, =_estack - 8 // r0 = stack pointer, T1 bootloader had 8 bytes reserved at end
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msr msp, r0 // set stack pointer
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dsb
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isb
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#endif
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// setup environment for subsequent stage of code
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ldr r0, =ccmram_start // r0 - point to beginning of CCMRAM
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ldr r1, =ccmram_end // r1 - point to byte after the end of CCMRAM
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ldr r2, =0 // r2 - the word-sized value to be written
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bl memset_reg
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ldr r0, =sram_start // r0 - point to beginning of SRAM
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ldr r1, =sram_end // r1 - point to byte after the end of SRAM
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ldr r2, =0 // r2 - the word-sized value to be written
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bl memset_reg
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// copy data in from flash
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ldr r0, =data_vma // dst addr
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ldr r1, =data_lma // src addr
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ldr r2, =data_size // size in bytes
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bl memcpy
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// setup the stack protector (see build script "-fstack-protector-all") with an unpredictable value
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bl rng_get
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ldr r1, = __stack_chk_guard
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str r0, [r1]
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// re-enable exceptions
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// according to "ARM Cortex-M Programming Guide to Memory Barrier Instructions" Application Note 321, section 4.7:
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// "If it is not necessary to ensure that a pended interrupt is recognized immediately before
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// subsequent operations, it is not necessary to insert a memory barrier instruction."
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#if TREZOR_MODEL == T
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cpsie f
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#elif TREZOR_MODEL == 1
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cpsie if
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#endif
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// enter the application code
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bl main
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b shutdown_privileged
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.end
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