11 Commits

Author	SHA1	Message	Date
tychovrahe	c3f84e2949	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	8150636a81	feat(core): add basic support for STM32U5	2024-02-29 23:05:56 +01:00
tychovrahe	8a4f376f20	refactor(core): prepare fw for differently sized fw chunks ... [no changelog]	2023-10-20 16:33:53 +02:00
Martin Milata	040f6c2c8e	Merge branch 'master' into release/23.09	2023-09-29 16:42:23 +02:00
matejcik	c892d4b0ba	refactor(core): inject full model name from build script ... so that we don't have to do awkward string operations when we need it [no changelog]	2023-09-29 16:27:27 +02:00
Martin Milata	07027a69e9	Merge branch 'master' into release/23.09	2023-09-15 14:33:20 +02:00
tychovrahe	bd0b0b2d15	refactor(core): move model specific norcow config to model header ... [no changelog]	2023-08-29 11:17:19 +02:00
tychovrahe	c9a657b074	feat(core): set final name for Safe 3 ... [no changelog]	2023-08-18 16:14:47 +02:00
tychovrahe	5a86add884	refactor(core): differentiate models by internal name in python ... [no changelog]	2023-08-15 22:08:11 +02:00
tychovrahe	238e3fd7c1	refactor(core): add abstraction over flash memory layout ... [no changelog]	2023-07-25 10:25:20 +02:00
tychovrahe	d3284baf21	feat(core): support STM32F429 discovery board	2023-06-15 17:08:14 +02:00